3D cell and array structures and processes

Abstract

Various 3D cell and array structures and processes are disclosed. In embodiments, a memory cell structure is provided that includes vertical bit lines, an insulator surrounding a first portion of the vertical bit lines, a continuous semiconductor layer surrounding the insulator and a second portion of the vertical bit lines, and an extension of conductive material surrounding the continuous semiconductor layer. The memory cell structure also includes a first dielectric layer surrounding the extension of conductive material, a first conductor layer surrounding the first dielectric layer, a second conductor layer surrounding the first conductor layer, a second dielectric layer on top of the first and second conductor layers, a third dielectric layer on bottom of the first and second conductor layers, a first gate on top of the second dielectric layer, and a second gate on the bottom of the third dielectric layer.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application is a U.S. provisional patent application entitled "3D Cell and Array Structures," filed on October 19, 2022, serial number 63 / 417,535; a U.S. provisional patent application entitled "3D Memory Cell and Array Structures," filed on October 19, 2022, serial number 63 / 417,606; a U.S. provisional patent application entitled "3D Cell and Array Structures," filed on October 20, 2022, serial number 63 / 418,011; a U.S. provisional patent application entitled "3D Cell and Array Structures," filed on October 22, 2022, serial number 63 / 418,534; a U.S. provisional patent application entitled "3D Array Structures and Processes," filed on November 1, 2022, serial number 63 / 421,522; a U.S. provisional patent application entitled "3D Cell and Array Structures," filed on November 1, 2022, serial number 63 / 421,522. U.S. Provisional Patent Application No. 63 / 458,634, filed April 11, 2023, entitled "3D Cell and Array Structures"; U.S. Provisional Patent Application No. 63 / 459,406, filed April 14, 2023, entitled "3D Cell and Array Structures and Processes"; U.S. Provisional Patent Application No. 63 / 460,406, filed April 19, 2023, entitled "3D Memory Cell and Array Structures"; U.S. Provisional Patent Application No. 63 / 463,040, filed April 30, 2023, entitled "3D Memory Cell and Array Structures"; U.S. Provisional Patent Application No. 63 / 465,526, filed May 10, 2023, entitled "3D Cell and Array U.S. Provisional Patent Application entitled "3D Cell and Array Structures," Application No. 63 / 466,155, filed May 12, 2023; U.S. Provisional Patent Application entitled "3D Cell and Array Structures," Application No. 63 / 467,004, filed May 16, 2023; U.S. Provisional Patent Application entitled "3D Cell and Array Structures," Application No. 63 / 542, filed October 5, 2023;526, which claims the benefit of priority under 35 U.S.C. §119(e) to U.S. provisional patent application entitled "3D Array Structures and Processes," all of which are incorporated herein by reference in their entireties.

[0002] Exemplary embodiments of the present invention relate generally to the field of memories, and more particularly to memory cell and array structures and related processes. [Background technology]

[0003] As electronic circuit complexity and density increase, memory size, complexity, and cost become important considerations. One approach to increasing memory capacity is to use three-dimensional (3D) array structures. However, cost-effective 3D array structures have not been fully realized. Summary of the Invention

[0004] In various exemplary embodiments, three-dimensional (3D) memory cells, array structures, and related processes are disclosed. In one embodiment, aspects of the invention are applied to construct dynamic random access memories (DRAMs). In other embodiments, aspects of the invention are applied to construct ferroelectric random access memories (FRAMs), resistive random access memories (RRAMs), phase change memories (PCMs), and magnetoresistive random access memories (MRAMs). In yet other embodiments, aspects of the invention are applicable to construct memory elements called "synapses" in artificial neural networks, and for any other memory applications.

[0005] In an exemplary embodiment, a memory cell structure is provided comprising a vertical bit line, an insulator surrounding a first portion of the vertical bit line, a continuous semiconductor layer surrounding the insulator and a second portion of the vertical bit line, and an extension of conductive material surrounding the continuous semiconductor layer. The memory cell structure also includes a first dielectric layer surrounding the extension of conductive material, a first conductor layer surrounding the first dielectric layer, a second conductor layer surrounding the first conductor layer, a second dielectric layer on top of the first and second conductor layers, a third dielectric layer on bottom of the first and second conductor layers, a first gate on top of the second dielectric layer, and a second gate on the bottom of the third dielectric layer.

[0006] In an exemplary embodiment, a memory cell structure is provided that includes a vertical bit line, an insulator surrounding a first portion of the vertical bit line, a continuous semiconductor layer surrounding the insulator and a second portion of the vertical bit line, an extension of conductive material surrounding a portion of the continuous semiconductor layer, a first dielectric layer on top of the extension of conductive material, a second dielectric layer on a bottom surface of the extension of conductive material, a first conductor layer on top of the first dielectric layer, and a second conductor layer on a bottom surface of the second dielectric layer.

[0007] Additional features and benefits of exemplary embodiments of the present invention will become apparent from the detailed description, drawings, and claims set forth below.

[0008] Exemplary embodiments of the present invention will be better understood from the detailed description given below and from the accompanying drawings of various embodiments of the present invention, which should not be construed as limiting the invention to the specific embodiments, but are for illustration and understanding only. [Brief explanation of the drawings]

[0009] [Figure 1A] 1 illustrates an embodiment of a cell structure for use in a 3D array according to the present invention. [Figure 1B] 1 illustrates an embodiment of a cell structure for use in a 3D array according to the present invention. [Figure 1C] 1 illustrates an embodiment of a cell structure for use in a 3D array according to the present invention. [Figure 1D] 1 illustrates an embodiment of a cell structure for use in a 3D array according to the present invention. [Figure 1E] 1 illustrates an embodiment of a 3D cellular structure according to the present invention. [Figure 1F] 1 illustrates an embodiment of a 3D cellular structure according to the present invention. [Figure 1G] 1 illustrates an embodiment of a 3D cellular structure according to the present invention. [Figure 2A] 1 shows an equivalent circuit of an embodiment of a cell structure for a DRAM. [Figure 2B] 1 shows an equivalent circuit of an embodiment of a cell structure for a DRAM. [Figure 2C] 1 shows an equivalent circuit of an embodiment of a cell structure for FRAM. [Figure 2D] 1 shows equivalent circuits of embodiments of cell structures for RRAM and PCM. [Figure 2E] 1 shows an equivalent circuit of an embodiment of a cell structure for an MRAM. [Figure 3A] 1 illustrates an embodiment of a 3D cellular structure according to the present invention. [Figure 3B] 1 illustrates an embodiment of a 3D cellular structure according to the present invention. [Figure 4A] 1 illustrates an embodiment of a 3D cellular structure according to the present invention. [Figure 4B] 1 illustrates an embodiment of a 3D cellular structure according to the present invention. [Figure 5A] 1 illustrates an embodiment of a 3D cellular structure according to the present invention. [Figure 5B] 1 illustrates an embodiment of a 3D cellular structure according to the present invention. [Figure 6A] 1 illustrates an embodiment of a 3D cellular structure according to the present invention. [Figure 6B] 1 illustrates an embodiment of a 3D cellular structure according to the present invention. [Figure 7A] 1 illustrates an embodiment of simplified process steps configured to form a 3D cellular structure according to the present invention. [Figure 7B]1 illustrates an embodiment of simplified process steps configured to form a 3D cellular structure according to the present invention. [Figure 7C] 1 illustrates an embodiment of simplified process steps configured to form a 3D cellular structure according to the present invention. [Figure 7D] 1 illustrates an embodiment of simplified process steps configured to form a 3D cellular structure according to the present invention. [Figure 7E] 1 illustrates an embodiment of simplified process steps configured to form a 3D cellular structure according to the present invention. [Figure 7F] 1 illustrates an embodiment of simplified process steps configured to form a 3D cellular structure according to the present invention. [Figure 7G] 1 illustrates an embodiment of simplified process steps configured to form a 3D cellular structure according to the present invention. [Figure 7H] 1 illustrates an embodiment of simplified process steps configured to form a 3D cellular structure according to the present invention. [Figure 8A] 1 illustrates an embodiment of a 3D array structure according to the present invention. [Figure 8B] 1 illustrates an embodiment of a 3D array structure according to the present invention. [Figure 8C] 1 illustrates an embodiment of a 3D array structure according to the present invention. [Figure 8D] 1 illustrates an embodiment of a 3D array structure according to the present invention. [Figure 8E] 1 illustrates an embodiment of a 3D array structure according to the present invention. [Figure 8F] 1 illustrates an embodiment of a 3D array structure according to the present invention. [Figure 8G] 1 illustrates an embodiment of a 3D array structure according to the present invention. [Figure 8H] 1 illustrates an embodiment of a 3D array structure according to the present invention. [Figure 8I] 1 illustrates an embodiment of a 3D array structure according to the present invention. [Figure 9A] 1 illustrates an embodiment of a 3D array structure according to the present invention. [Figure 9B]1 illustrates an embodiment of a 3D array structure according to the present invention. [Figure 10A] 1 illustrates an embodiment of a 3D cellular structure according to the present invention. [Figure 10B] 1 illustrates an embodiment of a 3D cellular structure according to the present invention. [Figure 10C] 1 illustrates an embodiment of a 3D cellular structure according to the present invention. [Figure 10D] 1 illustrates an embodiment of a 3D cellular structure according to the present invention. [Figure 11A] 1 illustrates an embodiment of a 3D cellular structure according to the present invention. [Figure 11B] 1 illustrates an embodiment of a 3D cellular structure according to the present invention. [Figure 12A] 10B illustrates an embodiment of simplified process steps configured to form the 3D cellular structure shown in FIG. 10A. [Figure 12B] 10B illustrates an embodiment of simplified process steps configured to form the 3D cellular structure shown in FIG. 10A. [Figure 12C] 10B illustrates an embodiment of simplified process steps configured to form the 3D cellular structure shown in FIG. 10A. [Figure 12D] 10B illustrates an embodiment of simplified process steps configured to form the 3D cellular structure shown in FIG. 10A. [Figure 12E] 10B illustrates an embodiment of simplified process steps configured to form the 3D cellular structure shown in FIG. 10A. [Figure 12F] 10B illustrates an embodiment of simplified process steps configured to form the 3D cellular structure shown in FIG. 10A. [Figure 12G] 10B illustrates an embodiment of simplified process steps configured to form the 3D cellular structure shown in FIG. 10A. [Figure 12H] 10B illustrates an embodiment of simplified process steps configured to form the 3D cellular structure shown in FIG. 10A. [Figure 12I] 10B illustrates an embodiment of simplified process steps configured to form the 3D cellular structure shown in FIG. 10A. [Figure 12J]10B illustrates an embodiment of simplified process steps configured to form the 3D cellular structure shown in FIG. 10A. [Figure 12K] 10D illustrates an embodiment of simplified process steps configured to form the 3D cellular structure shown in FIG. 10C. [Figure 12L] 10D illustrates an embodiment of simplified process steps configured to form the 3D cellular structure shown in FIG. 10C. [Figure 12M] 10D illustrates an embodiment of simplified process steps configured to form the 3D cellular structure shown in FIG. 10C. [Figure 12N] 10D illustrates an embodiment of simplified process steps configured to form the 3D cellular structure shown in FIG. 10C. [Figure 12O] 1 illustrates an embodiment of a 3D array structure according to the present invention. [Figure 12P] 1 illustrates an embodiment of a 3D array structure according to the present invention. [Figure 12Q] 1 illustrates an embodiment of a 3D array structure according to the present invention. [Figure 12R] 1 illustrates an embodiment of a 3D array structure according to the present invention. [Figure 12S] 1 illustrates an embodiment of a 3D array structure according to the present invention. [Figure 13A] 1 illustrates an embodiment of a 3D cellular structure according to the present invention. [Figure 13B] 1 illustrates an embodiment of a 3D cellular structure according to the present invention. [Figure 13C] 1 illustrates an embodiment of a 3D cellular structure according to the present invention. [Figure 13D] 1 illustrates an embodiment of a 3D cellular structure according to the present invention. [Figure 14A] 1 illustrates an embodiment of a 3D cellular structure according to the present invention. [Figure 14B] 1 illustrates an embodiment of a 3D cellular structure according to the present invention. [Figure 15A] 1 shows a side view of an embodiment of a 3D cellular structure according to the present invention. [Figure 15B] 1 shows a side view of an embodiment of a 3D cellular structure according to the present invention. [Figure 15C]1 illustrates an embodiment of a 3D cellular structure according to the present invention. [Figure 15D] 1 illustrates an embodiment of a 3D cellular structure according to the present invention. [Figure 16A] 1 illustrates an embodiment of a 3D cellular structure according to the present invention. [Figure 16B] 1 illustrates an embodiment of a 3D cellular structure according to the present invention. [Figure 17A] 1 shows a side view of an embodiment of a 3D cellular structure according to the present invention. [Figure 17B] 1 shows a side view of an embodiment of a 3D cellular structure according to the present invention. [Figure 18A] 1 shows a side view of a 3D cellular structure according to the present invention. [Figure 18B] 1 shows a side view of a 3D cellular structure according to the present invention. [Figure 18C] 1 shows a side view of a 3D cellular structure according to the present invention. [Figure 19A] 14B illustrates an embodiment of a cell structure having a source line configuration similar to the embodiment of the cell structure shown in FIG. 14A. [Figure 19B] 15B illustrates an embodiment of a cell structure having a source line configuration similar to the embodiment of the cell structure shown in FIG. 15A. [Figure 20A] 1 shows a side view of an embodiment of a 3D cellular structure according to the present invention. [Figure 20B] 1 shows a side view of an embodiment of a 3D cellular structure according to the present invention. [Figure 21A] 1 shows a side view of an embodiment of a 3D cellular structure according to the present invention. [Figure 21B] 1 shows a side view of an embodiment of a 3D cellular structure according to the present invention. [Figure 22A] 1 illustrates an embodiment of a 3D cellular structure according to the present invention. [Figure 22B] 1 illustrates an embodiment of a 3D cellular structure according to the present invention. [Figure 22C] 1 illustrates an embodiment of a 3D cellular structure according to the present invention. [Figure 23] 1 illustrates an embodiment of a 3D cellular structure according to the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0010] Those skilled in the art will realize that the following detailed description is for purposes of illustration only and is not intended to be in any way limiting. Other embodiments of the present invention will readily suggest themselves to those skilled in the art having the benefit of this disclosure. Reference will now be made in detail to examples of illustrative embodiments of the present invention as illustrated in the accompanying drawings. The same reference designations or characters are used throughout the drawings and the following detailed description to refer to the same or similar parts.

[0011] In various exemplary embodiments, three-dimensional (3D) memory cell and array structures and related processes are disclosed. For example, embodiments of the present invention relate to 3D NOR type cells and array structures. However, aspects of the present invention are applicable to many different memory technologies. In one embodiment, aspects of the present invention are applied to construct dynamic random access memories (DRAMs). In other embodiments, aspects of the present invention are applied to construct ferroelectric random access memories (FRAMs), resistive random access memories (RRAMs), phase change memories (PCMs), and magnetoresistive random access memories (MRAMs). In other embodiments, aspects of the present invention are applied to construct memory elements, referred to as "synapses," in artificial neural networks. Furthermore, aspects of the present invention are applicable to construct various other memory structures and applications.

[0012] FIG. 1A shows an embodiment of a cell structure for use in a 3D array according to the present invention.

[0013] FIG. 1B shows the cell structure shown in FIG. 1A with the GATE 104a and GATE Dielectric Layer 105a removed to show the internal structure of the cell.

[0014] 1C-D show cross-sectional views of the cell structure shown in FIG. 1A along lines AA′ and BB′, respectively, and in some of the cross-sections shown, structural elements of additional material surrounding the bit lines are shown for clarity.

[0015] The cell structure includes a vertical bit line (BL) 101 made of a conductive material such as metal or a heavily doped semiconductor material such as polysilicon. The cell structure includes a semiconductor layer 102 made of a material such as silicon, polysilicon, germanium, silicon germanium, gallium arsenide, cadmium selenide, indium gallium zinc oxide (IGZO), or any other suitable semiconductor material. The semiconductor layer 102 forms the channel of the cell transistor. In one embodiment, the semiconductor layer 102 is doped with P-type or N-type impurities such as boron or phosphorus, respectively, using a diffusion, implantation, or in-situ doping process.

[0016] The cell structure includes gates 104a-b composed of a conductive material such as metal or a polysilicon material. The cell structure also includes gate dielectric layers 105a-b comprising a material such as a thin oxide or a high-k material such as hafnium oxide (HfO2). An insulator 107 is also provided, comprising an insulating material such as an oxide or nitride. The gates 104a-b may be connected to word lines (WL) of the memory array. The gates 104a-b, the gate dielectric layers 105a-b, and the semiconductor layer 102 form a dual-gate thin-film transistor 119. The source and drain of the transistor are connected to layer 106 and bit line 101, respectively.

[0017] Depending on the cell technology, layer 106 can be composed of different materials. In one embodiment for a dynamic random access memory (DRAM), layer 106 is a dielectric layer comprising a material such as a thin oxide or a high-k material such as HfO2. Conductor layer 103 comprises a material such as a metal or a polysilicon material. Conductor layer 103, dielectric layer 106, and semiconductor layer 102 form a capacitor.

[0018] In other embodiments constituting a ferroelectric random access memory (FRAM), layer 106 comprises multiple layers including a ferroelectric layer such as lead zirconate titanate (PZT), orthorhombic phase hafnium oxide (HfO2) or hafnium zirconium oxide (HfZrO2), and a buffer layer such as an oxide or high-k material such as HfO2.

[0019] In other embodiments comprising a resistive random access memory (RRAM), layer 106 comprises multiple layers including a tunable resistive layer such as hafnium oxide (HfOx), titanium oxide (TiOx), or tantalum oxide (TaOx).

[0020] In other embodiments constituting a phase change memory (PCM), layer 106 comprises multiple layers, including a phase change layer such as a chalcogenide glass, Ge2Sb2Te5 (GST).

[0021] In other embodiments that construct a magnetoresistive random access memory (MRAM), layer 106 comprises multiple layers, including upper and lower layers constructed of a ferromagnetic material such as an iron-nickel (NiFe) or iron-cobalt (CoFe) alloy, and an intermediate tunnel-barrier layer constructed of a thin insulator such as hafnium oxide (HfO2).

[0022] It should be noted that the materials forming layer 106 described above are exemplary and non-limiting, and any other suitable materials within the scope of the present invention may be used to form layer 106. For illustrative purposes, the following description will use dielectric materials in the embodiments, although any other suitable materials are within the scope of the present invention.

[0023] FIG. 1E shows an embodiment of a 3D cellular structure according to the present invention.

[0024] Figure 1F shows the cell structure shown in Figure 1E with the gate 104a and gate dielectric layer 105a removed to reveal the internal structure of the cell. This embodiment is similar to the embodiment shown in Figure 1A, except that heavily doped drain region 127 and source region 128 are formed in semiconductor layer 102. In one embodiment, the drain 127 and source 128 regions have an opposite doping to semiconductor layer 102 to form a junction transistor. In another embodiment, the drain 127 and source 128 regions have the same doping as semiconductor layer 102 to form a junctionless transistor.

[0025] In one embodiment, the drain region 127 is formed by applying a diffusion process to diffuse impurities into the semiconductor layer 102 before the bit line 101 is formed through the bit line hole created to form the bit line 101. The source region 128 is formed by applying a diffusion process to diffuse impurities into the semiconductor layer 102 before the conductor layer 103 is formed.

[0026] 1G shows another embodiment of a 3D cell structure according to the present invention. This embodiment is similar to the embodiment shown in FIG. 1A, except that the cell height has been increased to increase the area of ​​the dielectric layer 106 between the semiconductor layer 102 and the conductor layer 103. For the DRAM cell embodiment, the conductor layer 103, the dielectric layer 106, and the semiconductor layer 102 form a capacitor for charge storage. Increasing the value of the capacitor by increasing the cell height increases the charge stored in the capacitor, thus increasing the data retention time in the DRAM cell.

[0027] 2A-E show equivalent circuits of embodiments of cell structures for DRAM, FRAM, RRAM, PCM, and MRAM, respectively. In one embodiment, the circuit of the cell structure includes a dual gate select transistor 125 and selected memory elements (e.g., memory elements (capacitors) 126a-d). The dual gate select transistor 125 includes gates 104a and 104b. The gates 104a and 104b are connected to word lines WL1 and WL2, respectively. In another embodiment, shown in FIG. 2B, the gates 104a and 104b are connected to the same word line (WL) to form a single gate transistor. The memory elements 126a-d are comprised of a conductor layer 103, a layer 106, and a semiconductor layer 102. In other embodiments, the dielectric layer 106 is comprised of various materials to form various types of memory cells, as described with respect to FIG. 1A.

[0028] 2A shows an embodiment for a DRAM cell in which the memory element 126a is a capacitor. The capacitor is connected to a conductor layer 103 that forms what is also called a conductor plate or capacitor plate (CP). The conductor plate can be supplied with a constant voltage such as VDD or 1 / 2VDD.

[0029] Figure 2B shows an embodiment for a DRAM cell in which memory element 126a is a capacitor. This embodiment is similar to the embodiment shown in Figure 2A, except that gates 104a and 104b of dual-gate transistor 125 are connected together.

[0030] 2C shows an embodiment for a FRAM cell in which the memory element 126b is a ferroelectric capacitor connected to a conductor layer 103 forming a source line (SL).

[0031] 2D shows an embodiment for an RRAM cell and a PCM cell where the memory element 126c is either a resistive memory element or a phase change memory element, respectively. The memory element 126c is connected to a conductor layer 103 that forms a source line (SL).

[0032] 2E shows an embodiment for an MRAM cell in which the memory element 126d is a magnetoresistive memory element, which is connected to a conductor layer 103 forming a source line (SL).

[0033] 3A illustrates an embodiment of a 3D cell structure according to the present invention. This embodiment is similar to the embodiment illustrated in FIG. 1A, except that a conductor layer 109, comprising a material such as a metal, has been added between the dielectric layer 106 and the semiconductor layer 102, as shown. For some specific types of technologies, the conductor layer 109 is formed of the specific metal material required to form the memory element. For example, for an RRAM memory element embodiment, the conductor layer 109 may be formed of titanium (Ti), platinum (Pt), copper (Cu), gold (Au), and other suitable materials.

[0034] FIG. 3B shows the cell structure of FIG. 3A with the gate 104a and gate dielectric layer 105a removed to reveal the internal structure of the cell.

[0035] 4A shows another embodiment of a 3D cell structure according to the present invention. This embodiment is similar to the embodiment shown in FIG. 1A, except that the dielectric layer 106 is formed in a different manner. In the cell structure shown in FIG. 1A, the dielectric layer 106 is formed through the space occupied by the conductor layer 103 before the conductor layer 103 is formed. In the cell structure shown in FIG. 4A, the dielectric layer 106 is formed through the vertical bit line holes before the conductor layer 109 and the semiconductor layer 102 are formed.

[0036] FIG. 4B shows the cell structure shown in FIG. 4A with the gate 104a and gate dielectric layer 105a removed to reveal the internal structure of the cell.

[0037] Figure 5A shows another embodiment of a 3D cell structure according to the present invention. This embodiment is similar to the embodiment shown in Figure 1A, except that the select transistors are formed as conventional junction transistors instead of thin-film transistors. The source 108 and drain 122 regions of the transistor are formed of heavily doped diffusion regions in a semiconductor material. The body 123 of the transistor is formed of a lightly doped semiconductor material, such as a lightly doped silicon material.

[0038] 5B shows the cell structure shown in FIG. 5A with the gate 104a and gate dielectric layer 105a removed to reveal the internal structure of the cell. The source 108 and drain 122 regions have opposite doping to the body 123. For example, in one embodiment, the source 108 and drain 122 regions have N+ doping and the body 123 has P- doping. In another embodiment, the source 108 and drain 122 regions have P+ doping and the body 123 has N- doping.

[0039] Figure 6A shows another embodiment of a 3D cell structure according to the present invention. This embodiment is similar to the embodiment shown in Figure 1A, except that one of the gates, such as gate 104b, has been eliminated and replaced with an insulating layer 129 formed of a material such as oxide. This constitutes a single-gate transistor.

[0040] FIG. 6B shows the cell structure shown in FIG. 6A with the gate 104a and gate dielectric layer 105a removed to reveal the internal structure of the cell.

[0041] In one embodiment, the bottom of the semiconductor layer 102 is etched by first removing the insulating layer 129 using an isotropic etching process, such as a wet etch, and then applying an isotropic etching process, such as a wet etch, to etch the semiconductor layer 102. An insulator, such as an oxide, is then deposited to reform the insulating layer 129. Note that this single-gate transistor structure is applicable, with minor modifications, to all cell structures shown in other embodiments described herein. These modifications and variations are within the scope of the present invention.

[0042] 7A-H show an embodiment of simplified process steps configured to form a 3D cellular structure according to the present invention. To explain the process steps, the cellular structure shown in FIG. 3A is used as an example. It is clear that the process steps can be applied to form the cellular structures shown in other embodiments herein with minor modifications. These modifications and variations are within the scope of the present invention.

[0043] 7A shows how multiple first sacrificial layers, such as layers 110a and 110b, and multiple second sacrificial layers, such as layer 111, are alternately deposited to form a stack. The first and second sacrificial layers have high etch selectivity. For example, in one embodiment, first sacrificial layers 110a-b are nitride layers and second sacrificial layer 111 is an oxide layer. After the stack is formed, multiple vertical bit line holes, such as hole (i.e., opening) 112, are formed by etching through all of the layers in the stack using an anisotropic etching process, such as deep trench etching.

[0044] FIG. 7B shows how an isotropic etching process, such as a wet etch, is applied through the vertical bit line holes 112 to selectively etch the second sacrificial layer 111 to form a recess 113.

[0045] 7C shows a sequence of operations in which the vertical bit line holes 112 and recesses 113 are filled with a conductive material 109, such as a metal or polysilicon material, using a deposition process such as chemical vapor deposition (CVD). The conductive material in the bit line holes 112 is then etched using an anisotropic etching process, such as dry etching, to form a residual conductive layer 109 inside the recesses.

[0046] 7D illustrates how an isotropic etching process, such as a wet etch, is performed through the vertical bit line holes 112 to selectively etch the conductor 109 within the recesses 113 to form the residual conductor 109 shown. Note that in one embodiment, the process steps illustrated in FIGS. 7C-D may be omitted to form the cell structure shown in FIG. 1A.

[0047] FIG. 7E shows how a semiconductor layer 102, such as a silicon layer or an indium gallium zinc oxide (IGZO) layer, is formed on the surface of the sidewalls of the vertical bit line holes 112 and residual conductors 109 within the recesses 113 by using thin film deposition or epitaxial deposition.

[0048] 7F shows a series of operations in which the vertical bit line holes 112 and recesses 113 are filled with an insulator material 107, such as an oxide material, by using a deposition process. Then, an anisotropic etching process, such as dry etching, is performed to etch the insulator 107 from the vertical bit line holes 112, except for the residual insulator 107 inside the recesses 113. The vertical bit line holes 112 are then filled with a conductive material, such as metal or polysilicon, to form the vertical bit lines 101.

[0049] FIG. 7G shows how the second sacrificial layer 111 is removed using an isotropic etching process, such as wet etching. Next, a dielectric layer 106 is formed on the surfaces of the first sacrificial layers 110a-b and the sidewalls of the residual conductors 109 in the space previously occupied by the second sacrificial layer 111 using a thin film deposition process. Depending on the cell technology, the dielectric layer 106 may comprise multiple layers. In one embodiment, these multiple layers are formed by multiple applications of thin film deposition. After depositing the dielectric layer 106, the space is filled with a conductor layer 103, such as a metal or polysilicon layer, using a deposition process, such as chemical vapor deposition (CVD).

[0050] 7H shows a sequence of operations in which the first sacrificial layers 110a and 110b are removed by using an isotropic etching process, such as wet etching. Next, gate dielectric layers 105a-b comprising a thin oxide or high-k material are formed on the sidewall surfaces in the spaces previously occupied by the first sacrificial layers 110a-b by using a thin-film deposition process. The spaces are then filled with a conductive material, such as metal or polysilicon, to form the gates 104a-b. As a result, the cell structure shown in FIG. 3A is formed.

[0051] 8A-8G show an embodiment of a 3D array structure according to the present invention. The 3D array includes the cell structure shown in FIG. 1A by way of example. Note that the 3D array structure may include any of the cell structures shown or described in other embodiments herein. These modifications and variations are within the scope of the present invention.

[0052] FIG. 8A illustrates how multiple cells, such as cells 100a-100c, are stacked to form a 3D array. Cells 100a-100c are separated by insulating layers 114a-114c, which may comprise a material such as oxide or nitride. The array also includes vertical bit lines 101a-101c, word lines 104a-104f, and conductor layers 103a-103c. In this embodiment, each cell, such as cell 100a, can be selected by two word lines, such as word lines 104a and 104b, connected to each cell. In one embodiment, the two word lines connected to each cell, such as word lines 104a and 104b, are connected to different decoder signals. In another embodiment, the two word lines connected to each cell, such as word lines 104a and 104b, are connected to the same decoder signal.

[0053] FIG. 8B illustrates another embodiment of a 3D array structure in accordance with the present invention. This embodiment is similar to the embodiment illustrated in FIG. 8A, except that two adjacent cells, such as cells 100a and 100b, share one word line 104b. Similarly, adjacent cells 100c and 100d share word line 104e. In one embodiment, this reduces the height of the 3D array structure. In this embodiment, the shared word lines 104b and 104e can be connected to ground or supplied with 0V to turn off the transistors between the two adjacent cells. Cells 100a and 100b are selected by word lines 104a and 104c, respectively. Cells 100c and 100d are selected by word lines 104d and 104f, respectively.

[0054] Figure 8C shows another embodiment of a 3D array structure in accordance with the present invention. This embodiment is similar to the embodiment shown in Figure 8A, except that word lines 104a-104f are formed as layers rather than line patterns. In one embodiment, this reduces the die size by reducing the horizontal space between word lines. Also shown in Figure 8C are vertical bit lines 101a-101e. In one embodiment, bit line select transistors (shown in Figures 8H-I) are located at the top or bottom of the array and connected to each bit line to enable selection of the bit line.

[0055] The 3D array structure shown in FIG. 8C is suitable for FRAM, RRAM, PCM, and MRAM applications, but may not be suitable for DRAM applications. Because the read operation of a DRAM cell is destructive, unselected cells coupled to the selected word line layer may be turned on, causing charge sharing between the cell's capacitor and the bit line capacitance, causing them to lose their data. Therefore, for DRAM applications, the 3D array structure shown in FIG. 8D is provided.

[0056] 8D illustrates an embodiment of a 3D DRAM array structure according to the present invention, in which vertical slits, such as vertical slits 140a and 140b, are formed by cutting through all layers using an anisotropic etching process, such as deep trench etching. The slits 140a and 140b separate the word line layer into individual word lines, such as individual word lines 104a-104f.

[0057] Vertical bit lines, such as vertical bit lines 101a-101c, coupled to the same word line, such as 104a-104f, are connected to different horizontal bit lines 141a-141c. In one embodiment, horizontal bit lines 141a-141c are formed of a conductive material, such as metal or polysilicon material. Horizontal bit lines 141a-141b can be located at the top of the 3D array shown in FIG. 8D or at the bottom of the 3D array. By using this array structure, all cells selected by a word line are coupled to a horizontal bit line to perform read and write-back (refresh) operations. Therefore, the data loss problem described above is eliminated.

[0058] FIG. 8E shows how the vertical slits 140a and 140b shown in FIG. 8D are filled with an insulator material 142a-b, such as an oxide material, by using a deposition process such as chemical vapor deposition (CVD).

[0059] 8F shows how the vertical slits 140a and 140b shown in FIG. 8D are filled with a conductive material, such as a metal material, to form vertical capacitor plates 143a and 143b. The capacitor plates 143a and 143b are connected to conductive layers, such as layers 103a and 103b of the cell. In one embodiment, the capacitor plates 143a and 143b are connected to a constant voltage, such as VDD or ground.

[0060] In one embodiment, insulating layers, such as insulating layers 144a and 144b, are formed on the sidewalls of the word lines, such as word lines 104a-104f, prior to forming the capacitor plates to prevent the word lines from shorting out the vertical capacitor plates 143a and 143b. In one embodiment, insulating layers 144a and 144b are formed by etching word line layers 104a-104f through vertical slits 140a and 140b using an isotropic etching process, such as wet etching, to form recesses in the word lines. The recesses are then filled with an insulator, such as an oxide insulator, to form insulating layers 144a and 144b.

[0061] In another embodiment, the insulating layers 144a and 144b are formed by applying a metal-oxidation process through the vertical slits 140a and 140b to form a metal-oxide layer on the sidewalls of the word lines 104a-104f, which are then filled with a conductive material, such as a metal material, to form the capacitor plates 143a and 143b.

[0062] 8G shows another embodiment of a 3D DRAM array structure according to the present invention. In this embodiment, the conductor layer 103 of the cell structure shown in FIG. 1A is formed of a sacrificial material, such as a nitride material, that has a high etching selectivity from the word lines 104a and 104b. After the vertical slits 140a and 140b shown in FIG. 8D are formed, an isotropic etching process, such as wet etching, is performed through the vertical slits 140a and 140b to etch the sacrificial layer and form recesses, such as recesses 146a and 146b.

[0063] Next, a thin dielectric layer 106 comprising a material such as a thin oxide material or a high-k material such as HfO2 is formed on the surface of the sidewalls of the vertical slits 140a and 140b and recesses 146a and 146b by using a thin film deposition process. Next, the slits 140a and 140b and recesses 146a and 146b are filled with a conductive material such as a metal material by using a metal deposition process to form capacitor plates 145a and 145b.

[0064] 8H illustrates another embodiment of a 3D DRAM array structure using the array structure shown in FIG. 8C in accordance with the present invention. Vertical bit lines, such as bit lines 101a-101c, are connected to horizontal bit lines 141a-141c through bit line select transistors 170a-170c. Select lines 171a-171c are connected to the gates of select transistors, such as select transistors 170a-170c. In one embodiment, bit line select transistors 170a-170c are vertical channel transistors or any other suitable type of transistor.

[0065] 8I illustrates an embodiment using vertical channel transistors as bitline select transistors, such as bitline select transistor 170a, which is connected to horizontal bitline 141a through conductor contact 172.

[0066] Figure 9A shows an embodiment of a 3D cell structure according to the present invention. This embodiment is similar to the embodiment shown in Figure 1A, except that it includes insulating layers 114a and 114b between the different layers of the cell. In this embodiment, the channels of the select transistors are oriented horizontally, as indicated by the indicators in the semiconductor layer 102.

[0067] 9B shows another embodiment of a 3D cell structure according to the present invention. This embodiment is similar to the embodiment shown in FIG. 9A, except that the channels of the select transistors are vertically oriented, as indicated by the indicators in the semiconductor layer 102. This transistor structure is applicable to all the cell structures shown here in other embodiments. These modifications and variations are within the scope of the present invention.

[0068] FIG. 10A illustrates another embodiment of a 3D cell structure according to the present invention. This embodiment is similar to the embodiment shown in FIG. 3A, except that an extended portion 120 of conductor layer 109 has been added to increase the value of the capacitor. In one embodiment, extended portion 120 is formed of a conductive material, such as a metal or polysilicon material. Extended portion 120 is coupled to conductor layer 121, which is also formed of a material, such as a metal or polysilicon material. Conductive layer 121 is also connected to conductor layer 103.

[0069] FIG. 10B shows the cell structure shown in FIG. 10A with the gate 104a and gate dielectric layer 105a removed to reveal the internal structure of the cell.

[0070] 10A-B includes a vertical bit line 101, an insulator 107 surrounding a first portion of the vertical bit line 101, a continuous semiconductor layer 102 surrounding the insulator 107 and a second portion of the vertical bit line 101, an extension 120 of conductive material surrounding the continuous semiconductor layer 102, and a dielectric layer 106 surrounding the extension 120 of conductive material. The cell structure also includes a conductor layer 121 surrounding the dielectric layer 106, a conductor layer 103 surrounding the conductor layer 121, a dielectric layer 105a on top of the conductor layer 121 and the conductor layer 103, a dielectric layer 105b on the bottom of the conductor layer 121 and the conductor layer 103, a gate 104a on top of the dielectric layer 105a, and a gate 104b on the bottom of the dielectric layer 105b.

[0071] Figure 10C shows another embodiment of a 3D cellular structure according to the present invention. This embodiment is similar to the embodiment shown in Figure 10A, except that the extension portion 120 is formed to have a different shape than that shown in Figure 10A. In this embodiment, the extension portion 120 is located entirely inside the groove formed by the conductor layer 121.

[0072] FIG. 10D shows the cell structure shown in FIG. 10C with the gate 104a and gate dielectric layer 105a removed to reveal the internal structure of the cell.

[0073] 11A shows another embodiment of a 3D cell structure according to the present invention, which is similar to the embodiment shown in FIGS. 10A-B, except that the extension portion 120 is formed by extension of the semiconductor layer 102.

[0074] FIG. 11B shows the cell structure shown in FIG. 11A with the gate 104a and gate dielectric layer 105a removed to reveal the internal structure of the cell.

[0075] 12A-J illustrate an embodiment of simplified process steps configured to form the 3D cell structure shown in FIG. 10A.

[0076] 12A shows how multiple first sacrificial layers 115a and 115b comprising a material such as nitride and multiple second sacrificial layers 131 comprising a material such as oxide are alternately deposited to form a stack. The first sacrificial layers 115a and 115b and the second sacrificial layers 131 have high etch selectivity. Next, multiple vertical bit line holes, such as bit line holes (i.e., openings) 117, are formed by etching through all the layers of the stack using an anisotropic etching process, such as deep trench etching.

[0077] FIG. 12B shows how an isotropic etching process, such as a wet etch, is performed through the vertical bit line holes 117 to selectively etch the second sacrificial layer 131 to form the recesses (RECESS) 118.

[0078] 12C shows how a conductor layer 121 is formed on the surface of the second sacrificial layer 131 and the sidewalls of the first sacrificial layers 115a-b within the recesses 118 using a thin film deposition process. The vertical bit line holes 117 and the recesses 118 are then filled with an insulator 119, such as an oxide or nitride material, using a deposition process. Afterwards, an anisotropic etching process, such as dry etching, is performed to etch the conductor 121 and repair the bit line holes 117.

[0079] Figure 12D shows how an isotropic etching process, such as a wet etch, is performed through the vertical bit line hole 117 to selectively etch the conductor layer 121 and the insulator 119 to form the illustrated extended recess 130. In another embodiment, the structure shown in Figure 12D is formed by using two separate isotropic etching processes. A first isotropic etching process is performed to etch only the insulator 119. Then, a second isotropic etching process is performed to etch the conductor layer 121 using the insulator 119 as a hard mask.

[0080] 12E shows how an isotropic etching process, such as a wet etch, is performed to remove the insulator 119. Next, a thin dielectric layer 106, such as a thin oxide or high-k material, is formed on the surface of the vertical bit line holes 117 and the sidewalls of the recesses 130 by using a thin film deposition process, such as atomic layer deposition (ALD).

[0081] FIG. 12F shows a series of steps in which a conductive material 120, such as a metal or polysilicon material, is deposited to fill the vertical bit line holes 117 and the recesses 130. An anisotropic etching process, such as a dry etch, is then performed to etch the conductor 120 in the vertical bit line holes 117 while leaving a remaining portion of the conductor 120 inside the recesses. An isotropic etching process, such as a wet etch, is then performed through the vertical bit line holes 117 to selectively etch the conductive layer 120 and partially form the recesses 130. The remaining portion of the conductive layer 120 forms the extension portion 120 shown in FIG. 10A. For the cell structure shown in FIGS. 11A-B, the process step shown in FIG. 12F can be omitted.

[0082] FIG. 12G shows how a semiconductor layer 102 comprising silicon, polysilicon, or indium gallium zinc oxide (IGZO) material is formed on the surface of the dielectric layer 106 and the sidewalls of the conductor 120 by using thin film growth, such as atomic layer deposition (ALD), epitaxial growth, or epitaxial deposition, through the bit line hole 117.

[0083] 12H shows a series of steps in which the vertical bit line holes 117 and recesses 130 are filled with an insulator material 107, such as an oxide material, by using a deposition process, such as CVD, through the bit line holes 117. Then, an anisotropic etching process, such as dry etching, is performed to etch the insulator 107 in the vertical bit line holes 117 while leaving behind remaining portions of the insulator 107 inside the recesses 130. Next, the vertical bit line holes 117 are filled with a conductor material 101, such as a metal or polysilicon material, to form the vertical bit lines 101.

[0084] 12I shows how the second sacrificial layer 131 shown in FIG. 12H is removed by using an isotropic etching process such as wet etching. The resulting space is then filled with a conductive material such as metal or polysilicon to form the conductive layer 103.

[0085] FIG. 12J shows how the first sacrificial layers 115a and 115b are removed by using an isotropic etching process, such as wet etching. Gate dielectric layers 105a and 105b, comprising a material such as a thin oxide or a high-k material, are formed on the sidewall surfaces in the spaces previously occupied by the first sacrificial layers 115a and 115b by using a thin-film deposition process. The spaces are then filled with a conductive material, such as a metal or polysilicon material, to form the gates 104a and 104b. As a result, the cell structure shown in FIG. 10A is formed.

[0086] 12K-N illustrate an embodiment of simplified process steps configured to form the 3D cell structure shown in FIG. 10C.

[0087] Figure 12K shows the cell structure formed after performing the process steps shown in Figure 12E. The reader is referred to Figures 12A-E for a detailed description of the process steps performed to form the cell structure shown in Figure 12E.

[0088] 12L shows a series of process steps in which a conductor material 120, such as a metal or polysilicon material, is deposited to fill the vertical bit line holes 117 and the recesses 130. Next, an anisotropic etching process, such as a dry etch, is performed to etch the conductor 120 in the vertical bit line holes 117 and the conductor 120 inside the recesses. Next, an isotropic etching process, such as a wet etch, is performed through the vertical bit line holes 117 to selectively etch the conductor layer 120 to form the recesses 130. The remaining portion of the conductor layer 120 forms the extension portion 120 shown in FIG. 10A. Note that the shape of the conductor layer 120 is different from that shown in FIG. 12F.

[0089] FIG. 12M shows how a semiconductor layer 102 comprising a material such as silicon or indium gallium zinc oxide (IGZO) is formed on the surface of the dielectric layer 106 and on the sidewalls of the conductor 120 by using thin film deposition or epitaxial deposition.

[0090] 12N shows a series of steps in which the vertical bit line holes 117 and recesses 130 are filled with an insulator material 107, such as an oxide material, by performing a deposition process through the bit line holes 117. Next, an anisotropic etching process, such as a dry etch, is performed to etch the insulator 107 in the vertical bit line holes 117, except for the remaining portions of the insulator 107 within the recesses 130. The vertical bit line holes 117 are then filled with a conductive material, such as a metal or polysilicon material, to form the vertical bit lines 101. Next, the process steps shown in FIGS. 12I-J are performed to form the cell structure shown in FIG. 10C.

[0091] Figure 12O shows another embodiment of a 3D array structure according to the present invention. This embodiment is similar to the embodiment shown in Figure 8A, except that the cell structure shown in Figure 10C is used as an example. Note that all cell structures shown in this other embodiment are also applicable to all 3D array structures shown in Figures 8A to 8I.

[0092] The embodiment shown in Figure 12O illustrates how multiple cells, such as cells 100a-100c, are stacked to form a 3D array. Cells 100a-100c are separated by insulating layers 114a-114c, which may comprise a material such as oxide or nitride. The array also includes vertical bit lines 101a-101c, word lines 104a-104f, and conductor layers 103a-103c.

[0093] FIG. 12P shows the 3D array structure shown in FIG. 12O with the top word lines 104a and portions of the layers removed to reveal the internal structure of the array.

[0094] FIG. 12Q illustrates a top view embodiment of the 3D array structure shown in FIGS. 12O-P in accordance with the present invention. FIG. 12Q illustrates cells 173a-173h, vertical bit lines 101a-101h, and horizontal bit lines 141a-141h. Layer 174 can be either a word line or a select line for a bit line select transistor, depending on the type of 3D array structure. For example, with the 3D array structure shown in FIG. 8D, layer 174 forms word lines, such as word line 104a. With the 3D array structure shown in FIGS. 8H-I, layer 174 forms select lines, such as select line 171a. In one embodiment, the first row of cells 173a-173g and the second row of cells 173b-173h are staggered as shown. This allows two rows of cells to be connected to a single word line or select line 174.

[0095] FIG. 12R illustrates another embodiment of the top view of the 3D array structure shown in FIGS. 12O-P in accordance with the present invention. This embodiment is similar to the embodiment shown in FIG. 12Q, except that four rows of cells, such as cells 173a-173p, are staggered as shown. This allows four rows of cells 173a-173p to be connected to a single word line or select line 174. This embodiment doubles the number of horizontal bit lines 141a-141p compared to the embodiment shown in FIG. 12Q. This enhances memory performance by increasing the "page" size used in read and write operations.

[0096] FIG. 12S shows a top view of another embodiment of the 3D array structure shown in FIGS. 12O-P in accordance with the present invention. This embodiment is similar to the embodiment shown in FIG. 12Q, except that six rows of cells 173a-173x are staggered as shown. This allows six rows of cells 173a-173x to be connected to a single word line or select line 174. This embodiment has three times the number of horizontal bit lines 141a-141x compared to the embodiment shown in FIG. 12Q. Memory performance is enhanced by increasing the "page" size used in read and write operations.

[0097] The embodiments shown in Figures 12Q-S are exemplary and not limiting. In other embodiments, the cells are staggered in any other number of rows or staggered in any other manner. These variations and modifications are within the scope of the present invention.

[0098] 13A-D show an embodiment of a 3D cell structure according to the present invention.

[0099] FIG. 13A shows a side view of a 3D cell structure. This embodiment of the 3D cell structure is similar to the embodiment shown in FIGS. 10A-B, except that the conductor layer 121 shown in FIGS. 10A-B is divided into two conductor layers 133a and 133b formed of a metal or polysilicon material. The conductor plate 132 is formed of a metal or polysilicon material and is connected to the semiconductor layer 102. The capacitor dielectric layers 106a and 106b comprise a material such as a thin oxide or a high-k material (e.g., HfO2). The insulating layer 134 comprises a material such as an oxide or nitride material. The conductor layers 133a and 133b, the capacitor dielectric layers 106a and 106b, and the conductor plate 132 form a capacitor.

[0100] The array also includes vertical bit lines 101 and gates 104a and 104b formed of a conductive material, such as a metal or polysilicon material. The array also includes gate dielectric layers 105a and 105b comprising a material such as a thin oxide or a high-k material, such as hafnium oxide (HfO2). The array also includes a semiconductor layer 102 comprising a material such as silicon or indium gallium zinc oxide (IGZO). The array also includes an insulator 107 comprising a material such as an oxide or nitride material. The array also includes insulating layers 114a and 114b comprising a material such as an oxide or nitride material. In an embodiment, the gates 104a and 104b, the gate dielectric layers 105a and 105b, and the semiconductor layer 102 form two thin-film select transistors.

[0101] 13B to 13D show top views of the cross section of the 3D cell structure taken along lines AA', BB', and CC' shown in Fig. 13A, respectively. Note that the side view shown in Fig. 13A shows half of the cell with the bit line 101 on the right side. The top views shown in Fig. 13B to 13D show the entire cell with the bit line 101 at the center.

[0102] 14A-B show an embodiment of a 3D cell structure according to the present invention. This embodiment is similar to the embodiment shown in FIGS. 13A-D, except that conductor layers 133a and 133b have been replaced with conductor layer 135. Conductor layer 135 is formed by removing layers 133a, 133b, and 134 using an isotropic etching process, such as wet etching, followed by forming capacitor dielectric layer 106 using thin film deposition and forming conductor layer 135 using a deposition process.

[0103] FIG. 14B shows a top view of a cross section taken along line AA' in FIG. 14A. The cross sections taken along lines BB' and CC' in FIG. 14A are the same as those shown in FIGS. 13B to 13C. The side view shown in FIG. 14A shows half of the cell with the bit line 101 on the right side. The top view shown in FIG. 14B shows the entire cell with the bit line 101 at the center. The cell structures shown in FIGS. 13A and 14A are applicable to the cell structures of all other embodiments of the present invention shown herein.

[0104] 14A-B includes a vertical bit line 101, an insulator 107 surrounding a first portion of the vertical bit line 101, a continuous semiconductor layer 102 surrounding the insulator 107 and a second portion of the vertical bit line 101, an extended portion 132 of conductive material surrounding a first portion of a side of the continuous semiconductor layer 102, a dielectric layer 106 surrounding the extended portion 132 of conductive material and a second portion of a side of the continuous semiconductor layer 102, and a conductor layer 135 surrounding the first dielectric layer. The cell structure also includes a dielectric layer 105a above a top surface of the conductor layer 135, a dielectric layer 105b below a bottom surface of the conductor layer 135, a conductor layer 104a on top of the dielectric layer 105a, and a conductor layer 104b on a bottom surface of the dielectric layer 105b.

[0105] Figure 15A shows a side view of another embodiment of a 3D cell structure according to the present invention. This embodiment is similar to the embodiment shown in Figure 14A, except that the gates 104a and 104b are formed to have different shapes. While in Figure 14A the channels of the select transistors are oriented horizontally, in this embodiment the channels of the select transistors, as indicated by indicator 102, are oriented vertically.

[0106] Figure 15B shows a side view of another embodiment of a 3D cell structure according to the present invention. This embodiment is similar to the embodiment shown in Figure 14A, except that the gates 104a and 104b are formed to have different shapes. In this embodiment, the channels of the select transistors, indicated by indicators 102, are positioned horizontally.

[0107] It should be noted that the different shapes of gates 104a and 104b shown in Figures 14A, 15A and 15B are applicable to the cell structures of all other embodiments of the present invention shown herein.

[0108] Although the previous embodiment shows one conductor plate 132 in the cell structure, according to the present invention, the cell structure may have multiple conductor plates 132 .

[0109] 15C shows a side view of an embodiment of a cell structure having two conductive plates 132a and 132b in accordance with the present invention. In other embodiments, the cell structure can be configured with any number of conductive plates.

[0110] FIG. 15D shows a cross-sectional view of the cell structure shown in FIG. 15C taken along line AA' in FIG. 15C. The multiple conductor plate structure shown in FIG. 15C is applicable to the cell structures of all other embodiments of the present invention. Note that the side view shown in FIG. 15C shows half of the cell with the bit line 101 on the right. The top view shown in FIG. 15D shows the entire cell with the bit line 101 at the center.

[0111] FIGS. 16A-B illustrate embodiments of a 3D cell structure according to the present invention. These embodiments are similar to the embodiment shown in FIGS. 14A-B, except that the select transistors are formed as conventional junction transistors instead of thin-film transistors. As shown in FIG. 16A, drain 136 and source 137 regions are formed of a heavily doped semiconductor layer, such as a heavily doped silicon layer. Transistor body 138 is formed of a lightly doped semiconductor material, such as a lightly doped silicon material. In embodiments, drain 136 and source 137 regions have opposite doping to body 138. Note that the side view shown in FIG. 16A illustrates half of the cell, with bit line 101 on the right. The top view shown in FIG. 16B illustrates the entire cell, with bit line 101 at the center. The junction transistor structure shown in this embodiment is applicable to all other cell structure embodiments shown herein according to the present invention.

[0112] 17A-B show side views of embodiments of a 3D cell structure according to the present invention. These embodiments are similar to the embodiment shown in FIG. 15B, except that the conductive plate 132 is formed of a P-type semiconductor material, such as silicon or polysilicon material. This allows the semiconductor plate 132 to store electrical holes 150 to represent data. The holes 150 can be generated using any one of a number of suitable mechanisms. In one embodiment, the holes 150 are generated using a band-to-band tunneling (BTBT) mechanism. The gates 104a and 104b are supplied with a positive voltage to turn on a channel in the semiconductor layer 102 and transfer an appropriate positive voltage, such as 2.5V, to the semiconductor plate 132. A suitable negative voltage, such as −2V, is supplied to the semiconductor plate 132. This causes band-to-band tunneling to occur at the junction between the semiconductor layer 102 and the semiconductor plate 132, and the holes 150 are injected into the semiconductor plate 132, as indicated by the arrows in FIG. 17A. When gates 104 a and 104 b are supplied with a low voltage, such as 0 V, to turn off the channel in semiconductor layer 102 , holes 150 are trapped within semiconductor plate 132 .

[0113] FIG. 17B illustrates a read operation. During a read operation, bit line 101 is precharged to an appropriate voltage. Gates 104a and 104b are supplied with a positive voltage to turn on the channel in semiconductor layer 102. Holes 150 stored in semiconductor plate 132 flow through the channel to bit line 101, as indicated by the arrows in FIG. 17B, resulting in charge sharing with the capacitance of bit line 101. This condition changes the voltage on bit line 101. If semiconductor plate 132 does not store holes, the voltage on bit line 101 remains uncharged. Sensing circuitry (not shown) is coupled to bit line 101 to detect the voltage change and determine data. The cell structure and operation illustrated in FIGS. 17A-B are applicable to all other embodiments of the cell structure of the present invention.

[0114] 18A-C show side views of a 3D cell structure according to the present invention. This embodiment is similar to the embodiment shown in FIGS. 17A-B, except that the semiconductor plate 132 is connected to a source line 151 formed of a conductive material such as a metal or a heavily doped polysilicon material. The semiconductor plate 132 is formed of a P-type semiconductor material such as silicon or a polysilicon material. This allows the semiconductor plate 132 to accumulate electrical holes 150 to represent data. This cell structure is also referred to as a "floating body" cell structure.

[0115] The holes 150 are generated using any one of a number of suitable mechanisms. In one embodiment, the holes 150 are generated using the band-to-band tunneling (BTBT) mechanism described in Figure 17A. The reader is referred to the description of Figure 17A for detailed operation.

[0116] In another embodiment, holes 150 are generated using an "impact ionization" mechanism. Gates 104a and 104b are supplied with a positive voltage to turn on the channel in semiconductor layer 102 and transmit an appropriate positive voltage, such as 2.5 V, to semiconductor plate 132. Conductor layers 135a and 135b are supplied with a low voltage, such as 0.7 V to 1 V, that is higher than the threshold voltage Vt, to weakly turn on the channel in the surface of semiconductor plate 132 below conductor layers 135a and 135b. As a result, holes 150 are generated at the junction between semiconductor layer 102 and semiconductor plate 132, and the holes 150 are injected into semiconductor plate 132, as shown by the arrows in FIG. 18A . When gates 104a and 104b are supplied with a low voltage, such as 0 V, to turn off the channel in semiconductor layer 102, holes 150 are trapped within semiconductor plate 132.

[0117] 18B shows the operation of removing holes 150 from semiconductor plate 132. Gates 104a and 104b are supplied with a positive voltage to turn on the channel in semiconductor layer 102. Bit line 101 is supplied with a negative voltage, such as -1 V. As a result, a PN forward bias current flows from semiconductor plate 132 through the channel in semiconductor layer 102 to bit line 101, as shown by the arrow in FIG. 18B. This current discharges holes 150 accumulated in semiconductor plate 132.

[0118] In another embodiment, bit line 101 is supplied with 0V. Conductor layers 135a and 135b are supplied with a positive voltage, such as 2V, providing capacitive coupling to semiconductor plate 132. This raises the voltage on semiconductor plate 132 above the threshold voltage of the PN junction, causing a PN forward current to flow from semiconductor plate 132 to bit line 101, draining holes 150.

[0119] In other embodiments, a negative voltage such as −1 V or 0 V is supplied to the source line 151 instead of the bit line 101. This causes a PN forward current to be generated at the junction between the semiconductor plate 132 and the source line 151, causing holes to be pumped into the source line 151.

[0120] 18C illustrates a read operation for the cell. Bit line 101 and source line 151 are supplied with different voltages, such as 1V and 0V, respectively. Gates 104a and 104b are supplied with a positive voltage to turn on the channel in semiconductor layer 102. Assuming there are holes 150 stored in semiconductor plate 132, the holes 150 lower the threshold voltage of channels 152a and 152b in semiconductor layer 132 below conductor layers 135a and 135b. A read voltage higher than the threshold voltage is supplied to conductor layers 135a and 135b. This turns on channels 152a and 152b, allowing current to conduct from bit line 101 to source line 151.

[0121] When semiconductor plate 132 is not storing holes, the threshold voltage of channels 152a and 152b in semiconductor layer 132 is higher than the read voltage applied to conductive layers 135a and 135b. Therefore, channels 152a and 152b are turned off and do not conduct current. Sensing circuitry (not shown) coupled to bit line 101 detects the current and determines the data. The structure and operation of source line 151 shown in Figures 18A-C are applicable to all other embodiment cell structures shown herein according to the present invention.

[0122] 19A-B show embodiments of a cell structure having a source line configuration similar to source line 151 in the embodiments of the cell structure shown in FIGS. 14A and 15A, respectively.

[0123] FIG. 20A shows a side view of another embodiment of a 3D cell structure according to the present invention. This embodiment is similar to the embodiment shown in FIG. 15A, except that additional insulating layers 160a and 160b, comprising materials such as oxide or nitride, are formed between the conductor layer 135 and the gates 104a and 104b. This configuration reduces the parasitic capacitance of the gates 104a and 104b, thereby reducing the RC delay of the gates. This configuration also reduces the capacitive coupling of the gates 104a and 104b to the conductor layer 135. This feature is applicable to all other embodiments of the cell structure shown herein according to the present invention.

[0124] Figure 20B shows a side view of another embodiment of a 3D cell structure according to the present invention. This embodiment is similar to the embodiment shown in Figure 20A, except that the gate dielectric layers 105a and 105b are formed with a different shape. In Figure 20A, the gate dielectric layers 105a and 105b are formed to surround the gates 104a and 104b. In Figure 20B, the gate dielectric layers 105a and 105b are formed on the sidewalls of the semiconductor layer 102. This configuration of the gate dielectric layers is applicable to all other embodiments of the cell structure shown herein according to the present invention.

[0125] FIG. 21A shows a side view of another embodiment of a 3D cell structure according to the present invention. This embodiment is similar to the embodiment shown in FIG. 15A, except that additional channel regions 161 a and 161 b are formed in the semiconductor layer 102. In one embodiment, the channel regions 161 a and 161 b are formed by doping the semiconductor layer 102 with an opposite-type dopant using an isotropic doping process, such as plasma doping or vapor-phase doping, to reverse the doping type of the channel regions 161 a and 161 b. For example, if the semiconductor layer 102 has N+ doping, the channel regions 161 a and 161 b are doped with a P-type dopant, such as bromine, to form P-channel regions. If the semiconductor layer 102 has P+ doping, the channel regions 161 a and 161 b are doped with an N-type dopant, such as phosphorus, to form N-channel regions.

[0126] In one embodiment, the doping process is performed through the space occupied by gates 104a and 104b before gate dielectric layers 105a and 105b are formed. The features shown in Figure 21A are applicable to the cell structures of all other embodiments shown herein according to the present invention.

[0127] FIG. 21B shows a side view of another embodiment of a 3D cell structure according to the present invention. This embodiment is similar to the embodiment shown in FIG. 15A, except that the transistors of the cell are formed as junction transistors. The cell structure includes a semiconductor layer 163, which comprises materials such as silicon and polysilicon that form the body of the transistor. The semiconductor layer 163 can have a P-type or N-type doping. A source region 164 is formed by doping the semiconductor layer 163 with an opposite-type dopant, such as an N-type or P-type dopant, using an isotropic doping process, such as plasma doping or vapor-phase doping. In one embodiment, the doping process is applied through the space occupied by the conductive plate 132 and conductive layer 135 before the formation of the conductive plate 132 and conductive layer 135 and the dielectric layer 106.

[0128] In one embodiment, drain regions 165a and 165b are formed of a semiconductor material having an opposite doping to semiconductor layer 163. For example, in one embodiment, semiconductor layer 163 has a P-doping and source region 164 and drain regions 165a and 165b have an N+ doping. In another embodiment, semiconductor layer 163 has an N-doping and source region 164 and drain regions 165a and 165b have a P+ doping.

[0129] In this embodiment, bit line 101 is formed of a highly doped semiconductor material, such as a highly doped silicon or polysilicon material, having an opposite doping to semiconductor layer 163. In other embodiments, if bit line 101 is formed of a metal, an insulating layer (not shown) comprising oxide or nitride is formed between semiconductor layer 163 and bit line 101 to prevent them from shorting together. The features shown in Figure 21B are applicable to the cell structure of all other embodiments shown herein according to the present invention.

[0130] Figures 22A-C show another embodiment of a 3D cell structure according to the present invention. This embodiment is similar to the embodiment shown in Figure 20A, except that the capacitor formed by the conductive plate 132 and the conductive layer 135 is formed with a different shape. For example, in Figure 20A, the conductive layer 135 surrounds the conductive plate 132, and in Figure 22A, the conductive plate 132 surrounds the conductive layer 135.

[0131] In this embodiment, insulating layers 160a and 160b comprise a material such as an oxide or nitride material and are formed between conductive plate 132 and gates 104a and 104b. This configuration reduces capacitive coupling from gates 104a and 104b to conductive plate 132. In other embodiments, insulating layers 160a and 160b are eliminated to form a cell structure similar to the embodiment shown in Figure 15A. The capacitor geometry shown in this embodiment is applicable to the cell structures of all other embodiments shown herein according to the present invention.

[0132] 22B-C show top cross-sectional views of the cell structure shown in FIG. 22A taken along lines AA' and BB', respectively.

[0133] FIG. 23 illustrates another embodiment of a 3D cell structure according to the present invention. This embodiment is similar to the embodiment shown in FIG. 15A, except that the gate 104b and gate dielectric layer 105b are eliminated. The cell has only one gate 104a and an insulating layer 114b made of a material such as an oxide or nitride material. This embodiment reduces the height of the cell. Reducing the cell height allows more cells to be stacked in a 3D array. This feature is applicable to all other embodiments of the cell structure according to the present invention shown here.

[0134] Although the embodiment shown in Figures 20A-23 uses the cell structure shown in Figure 15A for purposes of illustration, it will be apparent that the features of the embodiment shown in Figures 20A-23 are also applicable to the cell structures of all other embodiments of the present invention shown herein.

[0135] While exemplary embodiments of the present invention have been shown and described, it will be apparent to those skilled in the art that, based on the teachings herein, changes and modifications may be made without departing from the exemplary embodiments and their broader aspects. Therefore, the following claims are intended to encompass within their scope all such changes and modifications as are within the true spirit and scope of the exemplary embodiments of the present invention.

Claims

1. 1. A memory cell structure comprising: vertical bit lines; an insulator surrounding a first portion of the vertical bit line; a continuous semiconductor layer surrounding the insulator and a second portion of the vertical bit line; an extension of conductive material surrounding the continuous semiconductor layer; a first dielectric layer surrounding the extension of conductive material; a first conductor layer surrounding the first dielectric layer; a second conductor layer surrounding the first conductor layer; a second dielectric layer on top of the first and second conductor layers; a third dielectric layer below the first and second conductor layers; a first gate on the top surface of the second dielectric layer; a second gate on the lower surface of the third dielectric layer; A memory cell structure comprising:

2. 1. A memory cell structure comprising: vertical bit lines; an insulator surrounding a first portion of the vertical bit line; a continuous semiconductor layer surrounding the insulator and a second portion of the vertical bit line; an extension of conductive material surrounding a first portion of a side of the continuous semiconductor layer; a first dielectric layer surrounding the extension of conductive material and a second portion of the side of the continuous semiconductor layer; a first conductor layer surrounding the first dielectric layer; a second dielectric layer above a top surface of the first conductor layer; a third dielectric layer below the lower surface of the first conductor layer; a second conductor layer on top of the first dielectric layer; a third conductor layer on the lower surface of the third dielectric layer; A memory cell structure comprising:

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