Apparatus and method for single-pass access of ECC information, metadata information, or a combination thereof

Abstract

An apparatus, system, and method for single-pass access of ECC information, metadata information, or a combination thereof. A memory array includes several column planes and a spare column plane. The memory device can be set to a 4x single-pass operating mode. In this mode, the memory can store data in selected ones of the column planes and metadata can be stored in the spare column plane. An error correction code circuit (ECC) can store parity bits associated with the data and metadata in unselected ones of the column planes. In this manner, the data, metadata, and parity can be accessed as part of a single access of the memory array.

Description

[Technical Field]

[0001] Cross-reference to related applications This application claims the benefit of U.S. Provisional Application No. 63 / 383,871, filed November 15, 2022, which is incorporated by reference herein in its entirety and for all purposes.

[0002] The present disclosure relates generally to semiconductor devices, and more particularly to semiconductor memory devices. In particular, the present disclosure relates to volatile memories such as dynamic random access memories (DRAMs). Information may be stored in individual memory cells of the memory as physical signals (e.g., charges on capacitive elements). During an access operation, an access command may be received along with address information specifying which memory cell should be accessed. [Background technology]

[0003] There is growing interest in enabling memories to store information in an array associated with data. For example, error correction information and / or metadata may be stored in an array with its associated data. There may be a need to ensure that such information can be accessed along with the designated data without unduly impacting device performance. Summary of the Invention

[0004] In at least one aspect, the present disclosure relates to an apparatus including a first data column plane including first and second bit lines, a second data column plane including third and fourth bit lines, and a spare column plane including fifth and sixth bit lines. The apparatus also includes a column decoder that activates the first, fourth, and fifth bit lines as part of an access operation, and an error correction code (ECC) circuit that accesses the data bits along the first bit line, the metadata bits along the fifth bit line, and the parity bits along the fourth bit line as part of the access operation.

[0005] The column decoder can activate the second bit line, the third bit line, and the fifth bit line as part of the second access operation, and the ECC circuit can access the data along the third bit line, the parity bit along the second bit line, and the metadata along the sixth bit line as part of the second access operation. The column decoder can selectively activate the bit lines based on a received column address, the column address including a column plane select bit that specifies whether the data is stored in the first data column plane or the second data column plane.

[0006] The device may include an input / output circuit that receives data and metadata from the ECC circuit when the access operation is a read operation and provides the data and metadata to the ECC circuit when the access operation is a write operation. The ECC circuit may locate and correct errors in the data and metadata based on the metadata and parity of the data when the access operation is a read operation.

[0007] The parity bits stored along the second bit lines may be associated with the data bits stored along the third bit lines, and the data bits along the first bit lines may be associated with the parity bits stored along the fourth bit lines. In response to a column address received as part of the access operation, the column decoder may provide a column select signal with a first value to the first data column plane, a second column select signal with a second value to the second data column plane, and a third column select signal with the first value to the spare column plane.

[0008] In at least one aspect, the present disclosure relates to an apparatus including a memory bank and a column decoder. The memory bank includes a first plurality of column planes, a second plurality of column planes, and a spare column plane. The column decoder selects one of the first or second plurality of column planes based on a column address received as part of an access operation, and as part of the access operation, data bits are accessed in the selected one of the first or second plurality of column planes, parity bits are accessed in the unselected one of the first or second plurality of column planes, and metadata bits are accessed in the spare column plane.

[0009] The device may include an error correction code (ECC) circuit that, when the access operation is a read operation, locates and corrects errors in the data bits and metadata bits based on the parity bits. The ECC circuit may implement single error correct double error detect (SECDED). The column address may include a column plane select bit, and the first plurality of column planes or the second plurality of column planes may be selected based on the column plane select bit. Multiple bits may be accessed from a spare column plane, and the column decoder may select the first or second half of the multiple bits as metadata bits.

[0010] The device may include a first plurality of local input / output (LIO) lines coupled to a first plurality of column planes and a second plurality of LIO lines coupled to a second plurality of column planes. The column decoder may activate, as part of an access operation, all of the first or second plurality of LIO lines coupled to selected ones of the first or second plurality of column planes and less than all of the first or second plurality of LIO lines coupled to unselected ones of the first or second plurality of column planes. The device may be a memory device operating in 4x mode.

[0011] In at least one aspect, the present disclosure may relate to a method that includes receiving a column address as part of an access operation; selecting a first portion of a plurality of column planes based on the column address; accessing data bits from columns in the first portion of the plurality of column planes as part of the access operation; accessing parity bits from columns in column planes that are not in the first portion as part of the access operation; and accessing metadata bits from a spare column plane as part of the access operation.

[0012] The method may also include locating errors, correcting errors, or a combination thereof, in the data bits and metadata bits based on the parity bits in an error correction code (ECC) circuit. The method may include performing single error correct double error detect (SECDED) in the ECC circuit. The method may include accessing a set of bits from a spare column plane and selecting half of the set of bits as metadata bits based on the column address.

[0013] The method can include selecting a first half of the plurality of column planes as the first portion and selecting a column plane in a second half of the plurality of column planes as a column plane that is not in the first portion. The method can include receiving a second column address as part of a second access operation, selecting a second half of the plurality of column planes based on the second column address, accessing second data bits from the second half as part of the second access operation, accessing parity bits from a column in the first half as part of the second access operation, and accessing metadata bits from a spare column plane as part of the second access operation. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 is a block diagram of a semiconductor device according to an embodiment of the present disclosure. [Figure 2] FIG. 1 is a block diagram of a memory device according to some embodiments of the present disclosure. [Figure 3] FIG. 1 is a block diagram illustrating an example of a memory read operation according to some example embodiments of the present disclosure. [Figure 4] FIG. 1 is a schematic diagram of a portion of a memory bank according to some embodiments of the present disclosure. [Figure 5] 1 is a flowchart of a method according to some embodiments of the present disclosure. [Figure 6] FIG. 10 is a timing diagram of a mode register write operation according to some embodiments of the present disclosure. [Figure 7] 1 is a flowchart of a method according to some embodiments of the present disclosure. [Figure 8] 1 is a flowchart of a method according to some embodiments of the present disclosure. [Figure 9] 1 is a flowchart of a method according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0015] The following descriptions of specific embodiments are merely exemplary in nature and are in no way intended to limit the scope of the present disclosure or its application or uses. In the following detailed description of embodiments of the present system and method, reference is made to the accompanying drawings, which form a part hereof, and which show by way of illustration specific embodiments in which the described systems and methods may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the presently disclosed systems and methods, it being understood that other embodiments may be utilized and that structural and logical changes may be made without departing from the spirit and scope of the present disclosure. Moreover, for the sake of clarity, detailed descriptions of specific features will not be discussed when these would be apparent to those skilled in the art so as not to obscure the description of the embodiments of the present disclosure. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present disclosure is defined only by the appended claims.

[0016] A memory array may generally include several memory cells arranged at the intersections of word lines (rows) and bit / digit lines (columns). The columns may be grouped together into column planes, and a column select (CS) signal may be used to select a set of columns in each of the active column planes to provide data. When an access command is received, the memory may pre-fetch a code word (e.g., several bits of data) along with one or more associated bits from the memory and replace the pre-fetched data with new data (e.g., as part of a write operation) or remove the pre-fetched data from the memory device (e.g., as part of a read operation). Some memory modes may include removing less than all of the pre-fetched data from the memory device. For example, in conventional memory devices, in a particular mode, half of the pre-fetched data may be removed from the device, and the rest may be ignored.

[0017] The memory device may store additional information associated with each codeword. For example, the additional information may include parity bits used as part of an error correction scheme, metadata containing information about the data codeword (or being part of information about a larger set of data that includes the codeword), or a combination thereof. Nevertheless, the maximum number of bits that can be retrieved as part of a single access pass may be limited by the architecture of the memory, and this number may generally be based on the maximum number of data bits in a codeword plus a few additional bits (e.g., 128 data bits + 8 additional bits).

[0018] As used herein, the term data can refer to any bit of information that the controller wants to store and / or retrieve from memory. The term metadata can refer to any bit of information about data that the controller writes to and / or receives from memory. For example, metadata can be information generated by the controller, such as information about the data, information about how or where the data is stored in memory, information about how many errors were detected in the data, etc. Data and metadata together represent information written to memory by the controller and then further read from memory by the controller; data and metadata differ in content and how they were generated in that metadata is based on information about the data. The term parity can refer to any bit generated by the memory's error correction circuitry based on data, metadata, or a combination thereof. Parity can generally remain in memory. In some embodiments, the amount of data and / or metadata retrieved as part of a single access operation can represent a set of bits that is a larger piece of information. For example, metadata bits (e.g., 4 bits) retrieved as part of a single access operation may have no meaning on their own, but may have meaning when combined with sets of metadata bits retrieved as part of other access operations (e.g., to other memory arrays and / or to the same array at different times).

[0019] Some memories may include a set of data column planes and a spare column plane storing additional information. Nevertheless, it may be desirable to include more bits of additional information than can be retrieved from the spare column plane for various uses (e.g., including parity bits and metadata, including more parity bits, etc.). Some memory devices may use a "two-pass" architecture, where at least some of the additional bits are first retrieved and stored, and then a second access pass retrieves the codeword data bits. Nevertheless, this may incur a penalty in the latency of any given access operation. There may be a need for one-pass or single-pass storage of the expanded additional information, such that the codeword and additional bits are retrieved as part of a single access pass to the memory array.

[0020] This disclosure is interested in apparatus, systems, and methods for single-pass access of ECC information, metadata information, or a combination thereof, along with an associated codeword. Some memory devices can operate in a mode in which less than all of the data bits that can be pre-fetched are removed from the device. For example, a memory device may pre-fetch 128 data bits as part of a codeword in 8x or 16x mode, while in 4x memory mode a 64-bit codeword is provided at the device's data terminal. In 4x memory mode, the data bits of the codeword are stored in some, but not all, of the data column planes (e.g., half of the column planes). Which half of the data column planes is selected may be based on a column address. Additional bits associated with the data (e.g., parity bits and / or metadata bits) may be stored in both a spare column plane and also in data column planes not selected by the column address as part of the current access.

[0021] According to some embodiments of the present disclosure, an example memory device may include a set of data column planes and a spare column plane. The memory may be set in a mode in which metadata is stored along with its associated data. When an access operation is performed, column select signals with a first value are provided to columns in a first portion of the data column planes and to the spare column plane, and column select signals with a second value are provided to one or more columns not in the first portion of the data column planes. The memory may store data in the first portion of the data column planes, metadata in the spare column plane, and error correction parity bits in accessed columns not in the first portion of the data column planes. In this manner, data, metadata, and ECC information for a codeword may be pre-fetched together as part of a single access pass without pre-fetching additional data bits.

[0022] In some embodiments, a mode register may be used to switch the behavior of the memory device. For example, when metadata is enabled, the memory may have a first 4x operating mode (e.g., a two-pass 4x operating mode), in which, as part of an access operation, the memory stores data bits from a first portion of the data column planes and a second portion of the data column planes, and pre-fetches ECC parity information from a spare column plane. In this two-pass 4x operating mode, the memory's ECC circuitry may correct errors in the pre-fetched data bits based on the pre-fetched parity bits, and then remove half of the corrected data bits (e.g., the corrected bits from the first portion) from the memory. In a second operating mode (e.g., a one-pass 4x operating mode), as part of an access operation, the memory pre-fetches data bits from a first portion of the data column planes and ECC parity bits from column planes in the second portion of the data column planes, and pre-fetches metadata bits from a spare column plane. The ECC circuitry corrects errors in the data and metadata based on the parity bits, and the corrected data and metadata are removed from the device. Thus, fewer bits may be pre-fetched and processed by the ECC in the second mode than in the first mode. The memory may also have a metadata-disabled mode, which may be similar in operation to the two-pass mode, except that only a single pass is performed because metadata is not stored or accessed.

[0023] 1 is a block diagram of a semiconductor device according to an embodiment of the present disclosure. The semiconductor device 100 may be a semiconductor memory device, such as a DRAM device, integrated on a single semiconductor chip. The device may be operated by a controller 150, such as a processor.

[0024] Semiconductor device 100 includes a memory array 118. Memory array 118 is shown to include multiple memory banks. In the embodiment of FIG. 1, memory array 118 is shown to include eight memory banks, BANK0 through BANK7. More or fewer banks may be included in memory array 118 in other embodiments. As described in more detail herein, each bank may be further divided into two or more sub-banks. Although embodiments in which each bank includes two sub-banks are generally described herein, other embodiments may include more sub-banks per bank.

[0025] Each memory sub-bank includes a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC arranged at intersections of the plurality of word lines WL and the plurality of bit lines BL. Selection of the word lines WL is performed by a row decoder 108, and selection of the bit lines BL is performed by a column decoder 110. In the embodiment of FIG. 1, the row decoder 108 includes a respective row decoder for each memory bank, and the column decoder 110 includes a respective column decoder for each memory bank. In some embodiments, components that are repeated for each bank, such as row and column decoders and refresh control circuitry 116, may also include components that are repeated for each sub-bank. For example, there may be a refresh control circuitry 116 for each sub-bank.

[0026] The bit lines BL are coupled to respective sense amplifiers (SAMP). Read data from the bit lines BL is amplified by the sense amplifiers SAMP and transferred to the ECC circuit 120 via local data lines (LIO), transfer gates (TG), and global data lines (GIO). Conversely, write data output from the ECC circuit 120 is transferred to the sense amplifiers SAMP via complementary main data lines GIO, transfer gates TG, and complementary local data lines LIO, and written in the memory cells MC coupled to the bit lines BL.

[0027] The semiconductor device 100 may employ a number of external terminals, such as solder pads, including a command and address (C / A) terminal coupled to a command and address bus for receiving commands and addresses, a clock terminal for receiving clocks CK and / CK, a data terminal DQ coupled to a data bus for providing data, and power supply terminals for receiving power supply potentials VDD, VSS, VDDQ, and VSSQ.

[0028] The clock terminals are supplied with external clocks CK and / CK, which are provided to the input circuit 112. The external clocks may be complementary. The input circuit 112 generates an internal clock ICLK based on the CK and / CK clocks. The ICLK clock is provided to the command decoder 106 and the internal clock generator 114. The internal clock generator 114 provides various internal clocks LCLK based on the ICLK clock. The LCLK clock may be used for timing operations of various internal circuits. The internal data clock LCLK is provided to the input / output circuit 122 to time the operation of circuits included therein, for example, to a data receiver to time the receipt of write data. The input / output circuit 122 may include several interface connections, each of which may be couplable to one of the DQ pads (e.g., solder pads that may serve as external connections to the device 100).

[0029] A memory address may be supplied to the C / A terminal. The memory address supplied to the C / A terminal is transferred to the address decoder 104 via the command / address input circuit 102. The address decoder 104 receives the address and supplies a decoded row address XADD to the row decoder 108 and a decoded column address YADD to the column decoder 110. The decoded row address XADD may be used to determine which row should be opened so that data along a bit line can be read along the bit line. The column decoder 110 may provide a column select signal CS, which may be used to determine which sense amplifier provides data to the LIO. The address decoder 104 may also provide a decoded bank address BADD, which may indicate a bank of the memory array 118 that includes the decoded row address XADD and column address YADD.

[0030] Commands may be supplied to the C / A terminal. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing memory, such as read commands for performing read operations and write commands for performing write operations, and other commands and operations. An access command may be associated with one or more row addresses XADD, column addresses YADD, and bank addresses BADD to indicate the memory cells to be accessed.

[0031] Commands may be provided as internal command signals to command decoder 106 via command / address input circuit 102. Command decoder 106 includes circuitry that decodes the internal command signals to generate various internal signals and commands for performing operations. For example, command decoder 106 may provide signals that indicate whether data is to be read, written, etc.

[0032] Device 100 can receive an access command that is a read command. When the read command is received and a bank address, row address, and column address are supplied in a timely manner, data to be read is read from memory cells in memory array 118 corresponding to the row address and column address. The read command is received by command decoder 106, which provides an internal command that results in data read from memory array 118 being provided to ECC circuit 120. ECC circuit 120 receives data bits, metadata bits, and parity bits from the array and detects and / or corrects errors in the data and metadata bits. The correct read data is provided along a data bus and output to the outside from data terminals DQ via input / output circuit 122.

[0033] The device 100 can receive an access command that is a write command. When the write command is received and a bank address, a row address, and a column address are provided in a timely manner, write data provided to the data terminals DQ is provided along the data bus and written to memory cells in the memory array 118 corresponding to the row address and column address. The write command is received by the command decoder 106, which provides an internal command such that the write data, along with metadata, is received by a data receiver in the input / output circuit 122. The write data and metadata are provided to the ECC circuit 120 via the input / output circuit 122. The ECC circuit generates parity bits based on the received data and metadata, and the data, metadata, and parity are provided by the ECC circuit 120 to the memory array 118 to be written to memory cells MC.

[0034] Device 100 includes refresh control circuits 116 associated with each bank of memory array 118. Each refresh control circuit 116 can determine when to perform a refresh operation on the associated bank. Refresh control circuit 116 provides a refresh address RXADD (along with one or more refresh signals not shown in FIG. 1 ). Row decoder 108 performs the refresh operation on one or more word lines associated with RXADD. Refresh control circuit 116 can perform multiple types of refresh operations, and the refresh operation can determine other details, such as how address RXADD is generated and how many word lines are associated with address RXADD.

[0035] ECC circuit 120 can detect and / or correct errors in accessed data. As part of a write operation, ECC circuit 120 can receive bits from IO circuit 122 and generate parity bits based on the received bits. The received bits and parity bits are written to memory array 118. During an example read operation, ECC circuit 120 receives a set of bits and their associated parity bits from array 118 and uses them to locate and / or correct errors. For example, a single error correction (SEC) scheme locates and detects up to one bit of error. A single error correction double error detection (SECDED) scheme corrects up to one bit of error, but two errors may be detected (however, the bits causing these errors are not individually located and therefore cannot be corrected). ECC circuit 120 can correct the information and then provide the corrected information (and / or the detected error indicated by the signal) to IO circuit 122. Parity bits may generally not be provided to IO circuitry 122 .

[0036] Mode register 130 can contain various settings and can be used to enable a metadata mode for memory 100. When metadata is enabled, device 100 can store metadata associated with data. For example, as part of a write operation, controller 150 can provide data with its associated metadata, and as part of a read operation, it can receive data and its associated metadata. In some embodiments, ECC circuit 120 can include metadata bits as part of the error correction process; in some embodiments, metadata bits may be excluded. In some embodiments, whether metadata is included in the ECC process may be a memory setting (e.g., in mode register 130). The metadata may include information about the associated data.

[0037] The memory 100 can be operated in various modes based on the number of DQ pads used. The mode can determine both how many DQ pads the controller 150 expects to send / receive data along as well as the format and / or number of bits the controller 150 expects as part of a single access command. For example, the memory can have 16 physical DQ pads. In 16x mode, all 16 DQ pads are used. In 8x mode, eight of the DQ pads are used, and in 4x mode, four of the DQ pads are used. The mode can also determine the burst length on each DQ terminal as part of the DQ operation. The burst length represents the number of consecutive bits on each DQ terminal during an access operation.

[0038] For example, in 8x mode, the memory can send or receive 128 data bits along eight DQ terminals, each with a burst length of 16. In an example 4x mode, a burst length of 16 may also be used, so 64 bits may be sent or received as part of an access operation. This disclosure is generally described with respect to an example embodiment in which, as part of 4x mode, a 64 data bit codeword is accessed along with 4 bits of metadata, and ECC circuit 120 uses 8 bits of ECC parity. Other example embodiments may use different numbers of data, metadata, and parity.

[0039] The device 100 includes a mode register 130 that can be used to control various optional modes of the memory. For example, the mode register 130 can include a setting that determines whether metadata is used. If metadata is enabled, the mode register 130 can set a first quad operating mode (e.g., a two-pass quad operating mode) or a second quad operating mode (e.g., a one-pass quad operating mode). The controller 150 can perform a mode register write (MRW) operation to set a value in the mode register 130 or can perform a mode register read (MRR) operation to check what the value in the mode register 130 is. The mode register 130 includes several registers that can each store one or more bits corresponding to a setting or piece of information about the memory.

[0040] The controller 150 can provide a command and a row and column address as part of an access operation. In a two-pass 4x mode of operation, in response to an access operation from the controller 150, the column decoder can perform a first access pass to the memory array to retrieve a first portion of information that may then be stored, and then a second access pass to the memory array to retrieve the remainder of the information to be combined with the stored information. For example, during a read operation, the controller 150 can provide an address and a single read command, in response to which the memory 100 can retrieve four metadata bits as part of a first pass, and then the remaining 64 data bits and eight parity bits as part of a second pass. In a single-pass 4x mode of operation, in response to the address and read command, the memory can retrieve data, metadata, and parity as part of a single access pass to the memory array.

[0041] The power supply terminals are supplied with power supply potentials VDD and VSS. The power supply potentials VDD and VSS are supplied to an internal voltage generation circuit 124. The internal voltage generation circuit 124 generates various internal potentials VARY and the like based on the power supply potentials VDD and VSS supplied to the power supply terminals.

[0042] Power supply potentials VDDQ and VSSQ are also supplied to the power supply terminals. The power supply potentials VDDQ and VSSQ are supplied to the input / output circuit 122. In one embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminals may be the same potential as the power supply potentials VDD and VSS supplied to the power supply terminals. In another embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminals may be different potentials from the power supply potentials VDD and VSS supplied to the power supply terminals. The power supply potentials VDDQ and VSSQ supplied to the power supply terminals are used for the input / output circuit 122 to prevent power supply noise generated by the input / output circuit 122 from propagating to other circuit blocks.

[0043] 2 is a block diagram of a memory device according to some embodiments of the present disclosure. Memory device 200 may, in some embodiments, represent a portion of memory device 100 of FIG. 1. The view of FIG. 2 shows portions of memory arrays 210-214 and 220-224, which may be part of a memory bank (e.g., 118 of FIG. 1), along with selected circuitry used in the data path, such as ECC circuitry 232 (e.g., 120 of FIG. 1) and IO circuitry 234 (e.g., 122 of FIG. 1). For clarity, certain circuits and signals have been omitted from the view of FIG. 2.

[0044] The memory device 200 is organized into several column planes 210-214. Each column plane represents a portion of a memory bank. Each column plane 210-214 includes several memory cells at the intersections of word lines WL and bit lines. The bit lines may be grouped together into sets that are activated by the value of a CS signal. For clarity, only a single vertical line is used to represent the bit lines of each column select set, but there may be multiple columns accessed by this value of CS. For example, each line may represent eight bit lines that are all commonly accessed by the value of CS. As used herein, a "value" of CS may represent a decoded signal provided to a set of bit lines. Thus, a first value may represent the first value of a multi-bit CS signal or, after decoding, the signal line associated with this value that is active. Word lines may extend across multiple column planes 210-214.

[0045] The memory 200 includes a set of data column planes 210 and a spare column plane 212. The spare column plane 212 may be used to store additional information, such as error correction parity bits or metadata bits.

[0046] In some embodiments, memory 200 may also include an optional global column redundancy (GCR) column plane 214. In some embodiments, GCR plane 214 may have fewer memory cells (e.g., fewer column select groups) than data column plane 210. GCR CP 214 includes some redundant columns that may be used as part of a repair operation. If the value of the CS signal identifies one of data column planes 210 as including a defective memory cell, the memory may be remapped such that the data that would have been stored in this column plane for this value of CS is instead stored in GCR CP 214.

[0047] For example, in some embodiments, memory 210 may include 16 data column planes 210(0) through 210(15). Each of these data column planes 210 includes 64 sets of bit lines that are activated by the value of a column select signal, with each set of bit lines including 8 bit lines. Thus, when a word line is opened in response to a row address and a column select signal is provided to each of the 16 column planes, 8 bits are accessed from each of the 16 column planes, totaling 128 bits. A column select signal is also provided to spare column plane 212, but this column select signal may be a different value than that provided to data column plane 210 as an additional 8 bits. If a repair is performed, GCR CP 214 may be accessed similarly, and the value on the GCR LIO may be used while ignoring the LIO of the column plane that GCR CP 214 is replacing. Therefore, the maximum number of bits that can be retrieved as part of the access path is 128 bits from the data column plane 210 (with 8 bits substituted from the GCR CP 214 if there was a repair), along with 8 additional bits from the spare CP 212.

[0048] The memory may be operated in 4x mode, with less than the maximum number of bits provided to an external device. A column address may indicate which of the column planes 210 is used to store data accessed in 4x mode. For example, a CP select bit in the column address (e.g., the 10th bit of column address C10) may select data from an even column plane or an odd column plane, or from the first half of a column plane or the second half of a column plane. Other schemes may be used in other example embodiments.

[0049] A mode register (e.g., 130 in FIG. 1), not shown in FIG. 2, may be used to enable metadata on the device. When metadata is enabled, the mode register may have a setting that places the memory device in a first 4x operating mode (2-pass mode) or a second 4x operating mode (1-pass mode). In both operating modes, all information received from / sent to an external device is the same. For example, the memory's controller (e.g., 150 in FIG. 1) may expect 64 data bits and 4 metadata bits per access of memory 200 in either mode, but the operating mode can determine how the memory array is accessed, how many access paths are used to fetch data (e.g., how quickly the data is accessed), the power consumption of the access operation, the size of the pre-fetched information, the behavior of ECC circuit 232, and which information is stored in which column plane. In a first 4x operating mode, two access paths are used to retrieve data (e.g., metadata from a first path and data and ECC bits from a second path), while in a second 4x operating mode, a single path is used to retrieve information.

[0050] In an example read command, in a first 4x operation mode, a column, row, and bank address are received from the controller. A row decoder (e.g., 108 in FIG. 1 ) opens a selected word line based on the row address. The column decoder generates a column select signal based on the column address. As part of a first access pass, a column select signal is provided to one of the column planes 210 selected by a CP select bit in the column address (e.g., C10). A set of metadata (e.g., 128 metadata bits) partially associated with the current access operation is retrieved from the column plane 210 along with a parity bit (associated with this set of metadata) from the spare column plane 212. The ECC circuit 232 can check and correct errors based on the 128 metadata bits plus the 8 associated parity bits. The metadata bits (e.g., 4 metadata bits) in this set associated with the current access operation (e.g., as indicated by the column address) are stored in a buffer (not shown) as part of the IO circuit 234. As part of the second access path, column select signals are provided to all of the data column planes 210, and spare column select signals are provided to the spare column planes. The column select signals and spare column select signals have the same values ​​as each other, and do not necessarily have the same values ​​as the column select signals provided as part of the first access path. As part of the second access path, data bits are retrieved from the data column planes 210, and parity bits are retrieved from the spare column planes 212. The ECC circuit 232 uses the retrieved data and parity bits to locate and / or correct errors in the data. Half of the retrieved (corrected) data bits are then combined with the previously retrieved metadata in the IO circuit 234, which removes the data and metadata from the device at the DQ pads.

[0051] An example write command may be generally similar in the first 4x mode of operation. The controller provides data and metadata bits along with the command and address. The metadata is stored in a buffer in IO circuit 234. Data is pre-fetched from the array, and half of this data is replaced with new write data. ECC circuit 232 then generates new parity from the updated set of data, and the data is written to data column plane 210. Similarly, in a second access pass, a set of metadata is retrieved, allowing the metadata to be added to the set of metadata, and ECC circuit 232 can generate new parity associated with the updated set of metadata. The updated set of metadata and parity is then written to the array. In the second access pass, meanwhile, parity is written to spare column plane 212.

[0052] There may be a latency time tCCD_L_WR that is part of the memory's design specifications. The time tCCD_L_WR represents the minimum time that must elapse before a bank within the same bank group can be accessed again. The time tCCD_L_WR represents the long inter-column (or command) delay period for writes, which may also be a memory specification. During write operations, a two-pass mode of operation can incur a latency of twice tCCD_L_WR because each access pass requires a delay of tCCD_L_WR before the bank can be accessed again. One tCCD_L_WR is incurred from adding an extra pass to overwrite the metadata, and an additional tCCD_L_WR is incurred because, to generate parity bits based on all of the pre-fetched data in this mode, half of the unwritten pre-fetched data bits must still be pre-fetched (e.g., read) so that they can be added to the write bits received from the controller.

[0053] The second 4x mode of operation may be a "one-pass" mode in which fewer data bits are pre-fetched and the location of the metadata and parity is changed compared to the first 4x mode of operation. Instead of pre-fetching additional data bits that are not part of the access operation as in the first 4x mode of operation, in the second 4x mode of operation, only the accessed data bits are pre-fetched.

[0054] In an example read command, in a second 4x mode of operation, a column, row, and bank address are received from the controller. A row decoder (e.g., 108 in FIG. 1) opens a selected word line based on the row address. The column decoder generates a column select signal based on the column address. As part of a single access pass, a column select value with a first value is provided to a first portion of the column planes, and a column select signal with a second value is provided to at least one column plane not in the first portion. Along with this, a column select signal (which may or may not have the same value of the first or second column select signal) is provided to the spare column plane 212. Which columns are in the first portion may be based on a CP select bit in the column address (e.g., C10). The data column planes in the first portion provide data bits, the data column planes not in the first portion provide ECC parity bits, and the spare column plane 212 provides metadata bits. During the second 4x mode of operation, only a portion of column plane 210 is accessed, so only some of the data bits provided to / removed from the device are accessed (along with the metadata and ECC bits). ECC circuit 232 receives the data and metadata along with parity bits and locates and / or corrects any errors in the data and metadata. The (corrected) data and (corrected) metadata are provided to IO circuit 234, which provides the data and metadata to the DQ terminals.

[0055] In an example write command, in the second 4x operating mode, a column, row, and bank address are received from the controller along with data and metadata. The data and metadata are provided to the ECC circuit through the IO circuit, which generates parity bits based on the data and metadata and then writes the data, metadata, and parity to the column plane, which is accessed in a manner similar to that described for the read operation. In some embodiments, the number of bits retrieved when a column is accessed may be greater than the specified number of metadata bits. In such an embodiment, during a write operation, metadata may be pre-fetched (e.g., read), and then new metadata overwrites some of the bits. This may incur a tCCD_L_WR penalty. Nevertheless, the single-pass mode may have reduced latency because only a single extra tCCD_L_WR penalty is incurred (compared to two in the two-pass 4x operating mode).

[0056] In a first (two-pass) quad mode of operation, each of the data column planes 210 stores a mixture of data and metadata, with ECC parity bits stored in the spare column plane 212. In a second (one-pass) quad mode of operation, each of the data column planes 210 stores a mixture of data and ECC parity bits, with metadata stored in the spare column plane 212. In a single-pass mode, the ECC circuit 232 locates and corrects errors in both the data and metadata (e.g., because parity is based on both the data and the metadata). In a two-pass mode, the ECC circuit 232 locates and corrects errors in the metadata during the first pass. During the second pass, the ECC circuit 232 corrects only the data, since metadata is not used as parity in the second pass. In other words, in a one-pass mode, the parity bits are based on both the data and the metadata, while in a two-pass mode, there are separate parity bits for the data and the metadata.

[0057] Additionally, accesses in the one-pass 4x mode of operation may draw less power than accesses in the two-pass 4x mode of operation. In the two-pass mode of operation, all of the column planes are activated, and data read from their sense amplifiers 220 is sent along the LIOs to the ECC circuit 232, along with the sense amplifiers 222 and LIOs associated with the spare column plane 212 (and, if there is a repair, the sense amplifiers 224 and LIOs of the GCR 214). Nevertheless, in the one-pass 4x mode of operation, only a selected portion (e.g., half) of the data column planes 210 are activated, thus reducing all of the data LIOs by each sense amplifier 220. Similarly, various switches, signal lines, etc. may not be used in every access in the one-pass 4x mode of operation. Therefore, less power is drawn in the 4x mode of operation.

[0058] FIG. 3 is a block diagram illustrating an example of a memory read operation according to some example embodiments of the present disclosure. FIG. 3 shows a view of a memory array 300 showing a representation of which portions of the memory array are reserved for different types of information. The blocks shown in FIG. 3 represent a portion of the memory array but do not necessarily represent the spatial layout of where information is stored in the memory array. Memory array 300, in some embodiments, may be an implementation of memory array 118 of FIG. 1 and / or column planes 210-214 of FIG. 2 in the second 4x mode of operation as described herein.

[0059] 3 is depicted with respect to an example embodiment in which there are 16 data column planes, each providing 8 bits when activated by a column select signal, and a spare column plane that also provides 8 bits when activated by its respective column select value. The example memory is operated in 4x mode, in which 64 data bits and 4 metadata bits are accessed by a controller (e.g., 150 in FIG. 1). The CP select bit C10 of the column address is used to determine which column plane provides the data. Bits of the column address can further specify which bits (e.g., which of the retrieved metadata bits) are provided.

[0060] During an example read operation, when C10 is in a low logic state (e.g., C10=0), eight column planes are accessed in a first portion 301 of the memory array 300, each providing eight bits for a total of 64 data bits. A second column select is also provided to a column plane in a second portion 302. This second column select signal is provided to a single column plane, retrieving a total of eight ECC parity bits. A column select signal is also provided to a spare column plane 308, which provides eight metadata bits. However, four of these bits may be irrelevant to the current read data and therefore may not be removed from the device. An ECC circuit 310 (e.g., 232 in FIG. 2) receives the 64 data bits along with four metadata bits and eight parity bits and provides the 64 data bits along with the four metadata bits. Which of the eight retrieved bits from the spare column plane are provided as the four metadata bits can be based on C10 or another column address bit, such as CA9, which should represent the data selected from either the even or odd sense amplifier stripes.

[0061] In another example read operation, if C10 has the opposite value (e.g., C10=1), 64 data bits can be accessed from the second portion 302, 8 parity bits from the first portion 301, and metadata bits from the spare column plane 308.

[0062] In the example write operation, eight metadata bits are accessed, but only four are actually specified by the access operation, so four spare metadata bits can be protected. For example, memory 300 can employ a read-modify-write (or RMW) strategy in which all eight metadata bits are pre-fetched, then four of these bits are changed (if necessary) based on the newly written metadata, and then all eight bits are written back. This can protect the spare four bits (and therefore not be inadvertently changed by a direct write operation because data has not been written to these cells) at the expense of extra latency (e.g., tCCD_L_WR).

[0063] The blocks in the first and second portions 301 and 302 represent portions of these column planes that may be reserved for different storage purposes and do not necessarily represent the physical layout of where information is stored in the portions of the column planes or the spatial relationship of the column planes in each portion relative to each other. For example, the first portion could represent even column planes, while the second portion represents odd column planes, and the columns reserved for storing ECC bits could be distributed throughout the data column planes. In the example of FIG. 3, because 8 bits of ECC are required for every 64 bits of data, each portion 301 and 302 could have 87.5% of its total memory space used for data and 12.5% ​​used for ECC and metadata bits. In other words, from the controller's perspective, only 87.5% of the memory array can be addressed because the remaining portion is reserved for metadata that is expected to occur with the data. In a two-pass 4x operating mode, more memory array space may be available because metadata is stored in the data array and there are 4 bits of metadata for every 64 bits of data. Thus, in a two-pass 4x mode of operation, there may be 93.75% of the array set aside for data and 6.25% for metadata. When metadata is disabled, 100% of the array space may be used for data. The controller may address different addressable portions of the memory array based on generated column addresses associated with different ranges of CS values.

[0064] Table 1 summarizes the different behaviors in two different 4x modes with metadata according to some embodiments of the present disclosure. [Table 1]

[0065] In Table 1, the notations d, p, and md are used to represent data bits, parity bits, and metadata bits, respectively. For example, the first row uses the notation 8p+128md / 128d+8p to represent that in two-pass mode, 128 bits are fetched along with 8 parity bits in the first pass (four of which are metadata bits), and then 128 data bits and 8 parity bits are fetched in the second pass, while the notation 64d+4md+8p is used to represent pre-fetching 64 data bits, 4 metadata bits, and 8 parity bits as part of a single access pass. The mode register can also have a setting that disables metadata. When metadata is not used, the device can function similarly to the "two-pass" mode, except that only a single pass is required to pre-fetch the 128 data bits and 8 parity bits.

[0066] In a two-pass quad mode of operation (and in a metadata-disabled mode), 128 metadata bits (four of which are associated with data access) and eight parity bits associated with these 128 metadata bits are used by ECC circuit 232 in the first pass, while 128 bits of data and eight parity bits are used by ECC circuit 232 in the second pass. In a one-pass quad mode of operation, 64 bits of data, four bits of metadata, and eight bits of parity are used by ECC circuit 232. In a two-pass quad mode, ECC circuit 232 can implement the SEC scheme separately for both the 128 metadata bits and the 128 data bits, while in a one-pass quad mode, the SECDED scheme can be used jointly for both data and metadata. In other words, in a two-pass mode, each set of parity may correspond to data or metadata, while in a one-pass mode, parity corresponds to data and metadata jointly. More protection may be provided because a greater number of parities for other bits are used in one-pass mode. Additionally, in one-pass mode, the metadata may also be checked by the ECC circuitry, while in two-pass mode, the metadata may not be protected by the ECC circuitry of the second pass.

[0067] In a two-pass 4x operating mode, there may be an extra latency of 2x tCCD_L_WR because both access paths (metadata and pre-fetched data) may need to undergo an RMW cycle. In a one-pass 4x operating mode, only a single extra tCCD_L_WR is incurred. A metadata-disabled mode can also only incur an extra tCCD_L_WR because the amount of pre-fetched data is greater than the amount to be written, so an RMW is used to pre-fetch the complete set of data and then overwrite selected bits.

[0068] The one-pass 4x operating mode can draw less power than the two-pass 4x operating mode (or metadata disabled mode). In one-pass mode, the CS signal may be provided to only a selected half of the column planes (based on C10). Thus, only half of the column planes need to activate their switches, drive voltages along the LIO lines, etc. This can reduce power draw from a single-access operation. For example, in two-pass mode, 17 different CS signals (16 data column planes and 1 spare column plane) and their associated LIO / GIO, etc. are asserted, while in one-pass mode, 9 different CS signals and their associated LIO / GIO, etc. are asserted (17 column planes for data and ECC when metadata is disabled).

[0069] 4 is a schematic diagram of a portion of a memory bank according to some embodiments of the present disclosure. Memory bank 400 may, in some embodiments, be included in memory 100 of FIG. 1, 200 of FIG. 20, and / or 300 of FIG. 3. Memory bank 400 shows a simplified schematic view of the layout of the memory bank along with example signals that may be used to activate various columns in the column plane as part of a second 4x mode of operation (e.g., a one-pass 4x mode of operation).

[0070] 4 is depicted in terms of an example embodiment in which there are 16 data column planes, each including 64 sets of bit lines (e.g., 64 values ​​of the CS signal), each providing 8 bits of data when activated by a respective CS signal. It should be understood that this is one example implementation of the present disclosure, and that other arrangements (e.g., more or fewer CS sets per CP, more or fewer CPs per memory bank, etc.) may be used in other example embodiments.

[0071] Memory bank 400 illustrates memory organized into 16 column planes 412-448 (e.g., 210 in FIG. 2 and / or 301-302 in FIG. 3), each associated with a DQ pad 410-440. Thus, a first DQ pad 410 is associated with a column plane 412-418, a second DQ pad 420 is associated with a column plane 422-428, a third DQ pad 430 is associated with a column plane 432-438, and a fourth DQ pad is associated with a column plane 442-448. In the 4x mode of the example of FIG. 4, each of the four DQ pads 410, 420, 430, and 440 handles 16 data bits as part of an access operation, for a total of 64 data bits. In addition to the four DQ pads 410, 420, 430, and 440, memory bank 400 may also be associated with a metadata terminal 450 that may be used to send / receive metadata as part of an access operation. The metadata terminal is associated with a spare column plane 452 (e.g., 212 in FIG. 1 and / or 308 in FIG. 3). In the simplified view of FIG. 4, a single word line WL is shown, along with a global row decoder 402 that drives the word line. Similarly, only selected lines are shown as bit lines, each representing a set of bit lines activated by a common CS signal in this CP. When activated, the bit lines are coupled to respective LIO lines.

[0072] The memory bank 400 is organized with the cells of the memory array between two sense amplifier regions 404. The sense amplifier regions 404 may extend in the same direction as the word lines WL. Column planes 412-448 are separated by sub-word line (SWL) drivers 406. Each column plane is adjacent to one other column plane and to an SWL driver 406. For example, column plane 412 is adjacent to an SWL driver 406 on one side and to column plane 414 on the other side. Column plane 414 is adjacent to column plane 412 on a first side and to a second SWL driver 406 on the opposite side. Opposite the SWL driver 406 is another column plane 416, and so on.

[0073] Thus, each data terminal is associated with four column planes, two pairs of column planes adjacent to each other and separated from the other pairs by SWL drivers. Each pair is associated with a different value of column plane select bit C10. For example, first DQ pad 410 is associated with column planes 412 and 414, both activated by C10 at a high logic level, and with column planes 416 and 418, both activated by C10 at a low logic level. Thus, column planes 412, 414, 422, 424, 432, 434, 442, and 444 all contain data accessed when C10=1, and column planes 416, 418, 426, 428, 436, 438, 446, and 448 all contain data accessed when C10=0. Whichever set of column planes is selected by C10, one or more column planes of other sets may be used to store ECC parity bits.

[0074] FIG. 4 illustrates an example access operation in a second 4x operating mode (e.g., one-pass 4x mode). The memory device receives a column address including C10=0 and having a value decoded to a first column select signal CS0. Thus, CS0 is provided by the column decoder to column planes 416, 418, 426, 428, 436, 438, 446, and 448, with the bit lines associated with CS0 in each of these column planes each providing eight bits of data. The column decoder also provides CS0 to a spare column plane 452, from which eight bits of metadata are accessed (four of which may be selected based on the value of C10). In addition, the column decoder also generates an additional CS signal and provides it to one of the column planes not selected by the value of C10. In this example embodiment, the value CS56 is provided to column plane 444. Thus, column plane 444 provides eight bits of ECC parity. Thus, from a single access pass, 64 bits of data (8 each from column planes 416, 418, 426, 428, 436, 438, 446, and 448), 4 bits of metadata (half taken from spare column plane 452), and 8 bits of parity (from column plane 444) are accessed. Arrows are used to indicate which CS signals and which column planes are accessed as part of a single access pass.

[0075] In other words, the column decoder (e.g., 110 in FIG. 1) can activate digit lines and couple them to the LIOs for column planes 416, 418, 426, 428, 436, 438, 446, and 448. This allows column planes activated by C10=0 to represent all of the available LIOs (e.g., eight LIOs per column plane). Nevertheless, in the set of column planes associated with C10=1, the column decoder can activate less than all of the LIOs because only CS 56 in column plane 444 is coupled to an LIO. The remaining LIOs associated with column planes activated by C10=1 are unused in this access operation.

[0076] 4, a similar access may occur as part of a second access operation, where a column address is received with C10=1 but including the same decoded value of CS. In this example, the column decoder provides CS0 to column planes 412, 414, 422, 424, 432, 434, 442, and 444, as well as to spare column plane 450, while the CS56 value is provided to column plane 448. Note that the same 8 bits may be provided from spare column plane 452, but the value of C10 controls which portion of these 8 bits are provided as the four metadata bits.

[0077] The controller may have different ranges of addressable values ​​based on the mode the memory is operating in. In this example, the controller may generate column addresses associated with CS values ​​beyond the range CS0 through CS55. Yet, CS55 through CS63 may represent "unaddressable" space because the controller cannot directly access these columns (reserved for parity).

[0078] 5 is a flowchart of a method according to some embodiments of the present disclosure. Method 500 may, in some embodiments, be performed by one or more of the devices or systems described herein. For example, method 500 may be performed by memory 100 of FIG. 1, 200 of FIG. 2, 300 of FIG. 3, and / or 400 of FIG. 4.

[0079] Method 500 generally begins at box 510, which describes receiving a column address as part of an access operation. Method 500 may also include receiving a row and bank address and an access command as part of the access operation. For example, the address and command may be received along a C / A terminal of the memory, such as the C / A terminal of FIG. 1.

[0080] Box 510 may generally be followed by box 520, which describes selecting a first portion of a plurality of column planes based on a column address. Method 500 may include selecting a first half of the column planes as the first portion or selecting a second half of the column planes as the first portion. The column address may include a column plane select bit (e.g., C10) that specifies which column planes are in the first portion or not. For example, method 500 may include selecting the first half when the column plane select bit is in a first state and selecting the second half when the column plane select bit is in a second state. Method 500 may include generating a column select signal associated with the access operation with a column decoder (e.g., 110 in FIG. 1 ).

[0081] Box 520 may generally be followed by boxes 530-550, which may occur sequentially (as shown or in any order) or may occur substantially simultaneously with one another. Box 530 describes accessing data bits from columns in a first portion of a plurality of column planes as part of an access operation. Box 540 describes accessing parity bits from columns in column planes not in the first portion as part of the access operation. Box 550 describes accessing metadata bits from a spare column plane as part of the access operation.

[0082] For example, method 500 may include generating, at a column decoder, a first column select signal and providing it to a first portion of column planes, generating a second column select signal and providing it to column planes not in the first portion, and generating a third column select signal and providing it to a spare column plane. The first column select signal and the third column select signal may have the same value. The second column select signal may have a different value than the first column select signal. In an example implementation, method 500 may include accessing 64 data bits from columns in the first portion, accessing 4 metadata bits from the spare column plane, and accessing 8 parity bits from column planes not in the first portion.

[0083] In some embodiments, method 500 may include locating errors, correcting errors, or a combination thereof, in the data bits and metadata bits based on the parity bits in an ECC circuit (e.g., 120 of FIG. 1 , 232 of FIG. 2 , and / or 310 of FIG. 3 ). For example, as part of a read operation, the data, parity, and metadata are all provided to the ECC circuit. In some embodiments, method 500 may include performing SECDED error correction in the ECC circuit.

[0084] The first portion can represent a first half of the column planes, and the column planes not in the first portion can be a single column plane in a second half of the column planes. In some embodiments, method 500 can include receiving a second column address as part of a second access operation, selecting a second half of the plurality of column planes based on the second column address, accessing second data bits from the second half as part of the second access operation, accessing parity bits from columns in the first half as part of the second access operation, and accessing metadata bits from a spare column plane as part of the second access operation.

[0085] 6 is a timing diagram of a mode register write operation according to some embodiments of the present disclosure. Timing diagram 600 may represent an example of how a controller may write a value to a mode register (e.g., 130 in FIG. 1) to set the mode of a memory.

[0086] Timing diagram 600 shows clock signals CK_t / CK_c (e.g., CK and / CK in FIG. 1) along with a chip select signal. The chip select signal is used to indicate that the controller is addressing this particular memory device (e.g., chip). In FIG. 6, a higher level is used to represent that the chip select signal is active, but in some embodiments, the chip select signal may be active low. Signals along the command / address bus CA and command CMD are also shown.

[0087] Timing diagram 600 shows three MRW operations occurring in sequence at times Ta0R, Tb1R, and Tc1R. Each MRW operation involves providing an address in the mode register along with the data to be written to this register along the CA bus (shown in the box marked "valid" to indicate that the value MR address and data are being provided). Two sequential MRW commands, marked MRW-1 and MRW-2, are used to indicate that the information along the CA bus is part of an MRW operation.

[0088] 7 is a flowchart of a method according to some embodiments of the present disclosure. Method 700 may, in some embodiments, be a method of operating a memory device. For example, method 700 may be performed by a controller, such as controller 150 of FIG. 1, when operating a memory, such as 100 of FIG. 1, 200 of FIG. 2, 300 of FIG. 3, and / or 400 of FIG. 4.

[0089] Method 700 includes box 710, which describes writing a mode register value to set the memory in a first quad mode or a second quad mode. For example, the controller can perform an MRW operation similar to that described with respect to Figure 6. The MRW operation can write values ​​to one or more registers that control which quad mode the memory is in.

[0090] Box 710 may be followed by box 720, which describes writing data and metadata to the memory array. For example, method 700 may include providing an address and a write command along the CA bus, and providing data along the DQ terminals and metadata along the metadata terminals. For example, the controller may provide 64 bits of data in four 16-bit bursts and four bits of metadata (e.g., in a 4-bit burst).

[0091] Box 720 may generally be followed by box 730, which describes addressing a first percentage of the memory array in a first 4x mode of operation or a second percentage of the memory array in a second 4x mode of operation. The mode can determine what percentage of the array is used for data and what percentage is reserved for additional information. For example, as described herein with respect to FIG. 3 , when the memory is in the second (single-pass) mode of operation, more of the data array may be set aside for metadata than when the memory is in the first (two-pass) mode of operation. For example, method 700 can include storing a greater total amount of data in the memory in the first mode than in the second mode.

[0092] The method 700 can include generating column addresses associated with an addressable area of ​​a memory array. Thus, when the memory is in a first mode of operation, the controller can generate column addresses associated with a first range of CS values ​​(e.g., CS0 through CS59), and when in a second mode of operation, the controller can generate column addresses associated with a second range of CS values ​​(e.g., CS0 through CS54).

[0093] In some embodiments, method 700 may include writing an MR value to set the memory in a metadata-disabled mode and writing data (but not metadata) to the memory array. In such a mode, the controller may address a third percentage in the metadata-disabled mode. The third percentage may be 100% of the memory array. For example, when the memory is in the third mode, the controller may generate column addresses associated with a third range of CS values ​​(e.g., CS0 through CS63).

[0094] 8 is a flowchart of a method according to some embodiments of the present disclosure. Method 800 may, in some embodiments, be a method of operating a memory device. For example, method 800 may be performed by a controller, such as controller 150 of FIG. 1, when operating a memory, such as 100 of FIG. 1, 200 of FIG. 2, 300 of FIG. 3, and / or 400 of FIG. 4.

[0095] Method 800 includes box 810, which describes writing a mode register value to set the memory in a first quad mode or a second quad mode. For example, the controller can perform an MRW operation similar to that described with respect to Figure 6. The MRW operation can write values ​​to one or more registers that control which quad mode the memory is in.

[0096] Box 810 may be followed by box 820, which describes writing data and metadata to the memory array. For example, method 800 may include providing an address and a write command along the CA bus, and providing data along the DQ terminals and metadata along the metadata terminals. For example, the controller may provide 64 bits of data in four 16-bit bursts and four bits of metadata (e.g., in a 4-bit burst).

[0097] Box 820 may be followed by box 830, which describes writing data and metadata to the memory array with a first latency in a first 4x mode of operation or with a second latency in a second 4x mode of operation. The first latency may be greater than the second latency. For example, the first latency may include two additional tCCD_L_WR periods, while the second latency may include one additional tCCD_L_WR period.

[0098] 9 is a flowchart of a method according to some embodiments of the present disclosure. Method 900 may, in some embodiments, be a method of operating a memory device. For example, method 900 may be performed by a controller, such as controller 150 of FIG. 1, when operating a memory, such as 100 of FIG. 1, 200 of FIG. 2, 300 of FIG. 3, and / or 400 of FIG. 4.

[0099] Method 900 includes box 910, which describes writing a mode register value to set the memory in a one-pass quad mode of operation. For example, the controller can perform an MRW operation similar to that described with respect to Figure 6. The MRW operation can write values ​​to one or more registers that control which quad mode the memory is in.

[0100] Box 910 may be followed by box 920, which describes reading data and metadata to a memory array. For example, method 900 may include providing an address and a read command along a CA bus. Method 900 may include receiving the data and metadata along DQ terminals and one or more metadata terminals of the memory. For example, the controller may receive 64 bits of data in four 16-bit bursts and four bits of metadata (e.g., in a 4-bit burst).

[0101] Box 920 may generally be followed by box 930, which describes receiving a signal from the memory indicating double-bit error detection in the data and metadata. For example, in a one-pass quad mode of operation, the memory may perform SECDED on both the data and the metadata. If a single-bit error is detected, it may be corrected. If a double-bit error is detected, the memory may provide a signal indicating the double-bit error.

[0102] Of course, it should be recognized that any one of the examples, embodiments, or processes described herein may be combined with one or more other examples, embodiments, and / or processes, or may be separated and / or implemented among separate devices or device portions in accordance with the present systems, devices, and methods.

[0103] Finally, the above discussion is intended to be merely illustrative of the present system and should not be construed as limiting the scope of the appended claims to any particular embodiment or group of embodiments. Accordingly, while the present system has been described in particular detail with reference to exemplary embodiments, it should also be recognized that numerous modifications and alternative embodiments may be devised by those skilled in the art without departing from the broader and intended spirit and scope of the present system, as set forth in the following claims. Accordingly, the specification and drawings should be evaluated in an illustrative manner and are not intended to limit the scope of the appended claims.

Claims

1. a first data column plane including a first bit line and a second bit line; a second data column plane including a third bit line and a fourth bit line; a spare column plane including fifth and sixth bit lines; a column decoder configured to activate the first bit line, the fourth bit line, and the fifth bit line as part of an access operation; an error correction code (ECC) circuit configured to access data bits along the first bit lines, metadata bits along the fifth bit lines, and parity bits along the fourth bit lines as part of the access operation; An apparatus comprising:

2. 2. The apparatus of claim 1, wherein the column decoder is configured to activate the second bit line, the third bit line, and the fifth bit line as part of a second access operation, and the ECC circuitry is configured to access data along the third bit line, parity bits along the second bit line, and metadata along the sixth bit line as part of the second access operation.

3. 2. The apparatus of claim 1, wherein the column decoder is configured to selectively activate the bit lines based on a received column address, the column address including a column plane select bit that specifies whether the data is stored in the first data column plane or the second data column plane.

4. 2. The apparatus of claim 1, further comprising an input / output circuit configured to receive the data and the metadata from the ECC circuit if the access operation is a read operation, and configured to provide the data and the metadata to the ECC circuit if the access operation is a write operation.

5. 2. The apparatus of claim 1, wherein the ECC circuit is configured to locate and correct errors in the data and the metadata based on metadata of the data and the parity when the access operation is a read operation.

6. 2. The device of claim 1, wherein a parity bit stored along the second bit line is associated with data in a data bit stored along the third bit line, and the data bit along the first bit line is associated with the parity bit stored along the fourth bit line.

7. 2. The apparatus of claim 1, wherein the column decoder is configured to provide, in response to a column address received as part of the access operation, a column select signal with a first value to the first data column plane, a second column select signal with a second value to the second data column plane, and a third column select signal with the first value to the spare column plane.

8. a first plurality of column planes; a second plurality of column planes; and spare row plane a memory bank comprising: a column decoder configured to select the first or second plurality of column planes based on a column address received as part of an access operation, wherein as part of the access operation, data bits are accessed in selected ones of the first or second plurality of column planes, parity bits are accessed in unselected ones of the first or second plurality of column planes, and metadata bits are accessed in the spare column plane; and An apparatus comprising:

9. 9. The apparatus of claim 8, further comprising: an error correction code (ECC) circuit configured to locate and correct errors in the data bits and the metadata bits based on the parity bits when the access operation is a read operation.

10. 10. The apparatus of claim 9, wherein the ECC circuitry is configured to implement single error correct double error detect (SECDED).

11. 9. The apparatus of claim 8, wherein the column address includes a column plane select bit, and wherein the first plurality of column planes or the second plurality of column planes are selected based on the column plane select bit.

12. 12. The apparatus of claim 11, wherein a plurality of bits are accessed from the spare column plane, and the column decoder selects a first half or a second half of the plurality of bits as the metadata bits.

13. a first plurality of local input / output (LIO) lines coupled to the first plurality of column planes; a second plurality of LIO lines coupled to the second plurality of column planes, the column decoder being configured to activate, as part of the access operation, all of the first or second plurality of LIO lines coupled to selected ones of the first or second plurality of column planes and less than all of the first or second plurality of LIO lines coupled to unselected ones of the first or second plurality of column planes; The apparatus of claim 8 further comprising:

14. 9. The device according to claim 8, characterized in that it is a memory device operating in quadruple mode.

15. receiving a column address as part of the access operation; selecting a first portion of a plurality of column planes based on the column address; accessing data bits from columns in the first portion of the plurality of column planes as part of the access operation; accessing parity bits from columns in a column plane that are not in the first portion as part of the access operation; accessing metadata bits from a spare column plane as part of said access operation; A method comprising:

16. 16. The method of claim 15, further comprising locating errors, correcting errors, or a combination thereof, in the data bits and the metadata bits based on the parity bits with an error correction code (ECC) circuit.

17. 17. The method of claim 16, further comprising implementing single error correct double error detect (SECDED) in the ECC circuitry.

18. 16. The method of claim 15, further comprising: accessing a set of bits from the spare column plane; and selecting half of the set of bits as the metadata bits based on the column address.

19. selecting a first half of the plurality of column planes as the first portion; and selecting one column plane in a second half of the plurality of column planes as the column plane that is not in the first portion.

16. The method of claim 15, further comprising:

20. receiving a second column address as part of a second access operation; selecting the second half of the plurality of column planes based on the second column address; accessing second data bits from the second half as part of the second access operation; accessing parity bits from columns in the first half as part of the second access operation; accessing metadata bits from the spare column plane as part of the second access operation; 20. The method of claim 19 further comprising:

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