Apparatus and method for separate write permissions for single-pass access of data, metadata, and parity information - Patents.com

Abstract

An apparatus, system, and method for separate write enable signals for data, metadata, and parity information. A memory array is divided into a column plane and a spare column plane. In some modes of the memory device, data and parity information are stored in the column plane, and metadata is stored in the spare column plane. The spare column plane includes a separate write enable signal (or separate states of a single signal) that activates different portions of the bit lines (e.g., even and odd bit lines). In an example access operation, a column select signal is provided to the spare column plane along with one or other write enable signals, such that less than all of the bit lines activated by the column select signal provide data.

Description

[Technical Field]

[0001] Cross-reference to related applications This application claims the benefit of U.S. Provisional Application No. 63 / 383,738, filed November 15, 2022, which is incorporated by reference herein in its entirety and for all purposes.

[0002] The present disclosure relates generally to semiconductor devices, and more particularly to semiconductor memory devices. In particular, the present disclosure relates to volatile memories such as dynamic random access memories (DRAMs). Information may be stored in individual memory cells of the memory as physical signals (e.g., charges on capacitive elements). During an access operation, an access command may be received along with address information specifying which memory cell should be accessed. [Background technology]

[0003] There is growing interest in enabling memories to store information in an array associated with data. For example, error correction information and / or metadata may be stored in an array with its associated data. There may be a need to ensure that such information can be accessed along with the designated data without unduly impacting device performance. Summary of the Invention

[0004] In at least one aspect, the present disclosure relates to an apparatus including a first column plane including a first plurality of bit lines, a second column plane including a second plurality of bit lines, and input / output circuitry that receives data and metadata as part of a write operation, the data being written to the first plurality of bit lines and the metadata being written to even or odd ones of the second plurality of bit lines.

[0005] The apparatus may also include a column decoder configured to provide a column select signal based on a column address, wherein the first plurality of bit lines and the second plurality of bit lines are activated by the same value of the column select signal. The apparatus may also include a column decoder providing a first write enable signal and a second write enable signal, wherein data is written to the first plurality of bit lines in response to the first write enable signal, even or odd ones of the second plurality of bit lines are selected based on the value of the second write enable signal, and metadata is written to the selected ones of the even or odd ones of the second plurality of bit lines.

[0006] The device can also include a global column repair (GCR) column plane including a plurality of redundant bitlines, and a fuse array. The fuse array can remap the first plurality of bitlines or the second plurality of bitlines to the plurality of redundant bitlines, such that if the first plurality of bitlines are remapped to the plurality of redundant bitlines, data is written to the plurality of redundant bitlines, and if the second plurality of bitlines are remapped to the plurality of redundant bitlines, metadata is written to even or odd ones of the plurality of redundant bitlines. The device can also include logic circuitry that provides a first write enable signal if the first plurality of bitlines are remapped to the plurality of redundant bitlines, and that provides a second write enable signal if the second plurality of bitlines are remapped to the plurality of redundant bitlines.

[0007] The device can also include a third column plane including a third plurality of bit lines and an error correction code (ECC) circuit that receives data and metadata as part of a write operation and generates parity bits based on the metadata. The parity bits can be written to the third plurality of bit lines. The device can include an ECC mask circuit that receives a set of bits including the metadata from the second plurality of bit lines as part of a read operation and provides an even or odd number of the set of bits to the ECC circuit.

[0008] In at least one aspect, the present disclosure may relate to a method that includes activating a first write enable signal and a second write enable signal in response to a write operation, the second write enable signal having a first state or a second state based on a column address. The method also includes writing data to selected bit lines in a first column plane in response to the first write enable signal, and writing metadata to first or second portions of the selected bit lines in a second column plane in response to a state of the second write enable signal.

[0009] The first portion may be even ones of the selected bit lines, and the second portion may be odd ones of the selected bit lines. The method may also include generating a column select signal with a value based on a column address, and selecting selected bit lines in the first column plane and selected bit lines in the second column plane based on the value of the column select signal. The method may also include generating parity bits based on the data and the metadata, and writing the parity bits to selected bit lines in a third column plane.

[0010] The method can include selecting a first portion or a second portion of a plurality of column planes based on a column plane select bit of a column address. The first column plane can be in the first portion or the second portion, and the second column plane can be absent from the first portion or the second portion. The method can include reading a first set of bits from the first portion and a second set of bits from the second portion of selected bit lines in the second column plane as part of a read operation, selecting the first set of bits or the second set of bits, and providing the selected one of the first set of bits or the second set of bits to an error correcting code (ECC) circuit.

[0011] The method may include repairing selected bitlines in a first column plane or selected bitlines in a second column plane to selected bitlines in a global column repair (GCR) column plane; if the selected bitlines in the first column plane are repaired, writing data to the selected bitlines in the GCR column plane in response to a first write enable signal; and if the selected bitlines in the second column plane are repaired, writing metadata to a first portion or a second portion of the selected bitlines in the GCR column plane in response to a state of a second write enable signal.

[0012] In at least one aspect, the present disclosure may relate to an apparatus including a first column plane, a second column plane, and a column decoder. The first column plane includes a first local input / output (LIO) line coupled to a first read / write transfer gate and a second LIO line coupled to a second read / write transfer gate. The second column plane includes a third LIO line coupled to a third read / write transfer gate and a fourth LIO line coupled to a fourth read / write transfer gate. The column decoder provides a first write enable signal to the first column plane and a second write enable signal to the second column plane. The first and second read / write transfer gates are activated by the first write enable signal, and the third or fourth read / write transfer gate is activated by the second write enable signal.

[0013] The first column plane can also include a first plurality of bitlines, selected ones of which are coupled to the first LIO lines, and a second plurality of bitlines, selected ones of which are coupled to the second LIO lines. The second column plane can also include a third plurality of bitlines, selected ones of which are coupled to the third LIO lines, and a fourth plurality of bitlines, selected ones of which are coupled to the fourth LIO lines. Selected ones of the first, second, third, and fourth pluralities of bitlines can be selected by the same value of the column select signal.

[0014] The device can also include an error correction code (ECC) circuit and an ECC mask circuit that receives the first bit from the third read / write transfer gate and the second bit from the fourth read / write transfer gate and provides the first bit or the second bit to the ECC circuit. The device can also include a third column plane including a fifth LIO line coupled to the fifth read / write transfer gate and a logic circuit that provides a first write enable signal or a second write enable signal to the fifth read / write transfer gate. The logic circuit can provide the first write enable signal if the first or second LIO line is repaired to the fifth LIO line, and the logic circuit can provide the second write enable signal if the third or fourth LIO line is repaired to the fifth LIO line. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 1 is a block diagram of a semiconductor device according to an embodiment of the present disclosure. [Figure 2] FIG. 1 is a block diagram of a memory device according to some embodiments of the present disclosure. [Figure 3] FIG. 1 is a block diagram illustrating an example of a memory read operation according to some example embodiments of the present disclosure. [Figure 4] FIG. 1 is a schematic diagram of a portion of a memory bank according to some embodiments of the present disclosure. [Figure 5] FIG. 10 is a block diagram of a spare column plane according to some embodiments of the present disclosure. [Figure 6] FIG. 2 is a block diagram of a spare column according to some embodiments of the present disclosure. [Figure 7] FIG. 2 is a block diagram of a sense amplifier region according to some embodiments of the present disclosure. [Figure 8] 1 is a flowchart of a method according to some embodiments of the present disclosure. [Figure 9] FIG. 10 is a timing diagram of a mode register write operation according to some embodiments of the present disclosure. [Figure 10]1 is a flowchart of a method according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0016] The following descriptions of specific embodiments are merely exemplary in nature and are in no way intended to limit the scope of the present disclosure or its application or uses. In the following detailed description of embodiments of the present system and method, reference is made to the accompanying drawings, which form a part hereof, and which show by way of illustration specific embodiments in which the described systems and methods may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the presently disclosed systems and methods, it being understood that other embodiments may be utilized and that structural and logical changes may be made without departing from the spirit and scope of the present disclosure. Moreover, for the sake of clarity, detailed descriptions of specific features will not be discussed when these would be apparent to those skilled in the art so as not to obscure the description of the embodiments of the present disclosure. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present disclosure is defined only by the appended claims.

[0017] A memory array may generally include several memory cells arranged at the intersections of word lines (rows) and bit / digit lines (columns). The columns may be grouped together into column planes, and a column select (CS) signal may be used to select a set of columns in each of the active column planes to provide data. When an access command is received, the memory may pre-fetch a code word (e.g., several bits of data) along with one or more associated bits from the memory and replace the pre-fetched data with new data (e.g., as part of a write operation) or remove the pre-fetched data from the memory device (e.g., as part of a read operation). Some memory modes may include removing less than all of the pre-fetched data from the memory device. For example, in conventional memory devices, in a particular mode, half of the pre-fetched data may be removed from the device, and the rest may be ignored.

[0018] The memory device may store additional information associated with each codeword. For example, the additional information may include parity bits used as part of an error correction scheme, metadata containing information about the data codeword (or being part of information about a larger set of data that includes the codeword), or a combination thereof. Nevertheless, the maximum number of bits that can be retrieved as part of a single access pass may be limited by the architecture of the memory, and this number may generally be based on the maximum number of data bits in a codeword plus a few additional bits (e.g., 128 data bits + 8 additional bits).

[0019] As used herein, the term data can refer to any bit of information that the controller wants to store and / or retrieve from memory. The term metadata can refer to any bit of information about data that the controller writes to and / or receives from memory. For example, metadata can be information generated by the controller, such as information about the data, information about how or where the data is stored in memory, information about how many errors were detected in the data, etc. Data and metadata together represent information written to memory by the controller and then further read from memory by the controller; data and metadata differ in content and how they were generated in that metadata is based on information about the data. The term parity can refer to any bit generated by the memory's error correction circuitry based on data, metadata, or a combination thereof. Parity can generally remain in memory. In some embodiments, the amount of data and / or metadata retrieved as part of a single access operation can represent a set of bits that is a larger piece of information. For example, metadata bits (e.g., 4 bits) retrieved as part of a single access operation may have no meaning on their own, but may have meaning when combined with sets of metadata bits retrieved as part of other access operations (e.g., to other memory arrays and / or to the same array at different times).

[0020] Some memories may include a set of data column planes and a spare column plane storing additional information. Nevertheless, it may be desirable to include more bits of additional information than can be retrieved from the spare column plane for various uses (e.g., including parity bits and metadata, including more parity bits, etc.). Some memory devices may use a "two-pass" architecture, where at least some of the additional bits are first retrieved and stored, and then a second access pass retrieves the codeword data bits. Nevertheless, this may incur a penalty in the latency of any given access operation. There may be a need for one-pass or single-pass storage of the expanded additional information, such that the codeword and additional bits are retrieved as part of a single access pass to the memory array.

[0021] This disclosure is interested in apparatus, systems, and methods for single-pass access of ECC information, metadata information, or a combination thereof, along with an associated codeword. Some memory devices can operate in a mode in which less than all of the data bits that can be pre-fetched are removed from the device. For example, a memory device may pre-fetch 128 data bits as part of a codeword in 8x or 16x mode, while in 4x memory mode a 64-bit codeword is provided at the device's data terminal. In 4x memory mode, the data bits of the codeword are stored in some, but not all, of the data column planes (e.g., half of the column planes). Which half of the data column planes is selected may be based on a column address. Additional bits associated with the data (e.g., parity bits and / or metadata bits) may be stored in both a spare column plane and also in data column planes not selected by the column address as part of the current access.

[0022] According to some embodiments of the present disclosure, an example memory device may include a set of data column planes and a spare column plane. The memory may be set in a mode in which metadata is stored along with its associated data. When an access operation is performed, column select signals with a first value are provided to columns in a first portion of the data column planes and to the spare column plane, and column select signals with a second value are provided to one or more columns not in the first portion of the data column planes. The memory may store data in the first portion of the data column planes, metadata in the spare column plane, and error correction parity bits in accessed columns not in the first portion of the data column planes. In this manner, data, metadata, and ECC information for a codeword may be pre-fetched together as part of a single access pass without pre-fetching additional data bits.

[0023] In some embodiments, issuing a column select signal can retrieve more bits than necessary. For example, eight bit lines may be activated, but only four bits of metadata are required per prefetched codeword. To prevent the spare bits from being inadvertently modified, it may be useful to mask these bits from being accessed. A column plane may include two sets of sense amplifiers, each including a sense amplifier coupled to every other bit line (e.g., an even sense amplifier and an odd sense amplifier). During a write operation in one of the data column planes, a write enable signal activates both sets of sense amplifiers. Nevertheless, one or more metadata write enable signals may be used in the spare column plane. The metadata write enable signal includes a first write enable signal (e.g., an even write enable signal) that activates the first set of sense amplifiers and a second write enable signal (e.g., an odd write enable signal) that activates the second set of sense amplifiers. In some embodiments, the even and odd write enable signals can represent two states of a binary metadata write enable signal (e.g., high = write enable even active, low = write enable odd active). The column control circuitry can selectively activate one or the other write enable signal such that half of the bit lines activated by a given column select signal are activated. In this way, only the required metadata bits are accessed in the spare column plane.

[0024] To account for this change, a global column redundancy (GCR) plane used to repair columns can receive a write enable signal (if the repair occurs on the data column plane) or a metadata write enable signal (if the repair occurs on a spare column plane). For example, sense amplifiers in the GCR can be coupled to a multiplexer that passes the write enable signal or the metadata write enable signal depending on where the repair occurs. The memory can also include a mode register that can enable use of the metadata write enable signal.

[0025] FIG. 1 is a block diagram of a semiconductor device according to an embodiment of the present disclosure. The semiconductor device 100 may be a semiconductor memory device, such as a DRAM device, integrated on a single semiconductor chip. The memory device 100 may be operated by a controller 150. The controller 150 may be a separate device from the memory 100 that stores and retrieves information from the memory 100. For example, the controller 150 may be a processor, such as a CPU or GPU. In some embodiments, multiple memory devices may be packaged together in a single memory module, and the controller may send and receive information from multiple memories simultaneously. For clarity, FIG. 1 will be discussed with respect to a single memory device 100.

[0026] Semiconductor device 100 includes a memory array 118. Memory array 118 is shown to include multiple memory banks. In the embodiment of FIG. 1, memory array 118 is shown to include eight memory banks, BANK0 through BANK7. More or fewer banks may be included in memory array 118 in other embodiments. As described in more detail herein, each bank may be further divided into two or more sub-banks. Although embodiments in which each bank includes two sub-banks are generally described herein, other embodiments may include more sub-banks per bank.

[0027] Each memory sub-bank includes a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC arranged at intersections of the plurality of word lines WL and the plurality of bit lines BL. Selection of the word lines WL is performed by a row decoder 108, and selection of the bit lines BL is performed by a column decoder 110. In the embodiment of FIG. 1, the row decoder 108 includes a respective row decoder for each memory bank, and the column decoder 110 includes a respective column decoder for each memory bank. In some embodiments, components that are repeated for each bank, such as row and column decoders and refresh control circuitry 116, may also include components that are repeated for each sub-bank. For example, there may be a refresh control circuitry 116 for each sub-bank.

[0028] The bit lines BL are coupled to respective sense amplifiers (SAMP). Read data from the bit lines BL is amplified by the sense amplifiers SAMP and transferred to the ECC circuit 120 via local data lines (LIO), transfer gates (TG), and global data lines (GIO). Conversely, write data output from the ECC circuit 120 is transferred to the sense amplifiers SAMP via complementary main data lines GIO, transfer gates TG, and complementary local data lines LIO, and written in the memory cells MC coupled to the bit lines BL. A bit line is selected in response to a column select (CS) signal, and its sense amplifier is coupled to a respective LIO line. In response to a read or write enable signal, the LIO line can be coupled to a respective GIO line by a transfer gate TG.

[0029] The semiconductor device 100 may employ a number of external terminals coupled to the controller 150, such as solder pads, including a command and address (C / A) terminal coupled to a command and address bus for receiving commands and addresses, a clock terminal for receiving clocks CK and / CK, a data terminal DQ coupled to a data bus for providing data, and power supply terminals for receiving power supply potentials VDD, VSS, VDDQ, and VSSQ.

[0030] The clock terminals are supplied by the controller 150 with external clocks CK and / CK, which are provided to the input circuit 112. The external clocks may be complementary. The input circuit 112 generates an internal clock ICLK based on the CK and / CK clocks. The ICLK clock is provided to the command decoder 106 and the internal clock generator 114. The internal clock generator 114 provides various internal clocks LCLK based on the ICLK clock. The LCLK clock may be used to time the operation of various internal circuits. The internal data clock LCLK is provided to the input / output circuit 122 to time the operation of circuits included therein, for example, to a data receiver to time the receipt of write data. The input / output circuit 122 may include several interface connections, each of which may be couplable to one of the DQ pads (e.g., solder pads that may serve as external connections to the device 100).

[0031] The C / A terminal may be supplied with a memory address by the controller 150. The memory address supplied to the C / A terminal is transferred to the address decoder 104 via the command / address input circuit 102. The address decoder 104 receives the address and supplies a decoded row address XADD to the row decoder 108 and a decoded column address YADD to the column decoder 110. The decoded row address XADD may be used to determine which row should be opened so that data along the bit line can be read along the bit line. The column decoder 110 may provide a column select signal CS, which may be used to determine which sense amplifier provides data to the LIO. The address decoder 104 may also provide a decoded bank address BADD, which may indicate a bank of the memory array 118 that includes the decoded row address XADD and column address YADD.

[0032] Commands may be supplied to the C / A terminal by controller 150. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing memory, such as read commands for performing read operations and write commands for performing write operations, and other commands and operations. An access command may be associated with one or more row addresses XADD, column addresses YADD, and bank addresses BADD to indicate the memory cells to be accessed.

[0033] Commands may be provided as internal command signals to command decoder 106 via command / address input circuit 102. Command decoder 106 includes circuitry that decodes the internal command signals to generate various internal signals and commands for performing operations. For example, command decoder 106 may provide signals that indicate whether data is to be read, written, etc. For example, command decoder 106 may provide a write enable signal that couples data on GIO to LIO, allowing the data on GIO to be written to a bit line coupled to LIO by the CS signal.

[0034] Device 100 can receive an access command, which is a read command. When the read command is received and a bank address, row address, and column address are supplied in a timely manner, data to be read is read from memory cells in memory array 118 corresponding to the row address and column address. The read command is received by command decoder 106, which provides an internal command, such as a read enable signal, so that data read from memory array 118 is provided to ECC circuit 120. ECC circuit 120 receives data bits, metadata bits, and parity bits from the array and detects and / or corrects errors in the data and metadata bits. The correct read data is provided along a data bus and output to the outside from data terminals DQ via input / output circuit 122.

[0035] The device 100 can receive an access command that is a write command. When the write command is received and a bank address, a row address, and a column address are provided in a timely manner, write data provided to the data terminals DQ is provided along the data bus and written to memory cells in the memory array 118 corresponding to the row address and column address. The write command is received by the command decoder 106, which provides an internal command such as a write enable signal, so that the write data, along with metadata, is received by a data receiver in the input / output circuit 122. The write data and metadata are provided to the ECC circuit 120 via the input / output circuit 122. The ECC circuit generates parity bits based on the received data and metadata, and the data, metadata, and parity are provided by the ECC circuit 120 to the memory array 118 to be written to memory cells MC.

[0036] Device 100 includes refresh control circuits 116 associated with each bank of memory array 118. Each refresh control circuit 116 can determine when to perform a refresh operation on the associated bank. Refresh control circuit 116 provides a refresh address RXADD (along with one or more refresh signals not shown in FIG. 1 ). Row decoder 108 performs the refresh operation on one or more word lines associated with RXADD. Refresh control circuit 116 can perform multiple types of refresh operations, and the refresh operation can determine other details, such as how address RXADD is generated and how many word lines are associated with address RXADD.

[0037] ECC circuit 120 can detect and / or correct errors in accessed data. As part of a write operation, ECC circuit 120 can receive bits from IO circuit 122 and generate parity bits based on the received bits. The received bits and parity bits are written to memory array 118. During an example read operation, ECC circuit 120 receives a set of bits and their associated parity bits from array 118 and uses them to locate and / or correct errors. For example, a single error correction (SEC) scheme locates and detects up to one bit of error. A single error correction double error detection (SECDED) scheme corrects up to one bit of error, but two errors may be detected (however, the bits causing these errors are not individually located and therefore cannot be corrected). ECC circuit 120 can correct the information and then provide the corrected information (and / or the detected error indicated by the signal) to IO circuit 122. Parity bits may generally not be provided to IO circuitry 122 .

[0038] Mode register 130 can contain various settings and can be used to enable a metadata mode for memory 100. When metadata is enabled, device 100 can store metadata associated with data. For example, as part of a write operation, the controller can provide data with its associated metadata, and as part of a read operation, the controller can receive data and its associated metadata. In some embodiments, ECC circuit 120 can include metadata bits as part of the error correction process; in some embodiments, metadata bits may be excluded. In some embodiments, whether metadata is included in the ECC process can be a memory setting (e.g., in mode register 130). The metadata can include information about the associated data.

[0039] The memory 100 can be operated in various modes based on the number of DQ pads used. The mode can determine both how many DQ pads the controller expects to send / receive data along as well as the format and / or number of bits the controller expects as part of a single access command. For example, a memory can have 16 physical DQ pads. In 16x mode, all 16 DQ pads are used. In 8x mode, eight of the DQ pads are used, and in 4x mode, four of the DQ pads are used. The mode can also determine the burst length on each DQ terminal as part of a DQ operation. The burst length represents the number of consecutive bits on each DQ terminal during an access operation.

[0040] For example, in 8x mode, the memory can send or receive 128 data bits along eight DQ terminals, each with a burst length of 16. In an example 4x mode, a burst length of 16 may also be used, so 64 bits may be sent or received as part of an access operation. This disclosure is generally described with respect to an example embodiment in which, as part of 4x mode, a 64 data bit codeword is accessed along with 4 bits of metadata, and ECC circuit 120 uses 8 bits of ECC parity. Other example embodiments may use different numbers of data, metadata, and parity.

[0041] The device 100 includes a mode register 130 that can be used to control various optional modes of the memory. For example, the mode register 130 can include a setting that determines whether metadata is used. If metadata is enabled, the mode register 130 can set a first 4x operating mode (e.g., a two-pass 4x operating mode) or a second 4x operating mode (e.g., a one-pass 4x operating mode). The controller can perform a mode register write (MRW) operation to set a value in the mode register 130 or a mode register read (MRR) operation to check what the value in the mode register 130 is. The mode register 130 includes several registers, each of which can store one or more bits corresponding to a setting or piece of information about the memory. When the memory is in a one-pass 4x operating mode, further settings of the mode register 130 can be used to set the memory in an isolated write-enable mode or a common write-enable mode in a spare column plane as described in more detail herein.

[0042] The controller 150 can provide a command and row and column addresses as part of an access operation. In a two-pass 4x mode of operation, in response to an access operation from the controller, the column decoder can perform a first access pass to the memory array to retrieve a first portion of information that may then be stored, and then a second access pass to the memory array to retrieve the remainder of the information to be combined with the stored information. For example, during a read operation, the controller can provide an address and a single read command, in response to which the memory 100 can retrieve four metadata bits as part of a first pass, and then the remaining 64 data bits and eight parity bits as part of a second pass. In a single-pass 4x mode of operation, in response to an address and read command, the memory can retrieve data, metadata, and parity as part of a single access pass to the memory array.

[0043] Memory device 100 may also be repaired. The memory includes a fuse array 152, which includes several non-volatile storage elements (e.g., fuses or anti-fuses). The state of fuses in fuse array 152 may be used to permanently encode information into memory 100. For example, a repaired address may be programmed into fuse array 152. When an address is received as part of an access operation, if the address matches a repaired address in fuse array 152, the memory may access a redundant row or column of memory instead.

[0044] The power supply terminals are supplied with power supply potentials VDD and VSS. The power supply potentials VDD and VSS are supplied to an internal voltage generation circuit 124. The internal voltage generation circuit 124 generates various internal potentials VARY and the like based on the power supply potentials VDD and VSS supplied to the power supply terminals.

[0045] Power supply potentials VDDQ and VSSQ are also supplied to the power supply terminals. The power supply potentials VDDQ and VSSQ are supplied to the input / output circuit 122. In one embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminals may be the same potential as the power supply potentials VDD and VSS supplied to the power supply terminals. In another embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminals may be different potentials from the power supply potentials VDD and VSS supplied to the power supply terminals. The power supply potentials VDDQ and VSSQ supplied to the power supply terminals are used for the input / output circuit 122 to prevent power supply noise generated by the input / output circuit 122 from propagating to other circuit blocks.

[0046] 2 is a block diagram of a memory device according to some embodiments of the present disclosure. Memory device 200 may, in some embodiments, represent a portion of memory device 100 of FIG. 1. The view of FIG. 2 shows portions of memory arrays 210-214 and 220-224, which may be part of a memory bank (e.g., 118 of FIG. 1), along with selected circuitry used in the data path, such as ECC circuitry 232 (e.g., 120 of FIG. 1) and IO circuitry 234 (e.g., 122 of FIG. 1). For clarity, certain circuits and signals have been omitted from the view of FIG. 2.

[0047] The memory device 200 is organized into several column planes 210-214. Each column plane represents a portion of a memory bank. Each column plane 210-214 includes several memory cells at the intersections of word lines WL and bit lines. The bit lines may be grouped together into sets that are activated by the value of a CS signal. For clarity, only a single vertical line is used to represent the bit lines of each column select set, but there may be multiple columns accessed by this value of CS. For example, each line may represent eight bit lines that are all accessed in common by the value of CS. For example, there may be eight LIOs per column plane, and the CS signal may be used to determine which bit lines (through their respective sense amplifiers) are coupled to these LIOs. As used herein, a "value" of CS may represent a decoded signal provided to a set of bit lines. Thus, a first value may represent the first value of a multi-bit CS signal or, after decoding, the signal line associated with this value that is active. The word lines may extend across multiple column planes 210-214.

[0048] The memory 200 includes a set of data column planes 210 and a spare column plane 212. The spare column plane 212 may be used to store additional information, such as error correction parity bits or metadata bits.

[0049] In some embodiments, memory 200 also includes a global column redundancy (GCR) column plane 214. In some embodiments, GCR plane 214 may have fewer memory cells (e.g., fewer column select groups) than data column plane 210. GCR CP 214 includes some redundant columns that may be used as part of a repair operation. If the value of the CS signal is identified as repaired (e.g., the value of the CS signal matches an address stored in fuse array 152 of FIG. 1), the memory may be remapped such that data that would have been stored in this column plane for this value of CS is instead stored in GCR CP 214.

[0050] During a write operation, the column timing logic in the bank area, as well as the column select signal from the column decoder, provides a write enable signal WrEN to the transfer gate associated with the data column plane 210 and a metadata write enable signal WrEN_MD to the transfer gate associated with the spare column plane 212. Both write enable signals are provided to the transfer gate associated with the GCR column plane 214 through logic circuit 240. For clarity, a single logic circuit 240 is shown, but there may be a logic circuit 240 for each transfer gate (e.g., for each LIO / GIO). The column select signal CS determines which sense amplifier (and therefore which bit line) is coupled to the corresponding LIO. When active, the write enable signals WrEn and WrEn_MD couple the LIO to the GIO, allowing data along the GIO to be written along the LIO through the active sense amplifier and to the memory cell at the intersection with the active word line. When the write enable signal is inactive, the LIO may remain decoupled from the GIO, similar to a read operation. Therefore, when the write enable signal is inactive, data cannot be written to the bit line selected by CS.

[0051] As described in more detail herein, the sense amplifiers 220, 222, and 224 may be divided into two regions, an even region and an odd region. The different regions include sense amplifiers coupled to alternating bit lines. For example, the even sense amplifier region includes sense amplifiers coupled to even-numbered bit lines, and the odd sense amplifier region includes sense amplifiers coupled to odd-numbered bit lines. Similarly, there may be corresponding even and odd LIOs and GIOs associated with these regions. The write enable signal WrEn activates transfer gates associated with both the even and odd sense amplifier regions in the sense amplifiers 220 when the write enable signal WrEn is active. The metadata write enable signal WrEn_MD activates transfer gates associated with either the even or odd sense amplifier regions of the spare sense amplifiers 222, but not both simultaneously. The transfer gate associated with the GCR sense amplifiers 224 may be activated by WrEn or WrEn_MD, depending on whether the WrEn or WrEn_MD signal is provided by the logic 240. For example, if a given transfer gate is provided with WrEn_MD, then only the even or odd sense amplifiers in that set will be coupled to GIO as part of this write operation.

[0052] In the illustrative embodiment, memory 210 may include 16 data column planes 210(0) through 210(15). Each of these data column planes 210 includes 64 sets of bit lines that can be selected by a corresponding value of a column select signal (e.g., CS0 through CS63), with each set of bit lines including 8 bit lines coupled to a corresponding LIO when the CS signal has this value. Thus, when a word line is opened in response to a row address and column select signals are provided to all 16 column planes (e.g., as part of an 8x, 16x, or two-pass 4x mode), 8 bits are accessed from each of the 16 data column planes 210, corresponding to a total of 128 bits. A column select signal is also provided to spare column plane 212, which may or may not be the same value as the CS signal provided to data column planes 210 corresponding to up to an additional 8 bits. If a repair was performed, the GCR CP 214 may be accessed as well, and the value on the GCR LIO may be used, ignoring the LIO in the column plane that the GCR CP 214 is replacing. Thus, the maximum number of bits that can be retrieved as part of the access path is 128 bits from the data column plane 210 (with 8 bits substituted from the GCR CP 214 if there was a repair), along with 8 additional bits from the spare CP 212.

[0053] The memory may be operated in 4x mode, in which less than the maximum number of bits that can be accessed is sent / provided to an external device, such as controller 150 of FIG. 1. For example, in 4x mode, the controller may send / receive 64 data bits instead of 128. A column address may indicate which of the column planes 210 is used to store data accessed in 4x mode. For example, the CP select bit of the column address (e.g., the 10th bit of column address C10) may select data from an even column plane or an odd column plane, or from the first half of a column plane or the second half of a column plane. Other schemes may be used in other example embodiments.

[0054] A mode register (e.g., 130 in FIG. 1, not shown in FIG. 2) may be used to enable metadata on the device. When metadata is enabled, the mode register may have a setting that sets the memory device in a first 4x operating mode (2-pass mode) or a second 4x operating mode (1-pass mode). In both operating modes, the overall information received from / sent to an external device is the same. For example, the memory's controller may expect 64 data bits and 4 metadata bits per access of memory 200 in either mode, but the operating mode can determine how the memory array is accessed, how many access paths are used to fetch data (e.g., how quickly the data is accessed), the power consumption of the access operation, the size of the pre-fetched information, the behavior of ECC circuit 232, and which information is stored in which column plane. In a first 4x operating mode, two access paths are used to retrieve data (e.g., metadata from a first path and data and ECC bits from a second path), while in a second 4x operating mode, a single path is used to retrieve information.

[0055] In an example read command, in a first (two-pass) 4x operation mode, a column, row, and bank address are received from the controller. A row decoder (e.g., 108 in FIG. 1 ) opens a selected word line based on the row address. The column decoder generates a column select signal based on the column address. As part of the first access pass, a column select signal is provided to one of the column planes 210 selected by a CP select bit in the column address (e.g., C10). A set of metadata (e.g., 128 metadata bits) partially associated with the current access operation is retrieved from the column plane 210 along with a parity bit (associated with this set of metadata) from the spare column plane 212. The ECC circuit 232 can check and correct errors based on the 128 metadata bits plus the 8 associated parity bits. The metadata bits (e.g., 4 metadata bits) in this set associated with the current access operation (e.g., as indicated by the column address) are stored in a buffer (not shown) as part of the IO circuit 234. As part of the second access path, column select signals are provided to all of the data column planes 210, and spare column select signals are provided to the spare column planes. The column select signals and spare column select signals have the same values ​​as each other, and do not necessarily have the same values ​​as the column select signals provided as part of the first access path. As part of the second access path, data bits are retrieved from the data column planes 210, and parity bits are retrieved from the spare column planes 212. The ECC circuit 232 uses the retrieved data and parity bits to locate and / or correct errors in the data. Half of the retrieved (corrected) data bits are then combined with the previously retrieved metadata in the IO circuit 234, which removes the data and metadata from the device at the DQ pads.

[0056] An example write command may be generally similar in the first 4x mode of operation. The controller provides data and metadata bits along with a command and address, such as a write enable signal WrEn. In the first (two-pass) 4x mode of operation, the signal WrEn may be provided to the spare sense amplifiers 222, and both the even and odd sense amplifiers may be activated together. The metadata is stored in a buffer in the IO circuit 234. Data is pre-fetched from the array, and half of this data is replaced with new write data. The ECC circuit 232 then generates new parity from the updated set of data, and the data is written to the data column plane 210. Similarly, in the second access pass, a set of metadata is retrieved, allowing the metadata to be added to the set of metadata, and the ECC circuit 232 can generate new parity associated with the updated set of metadata. The updated set of metadata and parity is then written to the array. In the second access pass, meanwhile, the parity is written to the spare column plane 212.

[0057] There may be a latency time tCCD_L_WR that is part of the memory's design specifications. The time tCCD_L_WR represents the minimum time that must elapse before a bank within the same bank group can be accessed again. The time tCCD_L_WR represents the long inter-column (or command) delay period for writes, which may also be a memory specification. During write operations, a two-pass mode of operation can incur a latency of twice tCCD_L_WR because each access pass requires a delay of tCCD_L_WR before the bank can be accessed again. One tCCD_L_WR is incurred from adding an extra pass to overwrite the metadata, and an additional tCCD_L_WR is incurred because, to generate parity bits based on all of the pre-fetched data in this mode, half of the unwritten pre-fetched data bits must still be pre-fetched (e.g., read) so that they can be added to the write bits received from the controller.

[0058] The second 4x mode of operation may be a "one-pass" mode in which fewer data bits are pre-fetched and the location of the metadata and parity is changed compared to the first 4x mode of operation. Instead of pre-fetching additional data bits that are not part of the access operation as in the first 4x mode of operation, in the second 4x mode of operation, only the accessed data bits are pre-fetched.

[0059] In an example read command, in the second 4x operating mode (when the separate write enable mode is disabled), a column, row, and bank address are received from the controller. A row decoder (e.g., 108 in FIG. 1) opens a selected word line based on the row address. The column decoder generates a column select signal based on the column address. As part of a single access pass, a column select value with a first value is provided to a first portion of the column planes, and a column select signal with a second value is provided to at least one column plane not in the first portion. Along with this, a column select signal (which may or may not have the same value of the first or second column select signal) is provided to the spare column plane 212. Which columns are in the first portion may be based on a CP select bit in the column address (e.g., C10). The data column planes in the first portion provide data bits, the data column planes not in the first portion provide ECC parity bits, and the spare column plane 212 provides metadata bits. During the second 4x mode of operation, only a portion of column plane 210 is accessed, so only some of the data bits provided to / removed from the device are accessed (along with the metadata and ECC bits). ECC circuit 232 receives the data and metadata along with parity bits and locates and / or corrects any errors in the data and metadata. The (corrected) data and (corrected) metadata are provided to IO circuit 234, which provides the data and metadata to the DQ terminals.

[0060] In an example write command, in the second 4x operating mode (when separate write enable mode is disabled), column, row, and bank addresses are received from the controller along with data and metadata. The data and metadata are provided to the ECC circuit through the IO circuit, which generates parity bits based on the data and metadata and then writes the data, metadata, and parity to the column plane being accessed in a manner similar to that described for the read operation. Column select and WrEn signals are also provided to the spare sense amplifiers 222. Thus, when separate write enable mode is disabled, the number of bits retrieved when a column in the spare column plane is accessed (e.g., 8) may be greater than the specified number of metadata bits (e.g., 4). To protect the spare bits from being overwritten, the metadata may be pre-fetched (e.g., read), and then new metadata overwrites some of the bits as part of a read modify write (RMW) cycle. This may incur a tCCD_L_WR penalty(). Nevertheless, the single pass mode may have reduced latency since only a single extra tCCD_L_WR penalty is incurred (compared to two in the case of the two pass 4x operating mode).

[0061] The separate write enable mode can further reduce the latency of write operations by masking the spare metadata bits so that only the four metadata bits associated with the accessed data bit can be written. In the separate write enable mode, the signal WrEn_MD is provided to the sense amplifiers 222 of the spare column plane 212. The metadata write enable signal WrEn_MD activates either the even or odd sense amplifiers, but not both simultaneously. The state of WrEn_MD can be based on the column plane select bit (e.g., C10) of the column address. For example, the column select signal can indicate a group of eight bit lines and their associated eight sense amplifiers LIO and GIO. When the column select is active, all eight sense amplifiers are coupled to their respective LIOs. Nevertheless, the state of the WrEn_MD signal determines whether an even number of these LIOs is coupled to its GIO or an odd number is coupled to its GIO. In this way, only the selected even or odd LIOs (and therefore bit lines) can be written. This can eliminate the need for RMW cycles to protect the spare bits. Additionally, this can eliminate the extra RMW latency penalty from the 4x1-pass mode of operation when a separate write enable signal is enabled.

[0062] When a column repair is performed, information for remapping columns to the GCR column plane 214 may be programmed into a fuse array (e.g., 152 in FIG. 1 ). After the repair, when a column address is received, the column address may be compared with the repaired column address in the fuse array, and if there is a match, an enable signal is provided to the GCR column plane 214 along with the corresponding column select signal. The data on the LIO for the column plane containing the defective row may then be swapped with the GCR LIO, so that the GCR LIO becomes the memory cell in the GCR column plane 214 rather than the column plane with the damaged bit line that was accessed.

[0063] When separate write enable modes are enabled, the write enable behavior differs between the data column plane 210 and the spare column plane 212. If a repaired CS value is in the data column plane 210, the logic 240 associated with this CS value in the GCR-CP 214 can pass the write enable signal WrEn. If a repaired CS value is in the spare column plane 212 with metadata, the logic 240 associated with this CS value passes WrEn_MD. In this way, repair can function to match the set of repaired columns.

[0064] In a first (two-pass) quad mode of operation, each of the data column planes 210 stores a mixture of data and metadata, with ECC parity bits stored in the spare column plane 212. In a second (one-pass) quad mode of operation, each of the data column planes 210 stores a mixture of data and ECC parity bits, with metadata stored in the spare column plane 212. In a single-pass mode, the ECC circuit 232 locates and corrects errors in both the data and the metadata (e.g., because parity is based on both the data and the metadata). In a two-pass mode, the ECC circuit 232 only locates and corrects errors in the data in one cycle, while errors in the metadata are corrected in the other cycle. In other words, in one-pass mode, the parity bits are based on both the data and the metadata, while in two-pass mode, there are separate parity bits for the data and the metadata.

[0065] In separate write enable mode, only four bits of metadata provided to / received from the controller are provided to ECC circuit 232. When separate write enable mode is disabled, the ECC circuit operates on both the selected four bits of metadata and the unselected four bits accessed along with it. To accommodate this difference, when separate write enable mode is enabled, eight bits are accessed during a read operation and the spare bit may be discarded, thus providing only four selected metadata bits to ECC circuit 232. For example, ECC circuit 232 may include an ECC read mask circuit that passes a selected half of the GIO lines from the spare column plane based on one of the column plane select bits (e.g., C10) or a CS address such as CA9. This address will select data from either the even or odd sense amplifier stripes.

[0066] Additionally, accesses in the one-pass 4x mode of operation may draw less power than accesses in the two-pass 4x mode of operation. In the two-pass mode of operation, all of the column planes are activated, and data read from their sense amplifiers 220 is sent along the LIOs to the ECC circuit 232, along with the sense amplifiers 222 and LIOs associated with the spare column plane 212 (and, if there is a repair, the sense amplifiers 224 and LIOs of the GCR 214). Nevertheless, in the one-pass 4x mode of operation, only a selected portion (e.g., half) of the data column planes 210 are activated, thus reducing all of the data LIOs by each sense amplifier 220. Similarly, various switches, signal lines, etc. may not be used in every access in the one-pass 4x mode of operation. Thus, in the 4x mode of operation, then in the two-pass 4x mode of operation, less power is drawn. Because there are fewer LIOs during write operations and fewer GIOs during reads, even less power can be drawn when a separate write-enable mode is enabled.

[0067] FIG. 3 is a block diagram illustrating an example of a memory read operation according to some example embodiments of the present disclosure. FIG. 3 shows a view of a memory array 300 showing a representation of which portions of the memory array are reserved for different types of information. The blocks shown in FIG. 3 represent a portion of the memory array but do not necessarily represent the spatial layout of where information is stored in the memory array. Memory array 300, in some embodiments, may be an implementation of memory array 118 of FIG. 1 and / or column planes 210-214 of FIG. 2 in the second 4x mode of operation as described herein.

[0068] 3 is depicted for an example embodiment in which there are 16 data column planes, each providing 8 bits when activated by a column select signal, and a spare column plane that also provides 8 bits when activated by its respective column select value. The example memory is operated in 4x mode, with 64 data bits and 4 metadata bits accessed by the controller. The CP select bit C10 of the column address is used to determine which column plane provides the data.

[0069] During an example read operation, when C10 is in a low logic state (e.g., C10=0), eight column planes are accessed in a first portion 301 of the memory array 300, each providing eight bits for a total of 64 data bits. A second column select is also provided to a column plane in a second portion 302. This second column select signal is provided to a single column plane, deriving a total of eight ECC parity bits. A column select signal is also provided to a spare column plane 308, which provides eight metadata bits. If the device is in separate write enable mode, half of these bits are selected (based on the state of C10) and provided to the ECC circuit 310, while the unselected bits are discarded. If the device is not in separate write enable mode, a selected four of the eight bits are provided to the ECC circuit. The ECC circuit 310 (e.g., 232 in FIG. 2) receives 64 data bits along with 4 metadata bits and 8 parity bits and provides 64 data bits along with 4 metadata bits. Which of the 8 retrieved bits from the spare column plane are provided when the 4 metadata bits are provided may be based on C10 or a different column address bit (e.g., C9).

[0070] In another example read operation, if C10 has the opposite value (e.g., C10=1), 64 data bits can be accessed from the second portion 302, 8 parity bits from the first portion 301, and metadata bits from the spare column plane 308.

[0071] In an example write operation, when the separate write enable mode is disabled, eight metadata bits are accessed, but only four are actually specified by the access operation, so four spare metadata bits can be protected. For example, memory 300 can employ a read-modify-write (or RMW) strategy in which all eight metadata bits are pre-fetched, then four of these bits are changed (if necessary) based on the newly written metadata, and then all eight bits are written back. ECC circuit 310 generates parity based on the updated set of eight bits. This can protect the spare four bits (thus, the spare four bits are not inadvertently changed by a direct write operation because data has not been written to these cells) at the expense of extra latency (e.g., tCCD_L_WR).

[0072] In an example write operation, when the separate write enable mode is enabled, only the four metadata bits selected by the column plane select bits of the column address are accessed. ECC circuit 310 receives 64 data bits and four metadata bits and generates eight parity bits based on the 64+4 bits. The 64 data bits and eight parity bits are then written to data column plane 301 or 302, and the four metadata bits are written to spare column plane 308. Because only the required bits can be written (because only the selected transfer gate is activated by WrEn_MD), no spare tCCD_L_WR latency penalty is incurred.

[0073] The blocks in the first and second portions 301 and 302 represent portions of these column planes that may be reserved for different storage purposes and do not necessarily represent the physical layout of where information is stored in the portions of the column planes or the spatial relationship of the column planes in each portion relative to each other. For example, the first portion could represent even column planes, while the second portion represents odd column planes, and the columns reserved for storing ECC bits could be distributed throughout the data column planes. In the example of FIG. 3, because 8 bits of ECC are required for every 64 bits of data, each portion 301 and 302 could have 87.5% of its total memory space used for data and 12.5% ​​used for ECC and metadata bits. In other words, from the controller's perspective, only 87.5% of the memory array can be addressed because the remaining portion is reserved for metadata that is expected to occur with the data. In a two-pass 4x operating mode, more memory array space may be available because metadata is stored in the data array and there are 4 bits of metadata for every 64 bits of data. Thus, in a two-pass quad mode of operation, there may be 93.75% of the array set aside for data and 6.25% for metadata. When metadata is disabled, 100% of the array space may be used for data.

[0074] Table 1 summarizes the different behaviors in two different 4x modes with metadata according to some embodiments of the present disclosure. [Table 1]

[0075] In Table 1, the notations d, p, and md are used to represent data bits, parity bits, and metadata bits, respectively. For example, the first row uses the notation 8p+128md / 128d+8p to represent that in two-pass mode, 8 metadata bits are fetched in the first pass (but only 4 metadata bits are used), then 128 data bits and 8 parity bits are fetched in the second pass, while the notation 64d+8(4)md+8p is used to represent pre-fetching 64 data bits, 8 metadata bits, and 8 parity bits as part of a single access pass (but only 4 metadata bits are used). In one-pass mode, when separate write permission is active, only the four required metadata bits are accessed. The mode register can also have a setting to disable metadata. When metadata is not used, the device can function similarly to "two-pass" mode, except that only a single pass is required to pre-fetch the 128 data bits and 8 parity bits.

[0076] In a two-pass quad mode of operation (and in a metadata-disabled mode), 128 metadata bits (four of which are associated with data accesses) and eight parity bits associated with these 128 metadata bits are used by ECC circuit 232 in the first pass, while 128 bits of data and eight parity bits are used by ECC circuit 232 in the second pass. In a one-pass quad mode of operation, 64 bits of data, eight bits of metadata, and eight bits of parity are used by ECC circuit 232. When separate write permissions are enabled, four bits of metadata are used by ECC circuit 232. In a two-pass quad mode, ECC circuit 232 can implement the SEC scheme separately for both the 128 metadata bits and the 128 data bits, while in a one-pass quad mode, the SECDED scheme can be used together for both data and metadata. In other words, in two-pass mode, each set of parity may correspond to data or metadata, while in one-pass mode, parity corresponds to data and metadata together. Because a greater number of parities for other bits are used in one-pass mode, more protection can be provided. Additionally, in one-pass mode, metadata may also be checked by the ECC circuit, while in two-pass mode, metadata may be protected by the ECC circuit of the second pass.

[0077] In a two-pass 4x operating mode, there may be an extra latency of 2x tCCD_L_WR because both access paths (metadata and pre-fetched data) may need to undergo an RMW cycle. In a one-pass 4x operating mode, only a single extra tCCD_L_WR is incurred. When separate write permissions are enabled, the extra tCCD_L_WR penalty is not incurred. The metadata-disabled mode can also only incur an extra tCCD_L_WR because the amount of pre-fetched data is greater than the amount to be written, so an RMW is used to pre-fetch the complete set of data and then overwrite selected bits.

[0078] The one-pass 4x operating mode can draw less power than the two-pass 4x operating mode (or metadata disabled mode). In one-pass mode, the CS signal may be provided to only selected half of the column planes (based on C10). Thus, only half of the column planes need to activate their switches, drive voltages along the LIO lines, etc. This can reduce power draw from a single-access operation. For example, in two-pass mode, 17 different CS signals (16 data column planes and one spare column plane) and their associated LIO / GIOs, etc. are asserted, while in one-pass mode, 9 different CS signals and their associated LIO / GIOs, etc. are asserted. When separate write enable is enabled, only the spare column plane needs to assert half of the LIO / GIOs. This is listed in Table 1 as 8.5 CSs that need to be asserted for power reduction compared to one-pass mode when the separate write enable signal is disabled.

[0079] 4 is a schematic diagram of a portion of a memory bank according to some embodiments of the present disclosure. Memory bank 400 may, in some embodiments, be included in memory 100 of FIG. 1, 200 of FIG. 20, and / or 300 of FIG. 3. Memory bank 400 shows a simplified schematic view of the layout of the memory bank along with example signals that may be used to activate various columns in the column plane as part of a second 4x mode of operation (e.g., a one-pass 4x mode of operation) when a separate write enable signal is active.

[0080] 4 is depicted in terms of an example embodiment in which there are 16 data column planes, each including 64 sets of bit lines (e.g., 64 values ​​of the CS signal), each providing 8 bits of data when activated by a respective CS signal. It should be understood that this is one example implementation of the present disclosure, and that other arrangements (e.g., more or fewer CS sets per CP, more or fewer CPs per memory bank, etc.) may be used in other example embodiments.

[0081] Memory bank 400 illustrates memory organized into 16 column planes 412-448 (e.g., 210 in FIG. 2 and / or 301-302 in FIG. 3), each associated with a DQ pad 410-440. Thus, a first DQ pad 410 is associated with a column plane 412-418, a second DQ pad 420 is associated with a column plane 422-428, a third DQ pad 430 is associated with a column plane 432-438, and a fourth DQ pad is associated with a column plane 442-448. In the 4x mode of the example of FIG. 4, each of the four DQ pads 410, 420, 430, and 440 handles 16 data bits as part of an access operation, for a total of 64 data bits. In addition to the four DQ pads 410, 420, 430, and 440, memory bank 400 may also be associated with a metadata terminal 450 that may be used to send / receive metadata as part of an access operation. The metadata terminal is associated with a spare column plane 452 (e.g., 212 in FIG. 1 and / or 308 in FIG. 3). In the simplified view of FIG. 4, a single word line WL is shown, along with a global row decoder 402 that drives the word line. Similarly, only selected lines are shown as bit lines, each representing a set of bit lines activated by a common CS signal in this CP.

[0082] The memory bank 400 is organized into sections or mats 403 with the cells of the memory array between two sense amplifier regions 404. There may be several sections, each with several word lines and bit lines per column plane; for clarity, only a single section 403 is shown in FIG. 4. The sense amplifier regions 404 may extend in the same direction as the word lines WL. Different sections may extend perpendicular to the direction in which the word lines extend. Each section may be separated by a sense amplifier region (e.g., 404-409). The sense amplifiers in each of the regions may be coupled to bit lines within the section and to bit lines in adjacent sections. During an access operation, the bit lines in the section containing the active word line may be accessed, while the bit lines extending to the unaccessed section may serve as a reference. During a write operation, the sense amplifier sections 404 and 405 may be activated (e.g., coupled to GIO) in response to a write enable signal WrEn.

[0083] The spare column plane 452 is also surrounded by first and second sense amplifier sections 408 and 409, which may be generally similar to the sense amplifier regions 404 and 405, respectively. The first sense amplifier region 408 is activated by a first state of a column signal (CA10), and the second sense amplifier region 409 is activated by a second state of the column signal (CA10).

[0084] The column planes 412-448 in section 403 are separated by sub word line (SWL) drivers 406. Each column plane is adjacent to one other column plane and to an SWL driver 406. For example, column plane 412 is adjacent to an SWL driver 406 on one side and to column plane 414 on the other side. Column plane 414 is adjacent to column plane 412 on a first side and to a second SWL driver 406 on the opposite side. On the opposite side of this SWL driver 406 is another column plane 416, and so on.

[0085] Thus, each data terminal is associated with four column planes, two pairs of column planes adjacent to each other and separated from the other pairs by SWL drivers. Each pair is associated with a different value of column plane select bit C10. For example, first DQ pad 410 is associated with column planes 412 and 414, both activated by C10 at a high logic level, and with column planes 416 and 418, both activated by C10 at a low logic level. Thus, column planes 412, 414, 422, 424, 432, 434, 442, and 444 all contain data accessed when C10=1, and column planes 416, 418, 426, 428, 436, 438, 446, and 448 all contain data accessed when C10=0. Whichever set of column planes is selected by C10, one or more column planes of other sets may be used to store ECC parity bits.

[0086] 4 illustrates an example access operation in a second 4x operating mode (e.g., one-pass 4x mode) when a separate write enable mode is active. Section 403 is flanked on either side by a first sense amplifier region 404 and a second sense amplifier region. Each sense amplifier region receives a column select signal and a write enable signal WrEn. The sense amplifiers in each region 404 and 405 are alternately coupled to every other bit line in section 403. For example, sense amplifier region 404 may be an even sense amplifier region, and sense amplifier region 405 may be an odd sense amplifier region.

[0087] In an example write operation, the memory device receives a column address including C10=0 and having a value decoded to a first column select signal CS0. Thus, CS0 is provided by the column decoder to column planes 416, 418, 426, 428, 436, 438, 446, and 448 along with a write enable signal WrEn, and the bit line associated with CS0 in each of these column planes provides eight bits of data, four bits per column plane from each of sense amplifier regions 404 and 406, respectively. The column decoder also provides CS0 to spare column plane 452 along with one state of WrEn_MD (selected by C10). Thus, four bits of metadata are accessed from spare column plane 452 (e.g., from sense amplifier 408). In addition, the column decoder also generates an additional CS signal and provides it to one of the column planes not selected by the value of C10. In this example embodiment, the value CS56 is provided to column plane 444. Thus, column plane 444 provides 8 bits of ECC parity. Thus, from a single access pass, 64 bits of data (8 each from column planes 416, 418, 426, 428, 436, 438, 446, and 448), 4 bits of metadata (half of which are taken from spare column plane 452), and 8 bits of parity (from column plane 444) are accessed. Arrows are used to indicate which CS signals and which column planes are accessed as part of a single access pass.

[0088] 4, a similar access may occur as part of a second access operation in which a column address is received with C10=1 but including the same decoded value of CS. In this example, the column decoder provides CS0 to column planes 412, 414, 422, 424, 432, 434, 442, and 444, as well as to spare column plane 452, while the CS56 value is provided to column plane 448. In this operation, another value of WrEn_MD is provided, and the other four bits are accessed (e.g., from sense amplifier 409 rather than 408).

[0089] 5 is a block diagram of a spare column plane according to some embodiments of the present disclosure. Spare column plane 500, in some embodiments, may represent spare column plane 212 of FIG. 2, 308 of FIG. 3, and / or 452 of FIG. 4. Spare column plane 500 is shown with a command decoder 510 (e.g., 106 of FIG. 1) that provides various signals. The view in FIG. 5 shows how write permissions are provided to different sense amplifier regions 502 and 503 in spare column plane 500.

[0090] Spare sense amplifier area 500 includes several sections 506 (e.g., 403 in FIG. 4), each containing several memory cells at the intersections of word lines and bit lines. Sections 506 are each flanked by a pair of sense amplifier areas 502 and 503 (e.g., 408 and 409 in FIG. 4). Furthermore, each sense amplifier area 502 and 503 is flanked by two sections 506 (except at the edges of the array).

[0091] An even write enable signal, WrEn_Even, activates sense amplifiers in region 502 as part of a write operation, while an odd write enable signal, WrEn_Odd, activates sense amplifiers 503 as part of a write operation. In some embodiments, command decoder 510 may provide a single binary signal, WrEn_MD, that may be in a first state to activate WrEn_Even and in a second state to activate WrEn_Odd. For example, if WrEn_MD high activates WrEn_Even, then WrEn_MD low may activate WrEn_Odd (or vice versa).

[0092] Figure 6 is a block diagram of a spare column according to some embodiments of the present disclosure. Spare column plane 600 may, in some embodiments, represent spare column plane 212 of Figure 2, 308 of Figure 3, 452 of Figure 4, and / or 500 of Figure 5. In particular, spare column plane 500 may represent spare column plane 500, but in Figure 6, circuitry and signals related to a read operation are shown (instead of the write signals shown in Figure 5).

[0093] In FIG. 6, a read operation is being performed on one of the sections of spare column plane 600, with data being read along the GIOs. For example, section 606 may be accessed based on a row address, and a column select signal may be provided to sense amplifiers in adjacent sense amplifier regions 602 and 603. These sense amplifiers may read the data and couple the read data to their respective GIOs. Because eight bit lines are accessed, there may be eight sets of GIOs. In the example of FIG. 6, GIO<3:0> is coupled to even sense amplifier 602, and GIO<7:4> is coupled to odd sense amplifier 603.

[0094] During a read operation, eight metadata bits are accessed, including four selected bits and four unselected bits (as opposed to a write operation in which only four accessed metadata bits are accessed via a separate WrEn signal). Nevertheless, a parity bit is generated by the ECC circuit 612 during a write operation, and thus the parity bit is based only on the four selected metadata bits. To account for this, the memory can include an ECC mask circuit 610 that receives the GIO lines from the spare column plane 600 and provides one set or the other set to the ECC circuit 612 during a read operation. Which set of GIO lines is provided to the ECC circuit 612 can be based on the state of a column plane select bit in the column address (e.g., C10).

[0095] For example, if C10 indicates an even number of sense amplifiers, then ECC mask circuit 610 may provide GIO<3:0> as metadata bits MD<3:0> to ECC circuit 612. If C10 indicates an odd number of sense amplifiers, then ECC mask circuit 610 may provide GIO<7:4> as metadata bits MD<3:0> to ECC circuit 612. In this way, only selected bits are passed to ECC circuit 612 during read operations.

[0096] FIG. 7 is a block diagram of a sense amplifier region according to some embodiments of the present disclosure. Sense amplifier region 700 may, in some embodiments, represent a set of sense amplifiers including sense amplifier regions 404 and 408 (or 405 and 409) of FIG. 4 or sense amplifier region 502 or 503 of FIG. 5. FIG. 7 shows a simplified view with some components, signal lines, etc. omitted. Similarly, FIG. 7 shows a single data portion 710 along with a spare portion 720 and a GCR portion 730 all aligned next to each other, although there may be multiple data portions (e.g., 16) and any spatial arrangement of such portions (e.g., 8 data portions, a spare portion, 8 more data portions, etc.).

[0097] Sense amplifier region 700 includes a stripe of sense amplifiers 706 and portions of adjacent sections 702 and 704. A stripe of sense amplifiers 706 includes several individual sense amplifiers (not shown in FIG. 7 for clarity), each coupled to a bit line in both sections 702 and 704 (whichever is accessed, the other will act as a reference). A sense amplifier is coupled to every other bit line in sections 702 and 704, the other of which is coupled to a sense amplifier in the other stripe (not shown).

[0098] The sense amplifier area 700 includes three sections 710, 720, and 730. The first section 710 is associated with the data column plane (e.g., 210 in FIG. 2). The second section 720 is associated with the spare column plane (e.g., 212 in FIG. 2). The third section 730 is associated with the GCR column plane (e.g., 214 in FIG. 2). For each section, a respective read / write pass gate 712, 722, and 732 is shown. Each section may have several read / write pass gates (e.g., one for each LIO / GIO in this section), but for clarity, only one read / write pass gate per section is shown.

[0099] During an example read operation, data may be read along the bit lines and amplified by sense amplifiers, with column select signals determining which bit lines are coupled to their respective LIOs. Read / write pass gates 712, 722, and 732 may receive a read enable signal (not shown) that couples the data on LIOs to GIOs, so that the data can be read along GIOs to ECC (e.g., 120 in FIG. 1) and data terminals DQ.

[0100] During an example write operation, data and metadata are received, and ECC generates parity based on the data and metadata. The data, parity, and metadata are provided along the GIO lines, and read / write pass gates 712, 722, and 732 can receive respective write enable signals (WrEn or WrEn_MD). When the write enable signal is active, the data along GIO is coupled to LIO, which causes the sense amplifier to change the voltage on the bit line selected by CS, which changes the signal stored in the memory cell at the intersection of this bit line and the active word line.

[0101] A read / write pass gate 712 in the data portion 710 receives a signal WrEn. The signal WrEn may be a binary signal that is active (e.g., logic high) in a first state and inactive (e.g., logic low) in a second state. A read / write pass gate 722 in the spare portion 720 receives a signal WrEn_MD. When WrEn_MD is in a first state, the read / write pass gate 722 may be active if it is an even read / write pass gate, and when WrEn_MD is in a second state, the read / write pass gate 722 may be active if it is an odd pass gate.

[0102] Logic circuit 708 (e.g., one of logic circuits 240 in FIG. 2 ) provides WrEn or WrEn_MD to read / write pass gates 732 in GCR portion 730. For example, logic circuit 708 may be a multiplexer that provides WrEn or WrEn_MD to read / write pass gates 732. The multiplexer selects which write enable signal to provide based on a repair signal GCR_REPAIR_MD. The repair signal may be unique for each logic circuit 708 and for each read / write pass gate 732 in GCR portion 730 and may indicate whether this pass gate 732 is part of a repair operation on a column from data portion 710 or spare portion 720. If the repair signal indicates that the repair is from spare portion 720, WrEn_MD is passed and the read / write pass gate may mimic the behavior of read / write pass gate 722. If the repair signal indicates that the repair is from the data portion 710, the signal WrEn is passed and the read / write gate 732 can mimic the behavior of the read / write pass gate 712. The repair signal can be generated based on repair information stored in a fuse array (e.g., 152 in FIG. 1).

[0103] 8 is a flowchart of a method according to some embodiments of the present disclosure. Method 800 may, in some embodiments, be performed by one or more of the devices or systems disclosed herein. For example, method 800 may be performed by one or more of the systems or components of FIGS. 1-7.

[0104] Method 800 includes box 810, which recites activating a first write enable signal and a second write enable signal in response to a write operation, where the second write enable signal has a first state or a second state based on a column address. For example, the first write signal may be WrEn, while the second may be WrEn_MD. Method 800 may include determining a state of the second write enable signal based on a column plane select bit of the column address (e.g., C10).

[0105] Box 810 may be followed by box 820, which describes writing data to selected bit lines in a first column plane in response to a first write enable signal. For example, method 800 can include receiving data, providing the data along a GIO line, and coupling the GIO line to an LIO line associated with the first column plane with a transfer gate (e.g., 712 in FIG. 7) in response to the first write enable signal.

[0106] Box 830 represents a step that may occur substantially simultaneously with the step in box 820. Box 830 describes writing metadata to a first portion or a second portion of selected bit lines in a second column plane depending on the state of a second write enable signal. For example, the metadata may be provided along a GIO line, which is selectively coupled to an LIO line by a transfer gate (e.g., 722 in FIG. 7). The LIO line is coupled to selected bit lines in a second column plane (e.g., a spare column plane such as 212 in FIG. 2). The first or second portion of the transfer gate may be activated by a second write enable signal (e.g., WrEn_MD) based on its value. For example, when the second write enable signal is in a first state, an even number of the transfer gates may be activated, and thus, metadata is written to an even number of the selected bit lines. When the second write enable signal is in a second state, odd ones of the transfer gates may be activated, so that metadata is written to odd ones of the selected bit lines.

[0107] The method 800 may include generating a column select signal based on a column address and selecting bit lines in the first and second column planes based on the value of the column select signal. The method 800 may include selecting a first portion (e.g., 301 in FIG. 1 ) or a second portion (e.g., 302) of the plurality of column planes based on a column plane select bit (e.g., C10). The first column plane is in the first portion or the second portion, while the second column plane is not in either the first portion or the second portion (e.g., the second column plane is a spare column plane). The method 800 may include generating parity bits based on the received data and metadata bits and writing the parity bits to selected bit lines in a third column plane. The third column plane may be a column plane not selected by the column plane select bit.

[0108] Method 800 may include reading a first set of bits from a first portion and a second set of bits from a second portion of selected bit lines in a second column plane as part of a read operation, and selecting the first set of bits or the second set of bits (e.g., with an ECC read mask circuit, such as 610 of FIG. 6). The selection may be based on a column plane select bit (e.g., C10). Method 800 may include providing the selected one of the first set of bits or the second set of bits to an ECC circuit (e.g., 612 of FIG. 6).

[0109] Method 800 can include repairing selected bitlines in a first column plane or selected bitlines in a second column plane to selected bitlines in a global column repair (GCR) column plane. For example, method 800 can include programming addresses associated with the repaired bitlines in a fuse array (e.g., 152 in FIG. 1 ). Method 800 can include writing data to the selected bitlines in the GCR column plane in response to a first write enable signal if the selected bitlines in the first column plane are repaired, or writing metadata to a first portion or a second portion of the selected bitlines in the GCR column plane in response to a state of a second write enable signal if the selected bitlines in the second column plane are repaired. For example, logic (e.g., 240 in FIG. 2 ) can pass a first write enable signal or a second write enable signal to pass gates associated with the bitlines in the GCR column plane based on which bitlines are repaired.

[0110] 9 is a timing diagram of a mode register write operation according to some embodiments of the present disclosure. Timing diagram 900 may represent an example of how a controller (e.g., 150 in FIG. 1) may write a value to a mode register (e.g., 130 in FIG. 1) to set a mode of a memory.

[0111] Timing diagram 900 shows clock signals CK_t / CK_c (e.g., CK and / CK in FIG. 1) along with a chip select signal. The chip select signal is used to indicate that the controller is addressing this particular memory device (e.g., chip). In FIG. 6, a higher level is used to represent that the chip select signal is active, but in some embodiments, the chip select signal may be active low. Signals along the command / address bus CA and command CMD are also shown.

[0112] Timing diagram 900 shows three MRW operations occurring in sequence at times Ta0R, Tb1R, and Tc1R. Each MRW operation involves providing an address in the mode register along with the data to be written to this register along the CA bus (shown in the box marked "valid" to indicate that the value MR address and data are being provided). Two sequential MRW commands, marked MRW-1 and MRW-2, are used to indicate that the information along the CA bus is part of an MRW operation.

[0113] 10 is a flowchart of a method according to some embodiments of the present disclosure. Method 1000 may, in some embodiments, be performed by one or more of the devices or systems described herein. For example, method 1000 may be performed by controller 150 of FIG. 1.

[0114] Method 1000 includes block 1010, which describes writing a value to a mode register of a device to enable a first mode or a second mode. For example, the controller can perform an MRW operation, such as the MRW of the example of Figure 9. The first mode can be a one-pass quad operation mode in which a separate write enable signal is disabled, and the second mode can be a one-pass quad operation mode in which a separate write enable signal is enabled.

[0115] Block 1010 is followed by block 1020, which describes performing a first write operation to a memory bank of a memory device. The first write operation includes writing data and metadata to the device. For example, the controller may provide a write command along with a row, column, and bank address to the C / A terminal. The controller may provide data bits and metadata bits to the DQ terminal. For example, the controller may provide 64 data bits and 4 metadata bits. The controller may also generate a column address and provide it as part of the access operation. The column address may be generated to address an addressable portion of the memory array. For example, the column address may be generated based on a CS value desired to be addressed, and in both the first and second modes, the column address may be associated with a range of CS values ​​(e.g., CS0 to CS55) that is smaller than the range of all possible CS values ​​(e.g., CS0 to CS63).

[0116] Block 1020 may be followed by block 1030 or block 1040 depending on whether the memory device is in a first mode or a second mode. Block 1030 describes waiting at least a first period of time after a write operation when the device is in the first mode. Block 1040 describes waiting at least a second period of time after a write operation when the device is in the second mode. The first time may be at least tCCD_L_WR. The second period of time may be less than tCCD_L_WR. In some embodiments, method 1000 may include waiting the first or second period of time before accessing a different bank within the same bank group.

[0117] Blocks 1030 and 1040 may be followed by block 1050, which describes performing a second write operation to the memory bank. The second write operation may be generally similar to the first write operation described with respect to block 1020. In the first mode, the controller may wait at least a first period between the first and second write operations, and in the second mode, the controller may wait at least a second period between the first and second write operations.

[0118] The method 1000 can include reading data and metadata from the memory array as part of a read operation. Because both modes can enable the memory to operate with a SECDED ECC scheme, the method 1000 can include receiving a signal from the memory indicating that a double-bit error has been detected (but not corrected) in the data and metadata. The first or second write operation can include, when the device is in the first mode, reading metadata from a spare column plane by activating a column select signal, modifying some of the read metadata with newly written metadata, and writing back the modified metadata. The first or second write operation can include, when the device is in the second mode, activating a write enable signal associated with some (but not all) of the column lines associated with the column select signal, and writing the metadata only to the column lines selected by the write enable signal.

[0119] In some embodiments, the controller can write a value to a mode register to set the memory in a third mode (eg, two-pass mode).

[0120] Of course, it should be recognized that any one of the examples, embodiments, or processes described herein may be combined with one or more other examples, embodiments, and / or processes, or may be separated and / or implemented among separate devices or device portions in accordance with the present systems, devices, and methods.

[0121] Finally, the above discussion is intended to be merely illustrative of the present system and should not be construed as limiting the scope of the appended claims to any particular embodiment or group of embodiments. Accordingly, while the present system has been described in particular detail with reference to exemplary embodiments, it should also be recognized that numerous modifications and alternative embodiments may be devised by those skilled in the art without departing from the broader and intended spirit and scope of the present system, as set forth in the following claims. Accordingly, the specification and drawings should be evaluated in an illustrative manner and are not intended to limit the scope of the appended claims.

Claims

1. a first column plane including a first plurality of bit lines; a second column plane including a second plurality of bit lines; an input / output circuit configured to receive data and metadata as part of a write operation, the data being written to the first plurality of bitlines and the metadata being written to even or odd ones of the second plurality of bitlines; and An apparatus comprising:

2. 2. The apparatus of claim 1, further comprising: a column decoder configured to provide a column select signal based on the column address, the first plurality of bit lines and the second plurality of bit lines being activated by the same value of the column select signal.

3. a column decoder configured to provide a first write enable signal and a second write enable signal, wherein the data is written to the first plurality of bit lines in response to the first write enable signal, the even or odd ones of the second plurality of bit lines are selected based on a value of the second write enable signal, and the metadata is written to the selected ones of the even or odd ones of the second plurality of bit lines. The apparatus of claim 1 further comprising:

4. a global column repair (GCR) column plane including multiple redundant bitlines; a fuse array configured to remap the first plurality of bit lines or the second plurality of bit lines to the plurality of redundant bit lines, wherein when the first plurality of bit lines are remapped to the plurality of redundant bit lines, the data is written to the plurality of redundant bit lines, and when the second plurality of bit lines are remapped to the plurality of redundant bit lines, the metadata is written to even or odd ones of the plurality of redundant bit lines. The apparatus of claim 1 further comprising:

5. 5. The apparatus of claim 4, further comprising: logic circuitry configured to provide a first write enable signal if the first plurality of bit lines are remapped to the plurality of redundant bit lines, and to provide a second write enable signal if the second plurality of bit lines are remapped to the plurality of redundant bit lines.

6. a third column plane including a third plurality of bit lines; an error correction code (ECC) circuit configured to receive the data and the metadata and generate a parity bit based on the metadata as part of the write operation, the parity bit being written to the third plurality of bit lines; and The apparatus of claim 1 further comprising:

7. 7. The apparatus of claim 6, further comprising an ECC mask circuit configured to receive a set of bits comprising the metadata from the second plurality of bit lines as part of a read operation, and configured to provide an even or odd number of the set of bits to the ECC circuit.

8. activating a first write enable signal and a second write enable signal in response to a write operation, the second write enable signal having a first state or a second state based on a column address; writing data to selected bit lines in a first column plane in response to the first write enable signal; writing metadata to a first portion or a second portion of selected bit lines in a second column plane in response to the state of the second write enable signal; A method comprising:

9. 9. The method of claim 8, wherein the first portion is an even number of the selected bit lines and the second portion is an odd number of the selected bit lines.

10. generating a column select signal with a value based on the column address; selecting the selected bit lines in the first column plane and the selected bit lines in the second column plane based on the value of the column select signal; 9. The method of claim 8, further comprising:

11. generating parity bits based on the data and the metadata; writing the parity bit to selected bit lines in a third column plane; 9. The method of claim 8, further comprising:

12. 9. The method of claim 8, further comprising selecting a first portion or a second portion of a plurality of column planes based on a column plane select bit of the column address, wherein the first column plane is in the first portion or the second portion and the second column plane is not in either the first portion or the second portion.

13. reading a first set of bits from the first portion and a second set of bits from the second portion of the selected bit lines in the second column plane as part of a read operation; selecting the first set of bits or the second set of bits; providing the selected one of the first set of bits or the second set of bits to an error correcting code (ECC) circuit; 9. The method of claim 8, further comprising:

14. Repairing the selected bitlines in the first column plane or the selected bitlines in the second column plane to selected bitlines in a global column repair (GCR) column plane; writing the data to the selected bit lines in the GCR column plane in response to the first write enable signal if the selected bit lines in the first column plane are repaired; writing the metadata to a first portion or a second portion of the selected bitline in the GCR column plane according to the state of the second write enable signal if the selected bitline in the second column plane is repaired; 9. The method of claim 8, further comprising:

15. a first local input / output (LIO) line coupled to the first read / write transfer gate; a second LIO line coupled to the second read / write transfer gate; a first column plane comprising: a third LIO line coupled to the third read / write transfer gate; a fourth LIO line coupled to the fourth read / write transfer gate; a second column plane comprising: a column decoder configured to provide a first write enable signal to the first column plane and a second write enable signal to the second column plane, the first and second read / write transfer gates being activated by the first write enable signal and the third or fourth read / write transfer gate being activated by the second write enable signal; An apparatus comprising:

16. the first column plane: a first plurality of bit lines, selected ones of which are coupled to the first LIO lines; a second plurality of bit lines, selected ones of which are coupled to the second LIO lines; and wherein the second column plane is a third plurality of bit lines, selected ones of which are coupled to the third LIO lines; a fourth plurality of bit lines, selected ones of which are coupled to the fourth LIO lines; 16. The apparatus of claim 15, further comprising:

17. 17. The apparatus of claim 16, wherein the selected ones of the first, second, third, and fourth pluralities of bit lines are selected by the same value of a column select signal.

18. an error correction code (ECC) circuit; an ECC mask circuit configured to receive a first bit from the third read / write transfer gate and a second bit from the fourth read / write transfer gate and to provide the first bit or the second bit to the ECC circuit; 16. The apparatus of claim 15, further comprising:

19. a fifth LIO line coupled to the fifth read / write transfer gate; and a logic circuit configured to provide the first write enable signal or the second write enable signal to the fifth read / write transfer gate; a third column plane comprising:

16. The apparatus of claim 15, further comprising:

20. 20. The apparatus of claim 19, wherein the logic circuit is configured to provide the first write enable signal when the first or second LIO line is repaired to the fifth LIO line, and the logic circuit is configured to provide the second write enable signal when the third or fourth LIO line is repaired to the fifth LIO line.

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