Stacked FET with extremely small cell height

Abstract

A microelectronic structure includes a first stacked FET device including a first bottom FET device and a first top FET device. The first bottom FET device includes a plurality of first bottom channel layers, and the first top FET device includes a plurality of first top channel layers. A bottom gate surrounding the plurality of first bottom channel layers and an top gate surrounding the plurality of first top channel layers. A gate protrusion extending downward from a backside of the top gate and connected to the bottom gate. The gate protrusion partially overlaps a bottom gate cut region of the first bottom stacked FET device, and the gate protrusion partially overlaps a top gate cut region of the first top stacked FET device.

Description

[Technical Field]

[0001] The present invention relates generally to the field of microelectronics, and more particularly to the formation of stacked transistors and the formation of the necessary contacts.

[0002] Nanosheets are the dominant device architecture in continued CMOS scaling. However, nanosheet technology has shown challenges with scaling down, such as interference between devices as they become smaller and closer together. While device density can be increased by stacking devices, forming contacts to the devices is difficult due to the limited space between them. Summary of the Invention

[0003] Additional aspects and / or advantages will be set forth in part in the description that follows, and in part will be obvious from the description, or may be learned by practice of the invention.

[0004] A microelectronic structure includes a first stacked FET device including a first bottom FET device and a first top FET device. The first bottom FET device includes a plurality of first bottom channel layers, and the first top FET device includes a plurality of first top channel layers. A bottom gate surrounding the plurality of first bottom channel layers and an top gate surrounding the plurality of first top channel layers. A gate protrusion extending downward from a backside of the top gate and connected to the bottom gate. The gate protrusion partially overlaps a bottom gate cut region of the first bottom stacked FET device, and the gate protrusion partially overlaps a top gate cut region of the first top stacked FET device.

[0005] A microelectronic structure includes a first stacked FET device including a first bottom FET device and a first top FET device. The first bottom FET device includes a plurality of first bottom channel layers, and the first top FET device includes a plurality of first top channel layers. The first bottom FET device includes first and second source / drains, and the first top FET device includes third and fourth source / drains. The third and fourth source / drains have asymmetric profiles. The asymmetric shapes of the third and fourth source / drains are each composed of a narrow section and a wide section. Dielectric liners are positioned on sidewalls of the third and fourth source / drains, respectively.

[0006] A method includes forming a first stacked FET device including a first bottom FET device and a first upper FET device, wherein the first bottom FET device includes a plurality of first bottom channel layers and the first upper FET device includes a plurality of first upper channel layers. The first bottom FET device includes first and second source / drains, and the first upper FET device includes a third and fourth source / drains. Forming dielectric liners positioned on sidewalls of the third and fourth source / drains, respectively. The dielectric liner has a first vertical segment positioned on a first side of the third source / drain, and the dielectric liner has a second vertical segment positioned on a second side of the third source / drain. Forming a second stacked FET device positioned parallel to the first stacked FET device, wherein the second stacked FET device includes a second bottom FET device and a second upper FET device, wherein the second bottom FET device includes a plurality of second bottom channel layers and the second upper FET device includes a plurality of second upper channel layers. The second bottom FET device includes a fifth source / drain, and the second top FET device includes a sixth source / drain. Forming a first source / drain contact connected to the backside surface of the first source / drain. Forming a second source / drain contact connected to the third source / drain, the second source / drain contact consisting of a first section and a second section. The first section is connected to the top surface and sidewall of the third source / drain, and the second section is a via extending to the backside of the stacked FET device. Forming a third source / drain contact connected to the eighth source / drain, the third source / drain consisting of a third section and a fourth section. The third section is a via extending from the second top device to the second bottom device, and the fourth section extends horizontally from the third section across the top surface of the fifth source / drain. [Brief explanation of the drawings]

[0007] These and other aspects, features, and advantages of certain exemplary embodiments of the present invention will become more apparent from the following description read in conjunction with the accompanying drawings.

[0008] [Figure 1] 1 shows a top view of a plurality of nanodevices according to an embodiment of the present invention.

[0009] [Figure 2] 10 shows cross section X of a nanostack after formation of a bottom device, according to an embodiment of the present invention.

[0010] [Figure 3] 10 shows cross section Y1 of the gate region after formation of the bottom device according to an embodiment of the present invention.

[0011] [Figure 4] 10 shows cross section Y2 of the source / drain region after formation of the bottom device according to an embodiment of the present invention.

[0012] [Figure 5] 10 shows cross section X of the nanostack after formation of a second placeholder and formation of an upper nanolayer, according to an embodiment of the present invention.

[0013] [Figure 6] 10 shows a cross section Y1 of the gate region after formation of a second placeholder and formation of an upper nano-layer according to an embodiment of the present invention.

[0014] [Figure 7] 10 shows a cross section Y2 of the source / drain region after formation of a second placeholder and formation of an upper nano-layer according to an embodiment of the present invention.

[0015] [Figure 8] 1 shows cross section X of a nanostack after patterning an upper nanolayer, forming a dummy gate, forming an upper inner spacer, forming a top upper spacer, forming an upper source / drain, and forming a second interlayer dielectric layer according to an embodiment of the present invention.

[0016] [Figure 9] Cross section Y1 of the gate region after patterning of the upper nanolayer, forming a dummy gate, forming an upper inner spacer, forming a top upper spacer, forming an upper source / drain, and forming a second interlayer dielectric layer according to an embodiment of the present invention.

[0017] [Figure 10] Cross section Y2 of the source / drain region after patterning the upper nanolayer, forming a dummy gate, forming an upper inner spacer, forming a top upper spacer, forming an upper source / drain, and forming a second interlayer dielectric layer according to an embodiment of the present invention is shown.

[0018] [Figure 11] 10 shows cross section X of the nanostack after removal of the sacrificial layer and dummy gate and formation of a dielectric liner according to an embodiment of the present invention.

[0019] [Figure 12] 10 shows cross section Y1 of the gate region after removal of the sacrificial layer and dummy gate and formation of a dielectric liner according to an embodiment of the present invention.

[0020] [Figure 13] 10 shows cross section Y2 of the source / drain region after removal of the sacrificial layer and dummy gate and formation of a dielectric liner in accordance with an embodiment of the present invention.

[0021] [Figure 14] 10 shows cross section X of a nanostack after formation of an upper sacrificial layer and formation of a gate trench, according to an embodiment of the present invention.

[0022] [Figure 15] 10 shows cross section Y1 of the gate region after formation of an upper sacrificial layer and formation of a gate trench according to an embodiment of the present invention.

[0023] [Figure 16]10 shows cross section Y2 of the source / drain region after formation of an upper sacrificial layer and formation of a gate trench according to an embodiment of the present invention.

[0024] [Figure 17] 10 shows cross section X of the nanostack after removal of the upper sacrificial layer, according to an embodiment of the present invention.

[0025] [Figure 18] 10 shows cross section Y1 of the gate region after removal of the upper sacrificial layer, according to an embodiment of the present invention.

[0026] [Figure 19] 10 shows cross section Y2 of the source / drain region after removal of the upper sacrificial layer according to an embodiment of the present invention.

[0027] [Figure 20] 10 shows cross section X of a nanostack after formation of an upper gate and an upper gate cut, according to an embodiment of the present invention.

[0028] [Figure 21] 10 shows a cross section Y1 of the gate region after formation of an upper gate and an upper gate cut according to an embodiment of the present invention.

[0029] [Figure 22] 10 shows cross section Y2 of the source / drain region after formation of the upper gate and upper gate cut according to an embodiment of the present invention.

[0030] [Figure 23] 10 shows cross section X of the nanostack after formation of an additional second interlayer dielectric and formation of a contact trench, according to an embodiment of the present invention.

[0031] [Figure 24] 10 shows cross section Y1 of the gate region after forming an additional second interlayer dielectric and forming a contact trench according to an embodiment of the present invention.

[0032] [Figure 25] 10 shows cross section Y2 of the source / drain region after formation of an additional second interlayer dielectric and contact trenches according to an embodiment of the present invention.

[0033] [Figure 26] 10 shows cross section X of the nanostack after removal of the second placeholder, according to an embodiment of the present invention.

[0034] [Figure 27] 10 shows cross section Y1 of the gate region after removal of the second placeholder, according to an embodiment of the present invention.

[0035] [Figure 28] 10 shows a cross section Y2 of the source / drain region after removal of the second placeholder, according to an embodiment of the present invention.

[0036] [Figure 29] 1 shows cross section X of the nanostack after formation of contacts, metal lines, and additional layers, according to an embodiment of the present invention.

[0037] [Figure 30] 1 shows cross section Y1 of the gate region after formation of contacts, metal lines, and additional layers according to an embodiment of the present invention.

[0038] [Figure 31] 10 shows cross section Y2 of the source / drain region after formation of contacts, metal lines, and additional layers according to an embodiment of the present invention.

[0039] [Figure 32] 1 shows cross section X of the nanostack after removal of the first substrate, etch stop, and second substrate, according to an embodiment of the present invention.

[0040] [Figure 33] 10 shows cross section Y1 of the gate region after removal of the first substrate, etch stop, and second substrate according to an embodiment of the present invention.

[0041] [Figure 34] 10 shows cross section Y2 of the source / drain region after removal of the first substrate, etch stop, and second substrate according to an embodiment of the present invention.

[0042] [Figure 35] 10 shows cross section X of the nanostack after formation of a backside interlayer dielectric layer and a chemical mechanical planarization process to expose the backside surface of the backside via contact, according to an embodiment of the invention.

[0043] [Figure 36] 10 shows cross section Y1 of the gate region after forming a backside interlayer dielectric layer and a chemical mechanical planarization process to expose the backside surface of the backside via contact, according to an embodiment of the present invention.

[0044] [Figure 37] 10 shows cross section Y2 of the source / drain region after formation of a backside interlayer dielectric layer and a chemical mechanical planarization process to expose the backside surface of the backside via contact, according to an embodiment of the present invention.

[0045] [Figure 38] 10 shows cross section X of the nanostack after removal of the first placeholder and formation of a backside contact, according to an embodiment of the present invention.

[0046] [Figure 39] 10 shows cross section Y1 of the gate region after removal of the first placeholder and formation of a backside contact according to an embodiment of the present invention.

[0047] [Figure 40] 10 shows cross section Y2 of the source / drain region after removal of the first placeholder and formation of the backside contact according to an embodiment of the present invention.

[0048] [Figure 41]10 shows cross section X of a nanostack after formation of backside metal lines and backside electrical distribution networks, according to an embodiment of the present invention.

[0049] [Figure 42] 10 shows cross section Y1 of the gate region after backside metal line formation and backside distribution network formation according to an embodiment of the present invention.

[0050] [Figure 43] 10 shows cross section Y2 of the source / drain region after backside metal line formation and backside distribution network formation according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0051] The following description, which refers to the accompanying drawings, is provided to assist in a comprehensive understanding of exemplary embodiments of the present invention, as defined by the claims and their equivalents. Although various specific details are included to facilitate understanding, these are considered to be merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications to the embodiments described herein can be made without departing from the scope of the present invention. Also, for clarity and conciseness, descriptions of well-known functions and structures may be omitted.

[0052] The terms and phrases used in the following description and claims are not intended to be limited to their literary meanings, but are merely used to facilitate a clear and consistent understanding of the present invention. Therefore, it should be apparent to those skilled in the art that the following description of exemplary embodiments of the present invention is provided for illustrative purposes only and is not intended to limit the present invention, which is defined by the appended claims and their equivalents.

[0053] The singular forms "a," "an," and "the" are understood to include plural referents unless the context clearly indicates otherwise. Thus, for example, a reference to a "component surface" includes a reference to one or more of such surfaces unless the context clearly indicates otherwise.

[0054] Although detailed embodiments of the claimed structures and methods are disclosed herein, it should be understood that the disclosed embodiments are merely exemplary of the claimed structures and methods, which may be embodied in various forms. The present invention may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the present embodiments.

[0055] References herein to "one embodiment," "an embodiment," "an example embodiment," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but that not all embodiments may include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Furthermore, it is submitted that those skilled in the art will recognize that when a particular feature, structure, or characteristic is described in connection with one embodiment, it also affects such feature, structure, or characteristic in connection with other embodiments, whether or not explicitly described.

[0056] For purposes of the following description, the terms "upper," "lower," "right," "left," "vertical," "horizontal," "top," "bottom," and derivatives thereof, shall refer to the disclosed structures and methods as oriented in the drawings. The terms "overlying," "atop," "on top," "positioned on," or "positioned atop" mean that a first element, such as a first structure, is above a second element, such as a second structure, although an intervening element, such as an interface structure, may be present between the first and second elements. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without an intermediate conductive, insulating, or semiconducting layer at the interface of the two elements.

[0057] In the following detailed description, some process steps or operations known in the art may be combined together for purposes of presentation and illustration, and in some cases may not be described in detail, so as not to obscure the presentation of embodiments of the present invention. In other instances, some process steps or operations known in the art may not be described at all. It should be understood that the following description will instead focus on distinctive features or elements of various embodiments of the present invention.

[0058] Various embodiments of the present invention are described herein with reference to the associated drawings. Alternative embodiments may be devised without departing from the scope of the present invention. It should be noted that the following description and drawings describe various connections and relationships (e.g., above, below, adjacent, etc.) between elements. These connections and / or relationships may be direct or indirect unless otherwise specified, and the present invention is not intended to be limited in this respect. Thus, a connection between entities may refer to a direct or indirect connection, and a relationship between entities may be a direct or indirect relationship. As an example of an indirect relationship, reference in this description to forming layer "A" on layer "B" includes a situation in which one or more intermediate layers (e.g., layer "C") are between layers "A" and "B," as long as the relative properties and functionality of layers "A" and "B" are not substantially altered by the intermediate layer(s).

[0059] The following definitions and abbreviations should be used in interpreting the claims and the specification. As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," "contains," or "containing," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a complex, mixture, process, method, article, or device that includes a list of elements is not necessarily limited to only those elements but can include other elements not expressly listed or that are inherent in such complex, mixture, process, method, article, or device.

[0060] Additionally, the word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" may be understood to include any integer greater than or equal to one, i.e., one, two, three, four, etc. The term "a plurality" may be understood to include any integer greater than or equal to two, i.e., two, three, four, five, etc. The term "connection" may include both an indirect and a direct connection.

[0061] As used herein, the term "about" modifying the amount of a component, ingredient, or reactant of the present invention employed refers to variations in numerical values ​​that may occur, for example, through typical measuring and liquid handling procedures used to create concentrations or solutions. Additionally, variations may arise from inadvertent errors in measuring procedures, differences in the production, source, or purity of components employed to make compositions or perform methods, and the like. The terms "about" or "substantially" are intended to include the degree of error associated with measuring a particular quantity based on equipment available at the time of filing. For example, "about" can include a range of ±8%, 5%, or 2% of a given value. In another embodiment, the term "about" means within 5% of the reported numerical value. In another embodiment, the term "about" means within 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, or 1% of the reported numerical value.

[0062] The various processes used to form microchips that will be packaged into integrated circuits (ICs) fall into four general categories: film deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition is any process that grows, coats, or otherwise transfers material onto a wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD), among others. Removal / etching is any process that removes material from the wafer. Examples include etching processes (wet or dry), reactive ion etching (RIE), and chemical-mechanical planarization (CMP), and the like. Semiconductor doping is the modification of electrical properties by doping the source and drain of a transistor, for example, typically by diffusion and / or ion implantation. These doping steps are followed by furnace annealing or rapid thermal annealing (RTA). The annealing serves to activate the implanted dopants. Films of both conductors (e.g., aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and separate electrical components. Selective doping of various regions of a semiconductor substrate allows the conductivity of the substrate to be changed by applying a voltage.

[0063] Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. The present invention is directed to the formation of stacked devices. The width of the nanosheets of the upper device is narrower than the width of the nanosheets of the lower device. The narrower width of the upper device provides space for forming contacts to the lower device. However, narrowing the space of the upper device narrows the upper source / drain, limiting the amount of surface area available for connecting to the source / drain contacts. By blowing off one of the sidewalls of the spacer / liner prior to forming the source / drain, the source / drain can expand in the blown direction. This increases the surface area of ​​the source / drain available for forming connections to the source / drain contacts.

[0064] 1 shows a top view of multiple devices according to an embodiment of the present invention. Cross section X extends horizontally through one nanostack of the stacked device. Cross section Y1 is perpendicular to cross section X, where cross section Y1 passes through a gate region spanning multiple nanostacks. Cross section Y2 is perpendicular to cross section X, where cross section Y2 passes through a source / drain region of multiple nanostacks.

[0065] 2, 3, and 4 illustrate processing stages after formation of a bottom device, which includes a first substrate 105, an etch stop 106, a second substrate 108, a first placeholder 130, a bottom dielectric isolation (BDI) layer 110, a plurality of channel layers 114, inner spacers 116, upper spacers 120, a gate 125, a bottom source / drain 135, and a first interlayer dielectric layer 140.

[0066] The first substrate 105 and the second substrate 108 may be made of a material including, but not limited to, silicon (Si), silicon germanium (SiGe), Si:C (carbon-doped silicon), carbon-doped silicon germanium (SiGe:C), III-V, II-V compound semiconductors, or other similar semiconductors. Multiple layers of semiconductor material may also be used as the semiconductor material of the first substrate 105 and the second substrate 108. In some embodiments, the first substrate 105 and the second substrate 108 include both semiconductor and dielectric materials. The semiconductor first substrate 105 and the second substrate 108 may also include layered semiconductors or organic semiconductors, such as Si / SiGe, silicon-on-insulator, or SiGe-on-insulator. Part or all of the semiconductor first substrate 105 and the second substrate 108 may be amorphous, polycrystalline, or single-crystalline. The semiconductor first substrate 105 and second substrate 108 may be doped or undoped, or may include doped and undoped regions therein.

[0067] The inner spacers 116 are positioned adjacent to (close to) the gates 125 and positioned above / below the channel layers 114. The channel layers 114 may be made of, for example, Si. The gates 125 are positioned around each of the channel layers 114 and positioned between sections of the upper spacer 120. The gates 125 may be made of, for example, HfO2, ZrO2, HfL a O x The gate dielectric liner may be composed of a high-k dielectric such as TiN, TiAlC, TiC, etc., and a work function layer such as TiN, TiAlC, TiC, etc., and a conductive metal filler such as W.

[0068] The gate region is composed of a gate 125, multiple channel layers 114, inner spacers 116, upper spacers 120, and a BDI layer 110. Figure 2 shows multiple gate regions (columns). A source / drain 135 is positioned between each of the gate regions, where the source / drain 135 may be positioned on the BDI layer 110 or the source / drain 135 may be positioned on a first placeholder 130. The first placeholder 130 extends downward into the second substrate 108. A first interlayer dielectric layer 140 is positioned on the source / drain 135.

[0069] The source / drain 135 may be, for example, n-type epitaxy or p-type epitaxy. For n-type epitaxy, an n-type dopant selected from the group consisting of phosphorus (P), arsenic (As), and / or antimony (Sb) may be used. For p-type epitaxy, a p-type dopant selected from the group consisting of boron (B), gallium (Ga), indium (In), and / or thallium (Tl) may be used. Other doping techniques may be used, such as ion implantation, gas-phase doping, plasma doping, plasma immersion ion implantation, cluster doping, implant doping, liquid-phase doping, solid-phase doping, and / or any suitable combination of these techniques. In some embodiments, the dopant is activated by thermal annealing, such as laser annealing, flash annealing, rapid thermal annealing (RTA), or any suitable combination of these techniques.

[0070] FIG. 3 shows a cross section across the gate region. Portions of the second substrate 108 are removed during etching of the nanodevices. These sections are filled with shallow trench isolation layers 145. Gates 125 surround each of the channel layers 114. Multiple bottom gate cuts 150 are formed in the gates 125. The bottom gate cuts 150 are formed on the shallow trench isolation layers 145. The bottom gate cuts 150 separate the gates 125 into multiple different bottom devices. FIG. 4 shows a cross section across the source / drain region. Portions of the BDI layer 145 are formed as vertical segments and serve as a frame to house the source / drains 135. The BDI layer 110 can extend below the source / drains 135, or the bottom sections of the BDI layer 110 are removed during the formation of the first placeholders 130.

[0071] 5, 6, and 7 show processing steps after the formation of the second placeholder and the upper nano-layer. Portions of the first interlayer dielectric layer 140 are removed to create trenches (not shown). These trenches are filled with, for example, TiO x , AlO x 7, the backside via contact 170 is formed by creating a trench (not shown) in the first interlayer dielectric layer 140 and the shallow trench isolation layer 145 and filling the trench with a conductive metal such as Ru, Co, or W. The backside via contact 170 extends downward between the bottom source / drains 135A and 135B, such that the backside via contact 170 extends downward into the shallow trench isolation layer 145. The backside via contact 170 may abut a vertical segment of the BDI layer 110, or a portion of the first interlayer dielectric layer 140 may be positioned between the backside via contact 170 and the vertical segment of the BDI layer 110.

[0072] Half of the junction oxide 160 is formed on the upper spacer 120, the gate 125, the first interlayer dielectric layer 140, the second placeholders 155A, 155B, the bottom gate cut 150, and the backside via contact 170. The other half of the junction oxide is formed on another substrate including an alternative Si / SiGe epitaxial stack on a Si substrate (not shown). The two wafers are then bonded in an oxide-to-oxide bonding process. After wafer bonding, the Si substrate of the top wafer is removed. Thus, an upper nanolayer is formed on the junction oxide 160. The upper nanolayer includes alternating layers of a sacrificial layer 164 and an upper channel layer 166. The sacrificial layer 164 may be composed of SiGe, where Ge is in the range of approximately 15% to 35%. The upper channel layer 166 may be composed of, for example, Si.

[0073] 8, 9, and 10 illustrate processing stages after patterning the upper nanolayer, forming the dummy gate 177, the upper inner spacer 172, the top upper spacer 175, the upper source / drain 180, 180A, 180B, and forming the second interlayer dielectric layer 185. The upper nanolayer is patterned to form multiple nanocolumns (gate regions), as shown in FIG. 8. The upper channel layer 166 is narrower than the channel layer 114 of the bottom device, as shown in FIG. 9. The narrower width of the upper channel layer 166 enables the formation of shared gate and source / drain contacts. The sacrificial layer 164 is recessed to create space for the formation of the upper inner spacer 172. The top upper spacer 175 is formed on the upper channel layer 166, and the dummy gate 177 is formed between sections of the top upper spacer 175 and is positioned above the upper channel layer 166.

[0074] The upper source / drains 180, 180A, 180B are formed between the nanocolumns. The upper source / drains 180, 180A, 180B can be, for example, n-type epitaxy or p-type epitaxy. For n-type epitaxy, n-type dopants selected from the group consisting of phosphorus (P), arsenic (As), and / or antimony (Sb) can be used. For p-type epitaxy, p-type dopants selected from the group consisting of boron (B), gallium (Ga), indium (In), and / or thallium (Tl) can be used. Other doping techniques can be used, such as ion implantation, gas-phase doping, plasma doping, plasma immersion ion implantation, cluster doping, implantation doping, liquid-phase doping, solid-phase doping, and / or any suitable combination of these techniques. In some embodiments, the dopants are activated by thermal annealing, such as laser annealing, flash annealing, rapid thermal annealing (RTA), or any suitable combination of these techniques. A second interlayer dielectric layer 185 is formed over the upper source / drains 180, 180A, 180B.

[0075] As shown in FIG. 9, a dummy gate 177 surrounds three sides of the nanostack column. The dummy gate 177 is formed on the junction oxide 160. As shown in FIG. 10, source / drain liners 190 are formed to accommodate the upper source / drains 180, 180A, and 180B, where the source / drain liners 190 allow for asymmetric formation of the upper source / drains 180, 180A, and 180B. The source / drain liners 190 allow for the formation of narrow and wide sections of the upper source / drains 180, 180A, and 180B, respectively. One of the source / drain liners 190 is pulled down (blown away) to create a short source / drain liner 190S and a long source / drain liner 190L. The long source / drain liner 190L and the short source / drain liner 190S have different vertical heights, such that the vertical height of the long source / drain liner 190L is greater than the vertical height of the short source / drain liner 190S. During formation of the upper source / drains 180, 180A, 180B, the short source / drain liner 190S allows the upper source / drains 180, 180A, 180B to expand horizontally above the short source / drain liner 190S. This horizontal expansion of the upper source / drains 180, 180A, 180B increases the surface area of ​​the upper source / drains 180, 180A, 180B for forming contacts. The portions of the upper source / drains 180, 180A, 180B sandwiched between the short source / drain liner 190S and the long source / drain liner 190L have a first width. The upper source / drain 180, 180A, 180B positioned adjacent to the long source / drain liner 190L and above the short source / drain liner 190S has a second width, where the second width is greater than the first width. As seen in Figure 10, a second interlayer dielectric layer 185 is formed over the junction oxide 160 and around the source / drain liner 190 and the upper source / drain 180, 180A, 180B.

[0076] 11, 12, and 13 show the processing stage after removal of the sacrificial layer and dummy gate and formation of gate dielectric liner 195. The sacrificial layer 164 and dummy gate 177 are removed. On the exposed surfaces of these different layers, gate dielectric liner 195 is formed. Gate dielectric liner 195 can be, for example, HfO2, ZrO2, HfAlO x , HfL a O x It may be made of a high dielectric constant dielectric material such as

[0077] 14, 15, and 16 illustrate processing steps after the formation of the upper sacrificial layer 200 and the formation of the gate trench 205. As shown, the upper sacrificial layer 200, comprised of, for example, TiN / a-Si, is formed on the exposed surface. A gate trench 205 is formed in the upper sacrificial layer 200, the dielectric liner 195, the junction oxide 160, and the bottom gate cut 150. The gate trench 205 enables the formation of a shared gate between the gate 125 positioned around the bottom device periphery and the upper gate (discussed in more detail below). The gate trench 205 exposes a portion of the top surface of the gate 125 and a portion of the sidewall of the gate 125. Because the gate trench 205 removes a portion of the bottom gate cut 150, the gate trench 205 exposes a portion of the sidewall of the gate 125. The width of the upper channel 166 is smaller than the width of the channel layer 114 , and the smaller width of the upper channel 166 leaves room for forming the gate trench 205 .

[0078] 17, 18, and 19 show the processing stage after removal of the upper sacrificial layer 200. Removal of the upper sacrificial layer 200 exposes the dielectric liner 195. A portion of the gate trench 205 remains in the junction oxide 160 and bottom gate cut 150. The gate trench 205 creates a path connecting the gate 125 and the space surrounding the upper device. When gate material is added to the upper device, the gate trench 205 will be filled with gate material, connecting the gate 125 with the gate of the upper device (discussed in more detail below).

[0079] 20, 21, and 22 illustrate processing stages after the formation of the upper gate 210 and upper gate cut 215. The upper channel 166 and the dielectric liner 195 are surrounded by the upper gate 210. The gate trench 205 is filled with the material of the upper gate 210 (e.g., to form a protrusion) so that the upper gate 210 directly contacts the top surface and sidewalls of the gate 125 of one of the bottom devices, as highlighted by the dashed box 212. The upper gate 210 may be composed of a work function layer, such as TiN, TiAlC, TiC, etc., and a conductive metal fill material, such as W. A trench (not shown) is formed in the upper gate 210, where the trench is positioned above the dielectric liner 195 and the junction oxide 160. A portion of the trench may extend above a portion of where the gate trench 205 is positioned. The trench is filled with a dielectric material to form the upper gate cut 215. A top gate cut 215 separates the top nanostack (gate region) into multiple different top devices (gate regions). Dashed box 212 highlights a section (e.g., a protrusion) of the top gate 210 positioned around one of the top devices, where the protrusion is connected to the sidewall and front surface of the gate 125 positioned around one of the bottom devices. Dashed box 213 highlights a shared gate device, as the top gate 210 of the top device is connected to the gate 125 of the bottom device via a connection through the junction oxide 160 (highlighted by dashed box 212).

[0080] 23, 24, and 25 illustrate processing stages after the formation of the additional second interlayer dielectric layer 185 and the formation of contact trenches 220, 225, 230, and 235. Additional second interlayer dielectric layer material is formed over the upper gate 210, the upper gate cut 215, the top upper spacer 175, and the second interlayer dielectric layer 185. Different contact trenches are formed in different layers to expose different elements. As shown in FIG. 23, a first contact trench 220 and a second contact trench 225 are formed in the second interlayer dielectric layer 185 to expose the top surface of the upper source / drain 180A and the top surface of the upper source / drain 180. FIG. 25 illustrates the first contact trench 220, the third contact trench 230, and the fourth contact trench 235. The first contact trench 220 has two sections, where the first section exposes the top and side surfaces of the upper source / drain 180A. The first contact trench 220 also exposes a portion of the long source / drain liner 190L. The blown-out section of the upper source / drain 180A increases the surface area of ​​the upper source / drain 180A exposed by the first contact trench 220. The second section of the first contact trench 220 is a via that extends downward through the junction oxide 160 and exposes the top surface of the backside via contact 170. The third contact trench 230 exposes the top and side surfaces of the upper source / drain 180B. The third contact trench 230 does not expose the portion of the long source / drain liner 190L. The fourth contact trench 235 extends down through the second interlevel dielectric layer 185 and the junction oxide 160 to expose the surface of the second placeholder 155B.

[0081] 26, 27, and 28 show processing stages after removal of the second placeholders 155A and 155B. The second placeholders 155A and 155B are removed. A fourth contact trench 235 exposes the surface of the second placeholder 155B, allowing material removal. Another contact trench (not shown) connects to the second placeholder 155A, allowing its removal. Removal of the second placeholder 155A forms a first cavity 237, which is positioned above the bottom source / drain 135. The first cavity 237 exposes the top surface of the bottom source / drain 135. As shown in FIG. 28, removal of the second placeholder 155B forms a second cavity 238. The second cavity 238 is connected to the fourth contact trench 235. The second cavity 238 extends horizontally, exposing the top surface of the bottom source / drain 135B.

[0082] 29, 30, and 31 illustrate processing stages after the formation of contacts, metal lines, and additional layers. The contact trenches 220, 225, 230, and 235, the first cavity 237, and the second cavity 238 are filled with a conductive metal to form multiple contacts. Filling the first contact trench 220 forms a first contact 240A. The first contact 240A is connected to the top surface of the backside via contact 170. Filling the second contact trench 225 forms a second contact 240B. Filling the third contact trench 230 forms a third contact 240C. Filling the fourth contact trench 235 and the second cavity 238 forms a fourth contact 240D. The fourth contact 240D has a downward-facing via section and a bottom horizontal section that extends across the top surface of the bottom source / drain 135B. A fifth contact 240D2 is formed by filling the trench (not shown) and the first cavity 237. A dielectric layer 245 is formed on the second interlayer dielectric layer 185 and on the first contact 240A and the second contact 240B. As shown in FIG. 29, a metal line 250 is formed in the dielectric layer 245, and the metal line 250 is connected to the second contact 240B.

[0083] As shown in FIG. 30 , a dielectric layer 245 is positioned over the second interlevel dielectric layer 185. A trench (not shown) is formed in the dielectric layer 245 and the second interlevel dielectric layer 185, exposing the top surface of the upper gate 210 of one of the upper devices. The trench is filled with a conductive metal to form a gate contact 264. A plurality of metal lines 250 are positioned in the dielectric layer 245, where one of the metal lines 250 is connected to the gate contact 264. As shown in FIG. 31 , the dielectric layer 245 is positioned over the second interlevel dielectric layer 185, the first contact 240A, the third contact 240C, and the fourth contact 240D. A trench (not shown) is formed in the dielectric layer 245 and filled with a conductive metal to form the first S / D contact 270 and the second S / D contact 275. A first S / D contact 270 is connected to the third contact 240C, and a second S / D contact 275 is connected to the fourth contact 240D. A plurality of metal lines 250 are positioned in the dielectric layer 245, with one of the metal lines 250 connected to the first S / D contact 270 and one of the metal lines 250 connected to the second S / D contact 275. Backend-of-the-line (BEOL) layers 255 are formed on the dielectric layer 245 and on the metal lines 250. A carrier wafer 260 is formed on the BEOL layers 255. The carrier wafer 260 enables flipping of the first substrate 105 and backside processing of the device. While Figures 32-43 illustrate backside processing of the device, these figures do not show the device flipped.

[0084] 32, 33, and 34 illustrate processing stages after removal of first substrate 105, etch stop 106, and second substrate 108. After device inversion (not shown), first substrate 108 is removed, exposing etch stop 106. Etch stop 106 and second substrate 108 are removed, exposing first placeholder 130 and the backside surface of BDI layer 110. As shown in FIGS. 33 and 34, shallow trench isolation layer 145 is not removed.

[0085] 35, 36, and 37 illustrate processing stages after the formation of the backside interlayer dielectric layer 265 and a chemical mechanical planarization step to expose the backside surface of the backside via contact 170. The backside interlayer dielectric layer 265 is formed on the backside surface of the BDI layer 110 to surround the first placeholder 130 and fill the gaps between sections of the shallow trench isolation layer 145. Excess backside interlayer dielectric layer 265 is removed with chemical mechanical planarization (CMP) to expose the backside surface of the shallow trench isolation layer 145, the backside surface of the first placeholder 130, and the backside surface of the backside via contact 170.

[0086] 38, 39, and 40 illustrate processing stages after the removal of the first placeholder 130 and the formation of the backside contact 267. The first placeholder 130 is removed, exposing the backside surface of the bottom source / drain 135A. The space where the first placeholder 130 was located is filled with a conductive metal to form the backside contact 267. The backside contact 267 is connected to the backside surface of the bottom source / drain 135A. As shown in FIG. 40, a portion of the shallow trench isolation layer 145 is positioned between the backside contact 267 and the backside via contact 170 to prevent shorting between the backside contact 267 and the backside via contact 170.

[0087] 41, 42, and 43 illustrate processing stages after the formation of backside metal lines and backside distribution network 275. As shown in FIG. 41, backside metal lines 277 are positioned on the backside surfaces of backside inter-level dielectric layer 265 and backside contacts 267. FIG. 42 illustrates how multiple backside metal lines 277 are surrounded by an additional backside inter-level dielectric layer 280. FIG. 43 illustrates how backside metal line 277 is connected to backside contact 267 and how backside metal line 279 is connected to backside via contact 170. A backside distribution network 275 is formed on the backside surfaces of backside metal lines 277, 270, 280 and additional backside inter-level dielectric layer 280.

[0088] Although the present invention has been shown and described with reference to specific exemplary embodiments, it will be apparent to those skilled in the art that various changes in form and detail can be made therein without departing from the scope of the invention as defined by the appended claims and their equivalents.

[0089] The description of various embodiments of the present invention has been presented for purposes of illustration and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein has been selected to best explain the principles of one or more embodiments, practical applications of, or technical improvements to, technology found in the marketplace, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. a first stacked FET device having a first bottom FET device and a first top FET device, wherein the first bottom FET device includes a plurality of first bottom channel layers and the first top FET device includes a plurality of first top channel layers; a bottom gate surrounding the plurality of first bottom channel layers; an upper gate surrounding the plurality of first upper channel layers; and a gate protrusion extending downward from a backside of the upper gate and connected to the bottom gate, wherein the gate protrusion partially overlaps a bottom gate cut region of the first bottom stacked FET device, and the gate protrusion partially overlaps an upper gate cut region of the first upper stacked FET device; A microelectronic structure comprising:

2. a second stacked FET device positioned parallel to the first stacked FET device, wherein the second stacked FET device has a second bottom FET device and a second top FET device, the second bottom FET device including a plurality of second bottom channel layers, the second top FET device including a plurality of second top channel layers, the second bottom FET device including a fifth source / drain, the second top FET device including a sixth source / drain, and the first top FET device including a third source / drain; a first source / drain contact connected to a backside surface of the first source / drain; a second source / drain contact connected to the third source / drain, wherein the second source / drain contact is comprised of a first section and a second section, the first section being connected to a top surface and a sidewall of the third source / drain, and the second section being a via extending to a backside of the first stacked FET device; and a third source / drain contact connected to the top surface of the fifth source / drain; The microelectronic structure of claim 1 further comprising:

3. a backside via contact positioned between the first source / drain and the fifth source / drain; The microelectronic structure of claim 2 further comprising:

4. The microelectronic structure of claim 2 , wherein a backside surface of the second section of the second source / drain contact is connected to a frontside surface of the backside via contact.

5. a junction oxide layer positioned between the first bottom FET device and the first top FET device; The microelectronic structure of claim 1 further comprising:

6. 6. The microelectronic structure of claim 5, wherein the protrusion of the top gate contacts the front surface and sidewalls of the bottom gate.

7. 7. The microelectronic structure of claim 6, wherein the first bottom channel layer has a first width across the gate region and the first upper channel layer has a second width across the gate region.

8. The microelectronic structure of claim 7 , wherein the first width is greater than the second width.

9. a first stacked FET device having a first bottom FET device and a first top FET device, wherein the first bottom FET device includes a plurality of first bottom channel layers, the first top FET device includes a plurality of first top channel layers, the first bottom FET device includes first and second source / drains, and the first top FET device includes third and fourth source / drains, the third and fourth source / drains having asymmetric shapes, the asymmetric shapes of the third and fourth source / drains each consisting of a narrow section and a wide section; and dielectric liners positioned on the sidewalls of the third and fourth source / drains, respectively; A microelectronic structure comprising:

10. a second stacked FET device positioned parallel to the first stacked FET device, wherein the second stacked FET device has a second bottom FET device and a second top FET device, the second bottom FET device including a plurality of second bottom channel layers, the second top FET device including a plurality of second top channel layers, the second bottom FET device including a fifth source / drain, and the second top FET device including a sixth source / drain; a first source / drain contact connected to a backside surface of the first source / drain; a second source / drain contact connected to the third source / drain, wherein the second source / drain contact is comprised of a first section and a second section, the first section being connected to a top surface and a sidewall of the third source / drain, and the second section being a via extending to a backside of the first stacked FET device; and a third source / drain contact connected to the fifth source / drain, wherein the third source / drain is comprised of a third section and a fourth section, the third section being a via extending from the second top FET device toward the second bottom FET device, and the fourth section extending horizontally from the third section across a top surface of the fifth source / drain; The microelectronic structure of claim 9 further comprising:

11. 10. The microelectronic structure of claim 9, wherein the dielectric liner has a first vertical segment positioned on a first side of the third source / drain, and the dielectric liner has a second vertical segment positioned on a second side of the third source / drain.

12. The microelectronic structure of claim 11 , wherein the vertical height of the first vertical segment and the vertical height of the second vertical segment are different.

13. 13. The microelectronic structure of claim 12, wherein the third source / drain is comprised of a first area and a second area, the first area being sandwiched between the first vertical segment and the second vertical segment.

14. 14. The microelectronic structure of claim 13, wherein the second area of ​​the third source / drain extends horizontally above the first vertical segment.

15. The microelectronic structure of claim 10 , wherein the second source / drain contact is connected to the top surface and sidewalls of the second area of ​​the third source / drain.

16. a bottom gate surrounding the plurality of first bottom channel layers; an upper gate surrounding the plurality of first upper channel layers; and a junction oxide layer positioned between the first bottom FET device and the first top FET device; The microelectronic structure of claim 15 further comprising:

17. 17. The microelectronic structure of claim 16, wherein the top gate has a protrusion that extends through the junction oxide and connects to the bottom gate.

18. 20. The microelectronic structure of claim 17, wherein the protrusion of the top gate contacts a front surface and a sidewall of the bottom gate.

19. forming a first stacked FET device including a first bottom FET device and a first top FET device, wherein the first bottom FET device includes a plurality of first bottom channel layers, the first top FET device includes a plurality of first top channel layers, the first bottom FET device includes first and second source / drains, and the first top FET device includes third and fourth source / drains; forming a dielectric liner positioned on sidewalls of the third and fourth source / drains, respectively, wherein the dielectric liner has a first vertical segment positioned on a first side of the third source / drain and the dielectric liner has a second vertical segment positioned on a second side of the third source / drain; forming a second stacked FET device positioned parallel to the first stacked FET device, wherein the second stacked FET device has a second bottom FET device and a second top FET device, the second bottom FET device including a plurality of second bottom channel layers, the second top FET device including a plurality of second top channel layers, the second bottom FET device including a fifth source / drain, and the second top FET device including a sixth source / drain; forming a first source / drain contact connected to a backside surface of the first source / drain; forming a second source / drain contact connected to the third source / drain, wherein the second source / drain contact is comprised of a first section and a second section, the first section being connected to a top surface and a sidewall of the third source / drain, and the second section being a via extending to a backside of the first stacked FET device; and forming a third source / drain contact connected to the fifth source / drain, wherein the third source / drain is comprised of a third section and a fourth section, the third section being a via extending from the second top FET device toward the second bottom FET device, and the fourth section extending horizontally from the third section across a top surface of the fifth source / drain; A method for providing the above.

20. lowering the first vertical segment so that a vertical height of the first vertical segment and a vertical height of the second vertical segment are different.

20. The method of claim 19, comprising:

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