Chip-Level Packaged Photodiodes

Abstract

The chip-level package photodiode of the present invention has a first conductive layer located on a first side of the photodiode. A first contact is located on a second side of the chip-level package photodiode. A dopant diffusion layer is formed between the first conductive layer and the first contact to electrically connect the first conductive layer to the first contact. The dopant diffusion layer extends from the first side of the chip-level package photodiode through the entire depletion zone of the chip-level package photodiode to the second side of the chip-level package photodiode.

Description

[Technical Field]

[0001] A conventional photodiode has an anode on the top of the photodiode and a cathode on the bottom side of the photodiode, both of which must have contacts that connect to a printed circuit board (PCB) to transmit and process signals from the photodiode.

[0002] Chip level packaging is a technology that allows semiconductor dies to be soldered directly to a printed circuit board (PCB). Chip level packaging has an overall smaller size in terms of both width and height, as opposed to encapsulating dies in a package. Furthermore, the manufacturing cost of chip level packaging can be lower than that of traditional encapsulating dies in a package.

[0003] In chip level packaging, the active semiconductor structures as well as the solder contacts are typically on the bottom side of the die, and the top side of the die is used for markings, so there is no need to electrically connect the bottom and top sides in chip level packaging.

[0004] Chip-level packaging for photodiodes allows for smaller size and height of the photodiode, which has beneficial effects in all space-constrained applications such as wearable devices (e.g., heart rate monitoring and pulse oximetry). Summary of the Invention [Problem to be solved by the invention]

[0005] However, the active structure of a photodiode (e.g., a pn-junction diode) cannot be located on the bottom side of the device without significant performance degradation. That is, most of the light absorption by a photodiode, especially at short wavelengths, is believed to occur outside the depletion zone. This can result in reduced sensitivity due to recombination losses and very slow rise / fall times due to carrier diffusion. [Means for solving the problem]

[0006] Briefly, as will be described in more detail below, the present invention provides a chip-level photodiode that can be attached to a printed circuit board, for example, by soldering. [Brief explanation of the drawings]

[0007] A more detailed understanding may be had from the following description, given by way of example, with reference to the accompanying drawings, in which:

[0008] [Figure 1] FIG. 1 is a cross-sectional view of a conventional photodiode. [Figure 2] 1 is a cross-sectional view showing an integrated circuit chip with through silicon vias. [Figure 3] FIG. 1 is a cross-sectional view of a chip level package photodiode according to an example embodiment. [Figure 4] 1 is a flow diagram illustrating an example method for forming a chip-level packaged photodiode according to an example embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] The chip-level packaged photodiode of the present invention has a first conductive layer located on a first side of the chip-level packaged photodiode. A first contact is located on a second side of the chip-level packaged photodiode. A dopant diffusion layer is formed between the first conductive layer and the first contact and electrically connects the first conductive layer to the first contact. The dopant diffusion layer extends from the first side of the chip-level packaged photodiode through or completely through the depletion zone of the chip-level packaged photodiode to the second side of the chip-level packaged photodiode.

[0010] A method for forming a chip-level package photodiode includes forming a first conductive layer located on a first side of the chip-level package photodiode. A first contact is formed on a second side of the chip-level package photodiode. The first contact is located on the second side of the chip-level package photodiode. A dopant diffusion layer is formed between the first conductive layer and the first contact, electrically connecting the first conductive layer to the first contact. The dopant diffusion layer extends from the first side of the chip-level package photodiode through or completely through the depletion zone of the chip-level package photodiode to the second side of the chip-level package photodiode.

[0011] 1 is a cross-sectional view of a conventional photodiode 100. For illustrative purposes, an n-substrate photodiode is shown, but it should be noted that reverse polarity is also possible, for example, using a p-substrate.

[0012] The operation of a conventional photodiode is described below, but briefly, a conventional photodiode 100 has an anti-reflective coating (e.g., nitride) 101, a front-side electrical contact (e.g., anode) 102, an oxide coating 103 covering the resulting p-n junction 103, a p-type anode layer 104 located on the top side (light incident side) of the die, a depletion zone 105, an n-substrate 106, and a back-side electrical contact (e.g., cathode) 107.

[0013] Incoming photons are absorbed by the semiconductor material of the photodiode, resulting in the creation of electron-hole pairs. The penetration depth of a photon depends on its wavelength: shorter wavelengths have a shallower penetration depth than longer wavelengths.

[0014] If absorption occurs within the depletion zone 105 of the pn-junction, the electric field separates the carriers and photocurrent is immediately generated. If absorption occurs below the depletion zone 105, the carriers will exhibit random diffusive motion.

[0015] If one of the carriers diffuses into the depletion zone, a photocurrent will be generated. In this case, two possible disturbing effects occur that can hinder the performance of the photodiode. First, the current flow will be delayed due to the duration of the diffusion process. Second, the generated carriers may be lost through recombination before they reach the depletion zone. This results in a lower sensitivity of the photodiode.

[0016] For these reasons, photodiodes with active structures on the back side (common in standard die-level packaged devices) can suffer significant performance degradation in terms of sensitivity and response time.

[0017] In the embodiment shown in Figure 1, the anode contact is on the top (light incident) side of the die, and the cathode contact is on the backside of the die. Since both the anode and cathode are accessible from the top side, it is possible to provide both contacts on the top side. However, to provide both contacts on the bottom side, which is necessary for attaching the die as a die level package, for example by SMD soldering, it would be necessary to additionally make an electrical connection of the anode to the backside of the device.

[0018] One way to make electrical connections within a chip is through silicon vias (TSVs), which are areas that electrically connect silicon layers by filling the area with a conductor that matches a conductor from the layer above or below.

[0019] 2 is a cross-sectional view of an integrated circuit chip 200 having a plurality of TSVs. As shown in FIG. 2, the integrated circuit chip 200 has a front side of wafer 201 and a back side of wafer 202. A silicon layer 203 is interposed between the front side of wafer 201 and the back side of wafer 202.

[0020] To connect the front side of the wafer to the back side, a TSV can be used, which has a conductive material 204 and an isolation (insulating) region 205. In this method, the conductive material 204 connects the front side of wafer 201 to the back side of wafer 202 while remaining isolated or insulated from silicon layer 203.

[0021] The traditional manufacturing method for TVS involves a vertical etching process (e.g., the Bosch process) followed by sidewall passivation and hole filling with a conductive material (e.g., polysilicon). The passivation and fill residues are removed from the top and bottom of the wafer during fabrication into chips. This process is costly and significantly increases the die cost.

[0022] 3 is a cross-sectional view of an example embodiment of a chip-level packaged photodiode 300. The chip-level packaged photodiode includes a first conductive layer (e.g., anode) 301, a depletion zone (region) 302, a second conductive layer (e.g., n-substrate layer) 303, a first p-diffusion layer 304, a second p-diffusion layer 305, a solder contact anode 306, and a solder contact cathode 307.

[0023] 3, instead of using TSVs to connect the first conductive layer 301 to the underlying contact anode 306, a deep diffusion is utilized: a first p-diffusion layer 304, which may be formed by aluminum as a dopant in silicon, diffuses downward from the anode 301. A second p-diffusion layer 305, which may be formed by aluminum as a dopant in silicon, diffuses upward from the solder contact anode 306 toward the first p-diffusion layer 304.

[0024] Connecting the two diffusion layers (304 and 305) electrically connects the first conductive layer 301 and the contact anode 306. That is, the first conductive layer 301 can be formed on a first side (e.g., the top side) of the chip-level package photodiode 300, and the contact anode 306 can be formed on a second side (e.g., the bottom side) of the chip-level package photodiode 300.

[0025] Alternatively, the electrical connection can be made with only one diffusion layer originating from either the bottom or top side of the wafer, which would require a longer diffusion time.

[0026] FIG. 4 is a flow diagram illustrating an exemplary method 400 for forming a chip-level packaged photodiode according to an example embodiment.

[0027] In a first step (Step 410), a dopant diffusion layer is formed to connect the first conductive layer to a first contact, such as the solder contact anode 306. As described in connection with Figure 3, the dopant diffusion layer can comprise a first p- diffusion layer formed from a first side of the chip-level packaged photodiode toward a second side of the chip-level packaged photodiode.

[0028] A second dopant diffusion layer (eg, the second p-diffusion layer in FIG. 3) can be formed from the first contact on the bottom surface of the chip level package photodiode upward toward the top surface of the chip level package photodiode.

[0029] Connecting the first and second dopant diffusion layers electrically connects the first conductive layer on the top surface of the chip-level packaged photodiode to the anode contact on the bottom surface of the chip-level packaged photodiode.

[0030] In the second step, a photodiode is formed on the top side of the chip, that is, a first conductive layer is formed on a first side of the chip-level package photodiode (step 420).

[0031] In a third step, solder contacts are formed on the bottom side of the chip, for example, a first contact layer is formed on the second side of the photodiode (step 430).

[0032] Although these steps may be performed in any order, and other steps may be added to form a second conductive layer (e.g., n-substrate 303 in FIG. 3), it is preferable to perform step 410 before performing other steps 400 and any other steps that may be performed in the method of the present invention. If step 410 were performed after steps 420 and 430, for example, it is believed that the process of performing steps 420 and 430 would result in the disruption of the dopant diffusion layer(s).

[0033] It should be noted that many variations are possible based on this disclosure, and although features and elements have been described in specific combinations, each feature and element can also be used alone without the other features and elements, with or without other features and elements.

[0034] For example, as described above, the illustrated photodiode uses a p-layer anode conductive layer and an n-substrate layer as the cathode, but the reverse embodiment can also be used, and the dopant diffusion layer can be an aluminum dopant diffusion layer or other metallized diffusion layer.

[0035] The photodiode may be made of silicon or any other suitable material, and may also be a blue-enhanced photodiode.

[0036] By providing a contact on one side of the photodiode, the photodiode can be constructed in a smaller package that can be mounted in a smaller device. For example, it is possible to construct a wearable photodiode by connecting the light input side to a contact on the side where the photodiode is worn. [Explanation of symbols]

[0037] 100 Conventional photodiode 101 Anti-reflection coating 102 Front side electrical contact 103 Created pn junction 103 Oxide film 104 p-type anode layer 105 Depletion Zone 106 n-substrate 107 Rear electrical contact 200 integrated circuit chips 201 wafer 202 wafer 203 Silicon Layer 204 Conductive materials 205 Separation area 300 Chip-Level Package Photodiodes 301 First conductive layer, anode 302 Depletion Zone (Region) 303 Second conductive layer, n-substrate layer 304 1st p-diffusion layer 305 Second p-diffusion layer 306 Solder Contact Anode 307 Solder Contact Cathode 400 Formation method 410 Process 420 process 430 Process

Claims

1. A chip-level package photodiode, a first conductive layer located on a first side of the chip level package photodiode; a first contact located on a second side of the chip level package photodiode; a dopant diffusion layer formed between the first conductive layer and the first contact, electrically connecting the first conductive layer to the first contact, the dopant diffusion layer extending from a first side of the chip level package photodiode through an entire depletion region of the chip level package photodiode to the second side of the chip level package photodiode; A chip-level package photodiode comprising:

2. a second conductive layer further located on the second side of the chip level package photodiode; and a second contact located on the second side of the chip level package photodiode and electrically communicating with the second conductive layer; 10. The chip-level packaged photodiode of claim 1, comprising:

3. 3. The chip-level package photodiode of claim 2, wherein the first conductive layer is a p-substrate layer.

4. The chip-level packaged photodiode of claim 3 , wherein the first contact is an anode.

5. 4. The chip-level package photodiode of claim 3, wherein the second conductive layer is an n-substrate layer.

6. The chip-level packaged photodiode of claim 5 , wherein the second contact is a cathode.

7. 2. The chip-level package photodiode of claim 1, wherein the dopant diffusion layer is aluminum.

8. The chip-level package photodiode of claim 1 , wherein the dopant diffusion layer is formed from the first side to the second side.

9. 2. The chip-level package photodiode of claim 1, wherein the dopant diffusion layer has a first dopant diffusion portion formed from the first side to the second side, and a second dopant diffusion portion formed from the second side to the first side connecting to the first dopant diffusion portion.

10. The chip-level packaged photodiode of claim 1 , wherein the chip-level packaged photodiode is a blue enhanced photodiode.

11. 1. A method for forming a chip level packaged photodiode, comprising: forming a first conductive layer located on a first side of the chip level package photodiode; forming a first contact located on a second side of the chip level package photodiode; and forming a dopant diffusion layer between the first conductive layer and the first contact, electrically connecting the first conductive layer to the first contact, the dopant diffusion layer extending from the first side of the chip level package photodiode through an entire depletion region of the chip level package photodiode to the second side of the chip level package photodiode; 10. A method for forming a chip-level packaged photodiode, comprising:

12. further forming a second conductive layer located on a second side of the chip level package photodiode; and 12. The method of claim 11, further comprising forming a second contact located on the second side of the chip level package photodiode and electrically communicating with the second conductive layer.

13. The method of claim 12, wherein the first conductive layer is a p-substrate layer.

14. The method of claim 13 wherein the first contact is an anode.

15. The method of claim 13, wherein the second conductive layer is an n-substrate layer.

16. The method of claim 15 wherein the second contact is a cathode.

17. The method of claim 11 , wherein the dopant diffusion layer is aluminum.

18. The method of claim 11 , further comprising forming the dopant diffusion layer from the first side to the second side.

19. 12. The method of claim 11, wherein in the step of forming the dopant diffusion layer, a first dopant diffusion portion is formed from the first side to the second side, and a second dopant diffusion portion is formed from the second side to the first side and connected to the first dopant diffusion portion.

20. 12. The method of claim 11, wherein the chip level packaged photodiode is a blue enhanced photodiode.

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