Method and system for providing a fault-tolerant layout for a massively parallel processing array

Abstract

A system and method are disclosed for creating a robust topology of a layout of cores for performing functions on a grid-like core array. A defective core file is input, which indicates the location of defective cores in the array and an optimal ideal topology for the configuration layout of at least some of the cores. The location of at least one defective core in the array is determined. At least some of the cores in the core array are assigned to an optimal initial topography for the cores in the array. It is determined whether the at least one defective core is in the optimal initial topography. To create the robust topology, functions of cores in the row and column of the at least one defective core are assigned to additional adjacent cores in the core array.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to U.S. Patent Application No. 18 / 054,460, filed November 10, 2022, the entire contents of which are incorporated herein by reference.

[0002] TECHNICAL FIELD The present disclosure relates generally to applications running on multi-core systems. More specifically, aspects of the disclosure relate to techniques for selecting cores on an array to avoid cores with manufacturing defects. [Background technology]

[0003] An increasing number of computing systems are based on homogenous cores that can be configured to run different applications. These cores can therefore accommodate many different operations and be used for a variety of parallel programming tasks. Typically, cores are fabricated on a die. These dies can be fabricated in a way that allows them to be partitioned to allocate the required processing power. The processing performed by such a die therefore depends on the number of cores used to partition the programming operations. An example of such partitioning is the streaming model of programming multiple cores, employing different threads assigned to different cores.

[0004] Such a die therefore has an array of cores that can be selectively used for different operations, such as massively parallel processing. Groups of cores are selected for these different operations. An efficient layout selects the cores required to perform an operation as close together as possible. One issue with dies with a large number of cores is the possibility of defects due to fabrication or processing. For example, a massively parallel processing array (MPPA) containing 8192 cores may have a yield of less than 100% of its usable cores due to manufacturing or environmental defects. When configuring cores for different applications, defective cores cannot be included in the applications.

[0005] Proper testing of MPPA chips during verification provides a board map for each chip. However, currently, no algorithm exists that can reconfigure a configuration that includes one of the defective cores. Therefore, the problem of loading an application topology with a placement determined by an expert user or automatically by a place-and-route (PR) or mapping tool during core layout is a costly solution to an NP-hard problem. Such a solution cannot be recalculated in a rapid manner during dynamic loading into a potentially imperfect massively parallel processing array (MPPA) to correct for the absolute position of the mapping, which may be unavailable in a multicore chip due to incomplete or non-functional cores. The solution topology placement is a nondeterministic polynomial-time (NP)-hard static scheduling problem for a compiler that cannot be solved reliably or quickly if the MPPA has defective cores.

[0006] Therefore, a technique is needed to generate fault-tolerant layouts for massively parallel processing array (MPPA) topologies that incorporates techniques inspired by Hilbert-Hotel. Furthermore, a method is needed to provide the designed functionality of a core topology even when the designed cores are unavailable. There is also a need to provide a simple solution to the problem of automatically loading application topologies and avoiding defective cores by relying on placements determined by an expert user or automatically by a place-and-route (PR) tool. Summary of the Invention

[0007] One disclosed example is a method for creating a robust topology of a layout of cores to perform functions on a grid-array of cores. The location of at least one defective core in the array is determined. At least some of the cores in the core array are assigned to an optimal initial topographical configuration layout of the cores in the array. It is determined whether the at least one defective core is in the optimal initial topographical configuration layout. To create the robust topology, functions of cores in the row and column of the at least one defective core are assigned to additional adjacent cores in the core array.

[0008] Another disclosed example is a system for determining a robust topology for configuring a core array. The system includes a storage device that stores a core defect file that includes a location on the core array of at least one defective core and an ideal topology for several configuration layouts of the core array. A layout module is operable to configure cores on the core array according to the ideal topology. The layout module determines, from the core defect file, a location of at least one defective core among the configured cores on the array. The layout module assigns functions of cores in a row and column of the at least one defective core to additional adjacent cores in the core array to create the robust topology.

[0009] Another disclosed example is a method for increasing the yield of dies fabricated on a wafer. A core array having more than a target number of cores for each die is fabricated on the wafer. The core array on the die is tested. A location of at least one defective core on the die is determined. Rows and columns of cores containing at least one defective core are determined. At least some of the cores in the rows and columns are bypassed to provide the target number of cores.

[0010] The above summary is not intended to represent each embodiment or every aspect of the present disclosure. Rather, the above summary merely illustrates some of the novel aspects and features described herein. The above features and advantages, as well as other features and advantages of the present disclosure, will be readily apparent from the following detailed description of exemplary embodiments and modes for carrying out the invention when considered in conjunction with the accompanying drawings and appended claims.

[0011] The present disclosure will be better understood from the following description of exemplary embodiments, taken in conjunction with the accompanying drawings, in which: [Brief explanation of the drawings]

[0012] [Figure 1A] FIG. 1 is a diagram of a chip having four dies, each having multiple processing cores. [Figure 1B] FIG. 1B is a simplified diagram of one of the dies on the chip shown in FIG. 1A. [Figure 2A] FIG. 1C is a block diagram of a core array on the die of FIG. 1B. [Figure 2B] FIG. 1C is a three-dimensional view of the core array in the die of FIG. 1B. [Figure 3] FIG. 1 is a three-dimensional view of a core array suitable for selection for the implementation of different operations. [Figure 4] FIG. 1 is a block diagram of a system that provides a robust topology for the layout of cores on a core array. [Figure 5] 1 is a diagram of a region of a core showing the results of an exemplary algorithm for rerouting placement due to a defective core. [Figure 6] FIG. 10 is a diagram of a region illustrating the results of an exemplary algorithm for rerouting placement due to multiple defective cores. [Figure 7] 10 is an example of rerouting using a step-over routine to bypass a defective core. [Figure 8] 10 is an example of expanding and contracting the core layout for an exemplary function. [Figure 9A]1 is an example of a layout of a core that may be reduced according to an exemplary reduction algorithm. [Figure 9B] 10 is another exemplary layout of a core that may be reduced according to an exemplary reduction algorithm. [Figure 9C] 9C is a reduced layout of the core obtained from the example layout of FIG. 9B. [Figure 10] FIG. 1 is a flow diagram of an exemplary Master Algorithm routine that provides a robust topology for the layout of a core incorporating fault-tolerant and shrink routines. [Figure 11] An example of application of the system of FIG. 4 to improve the effective yield of cores fabricated on a wafer is shown. DETAILED DESCRIPTION OF THE INVENTION

[0013] The present disclosure is susceptible to various modifications and alternative forms. Several representative embodiments have been shown by way of example in the drawings and are described in detail herein. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed. Rather, the present disclosure is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

[0014] The present invention can be embodied in various forms. Representative embodiments are shown in the drawings and described in detail herein. The present disclosure is illustrative or explanatory of the principles of the present disclosure and is not intended to limit the broad aspects of the present disclosure to the illustrated embodiments. To that extent, elements and limitations disclosed, for example, in the Abstract, Summary, or Detailed Description sections, but not expressly recited in the claims, should not be incorporated into the claims, individually or collectively, by implication, inference, or otherwise. For purposes of this detailed description, unless otherwise noted, the singular includes the plural, and vice versa. The word "comprises" means "including without limitation." Furthermore, terms expressing approximation, such as "about," "approximately," "substantially," and "approximately," may be used herein to mean, for example, "at," "near," "approximately at," "within 3-5%," "within acceptable manufacturing tolerances," or any logical combination thereof.

[0015] This disclosure relates to a technique for generating fault-tolerant layouts for MPPA (Massively Parallel Processing Array) topologies using a Hilbert Hotel-inspired approach. The disclosed process can be used in combination with a core loader following the disclosed algorithm to provide the designed functionality of a user topology even when core resources specified by the topology's absolute position placement are unavailable. This exemplary technique provides a simple alternative for loading application topologies onto a massively parallel processing array (MPPA) with defective cores, with placement determined by an expert user or automatically determined by a place-and-route tool. The disclosed process utilizes fault-tolerant and reduction algorithms based on the Hilbert Hotel to rearrange the layout of cores in an ideal topology and rapidly generate robust topologies. Thus, the disclosed process enables rapid placement of preconfigured topologies on a core array, avoiding the incorporation of unknown defective cores (in the topology) in the placement. The present disclosure provides a polynomial complexity solution to a nondeterministic polynomial time (NP) problem, thereby increasing the practicality of semiconductor multi-core chips across demanding applications and increasing the yield rate of chip manufacturing by accepting defective cores within the die, thereby recovering a higher percentage of usable chips from the wafers produced.

[0016] FIG. 1A illustrates an exemplary chip 100 divided into four identical dies 102, 104, 106, and 108. Each of the dies 102, 104, 106, and 108 includes multiple processor cores, support circuitry, serial interconnects, and serial data control subsystems. For example, each of the dies 102, 104, 106, and 108 may have 4,096 processing cores and SERDES interconnect lanes to support different communication protocols. There are inter-die parallel connections between the dies 102, 104, 106, and 108. Thus, each of the dies 102, 104, 106, and 108 in this example is interconnected by an Interlaken connection. The chip 100 is designed to allow one, two, or all four of the dies 102, 104, 106, and 108 to be used. The pins on the package associated with the unused die are left unconnected within the package or board. The die is expandable because additional chips identical to chip 100 can be mounted on the device or circuit board. In this example, a single communication port, such as an Ethernet port, is provided on chip 100. Of course, other ports may be provided, such as one or more ports per die.

[0017] 1B is a block diagram of an example die 102. Die 102 includes a fractal array 130 of processing cores. The processing cores of fractal array 130 are connected to each other via system interconnect 132. Core array 130 as a whole serves as the primary processing engine of die 102 and chip 100. In this example, fractal array 130 has 4096 cores arranged in a grid.

[0018] The system interconnect 132 is coupled to a set of memory input / output processors (MIOPs) 134. The system interconnect 132 is coupled to a control and status register (CSR) 136, a direct memory access (DMA) 138, an interrupt controller (IRQC) 140, an I2C bus controller 142, and two inter-die interconnects 144. The two inter-die interconnects 144 enable communication between the die 102 and the arrays of processing cores 130 of the two adjacent dies 104 and 108 of FIG. 1A.

[0019] The chip includes a high-bandwidth memory controller 146 coupled to a high-bandwidth memory 148 that constitutes an external memory subsystem. The chip also includes an Ethernet controller system 150, an Interlaken controller system 152, and a PCIe controller system 154 for external communications. In this example, controller systems 150, 152, and 154 each have a media access controller, a physical coding sublayer (PCS), and inputs for data to and from the core. Each controller in each communication protocol system 150, 152, and 154 interfaces with the core to provide data in a respective communication protocol. In this example, Interlaken controller system 152 has two Interlaken controllers and respective channels. A SERDES allocator 156 can allocate SERDES lines to communication systems 150, 152, and 154 via a quad M-PHY unit 158. Each of the controllers in communication systems 150, 152, and 154 can access high-bandwidth memory 148.

[0020] In this example, an array 130 of directly interconnected cores is organized into tiles with 16 cores per tile. The array 130 functions as an on-chip memory network by providing a high-bandwidth interconnect for routing data streams between the cores and external DRAM via a memory IO processor (MIOP) 134 and a high-bandwidth memory controller 146. The array 130 functions as a link network on the chip interconnect to support communication between remote cores, including chip-to-chip communication via an "array of chips" bridge module. The array 130 includes an error reporter function that captures and filters fatal error messages from all components in the array 130.

[0021] FIG. 2A is a detailed view of core array 130 of FIG. 1B. FIG. 2B is a three-dimensional image of core array 130 of FIG. 1B. Core array 130 is organized into four core clusters, such as clusters 200, 210, 220, and 230 shown in FIG. 2A. For example, cluster 200 includes cores 202a, 202b, 202c, and 202d. Each of the four cores in each cluster 200, such as cores 202a, 202b, 202c, and 202d, is coupled by router 204. FIG. 2B shows other clusters 210, 220, and 230 with corresponding cores 212a-212d, 222a-212d, and 232a-232d, and corresponding routers 214, 224, and 234.

[0022] As can be seen particularly in FIG. 2B , in this example, cores 202a, 202b, 202c, and 202d each have up to four sets of three interconnects [L, A, R]. For example, a core at the center of the array, such as core 202d, includes four sets of interconnects 240, 242, 244, and 246, each connected to one of four adjacent cores. Thus, core 202b is connected to core 202d via interconnect 240, core 202c is connected to core 202d via interconnect 242, core 212b is connected to core 202d via interconnect 244, and core 202c is connected to core 202d via interconnect 246. Another connector 248 is coupled to the wire router 204 of cluster 200. Thus, each core in the center of the array has four sets of interconnects, while boundary cores such as core 202c only have three sets of interconnects 250, 252, and 246 connected to respective cores 202a, 202d, and 212a.

[0023] FIG. 3 is a perspective view of cores in core array 130. A region of cores is selected for the layout of selected cores that perform program functions, such as matrix multiplication. Assuming all cores are functional, the layout of cores for program functions is ideally laid out as densely as possible. Such an ideal topology can be defined as the layout of a 100% yield MPPA fractal array chip. However, the ideal topology layout must be adjusted to ensure that no faulty cores are included in the array.

[0024] FIG. 4 is a block diagram of a system 400 that provides a robust topology for an MPPA fractal core array, such as core array 130 on die 102 of FIG. 1B. System 400 includes a test module 410 that tests a core array 412 of an MPPA fractal array chip, such as chip 100 of FIGS. 1A-1B. Test module 410 generates a defective core file 420 that includes the locations of all defective cores on fractal array 412 of cores. Compiler 414 executes compiler tools, such as a place-and-route routine, that provide an ideal topology 422 for arranging cores in array 412 for desired operation. Alternatively, ideal topology 422 may be manually created by a skilled user.

[0025] To perform a desired operation or function, an ideal topology 422 for a layout configuration of at least some cores in the core array 412 is read by a layout module 430. The layout module 430 reads the defective core file 420 and uses an exemplary fault-tolerant algorithm to generate a robust topology 432 to be applied to the core array 412. Applying the robust topology 432 enables the core array 412 to perform the configured operation and avoid the use of defective cores in the layout configuration.

[0026] Three exemplary algorithms can apply an ideal topology to an MPPA fractal array chip with one or more defective cores. The exemplary algorithms include a fault-tolerant algorithm, a reduction algorithm, and a master algorithm. The master algorithm applies a fault-tolerant algorithm, tapping the reduction routine to free up more cores for other computations. This is useful when multiple topologies are configured in different regions on an exemplary MPPA fractal array chip, such as chip 100 (a multi-tenant situation). These exemplary techniques can be adapted to the problem of adjusting the topology to avoid defective cores in a fractal array, as described above. The exemplary techniques can also be applied to a network-on-chip (NOC) router failure scenario, where a block of 2x2 fractal cores becomes unavailable due to the router failure. Cores affected by the router failure function only as interconnects and are unavailable for place-and-route / layout, causing a deviation from the ideal layout topology.

[0027] The exemplary step-over algorithm can be applied to discard rows and columns of a NOC router and reconfigure unused cores to maintain topology functionality. This fault-tolerance mechanism may allow a topology to be designed to incorporate functional cores despite the presence of a relatively large number of faulty cores, thereby enabling the recovery of limited cores within a chip that would otherwise be discarded. Another application is to apply the disclosed routine to the fabrication of entire chips to improve yield, since even chips with a relatively large number of faulty cores can be used in different topologies using the techniques described above. This may increase the threshold for faulty cores that prevent chip production, potentially improving chip yield from foundries.

[0028] MPPA's exemplary fault-tolerant loading technique provides a simple solution to fix the complex NP-hard problem of placement: the solution's topology placement is an NP-hard static scheduling problem for the compiler, which cannot be solved reliably or quickly if the MPPA core is flawed.

[0029] A user application is represented as a topology of the core array, forming a primitive data flow graph (DFG) representation of the user computation running on the hardware accelerator fabric. A directed graph G can be represented as (V, E), where V is one of the cores or processing elements, and E is the nearest core or a bandwidth link representing a NoC multi-hop network connection for communicating data to and from the cores or processing elements. The layout problem hierarchy guarantees the existence of operators or macros (processing elements or fractal cores) as vertices of the graph, i.e., V∈E{FC}, where FC is a fractal core and V is a processing element or fractal core.

[0030] The "ideal placement" of an ideal topology on an MPPA or fractal array (FA) of cores assumes 100% yield on the MPPA(FA) by the compiler tools configuring the cores in the array for the desired operation. The place-and-route process (PR) of the MPPA(FA) can be expressed as: PR(V):V→(x,y) ((x,y) are integer positions) where V is the core and (x, y) are the coordinates in the MPPA(FA) domain.

[0031] Actual MPPA (FA), where the yield of functioning cores is less than 100%, is reported during core test and after tape-out by inspection of the core. A defective core file (DCF), such as defective core file 420 in Figure 4, outputs the location of defective cores in (x,y) coordinates of the core array for use by layout tools.

[0032] Defective Core Vd =(x d ,y d ) is assignable in the ideal layout, but this coordinate is also found in the Defective Core File (DCF), indicating that it is unmappable in the desired MPPA (FA). In this example, the layout starts at the top left and proceeds in a coarse raster fashion to the bottom right of the array. The displacement to avoid the defective core is inspired by the Hilbert Hotel Paradox, where a new guest is added to an already full hotel. The Hilbert Hotel Paradox is a paradoxical degree of freedom: adding a new guest by creating a new room that can be created on demand. This approach allows the incorporation of fault-tolerant algorithms (FTL), shrinkage algorithms, and master algorithms into a technique that exploits the relative displacements of the defective core's neighbors.

[0033] Fault-tolerant algorithms (FTL) are based on the ideal topology (T orig ) into a robust topology (T robust ) The algorithm is FTL:T orig →T robust The input of the algorithm is a defective core file of the MPPA (FA) array of cores, and the output is a robust topology. The algorithm considers the defective core site as the origin coordinate of a 2D grid. A relative displacement of one site to the right or one site down in the same row or column of the defective core site is used. The row and column cores of the topology in the row and column of the defective core are replaced by wire cores.

[0034] Next, the cores of the original topology surrounding the defect site in different quadrants are displaced one core to the right, one core down, and one core down right, respectively (e.g., the first, third, and fourth quadrants according to standard analytical geometry). The connectivity of the displaced nodes in the first, third, and fourth quadrants is patched up (connected) back to the original topology via row and column wire cores, respectively. The output topology (T robust ) is generated.

[0035] This technique is based on the Hilbert placement method and is described for one defective core as shown in Figure 5. Figure 5 shows an initial region 500 of cores required for the desired topology. The initial region includes an initial region of functional cores 510. A defective core 512 exists in the initial region 500 required for the desired topology. Therefore, the topology is expanded into specific quadrants, including a right quadrant 520, a bottom quadrant 522, and a bottom-right quadrant 524.

[0036] The location of defective core 512 is used as the origin of a 2D grid. As shown, cores in quadrants 520, 522, and 524 are displaced by one core length. This results in a core column 530 caused by defective core 512 and a core row 532 caused by defective core 512. Thus, the cores in column 530 and row 532 are unused in the topology, becoming "wires" connecting adjacent cores. In this way, the original topology is expanded to include functional cores surrounding defective core 512. After applying the placement method, the final topology of active cores 540 for the defective die is shown, excluding the row and column associated with defective core 512; this topology is logically a smaller rectangular grid of only non-defective cores.

[0037] This algorithm can also be applied to adjacent defective cores. Figure 6 illustrates the application of the algorithm to multiple defective cores. Figure 6 shows an initial region 600 of cores required for the desired topology. The initial region includes an initial region for functional core 610. Two defective cores, 612 and 614, exist in the initial region 600 required for the desired topology. Therefore, the topology is expanded to certain quadrants, including a right quadrant 620, a bottom quadrant 622, and a bottom-right quadrant 624.

[0038] The locations of defective cores 612 and 614 are used as the origin of a 2D grid. As shown, cores in quadrants 620, 622, and 624 of the topology are displaced by two core lengths because defective cores 612 and 614 occupy two core lengths. This results in a core column 630 of two core lengths caused by defective cores 612 and 614, and a core row 632 of two core lengths caused by defective cores 612 and 614. Thus, the cores in column 630 and row 632 are unused in the topology, but become "wires" connecting adjacent cores. In this way, the original topology is expanded to include functioning cores around the defective core. After applying the placement method, the final topology of active cores 640 for the defective die is shown, which is logically a smaller rectangular grid of only non-defective cores.

[0039] FIG. 7 illustrates an example of a step-over algorithm used to convert cores into "wires" and connect adjacent cores using top-level wires, which are generally not affected by lower-level defects. FIG. 7 shows a series of three cores 710, 712, and 714. Because core 712 has a defect, the step-over algorithm causes this core and its row of adjacent cores 710 and 714 to become wires, similar to core row 532 in FIG. 5. The exemplary core 712 includes three inputs: a left input 720, a right input 722, and an aggregator (agg) input 724. The core 712 also includes three outputs: a left output 730, a right output 732, and an agg output 734. As explained above, each core in an array, such as core 712, has input and output wires for feeding data into and draining data from the core. Additional hardware in the form of logical switches 740 is added to the inputs 720, 722, 724 and outputs 730, 732, 734 to allow wires to bypass the core under software control.

[0040] The exemplary core 712 includes a portion of a wire router 750 that includes four inputs / outputs (e.g., east, west, north, south), such as input / output 752 for network-on-chip functionality. The wire router 750 also bypasses network ingress and egress points using a logical switch 740. In this example, only the east and west inputs / outputs 752 are shown as being bypassed, but the corresponding north and south inputs / outputs (not shown) are also bypassed.

[0041] In this example, core 710 is physically located to the left of core 712. Core 714 is located immediately to the right of core 712. In normal operating mode, data to and from core 710 is sent and received by core 712, and data to and from core 714 is sent and received by core 712. If a fault detection algorithm detects a failure in core 712 and is part of a logical arrangement such as the example of Figures 5-6, that core is bypassed. Therefore, software routine 750 asserts a hardware signal to "bypass" core 712 by sending a command to logical switch 740, causing all wires that would have been originated or received by core 712 to be skipped. When core 712 is "stepped over," core 710 sends and receives data directly to and from core 714.

[0042] Simply put, this allows an entire "row" or "column" to be "skipped," bypassing an inoperable core, as shown in Figures 5-6. However, skipping a row or column containing a defective core, such as core 512 in Figure 5, also skips all "good" cores in row 532 and column 530.

[0043] A second exemplary algorithm is the shrink algorithm. The shrink algorithm is a loosely spaced topology (T) based on the expansion algorithm that allows the topology to avoid defective cores. orig ) input and a densely populated topology (T optimal) output. An exemplary reduction algorithm finds all adjacent runs of two or more wires (cores configured as connectors) of the same direction in an MPPA(FA) layout R, where R is the topology after running the Hilbert-Hotel algorithm. This set has wire cores referenced by pointers to objects rather than by absolute positions (x,y) on the MPPA(FA), because they are updated sequentially during the reduction algorithm. If no such runs of wire cores exist, the algorithm terminates and returns T. optimal =T curr is set to

[0044] FIG. 8 illustrates an example of core expansion and contraction in a topology in which cores may be arranged in groups. The original topology includes a first core 810 configured to perform an addition function and a second core 812 configured to perform a comparison. Thus, cores 810 and 812 are configured to perform the function a*b>15. Thus, inputs a and b are provided to core 810, and a multiplication output based on the addition function is output to core 812 for comparison. The original topology can be expanded by adding a third core 814. Core 814 is configured as a wire to pass data from core 810 to core 814.

[0045] Once the original topology has been expanded, the next step is to place the expanded topology onto cores. In one example of the placement step, an expanded topology having three cores 810, 812, and 814 can be placed onto a rectangle 820 of three good cores. Alternatively, the expanded topology may be placed onto a set of cores including a defective core, represented by rectangle 830. Using the process described above, wire core 814 can be dropped as a defective core that may be used for wire cores and stepped over by configuring inputs and outputs to bypass that core.

[0046] The algorithm is T curr =T origFor each travel path of a wire discovered in R, the algorithm identifies whether the terminal block of the travel path can be moved to the location of the terminal of the first wire in that travel path. Thus, the algorithm determines whether the wire satisfies criteria for allowable moves, such as maintaining connectivity between the terminals [L, A, R] of the cores and direction [N, E, W, S]. If so, the travel path of this wire is reduced by one wire core. The algorithm then moves the affected destination block (the block at the end of this travel path) to be adjacent to the tip of this wire. From these nodes, the algorithm manages the movement of one or more successors of the destination block and updates their placement locations by running depth-first search (DFS) and breadth-first search (BFS) style reachability algorithms. If all new placement locations discovered by the search reachability algorithm are allowable (non-overlapping and within defect-free board areas), the board layout is considered to be T. next =Moved[T curr ]. Thus, if a wire core is reduced such that a travel path of four wire cores connects to two wire cores ({W->W->W->W} => {W->W}), the reduction may shift the connectivity of other cores in a negative direction, changing the behavior of the topology. In such a case, the algorithm's search reachability is impaired, and the reduction algorithm marks the travel path of this wire core as untravelable and proceeds to the travel path of the next available wire core.

[0047] Therefore, if the reachability algorithm does not allow the wire core to be reduced, the wire core participating in the current travel path is marked as unmovable and the wire layout is marked (e.g., T next =T curr (The current node is set to T. curr =T next and additional cores designated as wires are evaluated. Once all wires have been evaluated, the reduction algorithm terminates and the optimal topology is reverted to the current topology, T optimal =Tcurr is set to

[0048] 9A-9C illustrate various examples of shrinkable topologies. FIG. 9A illustrates an example topology layout 900 that includes different cores displaced from the initial topology expanded to bypass a defective core. The topology layout 900 includes a constant circular buffer generation core 902, a TSA source / input core 904, an interleaver core 906, a minimum core 908, and a copy L to aggregate core 910. A set of wire cores 920 is distributed throughout the layout 900. The wire cores 920 are grouped into groups 922, 924, and 926, where adjacent travel paths of the wire cores 920 are detected. Therefore, certain spaces, such as a row or column of cores within group 924, contain cores that may be shrunk. Therefore, the shrink algorithm reviews groups 922, 924, and 926 for space for potential shrinkage of the entire topology 700.

[0049] Similarly, Figure 9B illustrates another exemplary topology 930 including various cores. The topology 930 includes a constant circular buffer generation core 932, a TSA source / input core 934, a minimum core 936, and a copy L to aggregate core 938. A set of wire cores 940 are grouped into groups 942 and 944 in which adjacent wire travel paths are detected. As shown in group 942, there is an adjacent travel path 950 of a wire core, and there is also an adjacent travel path 952 of another wire core. Furthermore, in group 944, there is an adjacent travel path of a wire core 954.

[0050] FIG. 9C shows a reduced topology 960 produced by the reduction algorithm applied to topology 930 of FIG. 9B. Adjacent travel paths 950 of wire cores in FIG. 9B can be reduced to allow the L output of core 932 to be sent through a single wire core 940 connected to the original wire core 940 and connected to the L input of core 936. Similarly, the travel path of core 952 in FIG. 9B is reduced to a single wire core 940 in FIG. 9C connecting the A output of core 936. After adjacent travel paths of wires such as travel paths 950 and 952 in FIG. 9B have been reduced, reduced topology 960 includes a new arrangement of the remaining wire cores 940 in groups 942 and 944.

[0051] The third exemplary algorithm is the Master Algorithm. The exemplary Master Algorithm ties together the various parts of a complete fault-tolerant placement strategy. This algorithm includes the defective core files of the MPPA (FA) cores and the topology with 100% yield (T orig ) and a robust topology without one or more defective cores (T robust ) output.

[0052] The algorithm runs through strongly connected components first, grouping adjacent defects into clusters while preserving defects that are sparsely distributed on the MPPA(FA) substrate as independent defect sites. This can be as simple as finding the largest rectangular region on a core that consists of wires or unused processing elements. This is because the Hilbert-Hotel algorithm needs to step over defective regions (along rows and columns). Thus, the entire defective cluster is configured as a wire with a four-way connection to neighboring clusters.

[0053] The master algorithm then runs the fault-tolerant algorithm on the entire MPPA, as described above. After generating a robust topology from the fault-tolerant algorithm, the master algorithm runs the reduction algorithm on the latest robust topology. Thus, the output of the reduction algorithm is the ideal robust topology (T robust ) Failure of the fault-tolerant algorithm indicates an inability to overcome defects in the substrate, and the topology may be too dense to fit on the MPPA(FA) chip due to too many faulty cores.

[0054] Flow diagram 1000 of FIG. 10 represents exemplary machine-readable instructions for a process for determining a robust topology that bypasses defective cores in a core array. In this example, the machine-readable instructions include an algorithm executed by (a) a processor, (b) a controller, and / or (c) one or more other suitable processing devices. The algorithm may be embodied in software stored on a tangible medium, such as a flash memory, CD-ROM, floppy disk, hard drive, digital video (versatile) disk (DVD), or other memory device. However, those skilled in the art will readily understand that, alternatively, the entire algorithm and / or portions thereof may be executed by devices other than a processor and / or may be incorporated in firmware or dedicated hardware in well-known manners (e.g., implemented by an application-specific integrated circuit [ASIC], a programmable logic device [PLD], a field-programmable logic device [FPLD], a field-programmable gate array [FPGA], discrete logic, etc.). For example, some or all of the components of the interface may be implemented by software, hardware, and / or firmware. Also, some or all of the machine-readable instructions depicted in the flowcharts may be executed manually. Additionally, although an exemplary algorithm is described with reference to the flowchart shown in Figure 8, those skilled in the art will readily appreciate that many other ways of implementing the exemplary machine-readable instructions may alternatively be used. For example, the order of execution of the blocks may be changed, and / or some of the described blocks may be changed, eliminated, or combined.

[0055] Flow diagram 1000 illustrates a master algorithm for generating a topography that is robust to the layout configuration of cores in a core array. This routine first reads 1010 the defect core files for all defective cores detected in the core array and the ideal topology for the core layout. The routine groups 1012 adjacent defects into clusters while preserving sparsely distributed defects on the substrate as individual sites. The algorithm then reads 1014 the ideal topology and determines whether a site exists on the core array that can accommodate the topology without including clusters of defective cores or individual sites. If a site is found, the topology is assigned to this region and the routine ends. If no site is found, the ideal topology is placed in the selected region (1016).

[0056] Next, the routine determines the locations of all defective cores within the region of the ideal topology located on the array (1018). The routine displaces nodes in the row and column of the defective core (1020). Next, the routine configures other cores in the row and column of the defective core as wires to connect the displaced cores to other cores in the topology (1022).

[0057] Next, the routine determines all adjacent travel paths for two or more cores configured as a wire (1024). The routine determines whether adjacent travel paths exist (1026). If there are no adjacent travel paths, the algorithm ends. If adjacent travel paths exist, the routine examines the first adjacent travel path to determine whether the end block of that travel path can be moved to the location of the end of the wire core for that travel path (1028). If the block cannot be moved, the routine returns to determine whether there are more adjacent travel paths (1026).

[0058] If the block is movable, the routine reduces the travel path by one wire core (1030). Next, the routine moves one or more destination blocks so that they are adjacent to the tip of the reduced wire core (1032). Next, the routine manages the movement of successor blocks by running a reachability algorithm to update their placement locations (1034). Next, the routine determines whether the new placement locations are acceptable (1036). If the new placement locations are acceptable, the routine finalizes the layout (1038) and returns to determine whether there are any more adjacent travel paths (1026). If the new placement locations are not acceptable, the routine marks the wires in the current travel path as unmovable (1040) and returns to determine whether there are any more adjacent travel paths (1026).

[0059] During chip fabrication, defects potentially occur in silicon dies. Large silicon dies are very likely to contain one or more such defects. When this defect occurs, the normal procedure is to discard the entire die, which affects the "yield" - how many "good" or functioning dies can be obtained from a wafer of silicon. By identifying the damaged cores, adding them to a "defective core file," and stepping over the defective cores during operation, the dead dies become operational and usable.

[0060] For example, if a single defect occurs on an 8,000-core die, rather than discarding the chip, step-over technology can be used to produce a functional 7,999-core die. Typically, by hiding a few extra cores from the programmer, these defects are hidden from the user. For example, an 8,000-core die is actually an 8,001-core die. This allows for one defect to be handled. Conversely, an 8,002-core die can tolerate two defects, and so on. Without the step-over mechanism, defects would typically result in the die being discarded. The aforementioned technology allows for the use of a step-over process, allowing the die with the defective core to be used. Therefore, the consumer never sees the dead core.

[0061] The illustrated technique is optimal when cores are relatively small and the wafer yield improvement from defect correction is significant. For example, on a wafer with a core size of 0.06 square millimeters (0.25 mm × 0.25 mm), a 2048-core (64 × 32 core) die measures 20 mm × 10 mm, while a 2145-core (65 × 33 core) die with one extra row and one extra column for redundancy measures 20.25 mm × 10.25 mm. This results in a total of 280 die on a 2048-IC wafer and 269 die on a 2145-IC wafer. The yield of a 2048-IC wafer (without redundancy) is 60%, which means 168 "good" die. In contrast, a 2114-IC wafer with one defect redundancy has a yield of 96%, which means 258 "good" die. This is a net increase of 90 dies. Since the cost per wafer is fixed, adding an extra row and column increases the revenue per wafer by over 53% (258 / 168).

[0062] There are several strategies for using the above principles. First, a die may actually have 2145 (65 x 33) cores, but the programmer only sees 2048 (64 x 32) cores. Therefore, extra cores beyond the target number of cores (e.g., 2048) are added to handle defects. For example, a topology requiring a 32 x 64 rectangle of cores can be fitted into a 33 x 65 array of cores by removing one row and one column of cores in hardware to handle a single defect. This eliminates the need to rearrange the topology to fit the rectangle of cores. Placing the topology is very fast because no extra software placement steps are required. However, the 97 "good" cores in the removed row and column are not used to handle the single defective core.

[0063] The second strategy is to allow the programmer to recognize that a chip has a variable number of cores. For example, a chip can have either 2145 or 2144 cores (if a die is defective). FIG. 11 shows an example core array 1100 that includes a defective core 1112. The programmer performs a software placement step to map the topology to a variable number of cores (in this case, 2145 or 2144). In this example, the programmer places the topology on four rectangles by removing rows and columns. A simplified example of this strategy is shown in layout 1120 of FIG. 11, where the topology is placed on four smaller rectangles 1122, 1124, 1126, and 1128. This approach uses 2048 cores and removes 33 columns of cores and 64 rows of cores, effectively wasting 97 good cores to accommodate the defective cores.

[0064] An alternative approach is to remove only one row and arrange the topology on two rectangles. A simplified example of this topology is shown in another layout 1130 in Figure 11. The topology is arranged on two smaller rectangles 1132 and 1134. This approach removes only one column of 33 cores, so 32 good cores are used to handle one bad core.

[0065] Alternatively, the programmer can arrange the topology on four rectangles, eliminating only the bad core. A simplified example of this topology is shown in layout 1140 in Figure 11. The topology is arranged on four smaller offset rectangles 1142, 1144, 1146, and 1148. As a result, only one defective core is wasted.

[0066] It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, when the terms "including," "includes," "having," "has," "with," or variations thereof are used in either the detailed description and / or claims, such terms are intended to be as inclusive as the term "comprising."

[0067] Unless otherwise specified, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art. Furthermore, terms as defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0068] While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. Many modifications to the disclosed embodiments may be made in accordance with the disclosure herein without departing from the spirit or scope of the invention. Thus, the breadth and scope of the present invention should not be limited by any of the above-described embodiments. Rather, the scope of the present invention should be defined in accordance with the following claims and their equivalents.

[0069] While the present invention has been shown and described with respect to one or more embodiments, equivalent changes and modifications will occur to or become apparent to others skilled in the art upon reading and understanding this specification and the accompanying drawings. In addition, while a particular feature of the invention may be disclosed with respect to only one of several embodiments, such feature can be combined with one or more other features of the other embodiments as desired or advantageous for a given or particular application.

Claims

1. 1. A method for creating a robust topology of a layout of cores for performing a function on an array of cores arranged in a grid, comprising: determining a location of at least one defective core in the array; assigning at least some of the cores in the core array to a configuration layout of an optimal initial topography of cores in the array; determining whether the at least one defective core is in the configuration layout of the optimal initial topography; and assigning the functions of the cores in the row and column of the at least one defective core to additional adjacent cores in the core array to create the robust topology. A method comprising:

2. The method of claim 1 , wherein the location of the at least one defective core in the array is determined from a core defect file generated from testing the core array.

3. 3. The method of claim 1, further comprising configuring the cores in the rows and columns as wire cores that connect the cores in the configuration layout with the additional adjacent cores.

4. determining whether any of the wire cores may be reduced; and shrinking the determined core to generate a modified robust topology; The method of claim 3 further comprising:

5. The method of claim 1 , wherein the initial topology is generated by a place-and-route algorithm.

6. The method of claim 1 , wherein the cores in the core array are homogeneous.

7. each of the cores in the array is coupled to at least one network-on-chip router; determining that a network-on-chip router of the robust topology has failed; and replacing the functionality of the row and column of cores coupled to the failed network-on-chip router with additional adjacent cores to create a new robust topology. The method of any one of claims 1 to 6, further comprising:

8. 1. A system for determining a robust topology for configuring a core array, comprising: a storage device that stores a core defect file that includes the location on the core array of at least one defective core and ideal topologies of several configuration layouts of the core array; configuring cores on the core array according to the ideal topology; determining the location of at least one defective core among the configured cores on the array from the core defect file; and assigning the functions of the cores in the row and column of the at least one defective core to additional adjacent cores in the core array to create the robust topology; A layout module that can be operated like this A system including:

9. The system of claim 8 , wherein the core defect file is generated by testing the core array.

10. 10. The system of claim 8, wherein the layout module is further operable to configure the cores in the rows and columns as wire cores that connect the cores in the configuration layout with additional adjacent cores.

11. The layout module: determining whether any of the wire cores may be reduced; and Shrinking the determined core to generate a modified robust topology. The system of claim 10 further operable to:

12. The system of claim 8 , wherein the initial topology is generated by a place-and-route algorithm.

13. The system of claim 8 , wherein the cores in the core array are homogeneous.

14. Each of the cores in the array is coupled to at least one network-on-chip router, and the layout module: determining that a network-on-chip router of the robust topology has failed; and and replacing the functionality of the row and column of cores coupled to the failed network-on-chip router with additional adjacent cores to create a new robust topology.

14. The system of any one of claims 8 to 13, further operable to:

15. 1. A method for increasing yield of dies fabricated on a wafer, comprising: creating a core array having more than a target number of cores for each die; testing the core array on a die; determining a location of at least one defective core on the die; determining the cores in the row and column containing the at least one defective core; and bypassing at least some of the cores in the rows and columns to provide a target number of cores. A method comprising:

16. determining whether the at least one defective core is in the configuration layout of the optimal initial topography; and assigning the functions of the cores in the row and column of the at least one defective core to additional adjacent cores in the core array to create a robust topology.

16. The method of claim 15, further comprising:

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