PCB Via Design and Manufacturing Methodology for Power Electronics Applications

Abstract

The circuit board comprises at least one epoxy-based composite layer (130), at least two conductive layers or tracks (110, 120) on either side of the epoxy-based composite layer (130), and first metallized vias (140) connecting the conductive layers or tracks (110, 120), at least some of the vias comprising metallized barrels (141, 141') terminating in at least one flared end (β, 142') of a junction between the metallized barrel and one of the conductive layers or tracks (110, 120).

Description

[Technical Field]

[0001] The present disclosure relates to the field of PCB manufacturing, and more particularly to the manufacturing of PCB vias. Priority is claimed to European Patent Application No. 23305908.8, filed June 7, 2023, the contents of which are incorporated herein by reference. [Background technology]

[0002] It is known to provide via holes in PCBs, such as multilayer PCBs.

[0003] Among other methods, laser drilling creates precise holes on PCBs to establish connections between different layers. Laser drilling technology uses highly concentrated laser energy to drill holes by vaporization, ensuring precision even when dealing with the smallest via sizes found on PCBs.

[0004] In commercial production, there are two laser technologies that can be used for laser drilling. CO2 lasers have wavelengths in the far-infrared band, while UV lasers have wavelengths in the ultraviolet band. The main difference between these two types is primarily due to the ability of UV beams to drill metal layers, while CO2 lasers can only drill organic materials. Therefore, CO2 lasers are widely used for the fabrication of industrial microvias in printed circuit boards. The diameter of the microvias needs to be larger than 100 μm. To produce these large diameter holes, CO2 lasers have very high productivity due to the very short time required to create large diameter holes. UV laser technology is widely used for the fabrication of microholes with diameters less than 100 μm. In microcircuit applications, the openings can even be less than 50 μm.

[0005] Several methods are known.

[0006] In single-pulse laser drilling, a single laser beam is fired into the material to create the required hole. In this method, both the laser source and the workpiece material are held stationary.

[0007] In percussion drilling, a series of laser pulses are repeatedly fired into the workpiece material. There is no relative motion between the laser beam and the workpiece during this process. This form of laser drilling effectively creates deeper, more precise holes with smaller diameters compared to single-shot laser drilling. In this process, a specific power output is selected to control melting and vaporization to produce holes with precise dimensions.

[0008] Trepanning is a process in which a laser beam is guided around a predetermined location. This location is the center of the via to be drilled. It is used in situations where the diameter of the via to be cut is larger than the diameter of the laser beam. The accuracy of the via is determined by the movement of the beam.

[0009] Helical laser drilling is a method in which a laser beam follows a helical path for movement while rotating about its own axis relative to the workpiece. A Dove prism controls the movement of the laser beam.

[0010] The advantage of helical drilling is that it provides a perfectly cylindrical hole, while percussion drilling is a faster process but produces a conical hole.

[0011] After the drilling process, the metallization process is realized by copper plating and chemical etching to metallize the hole barrels and provide electrical paths between the layers of the PCB.

[0012] The state-of-the-art processes for selectively depositing metal layers onto selected areas of semiconductor chips or onto copper surfaces of PCBs are photolithographic processes based on subtractive or additive transfer.

[0013] In the subtractive transcription process,

[0014] First, a continuous film of metal of uniform thickness is deposited using a deposition method, typically a physical vapor deposition (PVD) method such as sputtering or evaporation.

[0015] An etch resist layer is then deposited on the metal surface except where a metal layer is not desired, typically using a photolithographic process.

[0016] Finally, the exposed metal surfaces are removed using a wet etch and the etch resist layer is removed.

[0017] In the additive transfer process,

[0018] First, one or two etch resist layers are selectively deposited on surfaces where no metal layer is desired.

[0019] A uniform layer of metal is then deposited over both the etch resist layer and the final metallization surface.

[0020] Finally, the etch resist layer is removed, resulting in the metal layer being stripped from the unwanted surfaces.

[0021] In an example, copper deposition prior to a subtractive transfer process or during an additive transfer process may require three process steps (A-C). a. Copper deposition by: i. Deposition of a TaN / Ta diffusion barrier to protect the semiconductor chip from reaction with Cu. TaN can provide good adhesion on the dielectric, and Ta provides good wettability with the Cu seed layer. Alternatives are Ti-based layers (Ti / TiN stacks) and Ru-based layers. ii. Deposition of a Cu seed layer (typically done by PVD sputtering) to create nucleation sites for bulk Cu growth. b. Deposition of bulk Cu by electroplating (ECP). The ECP process is performed by immersing the wafer in a solution containing cupric ions, sulfuric acid, and trace organic additives. By applying an electric current, the Cu ions (Cu+2) are reduced to Cu, which is then deposited on the seed layer. c. Chemical mechanical polishing of excess copper using a rotating pad to planarize the surface and remove excess Cu.

[0022] Instead of seed layer deposition followed by Cu deposition by electroplating, other processes can be used, namely physical vapor deposition (PVD), chemical vapor deposition (CVD), laser reflow, and atomic layer deposition (ALD), among which CVD methods are the most widely used in industry (evaporation and sputtering). It should be noted that for the fabrication of composite structures (i.e., unlike power die plating, where a uniform layer thickness is deposited), the biggest challenge with sputtering processes is achieving good step coverage in high-aspect ratio structures such as vias. Other techniques, such as ionized PVD or ALD, exhibit better step coverage characteristics than sputtering.

[0023] When a PCB is completed with its layers, copper tracks, and vias, during temperature cycling of a conventional PCB, the expansion and contraction in the z-direction (the z-direction is defined as the cross-section of the PCB) is much greater than the expansion and contraction in the in-plane (xy) direction because the coefficient of thermal expansion (CTE) of the epoxy / glass fiber composite that provides the insulating layer is higher in this direction. The low-CTE glass fiber constrains the board in the xy plane, but not through its thickness, where it can expand and contract. Therefore, stress buildup in copper vias, such as known plated-through-hole (PTH) structures, can lead to cracks near the center of the barrel of such vias.

[0024] The literature, Y.-L. Cheng, C.-Y. Lee, Y.-L. Huang, “Copper Metal for Semiconductor Interconnects”, in: Noble Precious Met.-Prop. Nanoscale Eff. Appl., 2018. https: / / doi.org / 10.5772 / intechopen.72396 and B. Birch, “Troubleshooting Microvia Failures”, (2020) 0-12. https: / / doi.org / 10.13140 / RG.2.2.24717.77281, describes the effects of large temperature-induced dielectric expansion in the z-direction and its impact on different copper structures within a PCB, with structures having one or more of the following characteristics most likely to be problematic: a. Z-long structures such as PTH. Failure is most likely to occur in z-long structures. This is because, to a first approximation, the strain in the copper structure is ΔCTE.ΔT.l z (ΔCTE: CTE difference between copper and dielectric in the z direction; ΔT: temperature change from the stress-free state; l z : the length of the copper structure in the z-direction) and therefore the structure l z This is because it is proportional to the length in the z direction. b. In the interconnections between these structures and copper sheets: The interconnections between via structures and copper sheets typically involve the formation of corners or sharp angles that are locations of stress concentrations. While these stress issues may not be significant in cutting-edge PCB design applications, when PCB materials are deployed in power electronics applications, higher temperature swings, higher maximum junction temperatures, and higher cycle counts over product life result in higher stress magnitudes and faster damage accumulation, leading to fatigue failure in stress concentration areas of via structures. This is especially true when wide-bandgap chip materials are used, which allow for higher maximum junction temperature operation.

[0025] Another problem is the poor reliability of copper vias due to stresses in the x and y directions (in addition to the z direction) when power semiconductor chips or passive components are embedded in the PCB laminate.Power semiconductors are made of Si or SiC, materials with significantly lower CTEs than both copper and epoxy laminates.

[0026] Silicon Si has a CTE of about 3 ppm / K and a Young's modulus of about 130 to 188 GPa, while silicon carbide SiC has a CTE of about 4 ppm / K and a Young's modulus of about 300 to 700 GPa.

[0027] Similarly, examples of passive components are MnFe2O4 ferrite (magnetic) with a CTE of about 11-12 ppm / K, ceramic (capacitors, resistors) with a CTE of about 6-8 ppm / K, and silicon (capacitors) with a CTE of about 3 ppm / K.

[0028] Therefore, the CTE エポキシ複合材 ≒CTE Cu In comparison to the in-plane (xy) CTE of copper and epoxy resin / glass fiber laminate composite sheets, which are ≈18 ppm / K and therefore match, the CTE of power semiconductors and passive components is significantly lower and therefore generates larger x and y stress components.

[0029] Therefore, the introduction of semiconductor chips or passive components with low CTE values ​​into state-of-the-art PCB stackups creates greater stresses in the copper vias, making them more susceptible to failure due to fatigue crack propagation. In particular, the presence of sharp corners between the vias and the copper sheet, combined with additional thermomechanical stresses in the xy plane, can lead to more rapid fatigue crack propagation between the vias and the copper sheet, and ultimately separation between the vias and the copper sheet, compared to the situation without the semiconductor chips or passive components.

[0030] Thus, via failure can result from cracks initiating at the corner between the copper metallization and the via pillar, and is more likely to fail at the interface between the chip metallization layer and the first row of vias than at the interface between the first row of vias and the next metallization layer, or between the next metallization layer and the next row of vias. State-of-the-art via designs applied in the case of embedded semiconductor chips or passive components do not have suitable geometries to withstand the additional shear stresses in the xy plane during thermo-mechanical cycling. [Prior art documents] [Non-patent literature]

[0031] [Non-Patent Document 1] y.-L.Cheng, C.-y.Lee, y.-L.Huang, “Copper Metal for Semiconductor Interconnects”, in:Noble Precious Met.- Prop.Nanoscale Eff.Appl., 2018.https: / / doi.org / 10.5772 / intechopen.72396 [Non-patent document 2] B. Birch, “Troubleshooting Microvia Failures”, (2020) 0-12. https: / / doi.org / 10.13140 / RG.2.2.24717.77281 Summary of the Invention [Means for solving the problem]

[0032] The present disclosure provides improved via configurations for reducing fatigue crack propagation rates.

[0033] More precisely, the present disclosure proposes a circuit board comprising at least one epoxy-based composite layer, at least two conductive layers or tracks on either side of said epoxy-based composite layer, and a first metallized via connecting said conductive layers or tracks, at least some of said vias comprising a metallized barrel terminating in at least one flared end of the junction between said metallized barrel and one of said conductive layers or tracks.

[0034] The proposed via design offers a reduction in the rate of crack propagation at the via location due to reduced stresses created in the event of PCB temperature cycling. This is made possible by one or more flared ends created at both ends of the via, which reduce stress concentrations at locations where the CTE difference between the copper and one or more PCB epoxy insulating layers occurs.

[0035] Preferably, the flared end has a first angle α1 defined as the angle between the via barrel and the flared end, the angle being in the range of 0<α1<45°, a second angle α2 defined as the angle between the conductive layer and the flared end, the angle being in the range of 0<α2<45°, and a mean radius of curvature (143) R1 of the flared end having an absolute value |R1| of 5 μm or greater.

[0036] These ranges are well suited to reducing stress at the junction of the via and layer that are connected through the flared base.

[0037] In certain embodiments, α2=π−α1. In such embodiments, the flared base is oblique to the barrel of the via and the conductive layer to which the via is connected.

[0038] This provides a simple design where the via can be in a diabolo shape between two conductive layers.

[0039] The circuit board may include at least one embedded component, and one of the conductive layers may be a bonding layer for a conductive pad of the embedded component.

[0040] This improves the manufacturing of PCBs with embedded dies.

[0041] The composite material has an in-plane CTE xy and a first thermal expansion coefficient of z and the conductive layer or track has a second coefficient of thermal expansion of CTE cu wherein the flared end is calculated to limit the stress at the junction of the flared end and the copper layer to about 300 MPa under a temperature change of 100°K.

[0042] This keeps the stress in the copper metallized vias below the yield strength of copper.

[0043] The circuit board may include at least one further layer of composite material above or below one of said conductive layers or tracks.

[0044] This is the case for multilayer PCBs.

[0045] The present disclosure also relates to a method of manufacturing a circuit board as disclosed, the method comprising the steps of creating the via by forming a hole having a barrel in the epoxy-based composite material in a direction perpendicular to the conductive layer using a laser beam configured to drill the hole; providing at least one flared end at a top and / or bottom of the barrel; and filling the hole to provide the via.

[0046] The step of forming the hole may be performed by adjusting the focus of the laser beam at different heights of the hole to create the hole with a diabolo shape that provides flared ends on both ends of the via.

[0047] The flared end may be rounded by the via metallization process.

[0048] The method may include, for at least some of the vias, providing a substrate on a conductive layer or track on an underlying structure by an additive or subtractive metallization process; laminating an epoxy layer on the conductive layer or track with the substrate; and forming holes and filling the holes on the substrate to form the metallized vias disposed on the substrate, wherein the substrate provides a flared base for the vias.

[0049] The step of providing a substrate comprises: a. selectively depositing at least one etching resist layer on the surface of the conductive layer or track around the surface to be metallized where no metal layer should be deposited; b. depositing a uniform layer of metal over both the etch resist layer and the surface to be metallized; c. removing the etching resist layer, thereby stripping the metal layer from surfaces on which it should not be deposited; may include:

[0050] The method can include depositing a conductive precursor layer or track precursor layer, depositing an etch resist layer on the precursor layer at a location where a substrate will be provided, chemically etching the precursor layer to create the conductive layer or track, removing the etch resist layer to expose the substrate, laminating a further epoxy layer on the conductive layer or track, forming a hole, metallizing the hole, metallizing a further conductive layer or track, and filling the hole on the substrate to form the metallized via disposed on the substrate, wherein the substrate provides a flared base for the via.

[0051] The method can include creating holes for providing vias with flared ends at the top and bottom of the barrel by rotating a laser beam tilted at an angle β of 20° relative to the axis of the hole.

[0052] The method can include drilling a reduced diameter hole with a laser beam normal to the laminate being drilled, and further drilling the hole by rotating the laser beam at several angular positions about the axis of the hole with the laser beam tilted at increasing angles β1, β2, β3 relative to the axis, and can include further metallizing the via having flared ends at the top and bottom of the barrel.

[0053] In such a case, the diameter of the laser beam may be less than half the diameter of the hole.

[0054] Other features, details and advantages are set forth in the following detailed description and drawings. [Brief explanation of the drawings]

[0055] [Figure 1] 1A-1C are schematic cross-sectional side views of examples of stress locations within a via.

[0056] [Figure 2] FIG. 1 is a cross-sectional side view of a PCB component with embedded components, vias and conductive tracks.

[0057] [Figure 3A] FIG. 3 is an enlarged view of the crack location in FIG. 2. [Figure 3B] FIG. 3 is an enlarged view of the crack location in FIG. 2.

[0058] [Figure 4A] 1 is a schematic cross-sectional side view of an embodiment of the present disclosure. [Figure 4B] 1 is a schematic cross-sectional side view of an embodiment of the present disclosure. [Figure 4C] 1 is a schematic cross-sectional side view of an embodiment of the present disclosure.

[0059] [Figure 5] FIG. 2 is a schematic diagram of the steps of a first method embodiment.

[0060] [Figure 6] FIG. 4 is a schematic diagram of the steps of a second method embodiment.

[0061] [Figure 7] FIG. 10 is a schematic diagram of the steps of a fourth method embodiment.

[0062] [Figure 8] FIG. 10 is a schematic diagram of the steps of a fifth method embodiment.

[0063] [Figure 9] 1 shows a chart of stress versus via end radius for two configurations of vias. [Figure 10] 1 shows a chart of stress versus via end radius for two configurations of vias. DETAILED DESCRIPTION OF THE INVENTION

[0064] As mentioned above, introducing sharp corners into a loaded structure creates stress concentrations. Stress singularities arise from idealized infinitely sharp corners (i.e., the radius of curvature R tends to zero), and in the framework of linear elastic fracture mechanics, stresses tending to infinitely high as the corner is approached. At a distance r from the corner, the stress is

number

number

number

[0065]

number

number

number

[0066] In this regard, Figure 1 shows an example of stress locations from a prior art design that arise in the case of z-axis expansion 10. A first stress location 11 is the interconnection between a microvia 12 and a buried track 13, a second stress location 14 is the interconnection between a plated-through hole barrel and a track, a third stress location 15 is within the plated-through hole barrel 16, and a fourth stress location 17 is found at the corner between the plated-through hole barrel and a flange 18.

[0067] In practical cases, infinitely sharp corners are not realized (for manufacturing and tolerance reasons), and corners typically have a radius of curvature of about 0.5 μm. The actual stress at the corner is proportional to the remote stress, by a factor

number

number

number

number

[0068] This is the case for vias located between copper layers or copper tracks, and for PCBs with embedded components such as semiconductor chips that have vias between the component's connection pads and the copper layers.

[0069] An example of a PCB with an embedded semiconductor chip or die 24 is shown in Figure 2. In this example, a via 23 is made between tracks 21, 22 or between track 21 and an embedded chip with a connecting layer 25. Examples of typical damage are shown in Figures 3A and 3B, such as a crack 28 between the top of via 23' and track 21, or a crack 29 in the via barrel in Figure 3A, and cracks 26, 27 between the top of via 23 and the conductive layer 25 of component 24 in Figure 3B.

[0070] FEM calculations on simplified 2D geometries give the following results for a PCB with an embedded die where two regions can be distinguished, based on the proximity to the embedded silicon die: a region corresponding to a via that is not connected to the silicon die and is far from the silicon die, for detecting via breakage due to stress acting in the z-direction of the structure; The area corresponding to the vias connected to the silicon die makes it possible to determine the insufficient reliability of the copper vias due to stresses in the x and y directions (in addition to the z direction) when power semiconductor chips or passive components are embedded in the PCB stack-up.

[0071] In this example, a first via with a height of 70 μm is located between a first copper layer with a height of 50 μm and a second copper layer with a height of 50 μm embedded in the FR4 laminate, and a second via with a height of 70 μm is located between the second copper layer and the embedded die conductive pad bond layer.

[0072] Plane strain conditions are assumed (i.e., this 2D shape corresponds to a cross section through an infinitely long slab). The material properties are chosen as follows: a.CTE Si = 3 ppm / K; CTE Cu =CTE FR4x = 18 ppm / K; CTE FR4Z = 41 or 82 ppm / K; bE elastic modulus: Si: 116GPa; Cu: 127GPa; FR4xy: 20.4GPa; FR4z: 15GPa.

[0073] For simplicity, a linear elastic material is assumed. The complete system is subjected to a temperature change of 100°C. The radii of curvature of all vias are varied from R = 0.3 μm to R = 30 μm in a parametric study (two cases: CTEFR4Y = 41 or 82 ppm / K).

[0074] As an illustrative example of the first problem, which is via failure due to stress acting in the z-direction of the structure, CTEFR4Z=82 ppm / K and temperature change

number

[0075] The continuous line 320 corresponding to maximum von Mises stress 300 in Pa versus via corner radius 310 in mm in FIG. 9 is fit to the following equation:

number

[0076] During the ceremony,

[0077] A=4.1·10 12 ;C=4.0·10 -4 ;α=0,4.

[0078] Such a diagram shows that the difference in CTE in the z-direction as the via structure is deformed results in stress at the via radius. A=4.1·10 12 ;C=4.0·10 -4 ;The formula where α=0,4

number

[0079] Furthermore, the following is observed: a. For small via radii (R<<5 μm), the ultimate strength of copper is exceeded, demonstrating the critical effect of sharp corners on reliability. b. By increasing the corner radius of the via, the stress concentration is significantly reduced, but the value remains higher than the yield strength of copper.

[0080] In this calculation, the CTE of FR4 in the z-direction is chosen as a value in the high range (CTE FR4Z =82 ppm / K). CTE FR4Z By choosing a value in the low range of =41 ppm / K, it is possible to reduce the maximum stress below the ultimate strength for all corner radii and below the yield strength for corner radii R>5 μm.

[0081] Therefore, by applying a corner radius of R>5 μm, it is possible to significantly increase the reliability of the system. Remote stress, the product of Eq.

number

number

number

number

number

[0082] Therefore, applications where temperature changes of more than 100°C are expected and / or where the CTE FR4Z In applications where epoxy composite laminates with >41 ppm / K are used, corner radii R greater than 5 μm are required.

[0083] As an illustrative example of the second problem, FR4Z =41 ppm / K and temperature change

number

number

[0084] Due to the CTE difference in the z-direction perpendicular to the PCB plane, combined with the CTE differences in the x and y-directions, the via structure deforms in the in-plane direction, resulting in stress at the via radius. The analytical model in equation (2) shows that due to the coupled effects of ΔCTEx and ΔCTEz, stress increases as R decreases with an exponent of 0.4, similar to the theoretical exponent of 0.5.

[0085] Furthermore, the following is observed: a. For small via radii (R<<5 μm), the ultimate strength of copper is exceeded, demonstrating the critical effect of sharp corners on reliability. b. By increasing the corner radius of the via, the stress concentration is significantly reduced to a value close to the yield strength.

[0086] Therefore, applying corner radii of R > 5 μm allows to significantly increase the reliability of the system and is necessary for applications where parts are embedded in epoxy composite laminates, even when CTEz in the low range is used.

[0087] These calculations demonstrate that a higher via radius significantly reduces maximum stress in both problems addressed in this invention.

[0088] Reference is now made to FIG. 4A, which shows a base epoxy-based composite material including an FR4 PCB material 100, a first conductive layer or track 110, a second conductive layer or track 120, and several vias 140 connecting said first conductive layer 110 and said second conductive layer 120.

[0089] According to the present disclosure, via 140 is a fully metallized via, as seen in Figure 4B, having flanged ends 142 (the height of which is exaggerated in the drawing) of barrel 141 at their junctions with layers 110, 120. Returning to Figure 4A, the flanged ends include a curvature 143 having a radius R1 such that the absolute value of R1 is greater than 5 μm to reduce stress at the junction between the via and the layers.

[0090] 4C, via 140 connects conductive pad 160 of component 170 embedded in epoxy resin / fiberglass laminate to conductive layer or track 120. In such a design, the via also includes flared ends at the junction with conductive pad 160 and at the junction with conductive layer or track 120.

[0091] The flared end has a first angle α1 defined as the angle between the via barrel 141 and the flared end 142, a second angle α2 defined as the angle between the flared end 142 and the conductive layers 110, 120, and a mean radius of curvature 143 R1 of the flared end.

[0092] A first angle α1 in the range 0<α1<45° is preferred.

[0093] A second angle α2 in the range of 0<α2<45° is preferred, as is a mean radius of curvature of the flared edge having an absolute value |R1| of 5 μm or greater.

[0094] The preferred design is a. A straight cut where α1 = α2 = 45° and R1 tends to ∞; b. α1 = α2 = 0° and |R1| is greater than 5 μm, preferably greater than 30 μm; c. Designs where α1 and α2 are between such angles, especially designs where α2 = π - α1 Includes.

[0095] One example application is a via structure subjected to temperature changes of 100°C or more, such as those typically experienced in power electronics environments and / or where other material design constraints require the CTE of FR4 material in the out-of-plane direction to be significantly higher than 40 ppm / K, e.g., 82 ppm / K. For example, assuming a 2D geometry for simplicity and illustrative purposes, if the flared joint radius of curvature is changed from R=0.3 μm in a state-of-the-art design to R=30 μm, which is approximately half the distance between the copper layers of a via with a height of 70 μm and located between a 50 μm first copper layer and a 50 μm second copper layer embedded in an FR4 laminate as described above, the maximum stress at the corner of the via connected between the copper layers of the PCB corresponding to a 100 K temperature change from a stress-free condition is reduced from over 600 MPa, which exceeds the ultimate strength of copper, to approximately 300 MPa, which is below the ultimate strength of copper and close to the yield strength of copper, as shown in Figure 9. Therefore, the reliability of the structure is improved.

[0096] Another example of an application of the present invention is a power semiconductor chip embedded in a PCB with an interconnect package consisting of copper vias with a flared joint radius of curvature comparable to the distance between the copper layers. Thus, stress concentrations are significantly reduced and the magnitude of the stress is less than the ultimate strength of copper, preferably less than the yield strength of copper, delaying (fatigue) crack initiation and improving reliability.

[0097] As another example of the present invention, assuming a 2D geometry for simplicity and illustrative purposes, if the flared junction radius of curvature is changed from Rc=0.3 μm (state-of-the-art design) to Rc=30 μm, the maximum stress (at the corners) of the via connected to the semiconductor die corresponding to a temperature change of 100° K from the stress-free situation is reduced from about 490 MPa (above the ultimate strength of copper) to about 300 MPa, which is below the ultimate strength of copper and close to the yield strength of copper, as shown in Figure 10. Thus, the reliability of the structure is improved.

[0098] Referring to FIG. 4C, the circuit board may include at least one further composite layer 130, 135 above or below one of the conductive layers or tracks, but may also include further conductive and composite layers.

[0099] A method for manufacturing a circuit board containing such vias with flared ends includes using a laser beam to form holes in the epoxy-based composite material in a direction perpendicular to the conductive layer.

[0100] In Figures 5 and 7, laser beams 200, 201 are configured to drill the hole with a barrel and provide at least one flared end at the top and / or bottom of the barrel.

[0101] 5, the formed hole is achieved by adjusting the focus 210 of the laser beam 200 at different heights 220 of the hole to create the hole with a diabolo shape that provides flared joining ends on both ends of the via, which may be rounded by the via metallization process.

[0102] Forming the hole can be done by firing a laser beam from only one side of the via location, or by firing a laser beam from one side of the via location and then another laser beam from the other side of the via location.

[0103] In a further implementation, the method can include the steps of providing a substrate 250 for at least some of the vias by a subtractive metallization process starting from a thick conductive layer or track 110 on a substructure 100 as in Figures 6(a) to 6(d), laminating an epoxy layer 130 on the conductive layer or track 110 as in Figure 6(e), forming and metallizing holes 180 as in Figure 6(f), and filling the metallized holes on the substrate to form the metallized vias 140 arranged on the substrate 250 as in Figure 6(g), wherein the substrate provides a flared base 142 of the vias.

[0104] 6(a) to 6(d), the step of providing the substrate 250 includes depositing a conductive precursor layer or track precursor layer 110a in FIG. 6(a), depositing an etching resist layer 230 on the precursor layer at the location where the substrate 250 will be provided as in FIG. 6(b), chemically etching the precursor layer to create the conductive layer or track 110 in which the substrate 250 remains together with the etching resist layer 230 as in FIG. 6(c), and removing the etching resist layer 230 to expose the substrate 250 as in FIG. 6(d).

[0105] Another possible method, as in FIG. 7, involves creating a hole 195 by rotating a laser beam 201 tilted at an angle β relative to the axis A of said hole.

[0106] Another possible process for providing a via with flared ends 142′ at the top and bottom of the barrel 141′ by laser drilling a hole in a PCB can include rotating a laser beam 202 of width less than half the diameter of the hole, inclined relative to the axis A of the hole at increasing angles β, β1, β2 of 10° to 30°.

[0107] This can include drilling a reduced diameter hole 191 with a laser beam 202 perpendicular to the stack 130 and the copper layers 110, 120 to be drilled, as in Figure 8(a), and further drilling the hole by rotating the laser beam 202 at several angular positions around the hole axis A, with the laser beam 202 tilted to the axis A at increasing angles β1, β2, β3 of 20° to 45°, as in Figures 8(b), 8(c), and 8(d), and then metallizing the hole to provide a via 140' with flared ends 142' at the top and bottom of the barrel 141'.

[0108] The above description shows non-limiting examples of the object of the invention as defined in the appended claims. In particular, the described methods are the only possibilities for producing vias as defined in the appended claims.

Claims

1. At least one epoxy-based composite layer (130) and at least two conductive layers or tracks (110, 120) on either side of said epoxy-based composite layer (130); first metallized vias (140) connecting said conductive layers or tracks (110, 120), at least some of said vias comprising metallized barrels (141, 141') terminating in at least one flared end (β, 142') of a junction between said metallized barrel and one of said conductive layers or tracks (110, 120); Circuit board.

2. The flared end is set as a first angle α1 defined as an angle between the via barrel and the flared end, the first angle α1 being in the range of 0 < α1 < 45°, a second angle α2 defined as an angle between the flared end and the conductive layer, the second angle α2 being in the range of 0 < α2 < 45°, and a mean radius of curvature (143) R1 of the flared end having an absolute value |R1| of 5 μm or more. The circuit board according to claim 1 .

3. 3. The circuit board according to claim 2, wherein α2=π−α1.

4. At least one embedded component (170), wherein one of the conductive layers (110) is a bonding layer with a conductive pad (160) of the embedded component (170); The circuit board according to any one of claims 1 to 3.

5. The composite material (100) has an in-plane CTE ｘｙ and a first coefficient of thermal expansion of ｚ and said conductive layer or track has a second coefficient of thermal expansion of CTE ｃｕ 5. The circuit board of claim 1, wherein the via flare end is a copper layer or track having a flared end calculated to limit stress at the joint between the via flare end (142, 142') and the copper layer to about 300 MPa under a temperature change of 100° K.

6. 6. A circuit board according to any one of the preceding claims, comprising at least one further layer (100, 135) of composite material above or below one of said conductive layers or tracks.

7. 7. A method for manufacturing a circuit board according to claim 1, comprising the steps of: creating the via (140, 140') by forming the hole (180, 190) in the epoxy-based composite material (130) in a direction perpendicular to the conductive layer (110, 120) using a laser beam (200) configured to drill a hole having a barrel; providing at least one flared end at a top and / or bottom of the barrel; and filling the hole to provide the via.

8. 8. The method of claim 7, wherein forming the hole is performed by adjusting the focus (210) of the laser beam at different heights (220) of the hole to create the hole having a diabolo shape that provides flared ends on both ends of the via.

9. The method of claim 8 , wherein the flared end is rounded by metallization of the via.

10. 8. The method of claim 7, comprising the steps of: providing a substrate (250) on a conductive layer or track (110) on a substructure (100) by a subtractive metallization process for at least some of the vias; laminating an epoxy layer (130) on the conductive layer or track (110) with the substrate (250); and forming holes (180) and filling the holes on the substrate to form the metallized vias (140) disposed on the substrate (250), wherein the substrate provides a flared base (142) of the vias.

11. 8. The method of claim 7, comprising the steps of depositing a conductive precursor layer or track precursor layer (110a), depositing an etch resist layer (230) on the precursor layer at a location where a substrate (250) will be provided, chemically etching the precursor layer to create the conductive layer or track (110), removing the etch resist layer (230) to expose the substrate (250), laminating a further epoxy layer (130) on the conductive layer or track (110), forming a hole (180), metallizing the hole, metallizing a further conductive layer or track (120), and filling the hole on the substrate to form the metallized via (140) disposed on the substrate (250), wherein the substrate provides a flared base (142) of the via.

12. 8. The method of claim 7, comprising the step of creating a hole (195) for providing a via (140') with flared ends (142') at the top and bottom of the barrel (141') by rotating laser beams (201, 202) inclined at angles β, β1, β2 between 10° and 30° relative to an axis (A) of the hole.

13. 13. The method of claim 12, comprising the steps of drilling a reduced diameter hole (190) with a laser beam (202) perpendicular to the laminate (130) to be drilled, and further drilling the hole by rotating the laser beam (202) at several angular positions about a hole axis (A) with the laser beam (202) tilted to said axis at increasing angles β1, β2, β3 between 20° and 45°, and further metallizing the via having flared ends (142) at the top and bottom of the barrel (141′).

14. The method of claim 13, wherein the diameter of the laser beam (202) is less than half the diameter of the hole.

Images