Branch target buffer with shared target bit

Abstract

Embodiments of the present disclosure include techniques for branch prediction. A branch predictor may be included in the front end of a processor. The branch predictor may store branch targets in a branch target buffer. The branch target buffer includes shared bits that can be combined with branch target bits to specify a branch target address. The shared bits may, for example, result in more efficient memory usage in the processor.

Description

[Background technology]

[0001] background The present disclosure relates generally to computing, and more particularly to a branch prediction buffer with a shared target bit.

[0002] Modern high-performance processors often deploy a separated front-end architecture to improve processor performance. In some processor front-ends, a branch predictor (BP) executes ahead of the instruction fetch unit and places instruction fetch addresses into a fetch target queue (FTQ). The branch predictor accesses a branch target buffer (BTB) to generate a packet of fetch addresses that is placed into the FTQ. Front-end performance is primarily determined by branch prediction throughput, which is governed by how many branches the branch predictor can support per cycle.

[0003] To support a large number of branches predicted per cycle, a Branch Target Buffer (BTB) entry contains information for a large number of branches. The more branches supported, the larger the BTB entry. This directly impacts area, power, and access time / latency, which impacts clock frequency and performance. [Brief explanation of the drawings]

[0004] [Figure 1] 1 illustrates a front-end architecture of a processor according to an embodiment. [Figure 2] 1 illustrates a method for predictive branching according to an embodiment. [Figure 3] 1 illustrates an example of a branch predictor according to an embodiment. [Figure 4] 1 illustrates a conventional branch target bit. [Figure 5] 1 illustrates branch target bits and shared bits according to an embodiment. [Figure 6] 10 illustrates branch target bits and shared bits according to yet another embodiment. [Figure 7] 1 illustrates an example branch target buffer entry according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0005] Detailed Description Techniques for branch target buffers are now described. In the following specification, for purposes of explanation, numerous examples and specific details are set forth in order to provide a thorough understanding of certain embodiments. Various embodiments as defined by the claims may include some or all of the features in these examples, alone or in combination with other features described below, and may also include variations and equivalents of the features and concepts described herein.

[0006] Features and advantages of the present disclosure include a branch target buffer with shared bits. According to various embodiments, the shared bits in the branch target buffer may be used in conjunction with bits representing the branch target, reducing the overall number of bits used in the branch target buffer, thereby reducing memory requirements and improving speed and performance.

[0007] 1 illustrates a front-end architecture 101 of a processor 150 according to an embodiment. The processor 150 may include a front-end 101 that includes a branch predictor 110, a fetch target queue (FTQ) 120, and, in this example, an instruction cache 130. The branch predictor 110 receives and analyzes instructions (e.g., from a program executed by the processor 150) and makes predictions regarding the outcomes of branch instructions cached in a branch target buffer (BTB). Addresses for the predicted instructions may be loaded into the FTQ 120. Instructions may be retrieved from memory or the instruction cache 130 and passed to the back-end 102 of the processor 150 for execution.

[0008] The branch predictor 110 includes a branch target buffer (BTB) 111 that includes multiple branch targets (T) 112-114. The branch targets may include multiple branch instructions and attributes of the branch targets (the attributes may include, for example, the branch type and the branch target address). The branch target buffer may include shared bits to optimize the BTB 111. The shared bits may be used in conjunction with bits in the targets 112-114 to specify the address of the branch target destination (e.g., the address for the set of instructions being branched to). For example, rather than each target using a fixed set of bits sufficient to allow a branch to the target destination, fewer bits may be used by the targets, and the branches may utilize one or more of the shared bits to specify the branch target destination. This is illustrated in more detail in the example below.

[0009] 2 illustrates a method for predicting branches according to an embodiment. At 201, a stream of instructions is analyzed by a branch predictor circuit. At 202, branches in the stream of instructions are identified. At 203, bits describing the branch are stored in a branch target buffer with bits shared among multiple branch targets. These bits may be combined and analyzed to predict the address of the next basic block of instructions. A block of instructions starting from the starting address of the basic block containing the branch instruction and ending with the maximum size of an executed branch instruction is passed to the FTQ.

[0010] FIG. 3 illustrates an example of a branch predictor according to an embodiment. Branch predictor 300 includes a predictor circuit block 303 and a branch target buffer (BTB) 301 (e.g., a cache). As described above, branch predictor 300 may receive a program instruction address and analyze the code for branches. An example of a branch may be an IF-THEN-ELSE statement, where the instruction after THEN is one branch and the instruction after ELSE is another branch. For example, to make the example more specific, consider the following example of an IF-THEN-ELSE: IF(x==y) THEN(a=a+1) ELSE(b=b+1)

[0011] The above IF-THEN-ELSE may generate the following sequence of instructions in an Instruction Set Architecture (ISA): 0x0000 CMP r0,r1 0x0004 B.NE else 0x0008 ADD r2,#1 0x000C B end else: 0x0010 ADD r3,#1 end: 0x0014

[0012] CMP is a compare instruction performed on two general-purpose register operands (in this example, assume "x" is in GPR r0 and "y" is in GPR r1). In this example, CMP is located at memory address 0x0000. B.NE is a conditional branch instruction at memory address 0x0004 with the target address labeled "else", and the compiler generates a memory address (0x0010). If the result of the compare instruction is not equal (NE), the branch directs execution to the target address; otherwise, execution flows sequentially to the next instruction at memory address 0x0008. If B.NE is predicted not taken, it fetches ADD (in this example, assume "a" is in GPR r2). After add is an unconditional branch to the label "end", the compiler again generates a memory address (0x0014). Assume the final ADD instruction is located at the memory address associated with the label "else" and that "b" is in GPR r3. Therefore, if the branch predictor predicts the condition as equal (the conditional branch is not taken), the ADD r3,#1 instruction is executed; otherwise, the ADD r2,#1 instruction is executed, and the second branch skips the ADD r3 instruction. In either case, the end of the sequence of instructions is the memory address associated with the label "end," which is the next code after the IF-THEN-ELSE construct.

[0013] Thus, the BTB has information for two branch instructions in that line of code: first, a B.NE instruction, and second, a B instruction. The target of B.NE is the memory address associated with the label "else" (0x0010), and the target of the "B" instruction is the memory address associated with the label "end" (0x0014).

[0014] Those skilled in the art will appreciate that a variety of different branch types exist in different processor instruction set architectures.

[0015] Branches are analyzed by predictor 303, which may analyze the branch and generate a probability that the branch will be taken. Predictor 303 may determine that the branch is "taken" (e.g., that the instruction at a particular branch target should be executed). If the branch is taken, branch predictor 300 looks up the branch target in BTB 301 and loads the branch target into the FTQ, as described above.

[0016] In this example, BTB 301 includes multiple entries 302 (e.g., entry 310). Entry 302 includes multiple branch targets (e.g., branch target 311 in entry 310) and multiple shared bits (“sh”) (e.g., shared bit 312 in entry 310). In some embodiments, entry 302 may have a fixed bit length, including multiple branch targets and shared bits. Advantageously, shared bits 312 are used in conjunction with one or more of branch targets 311 to specify a branch target address. For example, each branch target may be used in conjunction with one or more of the shared bits to represent an offset to the branch target address. Thus, a target address corresponding to a branch target in an entry includes a branch target bit and a corresponding bit of the shared bits. For smaller jump branches, fewer bits (e.g., branch target bit and a few or even no shared bits) may be used, while for larger jumps, branch target bit and some (or all) shared bits may be used. In some cases, different shared bits 312 may be used, particularly in conjunction with different branch targets, to specify a jump to a branch target address. In some cases, the branch targets in entries 302 include a fixed bit length. The use of shared bits allows, for example, the use of fewer bits for each branch target.

[0017] FIG. 4 illustrates a conventional branch target bit. Traditionally, branch targets are stored as fixed-bit-length entries. In this example, 26 bits are used to store each branch target. However, using a fixed bit length with enough bits to contain all possible destination address jumps can be wasteful, as many jumps do not require the use of all bits. This can waste memory and, for example, increase search time and power consumption.

[0018] FIG. 5 illustrates branch target bits and shared bits according to an embodiment. In this example, each branch target uses 16 bits. However, fewer branch target bits can be used because any one or more of the 16-bit branch targets can use one or more of the 10 shared bits available in the common pool. In some cases, the number of shared bits may be reduced to improve performance. For example, in some embodiments, the combination of a branch target fixed bit length (e.g., 16) and multiple shared bits (e.g., 10) is less than the maximum branch offset required to perform a full branch jump. In this case, even after considering the common pool, the number of bits supports less than the maximum program counter (PC) movement. This is referred to as area-efficient sharing.

[0019] 6 illustrates branch target bits and shared bits according to yet another embodiment. In this example, more shared bits are used to contain more branch target jumps. For example, in this embodiment, the combination of a fixed branch target bit length (e.g., 16) and multiple shared bits (e.g., 30) exceeds the maximum branch offset. In this case, even after considering the common pool, the number of bits supports the full maximum PC move. This is also referred to as high-performance sharing.

[0020] 7 illustrates a branch target buffer entry according to yet another embodiment. In this example, branch targets 701-702 in one or more entries 710 include branch type bits 711, offset bits 712 that specify the address of the branch instruction, and branch target bits 713 that specify the address of the branch target. Branch type 711 may include, for example, direct conditional, call, return, indirect, and direct unconditional. Branch type field 711 may include, for example, four bits. Branch offset 712 indicates the offset between the branch and the conditional (e.g., the address offset between the address for the conditional instruction and the address for the branch instruction). As described above, branch target 713 may include an address offset that can be combined with one or more shared bits to jump to the branch target address.

[0021] Further examples Each of the following non-limiting features in the examples below may be used independently or may be combined with one or more of the other features in the examples below in various permutations or combinations.

[0022] In various embodiments, the present disclosure may be implemented as a system (eg, in a processor or central processing unit CPU) or as a method.

[0023] In one embodiment, the present disclosure includes a processor including a front end, the front end including a branch predictor including a branch target buffer including a plurality of branch targets, and a fetch target queue, and a processor back end, the branch target buffer including a shared bit.

[0024] In one embodiment, the shared bit is used in conjunction with one or more of the branch targets to specify the branch target address.

[0025] In one embodiment, each branch target and one or more shared bits represents an offset to a branch target address.

[0026] In one embodiment, the branch target buffer includes a plurality of entries, each entry including a first plurality of branch targets and a plurality of shared bits.

[0027] In one embodiment, the entries have a fixed bit length.

[0028] In one embodiment, the branch target in one or more entries comprises a fixed bit length.

[0029] In one embodiment, the combination of the branch target fixed bit length and the number of shared bits is less than the maximum branch offset.

[0030] In one embodiment, the combination of the branch target fixed bit length and the multiple shared bits exceeds the maximum branch offset.

[0031] In one embodiment, the destination address corresponding to the branch target in one or more entries includes a first plurality of branch target bits and one or more corresponding bits of the shared bits.

[0032] In one embodiment, the branch target in one or more entries includes type bits, offset bits that specify the address of the branch instruction, and target bits that specify the address of the branch destination.

[0033] In another embodiment, the present disclosure includes a method of predicting branches in a processor, the method including analyzing a stream of instructions with a branch predictor circuit, identifying a branch in the stream of instructions, and storing bits describing the branch in a branch target buffer, the branch target buffer including a shared bit.

[0034] In one embodiment of the method, the shared bit is used in conjunction with one or more of the branch targets to specify a branch target address.

[0035] In one embodiment of the method, each branch target and one or more shared bits represents an offset to a branch target address.

[0036] In one embodiment of the method, the branch target buffer includes a plurality of entries, each entry including a first plurality of branch targets and a plurality of shared bits.

[0037] In one embodiment of the method, the plurality of entries has a fixed bit length.

[0038] In one embodiment of the method, the branch target in one or more entries comprises a fixed bit length.

[0039] In one embodiment of the method, the combination of the branch target fixed bit length and the number of shared bits is less than the maximum branch offset.

[0040] The above description illustrates various embodiments, along with examples of how aspects of some embodiments may be implemented. The above examples and embodiments should not be considered the only embodiments, but are presented to illustrate the versatility and advantages of some embodiments as defined by the following claims. Based on the above disclosure and the following claims, other arrangements, embodiments, implementations, and equivalents may be used without departing from the scope of what is defined by the claims.

Claims

1. The front end, a branch predictor including a branch target buffer including a plurality of branch targets; Fetch target queue and a front end including Processor backend and Including, the branch target buffer includes a shared bit; Processor.

2. 2. The processor of claim 1, wherein the shared bit is used in conjunction with one or more of the plurality of branch targets to specify a branch target address.

3. 2. The processor of claim 1, wherein each branch target and one or more shared bits represents an offset to a branch target address.

4. 2. The processor of claim 1, wherein the branch target buffer includes a plurality of entries, each entry including a first plurality of branch targets and a plurality of the shared bits.

5. The processor of claim 4 , wherein the plurality of entries have a fixed bit length.

6. The processor of claim 5 , wherein the branch target in one or more entries comprises a fixed bit length.

7. The processor of claim 6 , wherein the combination of the branch target fixed bit length and the plurality of the shared bits is less than a maximum branch offset.

8. The processor of claim 6 , wherein a combination of the branch target fixed bit length and the plurality of the shared bits exceeds a maximum branch offset.

9. 8. The processor of claim 7, wherein a destination address corresponding to a branch target in the one or more entries includes a first plurality of branch target bits and one or more corresponding bits of the shared bits.

10. 7. The processor of claim 6, wherein the branch target in the one or more entries includes type bits, offset bits that specify an address of a branch instruction, and target bits that specify an address of a branch target.

11. 1. A method of predictive branching in a processor, comprising: analyzing the stream of instructions with a branch predictor circuit; identifying a branch in said stream of instructions; storing bits describing said branch in a branch target buffer; Including, the branch target buffer includes a shared bit; method.

12. 12. The method of claim 11, wherein the shared bit is used in conjunction with one or more bits describing a particular branch to specify a branch target address.

13. 12. The method of claim 11, wherein the bits describing a particular branch and the one or more shared bits represent an offset to a branch target address.

14. 12. The method of claim 11, wherein the branch target buffer includes a plurality of entries, each entry including a first plurality of branch targets and a plurality of the shared bits.

15. The method of claim 14 , wherein the plurality of entries have a fixed bit length.

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