Integrated circuit devices with interconnects made from layered topological materials

Abstract

An integrated circuit device is described that includes one or more interconnects. Each interconnect of the one or more interconnects may be structured as a stack of layers including multiple topological layers, each of which may be a layer of topological material. Any two consecutive layers of the multiple topological layers may be separated by one or more interfaces that each form a boundary between the two consecutive layers of the stack, where the two consecutive layers may be designed to maintain a topologically preserved surface state of each of the two consecutive layers of the multiple topological layers.

Description

[Technical Field]

[0001] The present disclosure relates generally to the field of integrated circuit devices and methods of manufacturing such devices. In particular, the present disclosure is directed to integrated circuit devices having interconnects made of layered topological materials. [Background technology]

[0002] Interconnect technology is closely linked to the development of integrated circuit (IC) technology, which is currently moving toward 2-nm processes. Copper remains the material of choice for interconnects in complementary metal-oxide-semiconductor (CMOS) structures. However, this material presents increasing challenges as miniaturization continues. In particular, copper's resistivity is limited by grain boundaries and surface scattering. For example, the resistivity of a 10-nm diameter copper wire is an order of magnitude higher than the bulk resistivity of copper. In fact, significantly scaling down the dimensions of copper interconnects results in an exponential increase in their resistivity. Summary of the Invention

[0003] According to one aspect of the present disclosure, an integrated circuit device includes one or more interconnects, each interconnect structured as a stack of layers including a plurality of topological layers, each of the plurality of topological layers being a layer of topological material. Any two consecutive layers of the plurality of topological layers are separated by one or more interfaces. Each of these interfaces forms a boundary between the two consecutive layers of the stack, and the two consecutive layers are engineered to maintain a topologically preserved surface state of each of the two consecutive layers of the plurality of topological layers.

[0004] The multilayer interconnect structure described above provides multilevel topological currents that reduce the overall interconnect resistance. That is, this interconnect structure can be viewed as a set of surface-dominated topological conductors that produce special resistance scaling behavior. To this end, several topological layers are stacked while preserving the surface state of the topological layers. The idea is to divide the interconnect into n topological layers to take advantage of surface conduction. That is, stacking n such topological layers roughly divides the bulk resistance by n, while multiplying the surface resistance by n. However, because the surface resistance of topological materials can be much smaller than the bulk resistance, this layer structure provides a substantial improvement in the scaling characteristics of the interconnect in terms of electrical performance. Compared to regular conductors, a stack of surface-dominated conductor layers can typically reduce resistance by more than 70%.

[0005] In some embodiments, the stack of layers further includes a plurality of intermediate layers, each intermediate layer of which extends between two successive layers of the plurality of topology layers and thus forms two interfaces with each of the two successive layers. In this case, any two successive topology layers are further separated by two interfaces so as to maintain a topologically preserved surface state of each of the plurality of topology layers.

[0006] The reliance on intermediate layers allows the same topological material to be used in each successive topological layer of the stack, thereby enabling each successive topological layer to be obtained by the same material synthesis process. In some embodiments, each of the multiple topological layers can have the same chemical composition and the same structural phase. The average thickness of each intermediate layer is typically between 1 nm and 10 nm, although in some cases it is between 1 nm and 4 nm. For example, each intermediate layer of the multiple intermediate layers can be made of an ultrathin electrically insulating material.

[0007] In some embodiments, any two consecutive layers of the plurality of topological layers have different chemical compositions, thereby forming a layer stack that forms a heterostructure. In some embodiments, the layer stack is formed by alternating two topological materials having different chemical compositions.

[0008] Such an approach is advantageous because it does not require the addition of an intermediate layer, which leads to greater scalability. This also facilitates the manufacturing process insofar as no intermediate layer needs to be deposited. However, this requires the controlled deposition of two or more topological materials of different compositions.

[0009] In some embodiments, any two consecutive layers of the plurality of topological layers are consecutive layers with the same chemical composition but different crystal structure characteristics, the latter ensuring opposite chiral orientations of the consecutive layers. In some embodiments, the different crystal structure characteristics consist of different crystal orientations, e.g., the consecutive layers have different crystal orientations.

[0010] Such an approach is also advantageous because it does not require the addition of an intermediate layer, however, it still requires control of chirality, for example, based on crystal symmetry within each layer.

[0011] In principle, a variety of topological materials can be used to obtain a stack of topological layers. Such materials can include, for example, two-dimensional (2D) or three-dimensional (3D) topological materials. Examples of potentially suitable topological materials that can be used in the stack include NbAs, NbP, TaAs, TaP, MoTe2, WP2, MoP2, Ag2S, CoSi, WTe2, and TaIrTe4. In addition, as indicated above, two consecutive layers can have different crystal structure properties or different chemical compositions, such that the stack may contain two or more of the above materials. In some embodiments, one or more topological materials of the plurality of topological layers are conductive topological materials, such that both the bulk and the surface areas are conductive. For example, one or more topological materials of the plurality of topological layers can be Dirac topology semimetals or Weyl topology semimetals.

[0012] The average in-plane dimension of the layers of the stack is typically greater than 10 μm, while the average thickness of the topological layers can be between 2 and 15 nm.

[0013] According to another aspect of the present disclosure, a method for fabricating an integrated circuit device including one or more interconnects comprises depositing and structuring each interconnect of the one or more interconnects as a stack of layers to obtain an integrated circuit. The stack of layers includes a plurality of topological layers, each of the plurality of topological layers being a layer of topological material. Also, any two consecutive layers of the plurality of topological layers are separated by one or more interfaces, each of which forms a boundary between the two consecutive layers of the stack, and the two consecutive layers are designed to maintain a topologically preserved surface state of each of the two consecutive layers of the plurality of topological layers. The stack of layers can be deposited and structured according to a subtractive deposition process or a damascene deposition process.

[0014] Fabricating the above-described integrated circuit device is advantageous because the resulting multi-layer interconnect structure provides multi-level topological currents that reduce overall interconnect resistance. [Brief explanation of the drawings]

[0015] These and other objects, features, and advantages of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which is to be read in connection with the accompanying drawings. The illustrations are for clarity in facilitating understanding of the disclosure by those skilled in the art in conjunction with the detailed description. The drawings illustrate certain embodiments only and do not limit the disclosure.

[0016] [Figure 1] FIG. 1 is a 3D diagram of a portion of a simplified exemplary integrated circuit device in which interconnects may be structured as a stack of layers including multiple layers of topological materials, according to some embodiments of the present disclosure.

[0017] [Figure 2] FIG. 1 is a 2D cross-sectional view of a stack of multiple topological material layers separated by intermediate layers, according to some embodiments of the present disclosure.

[0018] [Figure 3] 1A-1D are 2D cross-sectional views of a stack of multiple topological material layers forming a topological heterostructure, according to some embodiments of the present disclosure.

[0019] [Figure 4] 2A-2D cross-sectional views of stacks of different topological material layers having the same chemical composition but different crystal structure properties, according to some embodiments of the present disclosure.

[0020] [Figure 5] FIG. 5A illustrates an electrical conduction mechanism associated with a stack of topological material layers according to an embodiment of the present disclosure, and FIG. 5B illustrates an electrical conduction mechanism associated with a stack of topological material layers according to an embodiment of the present disclosure.

[0021] [Figure 6] FIG. 6A illustrates another electrical conduction mechanism associated with a stack of topological material layers according to an embodiment of the present disclosure, and FIG. 6B illustrates another electrical conduction mechanism associated with a stack of topological material layers according to an embodiment of the present disclosure.

[0022] [Figure 7] Figure 7A is a 2D cross-sectional view showing high-level manufacturing steps of an integrated circuit using a subtractive deposition process according to some embodiments of the present disclosure; Figure 7B is a 2D cross-sectional view showing high-level manufacturing steps of an integrated circuit using a subtractive deposition process according to some embodiments of the present disclosure; Figure 7C is a 2D cross-sectional view showing high-level manufacturing steps of an integrated circuit using a subtractive deposition process according to some embodiments of the present disclosure; and Figure 7D is a 2D cross-sectional view showing high-level manufacturing steps of an integrated circuit using a subtractive deposition process according to some embodiments of the present disclosure.

[0023] [Figure 8] Figure 8A is a 2D cross-sectional view showing high-level manufacturing steps of an integrated circuit using a damascene-like deposition process according to some embodiments of the present disclosure, Figure 8B is a 2D cross-sectional view showing high-level manufacturing steps of an integrated circuit using a damascene-like deposition process according to some embodiments of the present disclosure, Figure 8C is a 2D cross-sectional view showing high-level manufacturing steps of an integrated circuit using a damascene-like deposition process according to some embodiments of the present disclosure, Figure 8D is a 2D cross-sectional view showing high-level manufacturing steps of an integrated circuit using a damascene-like deposition process according to some embodiments of the present disclosure, and Figure 8E is a 2D cross-sectional view showing high-level manufacturing steps of an integrated circuit using a damascene-like deposition process according to some embodiments of the present disclosure.

[0024] The accompanying drawings show simplified representations of devices or portions thereof, including various embodiments. The technical features shown in the drawings are not necessarily drawn to scale. Unless otherwise noted, like or functionally similar elements in the drawings are assigned the same reference numerals.

[0025] Integrated devices and methods of manufacture employing the present disclosure will now be described by way of non-limiting examples. DETAILED DESCRIPTION OF THE INVENTION

[0026] Aspects of the present disclosure are directed to integrated circuit devices having interconnects made of layered topological materials, where the layer stack maintains a topologically preserved surface state of the layers of topological material. While not limited to such applications, embodiments of the present disclosure may be better understood in light of the above context.

[0027] One embodiment of the present disclosure will now be described with reference to Figures 1, 2, 3, and 4. This embodiment is directed to an integrated circuit (IC) device 1, such as that shown schematically in Figure 1. The IC device 1 is typically structured to form several levels of interconnects 10 that connect circuit elements 20 to each other and / or to ohmic contacts. The circuit elements 20 may be embedded in a dielectric material 30 (as envisioned in Figure 1) or may rest on a dielectric layer. Also, the various interconnect elements 101, 102, 103, 104 are typically embedded in a dielectric material (not shown for clarity).

[0028] In conventional IC devices, such interconnects are typically made of metal, such as copper. Conversely, in the context of the present disclosure, each of the interconnect elements 101, 102, 103, 104 is structured as a stack of layers 11, 12, and 13, as shown, for example, in Figures 2, 3, and 4. The layer stacks include multiple topological layers 101, 102, 103, and 104. As referred to herein, a "topological layer" refers to a layer of topological material.

[0029] A topological material is a material that can support the flow of electrons on its surface (e.g., within a surface region close to the surface) thanks to topologically protected surface states. Note that in the accompanying drawings, each of the topological layers 101, 102, 103, and 104 is schematically divided into bulk portions 101b, 102b, 103b, and 104b sandwiched between surface regions 101s, 102s, 103s, and 104s. The surface states of a topological material are said to be topologically protected as a result of the topological properties of such materials. Such properties are known per se and depend heavily on the dimensions of such materials and their symmetry. Topology protection means that the system cannot spontaneously and continuously break its topological properties, thereby providing protection for charge carriers against scattering events. This protection ensures low electrical resistivity through the material.

[0030] The topological layers 101, 102, 103, and 104 may be made of topological insulators and / or topological semimetals, such as topological Weyl semimetals, topological Dirac semimetals, and topological nodal-line semimetals. Such topological materials are typically obtained as crystalline materials, e.g., single- or polycrystalline materials. However, in principle, some of these materials can also be amorphous. The topologically protected surface states of such topological materials result in such materials being able to conduct charge carriers, regardless of whether their bulk is conductive or not. This also applies to topological insulators, which conduct charge carriers only at their surface.

[0031] In the present context, the topology layers 101, 102, 103, 104 are layers, which means that they are well separated, for example by well-defined interfaces 111, 112, 113, 114, which can be verified thanks to appropriate microscopic techniques, such as transmission electron microscopy (TEM). An interface is a boundary between two spatial regions occupied by different solid materials or solid materials with different structural properties, for example forming separate phases of the same solid material or having different crystallographic directions.

[0032] As shown in Figures 3 and 4, two successive topology layers of a stack may, in some cases, be separated by a single interface 113, 114. In a variant, as in Figure 2, an intermediate layer 105 is interspersed between two successive topology layers. The intermediate layer 105 results in two clearly defined interfaces 111, 112 separating the two successive topology layers. Thus, successive topology layers may be arranged consecutively, as in Figures 3 and 4, or may be separated by the intermediate layer 105 (e.g., a separation layer). Any two successive topology layers 101, 102, 103, 104 are separated by one or more interfaces 111, 112, 113, 114.

[0033] The topology layers are arranged successively along a stacking direction, which is assumed to be direction z in the accompanying drawings. Note that in the examples of Figures 2, 3 and 4, the stacking direction happens to coincide with the intended direction of current propagation, and hence there are electrodes 40 on the top and bottom of the stacks 11, 12, 13. However, this does not necessarily have to be the case. In practice, the interconnects can have a variety of possible shapes as needed to connect the circuit elements. See Figure 1.

[0034] Each of the separation interfaces 111, 112, 113, and 114 forms a boundary between two successive layers of the stacks 11, 12, and 13. These two successive layers may be topology layers (as in FIGS. 3 and 4), or may consist of a topology layer 101 and a separation layer 105, as in FIG. 2. The two successive layers on each side of the separation interface are designed (e.g., deposited and processed) to maintain a topologically preserved surface state of each of the successive topology layers separated by this interface. Thus, the separation interface itself can be considered to be designed to maintain a topologically preserved surface state of each of the successive topology layers.

[0035] Examples of suitable designs include, for example, separating intermediate layers 105 that conform to the topology layers to form native atomic interfaces, and successive topology layers that are treated to induce opposing chiral currents in the successive layers. The successive topology layers are separated by well-defined interfaces and are designed to maintain the topologically preserved surface states of the individual topology layers 101, 102, 103, 104, ultimately forming the topologically preserved surface state of the layer stack 11, 12, 13 itself. Such individual layer states contribute to, and are therefore reflected in, the state of the entire layer stack.

[0036] The proposed layer structure arrangement of the interconnect aims to improve the scaling characteristics in terms of the electrical performance of the interconnect. To that end, several topology layers are stacked while taking into consideration the preservation of the surface state of the topology layers. The idea is to divide the conductor into n topology layers and take advantage of the surface conduction. A detailed explanation will be given later.

[0037] Figure 5A shows the current propagation through the topology layers from the top electrode to the bottom electrode. Figure 5B shows the equivalent resistor circuit. Resistor R S and R B denote the unit resistance of the surface and bulk states, respectively. In ordinary electrical conductors, these two quantities are usually equal (R S =R BHowever, conductors with topologically protected surface states, as in the cases of topological semimetals and topological insulators, exhibit a high R S < <R B Therefore, as shown in FIG. 5B, the equivalent resistance of a surface-dominated topological conductor is R Eq ≒2R S +R B where stacking n such topology layers defines a layer transformation, which can be approximated as L n (R Eq )≒2nR S +R B / n. Thus, for example, for a topological material with a surface resistance 50 times smaller than its bulk resistance, a five-layer transformation reduces the resistance by approximately 70%. Even a two-layer transformation can reduce the resistance by approximately 50%. Therefore, using a stack of surface-dominated conductor layers can reduce the resistance by more than 70%.

[0038] 6A and 6B show the effect of dividing a surface-dominated topological conductor (SDTC) into four layers. To achieve the above-mentioned properties, the surface-dominated topological conductor must be divided appropriately, which can be achieved by stacking the topological material layers appropriately. Furthermore, to maintain the surface state of the topological layers, keeping clean interfaces should be considered. Several possibilities can be envisioned to obtain a suitable layer stack.

[0039] As mentioned above, one technique is to separate successive topology layers 101 by at least one intermediate layer 105, such as a single intermediate layer as assumed in FIG. 2. In that case, two successive topology layers 101 in the stack are not consecutive layers. In fact, any two successive topology layers 101 in the stack are separated by two interfaces. For example, a first interface 111 is formed between a given topology layer 101 and an adjacent intermediate layer 105 (directly below this layer 101 in FIG. 2), while a second interface 112 is formed between this intermediate layer 105 and the next topology layer 101 (directly below this intermediate layer 105 in FIG. 2). Therefore, each of these two separation interfaces must be designed to maintain (preserve) the surface state of the successive topology layers. That is, the materials, shapes, and topographical arrangements of the successive materials 101, 105, 101 involved on each side of the separation interface must not substantially change the surface state of the topology layer 101.

[0040] Another technique is to rely on sufficiently different topology layers, without intermediate layers, that can therefore be arranged consecutively in a stack, as in FIGS. 3 and 4. Successive topology layers can differ in terms of chemical composition and / or structural properties. That is, in some embodiments, the two regions on either side of the interface 113 between two consecutive topology layers 101, 102 can be occupied by different solid materials, resulting in a heterostructure, as in FIG. 3, with the successive topology layers having different chemical compositions. Note that the chemical compositions should be substantially different, such that the two consecutive topology layers 101, 102 contain different chemical elements, different proportions of such elements, or substantially different amounts of dopants. In a variant, the solid materials in the two layers 103, 104 on either side of the separation interface 114 have different structural properties, such as different phases or crystal orientations, resulting in opposite chiral directions, as envisioned in FIG. 4.

[0041] In the above example, any two consecutive layers of the multiple topological layers are separated by one or more clearly defined interfaces. These can be considered heterointerfaces because they separate distinct solid materials designed to maintain the topologically preserved surface state of the consecutive topological layers. This not only ensures electrical conduction across the interconnect, but also has benefits in terms of electrical resistance when scaling down the interconnect. The above-described multilayer interconnect structure results in multilevel topological currents that reduce the overall interconnect resistance. This interconnect structure can be considered a set of surface-dominated topological conductors that produce special resistance scaling behavior and improve the electrical performance of the interconnect 10.

[0042] An aspect of this approach is to achieve an interface that maintains the topologically protected state of successive topology layers. The separation interface should not substantially alter the protected surface state of the topology layers; that is, the separation interface should be compatible with such surface state. In particular, any two layers on each side of a separation interface that bounds a topology layer should be designed (e.g., deposited and processed) to maintain the topologically protected surface state of successive topology layers bounded by the separation interface.

[0043] In connection with certain embodiments of the present disclosure, the topological layer may include a topological semimetal and / or a topological insulator. As previously mentioned, topological insulators conduct charge carriers, but only at their surfaces. However, a multilayer stack of topological insulators contains more conductive surfaces, making it more conductive than a single layer of topological insulator. That is, while the reduction in resistance in a stack of topological insulators can already be significant, a multilayer stack of topological semimetals can, in principle, be more efficient at conducting current flow than a multilayer stack of topological insulators. As a result, some embodiments rely on topological semimetals, such as Dirac topological semimetals and Weyl topological semimetals.

[0044] The topological layers 101, 102, 103, and 104 can be made of, among others, Dirac semimetals (DSMs) or Weyl semimetals (WSMs). In particular, the topological layers can be made of 3D topological materials such as type-1 WSMs (e.g., NbAs, NbP, and TaAs) and type-2 WSMs (e.g., WP2, MoP2, WTe2, MoTe2, and TaIrTe4). However, in principle, the topological layers 101, 102, 103, and 104 can also be made of other types of topological materials, such as magnetic Weyl semimetals (e.g., PrAlGe, Co2MnGa, Co3Sn2S2, Mn3Sn, and Mn3Ge), various fermion-containing materials (e.g., CoSi and RhSi), and nodal line semimetals (e.g., Ag2S, Co2MnGa, ZrSiS, HfSiS, and PbTaSe2). As mentioned above, topological insulators can also be envisioned, such as materials from the Bi2X3 group, where X = O, S, Se, or Te. A further possibility is to use 2D van der Waals topological materials, such as graphene, transition metal dichalcogenides MX2 (where M = W or Mo and X = Te, S, Se, or MnBi2Te4). In addition, in some cases, 2D and 3D materials can be combined to form heterostructures. Thus, a variety of topological materials and their combinations can be envisioned.

[0045] The average in-plane dimensions of the layers in the stack 11, 12, 13 are typically greater than 10 μm. The in-plane dimensions are measured in a plane (x, y) perpendicular to the stacking direction z. The average thickness of the multiple topology layers 101, 102, 103, 104 can be between 2 and 15 nm. This thickness is measured along the axis z. Of course, the optimal thickness depends on the desired properties of the interconnect, the materials used, and the desired form factor of the IC device 1. In general, the thickness of each topology layer can be selected to avoid crosstalk between the top and bottom Fermi surface states, since crosstalk can cause electron backscattering and therefore increase resistance.

[0046] As mentioned above, some embodiments involve separator interlayers 105. See FIG. 2. Each interlayer extends between two consecutive topology layers 101. It functions as a spacer separating two consecutive topology layers in the stack. In some embodiments, a single interlayer 105 is provided between two consecutive topology layers 101. Each interlayer forms two interfaces 111, 112 with the adjacent layer 101. The layers of the stack are deposited and structured so as not to disrupt the topological surface states of the topology layers. To that end, the interlayer 105 should not have energy states at or near the Fermi level of the topological conductor or ultimately the entire layer stack. In principle, a properly designed interlayer 105 could potentially create additional surface states that contribute to enhancing surface currents.

[0047] Various types of materials can be envisioned for the intermediate layer 105, as long as they do not substantially affect the topologically protected surface state of the adjacent topological layer. For example, the material used in layer 105 should not have an energy state at or near the Fermi level of the topological conductor. Furthermore, in principle, various types of materials can be used to fabricate the intermediate layer 105, including dielectrics (e.g., SiO2, Al2O3), topological materials (e.g., topological insulators such as Bi2Se3 or Bi2Te3), and even metals (e.g., Al, Cu, Ta). In fact, if the intermediate layer is made of a sufficiently thin metal, the topological surface state of the adjacent topological layer may survive thanks to topology protection. 2D van der Waals (vdW) materials such as hexagonal boron nitride or CrCl3 are another option. Weak vdW bonds result in less strain induced at the interface, helping to maintain the topological surface state of the adjacent layer 101.

[0048] In other embodiments, the intermediate layers 105 are made of an electrically insulating material. Each intermediate layer 105 may be made, for example, as an ultrathin insulator, thereby resisting the flow of current across it in the classical physical sense. Nevertheless, this insulator may be made thin enough to allow transverse current to tunnel from one topology layer to the next, thus allowing current to flow laterally (along z) through the stack 11. When an ultrathin insulator is used as an intermediate layer 105, the resistance of the overall stack 11 does not increase substantially, but carriers can flow by tunneling completely through such an insulating layer. For example, the separator may be made of an ultrathin oxide or nitride having a thickness of one to a few nanometers.

[0049] For interconnects that are sufficiently long in the in-plane direction, i.e., in the plane (x, y), the lateral resistance (along z) of the interlayer will be relatively small because most current transfer occurs in-plane. Generally, the average thickness of the interlayer 105 will be less than 50 nm. In some embodiments, it may be between 1 nm and 10 nm. However, in embodiments in which the separator is an electrical insulator, it may be made thin enough to allow lateral tunneling. In such cases, the thickness of the interlayer is typically between 1 and 4 nm.

[0050] Relying on separator interlayers 105 allows for the use of the same topological material 101 in each successive topological layer of the stack 11, as envisioned in FIG. 2. This topological material may also have the same structural phase within each layer 101. This allows for relying on the same process of material synthesis to obtain each successive topological layer. Note that even if the topological layers 101 are isomorphic, they may differ locally, for example, with respect to grain size and / or grain orientation. However, a drawback of such additional interlayers 105 is that they increase the overall height of the interconnect structure. They may also increase the resistivity (mainly along the stacking direction).

[0051] Thus, in some embodiments, the layer stack 12 is designed as a topological heterostructure, as envisioned in FIG. 3 . Here, the topological layers 101 and 102 are arranged consecutively but made of different materials (e.g., materials of different chemical compositions). In fact, any topological material layer with a protected surface state can also function as a separator material. Therefore, proper separation can also be achieved thanks to the different topological materials. Thus, the layer stack 12 forms a topological heterostructure in which the surface state is still maintained. Such an approach is advantageous because it does not require the addition of an intermediate layer 105, which leads to greater scalability. This facilitates the manufacturing process insofar as an intermediate layer does not need to be deposited. However, this requires the controlled deposition of two or more topological materials of different compositions.

[0052] Some embodiments of the present disclosure rely on two different topological materials, i.e., the layer stack 12 forms alternating layers 101, 102 of two topological materials of different chemical composition, such that the topological layers of the two different compositions alternate along the stacking direction z.

[0053] For example, a layer stack can be made of two Weyl semimetals. Each Weyl semimetal layer is characterized by charge carriers with a specific chirality χ = ±1, i.e., a spin-momentum locking configuration. Chirality is an inherently conserved quantity. In Weyl semimetals, chirality conservation prevents carrier spin flips. At the very least, this property makes it more difficult for electrons to flip their spins. Chirality conservation in Weyl semimetals contributes to the robustness of protected surface states (e.g., it is a form of topological protection of charge carriers, including carriers associated with surface states).

[0054] However, chirality preservation does not prevent local differences. In particular, it is possible to design topology layer surfaces that exhibit opposite average chiral directions. One possibility for achieving this is to grow successive topology layers with the same chemical composition but different crystal structure properties, as in some embodiments described herein with reference to FIG. 4. In this example, the layer stack 13 includes successive topology Weyl semimetal layers 103 and 104 arranged in layers. The layers 103 and 104 have the same chemical composition but distinct crystal structure properties. Such properties are designed to provide chirality control. That is, the crystal structure properties of successive layers ensure opposite chiral directions, for example, from one layer 103 to the other 104, so that charge carriers have opposite average chiral directions.

[0055] Chirality control can be achieved, inter alia, by engineering different crystallographic directions in any two consecutive topological Weyl semimetal materials of the same composition. Thus, two consecutive layers 103, 104 can have different crystallographic directions, resulting in opposite chiral directions. One can, for example, exploit the unique property of topological Weyl semimetals, where the chirality of current is locked. This can be used to implement surface state separation between subsequent layers 103, 104 without the need for a separator as in Figures 2 or 3. Furthermore, Figure 4 can be considered a special case of Figure 3, where consecutive topological layers have different crystallographic directions instead of different compositions.

[0056] This approach allows topological materials of the same chemical composition to be used, but it still requires control of chirality based on crystal symmetry within each layer, which is considerably more difficult to achieve in practice. Therefore, it may be beneficial to rely on layer structures such as those in Figures 2 and 3. Overall, the layer stack in Figure 2 is the simplest to fabricate, but the stack in Figure 3 offers better performance due to the absence of intermediate layers.

[0057] Next, according to another aspect of the present disclosure, a method for manufacturing an IC device 1 including one or more interconnects 10 is described. The method aims to obtain the IC device 1 by depositing and structuring each interconnect 10 of the IC device 1 as a stack of layers 11, 12, 13, as previously described with reference to Figures 2, 3, and 4. Ultimately, the stack 11, 12, 13 includes a plurality of topology layers 101, 102, 103, 104, where any two consecutive topology layers 101, 102, 103, 104 are separated by one or more interfaces 111, 113, 114, each forming a boundary between the two consecutive layers of the stack 11, 12, 13, and the consecutive layers are designed to maintain a topologically preserved surface state of each of the two consecutive topology layers.

[0058] The layer stack 11, 12, and 13 can be deposited and structured according to a subtractive deposition process, for example, as shown in FIGS. 7A, 7B, 7C, and 7D. For example, the topology layer 12l can first be deposited sequentially on a support layer 35, such as a dielectric layer, as shown in FIG. 7A. The layers of the stack 12l are deposited using an appropriate film deposition technique. They can be deposited using epitaxial methods, such as physical vapor deposition (PVD) techniques like molecular beam epitaxy (MBE), or precision thin-film deposition techniques like atomic layer deposition (ALD). In this example, the deposited layer stack 12l forms a heterostructure like that in FIG. 3. Next, a mask layer 50 is deposited and structured on top of the stack 12l (FIG. 7B), and then the layer stack 12l is subtractively etched through the structured mask layer to form structured stacks 12s separated by gaps (FIG. 7C). These gaps are finally filled with a dielectric material 60, such as SiO2. See Figure 7D. Such steps may typically be completed by a planarization step and the deposition of an additional dielectric layer.

[0059] In a variant, the layer stack 11, 12, 13 is deposited and structured according to a deposition process such as damascene. For example, a dielectric damascene etching step can be performed through an oxide layer 65, which itself rests on a support layer 35. See FIG. 8A. Next, using the appropriate thin film deposition techniques described above, a seed layer 70 is deposited on the structured dielectric (FIG. 8B), and then a layer stack 12d of topological material is deposited on the seed layer 70 (FIG. 8C). The upper parts of the deposited layers are subsequently removed (FIG. 8D), and a dielectric layer 67 is deposited on top (FIG. 8E). Such a step can again be completed by a planarization step and the deposition of an additional dielectric layer.

[0060] While the present disclosure has been described with reference to a limited number of embodiments, variations, and accompanying drawings, those skilled in the art will recognize that various changes may be made and equivalents may be substituted without departing from the scope of the present disclosure. In particular, features (such as devices or methods) described in a given embodiment, variation, or illustrated in a drawing may be combined with or substituted for other features in other embodiments, variations, or drawings without departing from the scope of the present disclosure. Various combinations of features described with respect to any of the above embodiments or variations may be contemplated accordingly, while remaining within the scope of the appended claims. In addition, many minor modifications may be made to adapt a particular situation or material to the teachings of the present disclosure without departing from its scope. Therefore, the present disclosure is not limited to the particular embodiments disclosed, but it is intended that the present disclosure include all embodiments falling within the scope of the appended claims. Additionally, numerous variations other than those expressly mentioned above may be contemplated. For example, materials other than those explicitly mentioned may be contemplated, whether for topology layers, substrates, dielectric fillers, etc.

Claims

1. 1. An integrated circuit device comprising one or more interconnects, each interconnect of the one or more interconnects is structured as a stack of layers having a plurality of topological layers, each of the plurality of topological layers being a layer of topological material; any two successive layers of the plurality of topology layers are separated by one or more interfaces each forming a boundary between two successive layers of the stack, wherein the two successive layers are designed to maintain a topologically preserved surface state of each of the any two successive layers of the plurality of topology layers; Integrated circuit devices.

2. the topological material of one or more of the plurality of topological layers is an electrically conductive topological material; 10. The integrated circuit device of claim 1.

3. the two successive layers have different chemical compositions or different crystal structure characteristics; 10. The integrated circuit device of claim 1.

4. the average in-plane dimension of the layers of the stack is greater than 10 μm; 10. The integrated circuit device of claim 1.

5. the average thickness of the plurality of topology layers is between 2 nm and 15 nm; 10. The integrated circuit device of claim 1.

6. the topological material of one or more of the plurality of topological layers is a 3D topological material; 10. The integrated circuit device of claim 1.

7. the topological material of one or more of the plurality of topological layers is a Dirac topological semimetal; 10. The integrated circuit device of claim 1.

8. the topological material of one or more of the plurality of topological layers is a Weyl topological semimetal; 10. The integrated circuit device of claim 1.

9. The topological material of one or more of the plurality of topological layers is NbAs, NbP, TaAs, TaP, CoSi, MoTe ２ , W.P. ２ , MoP ２ , Ag ２ S, WTe ２ and TaIrTe ４ is one selected from the group consisting of:

9. The integrated circuit device of claim 8.

10. the stack of layers further comprises an intermediate layer; the intermediate layer extends between two successive layers of the plurality of topology layers, thereby forming two interfaces with each of the two successive layers, respectively; 10. The integrated circuit device of claim 1.

11. The integrated circuit device of claim 10 , wherein each of the plurality of topological layers has the same chemical composition and the same structural phase.

12. The intermediate layer is made of an electrically insulating material.

12. The integrated circuit device of claim 11.

13. The average thickness of each intermediate layer is between 1 nm and 10 nm.

13. The integrated circuit device of claim 12.

14. any two consecutive layers of the plurality of topology layers are consecutive layers having different chemical compositions, such that the layer stack forms a heterostructure; 10. The integrated circuit device of claim 1.

15. the stack of layers is an alternating stack of two topological materials of different chemical compositions; 15. The integrated circuit device of claim 14.

16. any two consecutive layers of the plurality of topological layers are consecutive layers having the same chemical composition and different crystal structure characteristics, and the different crystal structure characteristics ensure opposite chiral directions of the consecutive layers; 10. The integrated circuit device of claim 1.

17. the different crystal structure characteristics being composed of different crystal orientations, such that the successive layers have different crystal orientations; 17. The integrated circuit device of claim 16.

18. 1. A method of manufacturing an integrated circuit device including one or more interconnects, comprising: depositing and structuring each interconnect of said one or more interconnects as a stack of layers to obtain said integrated circuit; the stack of layers includes a plurality of topological layers, each of the plurality of topological layers being a layer of topological material; any two consecutive layers of the plurality of topology layers are separated by one or more interfaces, each of the one or more interfaces forming a boundary between two consecutive layers of the stack, wherein the two consecutive layers are designed to maintain a topologically preserved surface state of each of the any two consecutive layers of the plurality of topology layers. method.

19. the stack of layers is deposited and structured by a subtractive deposition process, 20. The method of claim 18.

20. The stack of layers is deposited using a damascene deposition process.

20. The method of claim 18.

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