Negative capacitance for ferroelectric capacitance memory cells.

Abstract

A capacitance memory cell includes an electrode, a tunnel barrier layer in direct contact with the electrode, a charge trapping layer in direct contact with the tunnel barrier layer, a ferroelectric layer in direct contact with the charge trapping layer, and another electrode in direct contact with the ferroelectric layer.

Description

[Technical Field]

[0001] The present invention relates to computer memory, and more particularly to ferroelectric capacitance memory devices. [Background technology]

[0002] Capacitive memory cells incorporating ferroelectric materials have been proposed as a replacement for other nonvolatile memory devices, such as resistive random access memory (RRAM) and phase change memory (PCM). This is because RRAM and PCM cells rely on current flow to sense their state, whereas capacitive memory does not. Instead, the capacitive memory state is stored as a zero-bias capacitance across the cell. Such capacitive memory cells could be useful in many applications, such as artificial intelligence and machine learning.

[0003] However, conventional capacitance memory cells rely on hysteresis in the ferroelectric layer to create different states. When the capacitance versus voltage behavior of such a capacitance memory cell is graphed, it results in what is known as a butterfly curve. Unfortunately, because the butterfly curve is rather short, the difference in capacitance between different hysteresis voltage states is rather small. This limits the number of states that can be stored and the reliability of reading those states. Summary of the Invention

[0004] According to one embodiment of the present disclosure, a capacitance memory cell includes an electrode, a tunnel barrier layer in direct contact with the electrode, a charge trapping layer in direct contact with the tunnel barrier layer, a ferroelectric layer in direct contact with the charge trapping layer, and another electrode in direct contact with the ferroelectric layer.

[0005] Because of the tunnel barrier layer and charge trapping layer, charge can be stored within the cell, thereby altering the capacitance of the cell. The altered capacitance can represent a state that persists even after the electrical bias is removed. This makes the cell a non-volatile memory device. Furthermore, the tunnel barrier layer and charge trapping layer allow an increased capacitance difference to exist, thereby increasing the operating window compared to cells that have only a ferroelectric layer and rely on hysteresis. This provides more granularity in states (e.g., more states than just 1 and 0) and / or more contrast between states (e.g., more reliable state reading).

[0006] According to another embodiment of the present disclosure, an integrated circuit includes a charge transistor, a capacitance memory cell connected to the charge transistor, a discharge transistor connected to the capacitance memory cell, and a sensing component configured to measure the discharge of the capacitance memory cell, the capacitance memory cell including an electrode, a tunnel barrier layer, a charge trapping layer, a ferroelectric layer, and another electrode.

[0007] Because of the tunnel barrier layer and charge trapping layer, charge can be stored within the cell, thereby altering the capacitance of the cell. The altered capacitance can represent a state that persists even after the electrical bias is removed. This makes the cell a non-volatile memory device. Furthermore, the tunnel barrier layer and charge trapping layer allow an increased capacitance difference to exist, thereby increasing the operating window compared to cells that have only a ferroelectric layer and rely on hysteresis. This provides more granularity in states (e.g., more states than just 1 and 0) and / or more contrast between states (e.g., more reliable state reading).

[0008] Additionally, because the integrated circuit measures the discharge of the cell, current does not need to be pushed through the cell to sense its condition, which reduces the power consumption of the integrated circuit and may allow for more capacitive memory cells to be present in the integrated circuit than if resistive memory cells were used.

[0009] According to another embodiment of the present disclosure, a method of operating a capacitance memory cell includes applying an electrical bias to an electrode to move electrons from another electrode through a tunnel barrier layer to a charge trapping layer, removing the electrical bias to preserve the memory state, and sensing the memory state with a sensing circuit.

[0010] Because of the tunnel barrier layer and charge trapping layer, charge can be stored within the cell, thereby altering the capacitance of the cell. The altered capacitance can represent a state that persists even after the electrical bias is removed. This makes the cell a non-volatile memory device. Furthermore, the tunnel barrier layer and charge trapping layer allow an increased capacitance difference to exist, thereby increasing the operating window compared to cells that have only a ferroelectric layer and rely on hysteresis. This provides more granularity in states (e.g., more states than just 1 and 0) and / or more contrast between states (e.g., more reliable state reading). [Brief explanation of the drawings]

[0011] [Figure 1A] 1 is a cross-sectional view of a metal-ferroelectric-insulator-insulator-metal (MFIIM) capacitive memory cell according to one embodiment of the present disclosure.

[0012] [Figure 1B] FIG. 1B is a cross-sectional view of the MFIIM cell of FIG. 1A including electrons, according to one embodiment of the present disclosure.

[0013] [Figure 2]FIG. 2A is a graph of capacitance versus voltage for an uncharged MFIIM cell according to one embodiment of the present disclosure, and FIG. 2B is a graph of capacitance versus voltage for a charged MFIIM cell according to one embodiment of the present disclosure.

[0014] [Figure 3] FIG. 3A is a graph of capacitance versus voltage for an MFIIM cell with a modified alpha value according to one embodiment of the present disclosure, and FIG. 3B is a graph of capacitance versus voltage for an MFIIM cell with a modified remnant polarization according to one embodiment of the present disclosure.

[0015] [Figure 4] FIG. 10 is a circuit array diagram of a neural network during a charging phase, according to one embodiment of the present disclosure.

[0016] [Figure 5] FIG. 10 is a circuit array diagram of a neural network during a discharge phase, according to one embodiment of the present disclosure.

[0017] [Figure 6] 1B is a flowchart of a method for fabricating the MFIIM cell of FIG. 1A according to one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0018] Various embodiments of the present disclosure are described herein with reference to the associated drawings. Alternative embodiments are possible without departing from the scope of the present disclosure. It should be noted that in the following description and drawings, various connections and relationships (e.g., above, below, adjacent, etc.) are described between elements. These connections and / or relationships may be direct or indirect unless otherwise specified, and the present disclosure is not intended to be limited in this respect. Thus, coupling of entities may refer to either direct or indirect coupling, and relationship between entities may be direct or indirect. As an example of an indirect relationship, a reference herein to forming layer "A" on layer "B" includes a situation in which one or more intermediate layers (e.g., layers ("C" and "D")) are between layer "A" and layer "B," so long as the associated properties and functions of layer "A" and layer "B" are not substantially altered by the intermediate layers.

[0019] The following definitions and abbreviations are used in interpreting the claims and this specification. As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," "contains," or "containing," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or device that includes a list of elements is not necessarily limited to only those elements but may include other elements not expressly listed or that are inherent in such composition, mixture, process, method, article, or device. Additionally, any numerical range contained herein includes its limits unless expressly stated otherwise.

[0020] For purposes of the following description, terms such as “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” and “bottom,” as well as their derivatives, refer to the structures and methods being described in terms of their orientation in the drawings. The terms “overlying,” “atop,” “on top,” “positioned on,” or “positioned atop” mean that a first element, such as a first structure, is on a second element, such as a second structure; intervening elements, such as interface structures, may be present between the first and second elements. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected at the interface between the two elements without any intermediate conductive, insulating, or semiconducting layers. Note that the term “selective,” for example, as in “a first element selective to a second element,” means that the first element can be etched and the second element can act as an etch stop.

[0021] For the sake of brevity, conventional techniques for the manufacture of semiconductor devices and integrated circuits (ICs) may or may not be described in detail herein. Moreover, various tasks and process steps described herein may be combined into more comprehensive procedures or processes having additional steps or functions not described in detail herein. In particular, because the various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known, for the sake of brevity, many conventional steps will only be briefly mentioned herein or will be omitted entirely without providing details of the well-known processes.

[0022] Generally, the various processes used to form microchips that are packaged into ICs fall into four general categories: film deposition, removal / etching, semiconductor doping, and patterning / lithography.

[0023] Vapor deposition can be any process that grows, coats, or otherwise transfers material onto a wafer. Available techniques include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently atomic layer deposition (ALD). Another vapor deposition technique is plasma-enhanced chemical vapor deposition (PECVD), a process that uses energy in a plasma to induce reactions at the wafer surface that would otherwise require the higher temperatures associated with conventional CVD. Energetic ion bombardment during PECVD deposition can also improve the electrical and mechanical properties of the film.

[0024] Removal / etching can be any process that removes material from a wafer. Examples include etching processes (either wet or dry), chemical mechanical planarization (CMP), and the like. One example of a removal process is ion beam etching (IBE). Generally, IBE (or milling) refers to a dry plasma etching method that utilizes a remote broad beam ion / plasma source to remove substrate material by means of physically inert and / or chemically reactive gases. Like other dry plasma etching techniques, IBE offers advantages such as etch rate, anisotropy, selectivity, uniformity, aspect ratio, and minimal substrate damage. Another example of a dry removal process is reactive ion etching (RIE). Generally, RIE uses a chemically reactive plasma to remove material deposited on the wafer. With RIE, a plasma is generated by an electromagnetic field under low pressure (vacuum). High-energy ions from the RIE plasma bombard and react with the wafer surface, removing the material.

[0025] Semiconductor doping can be the modification of electrical properties by doping the source and drain of a transistor, for example, typically by diffusion and / or ion implantation. These doping processes are followed by a furnace anneal or rapid thermal anneal ("Rapid Thermal Annealing" (RTA)). The anneal serves to activate the implanted dopants. Films of both conductors (e.g., polysilicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide (SiO2), silicon nitride (SiN), etc.) are used to connect and isolate transistors and their components. Selective doping of various regions of a semiconductor substrate allows the conductivity of the substrate to be changed by applying a voltage. By creating structures of these various components, millions of transistors can be constructed and wired together to form the complex circuits of modern microelectronic devices.

[0026] Semiconductor lithography allows for the creation of three-dimensional relief images or patterns on a semiconductor substrate, which can then be transferred into the substrate. In semiconductor lithography, the patterns are formed using a light-sensitive polymer called a photoresist. The lithography and etching pattern transfer steps are repeated multiple times to build the complex structures that make up transistors and the numerous wires that connect the millions of transistors in a circuit. Each pattern printed on the wafer is aligned with previously formed patterns, gradually building up conductors, insulators, and selectively doped regions to form the final device.

[0027] 1A is a cross-sectional view of a metal-ferroelectric-insulator-insulator-metal (MFIIM) capacitive memory cell 100 (hereinafter "cell 100"). In the embodiment shown, a bottom wire 102 is connected to cell 100, which comprises bottom wire 102, bottom electrode 104, tunnel barrier layer 106, charge trapping layer 108, ferroelectric layer 110, and top electrode 112. A top wire 114 is also connected to cell 100, and an insulator 116 surrounds cell 100 to provide electrical isolation.

[0028] In the embodiment shown, the bottom of the bottom electrode 104 is in direct contact with and electrically connected to the top of the bottom wire 102, which can receive electrical signals from other components of the IC (shown in FIG. 5 ). The bottom of the tunnel barrier layer 106 is in direct contact with and electrically connected to the top of the bottom electrode 104, the bottom of the charge trapping layer 108 is in direct contact with and electrically connected to the top of the tunnel barrier layer 106, the bottom of the ferroelectric layer 110 is in direct contact with and electrically connected to the top of the charge trapping layer 108, and the bottom of the top electrode 112 is in direct contact with and electrically connected to the top of the ferroelectric layer 110. The bottom of the top wire 114 is in direct contact with the top of the top electrode 112 and is electrically connected to the top of the top electrode 112, allowing the top wire 114 to supply electrical signals from the cell 100 to other components of the IC (shown in FIG. 9).

[0029] In the embodiment shown, the bottom electrode 104, tunnel barrier layer 106, charge trapping layer 108, ferroelectric layer 110, and top electrode 112 are all planar and have the same width (i.e., each of their widths is within 10% of the width of an adjacent layer). The thickness of the tunnel barrier layer 106 may be between 1 nanometer (nm) and 3 nm, or about 2 nm. The thickness of the charge trapping layer 108 may be between 1 nm and 5 nm, or about 3 nm. The thickness of the ferroelectric layer 108 may be between 6 nm and 10 nm, or about 8 nm. However, the size and shape of the bottom wire 102 (i.e., the electrically upstream contact) and / or the top wire 114 (i.e., the electrically downstream contact) may differ from those of the cell 100.

[0030] In the embodiment shown, the bottom wire 102, bottom electrode 104, top electrode 112, and top wire 114 are composed of a highly conductive material, such as a metal or a metal compound, e.g., titanium nitride (TiN), tantalum nitride (TaN), or tungsten (W). In the embodiment shown, the insulator 116 is composed of a dielectric (electrically insulating) material, e.g., silicon nitride (SiN), silicon oxide (SiO), silicon carbonitride (SiNC), or tetraethyl orthosilicate (TEOS).

[0031] In the illustrated embodiment, the tunnel barrier 106 is composed of SiN and / or aluminum oxide (AlO), and the charge trapping layer 108 is composed of tantalum oxide (TaO) and / or titanium oxide (TiO). The ferroelectric layer 110 includes a doped hafnium oxide (HfO) material, where the dopants can be zirconium (Zr), silicon (Si), and / or aluminum (Al), resulting in HfZrO, HfSiO, and HfAlO, respectively. This results in the cell 100 having two non-ferroelectric layers (106, 108) in series with one ferroelectric layer (110) between the electrodes 104 and 112. The paraelectric dielectric materials listed for the tunnel barrier 106 and charge trapping layer 108 and the ferroelectric dielectric materials listed for the ferroelectric layer 110 are exemplary and non-limiting. Therefore, other materials having the same basic properties can be substituted by those skilled in the art.

[0032] 1B is a cross-sectional view of cell 100 containing electrons 118. In the embodiment shown, a positive electrical bias 120 is applied to top electrode 112. However, in some embodiments, a negative electrical bias (not shown) is applied to bottom electrode 112, either alone or in combination with positive electrical bias 120.

[0033] In the illustrated embodiment, a positive electrical bias 120 causes electrons 118 to move from the bottom electrode 104 through the tunnel barrier layer 106 and into the charge trapping layer 108. Because the charge trapping layer 108 allows the electrons 118 to flow through itself at voltages above a threshold level but prevents the electrons 118 from flowing through itself at voltages below the threshold level, the electrons 118 remain in the charge trapping layer 108 even after the positive electrical bias 120 is removed. This preserves the memory state created when the positive electrical bias 130 was present using the electrons 118. Because the memory state persists after the positive electrical bias is removed, the cell 100 is a nonvolatile memory device. Although some of the electrons 118 may be trapped in the ferroelectric layer 110, the electrons 118 are primarily trapped in the charge trapping layer 108 due to its higher trap density and shallower trap level.

[0034] 2A is a graph of capacitance versus voltage for cell 100 in an uncharged state. Such a state of cell 100 is shown in FIG. 1A. In the illustrated embodiment, a capacitance curve 122 at 0 volts is indicated by circle 124. Generally, capacitance curve 122 is symmetrical, with its peak at 0 volts. Thus, cell 100 has its highest capacitance at 0 volts.

[0035] 2B is a graph of capacitance versus voltage for cell 100 in a charged state. Such a state of cell 100 is shown in FIG. 1B. In the illustrated embodiment, capacitance curve 126 has generally the same shape as capacitance curve 122. However, capacitance curve 126 is shifted to the right. Thus, the capacitance of cell 100 charged to zero volts (0V), as indicated by circle 128, is significantly lower than that of cell 100 not charged to 0V. Because the capacitance of cell 100 at 0V can be measured, different values ​​can represent different memory states.

[0036] In the embodiment shown, the amount of shift in capacitance curve 126 is proportional to the amount of trapped charge, so that the capacitance of cell 100 at 0V can be controlled accordingly, and thus the memory state can be set.

[0037] For comparison, a prior art capacitance memory cell (not shown) uses a metal-ferroelectric-metal (MFM) configuration. Because the variance in capacitance at 0V was due to hysteresis, the maximum capacitance variation was relatively low. In some prior art cells, the peak capacitance was only 1.2 times greater than the base capacitance. However, due to the implementation of the tunnel barrier layer 106, charge trapping layer 108, and ferroelectric layer 110, the variation in capacitance at 0V can be significantly larger. In some embodiments, the peak capacitance is more than 5 times greater than the base capacitance. In some embodiments, the peak capacitance is about 10 times greater than the base capacitance. This increase in process window allows for more granularity in states (e.g., more states than simply 1 and 0) and / or more contrast between states (e.g., more reliable state reading).

[0038] FIG. 3A is a graph of capacitance versus voltage for an alternative embodiment MFIIM capacitive memory cell 100′ (hereinafter “cell 100′”). Because cell 100′ has different physical parameters than cell 100, the capacitance of cell 100′ is illustrated by capacitance curve 130 (shown together with capacitance curve 122 for reference). In the illustrated embodiment, cell 100′ has a different alpha value for its ferroelectric layer 110. The alpha value is a physical parameter in the Landau-Kalatnikov (LK) equation that describes the relationship between electric field and polarization charge per unit area. In some embodiments, the alpha value is −0.8×10 11 Farad per centimeter (cm / F) and -2.0 x 10 11 cm / F; in some embodiments, the alpha value is between -1.2×10 11cm / F and -1.6×10 11 cm / F; in some embodiments, the alpha value is between -1.3×10 11 cm / F and -1.5×10 11 Between cm / F.

[0039] Varying the alpha value primarily controls the height of the peak in the capacitance curve 130. A lower peak typically results in a shallower slope downward from the peak, which allows intermediate states between the peak and the base to be more easily generated and detected. However, a lower peak provides less contrast from the base capacitance, which can affect the reliability and number of intermediate states that can be detected.

[0040] FIG. 3B is a graph of capacitance versus voltage for an alternative embodiment MFIIM capacitive memory cell 100″ (hereinafter “cell 100”). Because cell 100″ has different physical parameters than cell 100, the capacitance of cell 100″ is illustrated by capacitance curve 132 (shown along with capacitance curve 122 for reference). In the illustrated embodiment, cell 100″ has a different remnant polarization of its ferroelectric layer 110. The remnant polarization depends on the amount of dopant present in ferroelectric layer 110. In some embodiments, the remnant polarization is measured in microchromium per square centimeter (μC / cm 2 ) and 20μC / cm 2 in some embodiments, the remnant polarization is between 2 μC / cm 2 and 16 μC / cm 2 in some embodiments, the remnant polarization is between 5 μC / cm 2 and 10 μC / cm 2 It is between.

[0041] Varying the remnant polarization primarily controls the width of the capacitance curve 132. A wider curve typically results in a shallower slope down from the peak, which makes intermediate states between the peak and the base easier to generate and detect. However, a wider curve requires a higher operating voltage to shift the curve between states.

[0042] The opportunity to modify the physical properties (e.g., alpha value and remnant polarization) of cell 100 allows cell 100 to be tailored for different applications. For example, cell 100 can be an efficient binary memory cell by having a high, narrow capacitance curve. In another example, cell 100 can be a high-capacity memory cell by having a wide, gently sloping capacitance curve.

[0043] This memory state can then be sensed as a 0V capacitance. To do so, electrons 118 are moved out of cell 100. This occurs by electrons 118 escaping from charge trapping layer 108, flowing through ferroelectric layer 110 and top electrode 112, and into top wire 114.

[0044] 4 is a circuit array diagram of neural network (NN) 134 during the charging phase. In the embodiment shown, NN 134 has a "cross-point array" configuration and includes sub-circuits 136A-136D (collectively, "sub-circuits 136"). Each sub-circuit 136 includes a charge transistor 138A-138D (collectively, "charge transistor 138"), a discharge transistor 140A-140D (collectively, "discharge transistor 140"), and an MFIIM capacitance memory cell 100A-100D (collectively, "cell 100"), respectively.

[0045] In the embodiment shown, each of charge transistors 138A-138D has one end connected to input line 142 and the other end connected to cells 100A-100D and discharge transistors 136A-136D. Using cell 100 as computer memory is accomplished in two phases, the first phase (the charge phase) being shown here. In this phase, a charge transistor 138 (e.g., 138A) is turned on to allow current to flow to the corresponding cell 100 (e.g., 100A). However, the corresponding discharge transistor 140 (e.g., 140A) is turned off, thereby preventing current from flowing from cell 100.

[0046] 5 is a circuit array diagram of neural network 134 during the second (discharge) phase. In the illustrated embodiment, discharge transistor 140 (e.g., 140A) is energized, allowing current flow out of the corresponding cell 100 (e.g., 100A). However, the corresponding charge transistor 138 (e.g., 138A) is not energized, thereby preventing current flow into cell 100. The charge in cell 100 then transfers through output line 144 to sensing component 146. In some embodiments, sensing component 146 is a reference capacitor with a known capacitance. A voltage reading across sensing component 146 may then be sensed, for example, by a computer processor, which may reveal the state cell 100 was in, since the amount of charge stored in cell 100 proportionally changes the capacitance of sensing component 146.

[0047] Although each sub-circuit 136 can be operated independently as a separate memory cell, NN 134 can use multiple sub-circuits 136 simultaneously. In one such embodiment, component 146 can be an integrator that can sense the rate at which current flows from cells 100 as they are discharged. Such an arrangement allows for multiply-and-accumulate (MAC) operations.

[0048] Because memory states in NN 134 are stored capacitance-wise, the power consumption required to sense them is significantly reduced compared to, for example, resistive memory cells, which allows NN 134 to be scaled up to larger arrays than would be possible with, for example, resistive memory.

[0049] 6 is a flowchart of a method 200 for fabricating the cell 100. In the illustrated embodiment, the method 200 begins at operation 202, where an electrode material is deposited on an interconnect layer including the bottom wire 102. In operation 204, a tunnel barrier material is deposited on the electrode material. In operation 206, a charge trapping material is deposited on the tunnel barrier material. In operation 208, a ferroelectric material is deposited on the charge trapping material. In operation 210, an annealing process is used to crystallize the ferroelectric material. In operation 212, an electrode material is deposited on the ferroelectric material. In operation 214, the stack is patterned and etched to form the cell 100. In operation 216, an insulator material is deposited to surround the cell 100.

[0050] Description of Some Exemplary Embodiments The following is a non-exclusive description of some exemplary embodiments of the present disclosure.

[0051] A capacitance memory cell according to an exemplary embodiment of the present disclosure comprises, among other possible elements, a first electrode; a tunnel barrier layer in direct contact with the first electrode; a charge trapping layer in direct contact with the tunnel barrier layer; a ferroelectric layer in direct contact with the charge trapping layer; and a second electrode in direct contact with the ferroelectric layer.

[0052] The capacitance memory cell of the preceding paragraph may optionally additionally and / or alternatively comprise any one or more of the following features, configurations and / or additional components.

[0053] A further embodiment of any of the foregoing capacitance memory cells, wherein the tunnel barrier layer may comprise a silicon nitride material and / or an aluminum oxide material.

[0054] A further embodiment of any of the preceding capacitive memory cells, wherein the charge trapping layer may comprise a tantalum oxide and / or titanium oxide material.

[0055] A further embodiment of any of the preceding capacitive memory cells, wherein the ferroelectric layer may comprise a doped hafnium oxide material.

[0056] A further embodiment of any of the preceding capacitive memory cells, wherein the dopant in the hafnium oxide material may include zirconium.

[0057] A further embodiment of any of the preceding capacitive memory cells, wherein the dopant in the hafnium oxide material may include silicon.

[0058] A further embodiment of any of the preceding capacitive memory cells, wherein the dopant in the hafnium oxide material may include aluminum.

[0059] A further embodiment of any of the preceding capacitive memory cells, wherein the ferroelectric layer may be between 6 nanometers and 10 nanometers thick.

[0060] A further embodiment of any of the aforementioned capacitive memory cells, wherein the charge trapping layer can be between 1 nanometer and 5 nanometers in thickness.

[0061] A further embodiment of any of the aforementioned capacitance memory cells, wherein the tunnel barrier layer can be between 1 nanometer and 3 nanometers thick.

[0062] A further embodiment of any of the aforementioned capacitance memory cells, wherein each of the first electrode, the tunnel barrier layer, the charge trapping layer, the ferroelectric layer, and the second electrode may be planar and have the same width.

[0063] An integrated circuit according to an exemplary embodiment of the present disclosure includes, among other possible things: a charge transistor; a capacitance memory cell connected to the charge transistor, the capacitance memory cell having a first electrode; a tunnel barrier layer; a charge trapping layer; a ferroelectric layer; and a second electrode; a discharge transistor connected to the capacitance memory cell; and a sensing component configured to measure the discharge of the capacitance memory cell.

[0064] The integrated circuit of the preceding paragraph may optionally and / or alternatively comprise any one or more of the following features, configurations and / or additional components.

[0065] A further embodiment of the aforementioned integrated circuit, wherein the tunnel barrier layer may be in direct contact with the first electrode; the charge trapping layer may be in direct contact with the tunnel barrier layer; the ferroelectric layer may be in direct contact with the charge trapping layer; and the second electrode may be in direct contact with the ferroelectric layer.

[0066] Further embodiments of any of the aforementioned integrated circuits, wherein the tunnel barrier layer may comprise a silicon nitride material and / or an aluminum oxide material.

[0067] Further embodiments of any of the aforementioned integrated circuits, wherein the charge trapping layer may comprise a tantalum oxide material and / or a titanium oxide material.

[0068] Further embodiments of any of the preceding integrated circuits, wherein the ferroelectric layer may comprise a doped hafnium oxide material, where the dopant may be selected from the group consisting of zirconium, silicon, and aluminum.

[0069] A further embodiment of any of the aforementioned integrated circuits, wherein each of the first electrode, the tunnel barrier layer, the charge trapping layer, the ferroelectric layer, and the second electrode may be planar and may have the same width.

[0070] A method of operating a capacitance memory cell according to an exemplary embodiment of the present disclosure includes, among other possible things, applying an electrical bias to a first electrode to move electrons from the second electrode through the tunnel barrier layer to the charge trapping layer; removing the electrical bias to preserve the memory state; and sensing the memory state using a sensing circuit.

[0071] The method of the preceding paragraph may optionally and / or alternatively comprise any one or more of the following features, configurations and / or additional components.

[0072] A further embodiment of the foregoing method, wherein sensing the memory state may include discharging electrons to a reference capacitor in the sensing circuit; and measuring a voltage across the reference capacitor.

[0073] A further embodiment of any of the preceding methods, wherein the electrical bias can be positive.

[0074] The description of various embodiments of the present invention is presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein has been selected to best explain the principles of the embodiments, practical applications, or technical improvements over technologies found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. a first electrode; a tunnel barrier layer in direct contact with the first electrode; a charge trapping layer in direct contact with the tunnel barrier layer; a ferroelectric layer in direct contact with the charge trapping layer; and a second electrode in direct contact with the ferroelectric layer; A capacitance memory cell comprising:

2. The capacitive memory cell of claim 1 , wherein the tunnel barrier layer comprises a silicon nitride material and / or an aluminum oxide material.

3. The capacitive memory cell of claim 1 , wherein the charge trapping layer comprises a tantalum oxide and / or titanium oxide material.

4. The capacitive memory cell of claim 1 , wherein the ferroelectric layer comprises a doped hafnium oxide material.

5. The capacitive memory cell of claim 4 wherein the dopant in the hafnium oxide material comprises zirconium.

6. The capacitive memory cell of claim 4 wherein the dopant in the hafnium oxide material comprises silicon.

7. The capacitive memory cell of claim 4 wherein the dopant in the hafnium oxide material comprises aluminum.

8. 10. The capacitive memory cell of claim 1, wherein the ferroelectric layer is between 6 nanometers and 10 nanometers thick.

9. The capacitive memory cell of claim 1 , wherein the charge trapping layer is between 1 nanometer and 5 nanometers thick.

10. The capacitance memory cell of claim 1 , wherein the tunnel barrier layer has a thickness between 1 nanometer and 3 nanometers.

11. 10. The capacitance memory cell of claim 1, wherein each of the first electrode, the tunnel barrier layer, the charge trapping layer, the ferroelectric layer, and the second electrode is planar and has the same width.

12. charging transistor; a capacitance memory cell connected to the charge transistor, a first electrode; Tunnel barrier layer; charge trapping layer; a ferroelectric layer; and Second electrode a capacitance memory cell having a discharge transistor connected to the capacitance memory cell; and a sensing component configured to measure the discharge of the capacitive memory cell; 1. An integrated circuit comprising:

13. the tunnel barrier layer is in direct contact with the first electrode; the charge trapping layer is in direct contact with the tunnel barrier layer; the ferroelectric layer is in direct contact with the charge trapping layer; and The second electrode is in direct contact with the ferroelectric layer.

13. The integrated circuit of claim 12.

14. The integrated circuit of claim 12 , wherein the tunnel barrier layer comprises a silicon nitride material and / or an aluminum oxide material.

15. The integrated circuit of claim 12 , wherein the charge trapping layer comprises a tantalum oxide and / or titanium oxide material.

16. 13. The integrated circuit of claim 12, wherein the ferroelectric layer comprises a doped hafnium oxide material, wherein the dopant is selected from the group consisting of zirconium, silicon, and aluminum.

17. 13. The integrated circuit of claim 12, wherein each of the first electrode, the tunnel barrier layer, the charge trapping layer, the ferroelectric layer, and the second electrode is planar and has the same width.

18. 1. A method of operating a capacitive memory cell, comprising: applying an electrical bias to the first electrode to cause electrons to move from the second electrode through the tunnel barrier layer to the charge trapping layer; removing the electrical bias to preserve the memory state; and sensing said memory state using a sensing circuit; A method comprising:

19. The step of detecting a memory state includes: discharging the electrons to a reference capacitor in the sensing circuit; and measuring a voltage across the reference capacitor having 20. The method of claim 18.

20. 20. The method of claim 18, wherein the electrical bias is positive.

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