Improved contact structure for power supply on semiconductor devices

Abstract

The semiconductor structure with an improved backside metal contact includes a plurality of source / drain regions in a field effect transistor. The backside metal contact is electrically connected to at least one of the plurality of source / drain regions. The backside metal contact includes a first tapered profile. The semiconductor structure further includes a backside power rail electrically connected to the at least one source / drain region through the backside metal contact. The backside power rail includes a second tapered profile different from the first tapered profile.

Description

[Technical Field]

[0001] The present invention relates generally to the field of semiconductor devices, and more particularly to powering active devices.

[0002] Modern integrated circuits (ICs) consist of transistors, capacitors, and other devices formed on a semiconductor substrate. On the substrate, these devices are initially isolated from one another but are then interconnected together to form functional circuits. Typically, the interconnect structure includes horizontal interconnects such as metal lines (wires) and vertical interconnects such as vias and contacts. Power is provided to an integrated circuit through power rails located in the metal layers of the integrated circuit. For example, a lower metal layer (M0 or M1) may include multiple metal lines, such as a VDD power rail and a VSS power rail.

[0003] As ICs continue to scale smaller in size, backside power rails (BPRs), i.e., power rails formed on the backside of the wafer, typically formed under the transistor "fins," and backside power distribution ("backside" being under the transistor substrate), have been proposed to alleviate design challenges and enable the technology to scale beyond the 5-nm technology node. BPR technology can free up resources for dense logic connections that limit modern processor performance, enable further scaling of standard logic cells by eliminating the overhead in area occupied by power rails, and enable thicker, lower-resistance power rails that enable lower voltage (IR) drops. While existing approaches in semiconductor fabrication are generally adequate for their intended purposes, they are not entirely satisfactory in all respects. One particular area of ​​concern involves forming metal contacts on the backside of ICs. Summary of the Invention

[0004] According to one embodiment of the present disclosure, a semiconductor structure comprises: a plurality of source / drain regions in a field effect transistor; a backside metal contact electrically connected to at least one source / drain region of the plurality of source / drain regions, the backside metal contact having a first tapered profile; and a backside power rail electrically connected to the at least one source / drain region through the backside metal contact, the backside power rail having a second tapered profile, the second tapered profile being different from the first tapered profile.

[0005] According to another embodiment of the present disclosure, a method of forming a semiconductor structure includes forming a plurality of source / drain regions in a field effect transistor; forming a backside metal contact electrically connected to at least one source / drain region of the plurality of source / drain regions, the backside metal contact having a first tapered profile; and forming a backside power rail electrically connected to the at least one source / drain region through the backside metal contact, the backside power rail having a second tapered profile, the second tapered profile being different from the first tapered profile. [Brief explanation of the drawings]

[0006] The following detailed description is provided by way of example, and is not intended to be limiting of the invention only, and is best understood in conjunction with the accompanying drawings, in which:

[0007] [Figure 1] 1A-1C are top views of a semiconductor structure at intermediate stages during a semiconductor manufacturing process, showing different cross-sectional views used to explain embodiments of the present disclosure.

[0008] [Figure 2] 2A-2C are cross-sectional views of the semiconductor structure taken along Y1-Y1' shown in FIG. 1, illustrating stages of forming a nanosheet stack according to one embodiment of the present disclosure.

[0009] [Figure 3] 2 is a cross-sectional view of the semiconductor structure taken along line Y1-Y1' shown in FIG. 1, illustrating the steps of patterning the nanosheet stack and forming the nanosheet fin, according to one embodiment of the present disclosure.

[0010] [Figure 4-1] FIG. 4A is a cross-sectional view of the semiconductor structure taken along Y1-Y1' shown in FIG. 1 illustrating the step of depositing a dummy gate and a sacrificial hard mask according to one embodiment of the present disclosure.

[0011] [Figure 4-2] FIG. 4B is a cross-sectional view of the semiconductor structure taken along line Y2-Y2' shown in FIG. 1 according to one embodiment of the present disclosure.

[0012] FIG. 4C is a cross-sectional view of a semiconductor structure taken along line XX' according to one embodiment of the present disclosure.

[0013] [Figure 5-1] FIG. 5A is a cross-sectional view of the semiconductor structure taken along Y1-Y1' shown in FIG. 1 illustrating the step of removing the nanosheet stack sacrificial layer according to one embodiment of the present disclosure.

[0014] [Figure 5-2] FIG. 5B is a cross-sectional view of the semiconductor structure taken along line Y2-Y2' shown in FIG. 1 according to one embodiment of the present disclosure.

[0015] FIG. 5C is a cross-sectional view of a semiconductor structure taken along line XX' according to one embodiment of the present disclosure.

[0016] [Figure 6-1] FIG. 6A is a cross-sectional view of the semiconductor structure taken along Y1-Y1' shown in FIG. 1 illustrating a step of forming sidewall spacers according to one embodiment of the present disclosure.

[0017] [Figure 6-2] FIG. 6B is a cross-sectional view of the semiconductor structure taken along line Y2-Y2' shown in FIG. 1 according to one embodiment of the present disclosure.

[0018] FIG. 6C is a cross-sectional view of a semiconductor structure taken along line XX' according to one embodiment of the present disclosure.

[0019] [Figure 7-1] 7A is a cross-sectional view of the semiconductor structure taken along line Y1-Y1' shown in FIG. 1 illustrating the steps of recessing the nanosheet fins and forming inner spacers according to one embodiment of the present disclosure.

[0020] [Figure 7-2] FIG. 7B is a cross-sectional view of the semiconductor structure taken along line Y2-Y2' shown in FIG. 1 according to one embodiment of the present disclosure.

[0021] FIG. 7C is a cross-sectional view of a semiconductor structure taken along line XX' according to one embodiment of the present disclosure.

[0022] [Figure 8-1] 8A is a cross-sectional view of the semiconductor structure taken along Y1-Y1' shown in FIG. 1 illustrating forming a spacer protection layer and performing back contact patterning according to one embodiment of the present disclosure.

[0023] [Figure 8-2] FIG. 8B is a cross-sectional view of the semiconductor structure taken along line Y2-Y2' shown in FIG. 1 according to one embodiment of the present disclosure.

[0024] FIG. 8C is a cross-sectional view of a semiconductor structure taken along line XX' according to one embodiment of the present disclosure.

[0025] [Figure 9-1]FIG. 9A is a cross-sectional view of the semiconductor structure taken along Y1-Y1' shown in FIG. 1 illustrating a stage of sigma etching the first semiconductor layer according to one embodiment of the present disclosure.

[0026] [Figure 9-2] FIG. 9B is a cross-sectional view of the semiconductor structure taken along line Y2-Y2' shown in FIG. 1 according to one embodiment of the present disclosure.

[0027] FIG. 9C is a cross-sectional view of a semiconductor structure taken along line XX' according to one embodiment of the present disclosure.

[0028] [Figure 10-1] FIG. 10A is a cross-sectional view of the semiconductor structure taken along Y1-Y1' shown in FIG. 1 illustrating forming a placeholder layer and removing a planarizing layer according to one embodiment of the present disclosure.

[0029] [Figure 10-2] FIG. 10B is a cross-sectional view of the semiconductor structure taken along line Y2-Y2' shown in FIG. 1 according to one embodiment of the present disclosure.

[0030] FIG. 10C is a cross-sectional view of a semiconductor structure taken along line XX' according to one embodiment of the present disclosure.

[0031] [Figure 11-1] 11A is a cross-sectional view of the semiconductor structure taken along Y1-Y1' shown in FIG. 1 illustrating the steps of removing the spacer protection layer and forming a back-end interconnect level and a carrier wafer according to one embodiment of the present disclosure.

[0032] [Figure 11-2] FIG. 11B is a cross-sectional view of the semiconductor structure taken along line Y2-Y2' shown in FIG. 1 according to one embodiment of the present disclosure.

[0033] FIG. 11C is a cross-sectional view of a semiconductor structure taken along line XX' according to one embodiment of the present disclosure.

[0034] [Figure 12-1] FIG. 12A is a cross-sectional view of a semiconductor structure taken along Y1-Y1' shown in FIG. 1 illustrating a stage of completing a front-end-of-line (FEOL) processing stage, according to one embodiment of the present disclosure.

[0035] [Figure 12-2] FIG. 12B is a cross-sectional view of the semiconductor structure taken along line Y2-Y2' shown in FIG. 1 according to one embodiment of the present disclosure.

[0036] FIG. 12C is a cross-sectional view of a semiconductor structure taken along line XX' according to one embodiment of the present disclosure.

[0037] [Figure 13-1] 13A is a cross-sectional view of a semiconductor structure taken along Y1-Y1′ shown in FIG. 1 , illustrating steps of performing a replacement metal gate process, performing middle-of-line contact patterning and metallization, and forming a back-end interconnect level and carrier wafer, according to one embodiment of the present disclosure.

[0038] [Figure 13-2] FIG. 13B is a cross-sectional view of the semiconductor structure taken along line Y2-Y2' shown in FIG. 1 according to one embodiment of the present disclosure.

[0039] FIG. 13C is a cross-sectional view of a semiconductor structure taken along line XX' according to one embodiment of the present disclosure.

[0040] [Figure 14-1] FIG. 14A is a cross-sectional view of the semiconductor structure taken along Y1-Y1' shown in FIG. 1, illustrating the step of removing the semiconductor substrate, according to one embodiment of the present disclosure.

[0041] [Figure 14-2] FIG. 14B is a cross-sectional view of the semiconductor structure taken along line Y2-Y2' shown in FIG. 1 according to one embodiment of the present disclosure.

[0042] FIG. 14C is a cross-sectional view of a semiconductor structure taken along line XX' according to one embodiment of the present disclosure.

[0043] [Figure 15-1] 15A is a cross-sectional view of the semiconductor structure taken along Y1-Y1′ shown in FIG. 1, illustrating removing the first sacrificial layer and etching a portion of the first semiconductor layer to expose the placeholder layer, according to one embodiment of the present disclosure.

[0044] [Figure 15-2] FIG. 15B is a cross-sectional view of the semiconductor structure taken along line Y2-Y2' shown in FIG. 1 according to one embodiment of the present disclosure.

[0045] FIG. 15C is a cross-sectional view of a semiconductor structure taken along line XX' according to one embodiment of the present disclosure.

[0046] [Figure 16-1] FIG. 16A is a cross-sectional view of the semiconductor structure taken along Y1-Y1' shown in FIG. 1, illustrating a step of removing the remaining Si-containing areas, according to one embodiment of the present disclosure.

[0047] [Figure 16-2] FIG. 16B is a cross-sectional view of the semiconductor structure taken along line Y2-Y2' shown in FIG. 1 according to one embodiment of the present disclosure.

[0048] FIG. 16C is a cross-sectional view of a semiconductor structure taken along line XX' according to one embodiment of the present disclosure.

[0049] [Figure 17-1]FIG. 17A is a cross-sectional view of the semiconductor structure taken along Y1-Y1' shown in FIG. 1 illustrating a step of forming a first backside interlayer dielectric according to one embodiment of the present disclosure.

[0050] [Figure 17-2] FIG. 17B is a cross-sectional view of the semiconductor structure taken along line Y2-Y2' shown in FIG. 1 according to one embodiment of the present disclosure.

[0051] FIG. 17C is a cross-sectional view of a semiconductor structure taken along line XX' according to one embodiment of the present disclosure.

[0052] [Figure 18-1] FIG. 18A is a cross-sectional view of the semiconductor structure taken along Y1-Y1' shown in FIG. 1 illustrating the selective removal of the placeholder layer according to one embodiment of the present disclosure.

[0053] [Figure 18-2] FIG. 18B is a cross-sectional view of the semiconductor structure taken along line Y2-Y2' shown in FIG. 1 according to one embodiment of the present disclosure.

[0054] FIG. 18C is a cross-sectional view of a semiconductor structure taken along line XX' according to one embodiment of the present disclosure.

[0055] [Figure 19-1] FIG. 19A is a cross-sectional view of the semiconductor structure taken along Y1-Y1' shown in FIG. 1, illustrating the step of depositing backside metal, according to one embodiment of the present disclosure.

[0056] [Figure 19-2] FIG. 19B is a cross-sectional view of the semiconductor structure taken along line Y2-Y2' shown in FIG. 1 according to one embodiment of the present disclosure.

[0057] FIG. 19C is a cross-sectional view of a semiconductor structure taken along line XX' according to one embodiment of the present disclosure.

[0058] [Figure 20-1] FIG. 20A is a cross-sectional view of the semiconductor structure taken along Y1-Y1' shown in FIG. 1, illustrating the patterning of the backside power rail, according to one embodiment of the present disclosure.

[0059] [Figure 20-2] FIG. 20B is a cross-sectional view of the semiconductor structure taken along line Y2-Y2' shown in FIG. 1 according to one embodiment of the present disclosure.

[0060] FIG. 20C is a cross-sectional view of a semiconductor structure taken along line XX' according to one embodiment of the present disclosure.

[0061] [Figure 21-1] FIG. 21A is a cross-sectional view of the semiconductor structure taken along Y1-Y1' shown in FIG. 1 illustrating a stage of forming a backside power distribution network according to one embodiment of the present disclosure.

[0062] [Figure 21-2] FIG. 21B is a cross-sectional view of the semiconductor structure taken along line Y2-Y2' shown in FIG. 1 according to one embodiment of the present disclosure.

[0063] FIG. 21C is a cross-sectional view of a semiconductor structure taken along line XX' according to one embodiment of the present disclosure.

[0064] The drawings are not necessarily to scale. The drawings are merely schematic representations and are not intended to portray specific parameters of the invention. The drawings are intended to depict only typical embodiments of the invention. In the drawings, like numbering represents like elements. DETAILED DESCRIPTION OF THE INVENTION

[0065] Detailed embodiments of the claimed structures and methods are disclosed herein; however, it should be understood that the disclosed embodiments are merely exemplary of the claimed structures and methods, which may be embodied in various forms. However, the present invention may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0066] For purposes of the remainder of this specification, terms such as "upper," "lower," "right," "left," "vertical," "horizontal," "top," "bottom," and variations thereof, refer to the disclosed structures and methods as oriented in the drawings. Terms such as "above," "over," "atop," "on top of," "positioned on," or "positioned on top of" mean that a first element, such as a first structure, is on a second element, such as a second structure, and that an intervening element, such as an interface structure, may be present between the first and second elements. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediate conductive, insulating, or semiconducting layers at the interface of the two elements.

[0067] In order to avoid obscuring the presentation of embodiments of the present invention, in the following detailed description, some process steps or operations that are known in the art may be combined together for purposes of presentation and illustration, and in some cases may not be described in detail. In other cases, some process steps or operations that are known in the art may not be described at all. It should be understood that the following description will instead focus on distinctive features or elements of various embodiments of the present invention.

[0068] Although the disclosed embodiments include detailed descriptions of exemplary nanosheet FET architectures having silicon and silicon germanium nanosheets, it should be understood that implementation of the teachings referred to herein is not limited to the particular FET architecture described herein. Rather, embodiments of the present invention can be implemented in conjunction with any other type of FET device now known or later developed.

[0069]

[0003] Embodiments of the present disclosure provide a semiconductor structure having an improved backside metal contact formed thereon for connection to a power rail located on the backside of a wafer, and a method for fabricating the same. The backside metal contact and backside power rail are formed by a backside process performed after completing back-end-of-life (BEOL) processes and flipping the wafer. Specifically, a sigma etch process is performed to obtain a backside contact having a first taper angle, which is different from a second taper angle of the backside power rail. The sigma etch process and the use of a placeholder material allow the conductive metals for forming the backside contact and backside power rail to be deposited simultaneously in fewer processing steps, thereby simplifying the manufacturing process and increasing the contact area between the backside metal contact and backside power rail for improved device performance and reliability.

[0070] One embodiment by which a semiconductor structure having an improved backside metal contact can be formed is described in detail below with reference to the accompanying drawings of Figures 1-21C.

[0071] Referring now to FIG. 1 , a top view of a semiconductor structure 100 at an intermediate stage during a semiconductor fabrication process is shown, in accordance with one embodiment of the present disclosure. In particular, FIG. 1 shows different cross-sectional views of the semiconductor structure 100 that will be used to explain embodiments of the present disclosure. The cross-sectional views are taken along lines X-X′, Y1-Y1′, and Y2-Y2′. As shown in the figure, line X-X′ represents a cut along the nanosheet fin structure or nanosheet fin region 20 of the semiconductor structure 100, line Y1-Y1′ represents a cut across the source / drain regions in the NFET region 12 and PFET region 16 of the semiconductor structure 100, and line Y2-Y2′ represents a cut along the gate structure or gate region 24 of the semiconductor structure 100.

[0072] In this embodiment, a cross-sectional view taken along line Y1-Y1′ may further include a view of the NFET region 12, and / or the PFET region 16, and the area (NP boundary) 14 between the NFET and PFET regions 12, 16. Additionally, a cross-sectional view taken along line Y1-Y1′ may include a view of the shared buried power rail (BPR) region 22.

[0073] 2, there is shown a cross-sectional view of the semiconductor structure 100 after forming the nanosheet stack 10, according to one embodiment of the present disclosure. In this embodiment, FIG. 2 is a cross-sectional view of the semiconductor structure 100 taken along Y1-Y1′ shown in FIG.

[0074] In the illustrated example, the semiconductor structure 100 includes a substrate 102, a first sacrificial layer 104 overlying the substrate 102, and a first semiconductor layer 106 disposed over the first sacrificial layer 104. According to one embodiment, the first sacrificial layer 104 and the first semiconductor layer 106 are vertically stacked one on top of the other in a direction perpendicular to the substrate 102, as shown.

[0075] The substrate 102 may be, for example, a bulk substrate, which may be made from any of several known semiconductor materials, such as, for example, silicon, germanium, silicon germanium alloys, and compound (e.g., III-V and II-VI) semiconductor materials. Non-limiting examples of compound semiconductor materials include gallium arsenide, indium arsenide, and indium phosphide, or indium gallium phosphide. Typically, but not limited to, the substrate 102 may be about several hundred microns thick. In other embodiments, the substrate 102 may be a layered semiconductor, such as silicon-on-insulator or SiGe-on-insulator, where a buried insulator layer separates a base substrate from an upper semiconductor layer.

[0076] With continued reference to FIG. 2 , according to one embodiment, a first sacrificial layer 104 may be formed on the substrate 102 using an epitaxial growth process. For example, in the illustrated embodiment, the first sacrificial layer 104 is formed by epitaxially growing a layer of SiGe having a germanium concentration varying from about 15 atomic percent to about 35 atomic percent. In a preferred embodiment, the first sacrificial layer 104 is made of epitaxially grown SiGe having a germanium concentration of about 30 atomic percent. In one or more embodiments, the first sacrificial layer 104 may act as an etch stop layer during subsequent substrate removal. Similarly, the first semiconductor layer 106 is formed by epitaxially growing a Si layer to a thickness varying from about 30 nm to about 150 nm, although other thicknesses are within the contemplated scope of the present invention. In some embodiments, the first sacrificial layer 104 may comprise SiO 2 . In such an embodiment, the combined structure formed by the substrate 102, the first sacrificial layer 104, and the first semiconductor layer 106 may be an SOI wafer, and the first sacrificial layer 104 is a buried oxide (BOX) having a thickness ranging from about 20 nm to about 100 nm and ranges therebetween.

[0077] Generally, the first sacrificial layer 104 and the first semiconductor layer 106 can be formed by epitaxial growth using the substrate 102 as a seed layer. Terms such as "epitaxial growth and / or deposition" and "epitaxially formed and / or grown" refer to the growth of a semiconductor material on a deposition surface of the semiconductor material, where the growing semiconductor material has the same or substantially similar crystalline properties as the semiconductor material on the deposition surface. In an epitaxial deposition process, chemical reactants provided by source gases are controlled, and system parameters are set so that the depositing atoms reach the deposition surface of the semiconductor substrate with sufficient energy to move around on the surface and orient themselves to the crystalline structure of the atoms on the deposition surface. Thus, the epitaxial semiconductor material has the same or substantially similar crystalline properties as the deposition surface on which it is formed. For example, epitaxial semiconductor material deposited on a {100} crystalline surface will adopt a {100} orientation. In some embodiments, the epitaxial growth and / or deposition process is selective to form on semiconductor surfaces and does not deposit material on dielectric surfaces, such as silicon dioxide or silicon nitride surfaces.

[0078] Non-limiting examples of various epitaxial growth processes include rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), metalorganic chemical vapor deposition (MOCVD), low-pressure chemical vapor deposition (LPCVD), limited reaction processing CVD (LRPCVD), and molecular beam epitaxy (MBE). Temperatures for epitaxial deposition processes can range from 500°C to 900°C. Higher temperatures typically result in faster deposition, but faster deposition can lead to crystalline defects and film cracking.

[0079] A number of different precursors may be used for the epitaxial growth of the first sacrificial layer 104 and the first semiconductor layer 106. In some embodiments, the gas source for the deposition of the epitaxial semiconductor material includes a silicon-containing gas source, a germanium-containing gas source, or a combination thereof. For example, an epitaxial silicon layer may be deposited from a silicon gas source including, but not limited to, silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, and combinations thereof. An epitaxial germanium layer may be deposited from a germanium gas source including, but not limited to, germane, digermane, halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane, and combinations thereof. Alternatively, a combination of such gas sources may be used to form an epitaxial silicon-germanium alloy layer. Carrier gases such as hydrogen, helium, and argon may be used.

[0080] In the illustrated embodiment, an alternating arrangement of layers of sacrificial semiconductor material and layers of semiconducting channel material stacked vertically one on top of the other in a direction perpendicular to the substrate 102 forms a nanosheet stack 10, as shown in the figure. Specifically, the alternating arrangement includes a nanosheet stack sacrificial layer 108 on a first semiconducting layer 106, a second sacrificial semiconductor layer 110 on the nanosheet stack sacrificial layer 108, and a semiconducting channel layer 112 on the second sacrificial semiconductor layer 110. In the illustrated example, the alternating second sacrificial semiconductor layer 110 and semiconducting channel layer 112 are formed in the (nanosheet) stack 10 on the nanosheet stack sacrificial layer 108. As used herein, the term sacrificial refers to a layer or other structure (or portion thereof) that is removed prior to completion of the final device.

[0081] For example, in the illustrated example, a portion of the second sacrificial semiconductor layer 110 is removed from the stack in the channel region of the device to allow the semiconducting channel layer 112 to be released from the nanosheet stack 10. In this example, the second sacrificial semiconductor layer 110 and the semiconducting channel layer 112 are made of silicon germanium (SiGe) and silicon (Si), respectively, although it should be noted that any combination of sacrificial and channel materials may be utilized in accordance with the present technique. For example, a selective etching technique that allows the use of Si as the sacrificial material between the SiGe channel layers may instead be utilized.

[0082] With continued reference to FIG. 2 , the first (sacrificial) layer in the stack, i.e., the nanosheet stack sacrificial layer 108, is formed on the first semiconductor layer 106 using an epitaxial growth process. For example, in the described embodiment, the nanosheet stack sacrificial layer 108 is formed by epitaxially growing a layer of SiGe having a higher germanium concentration that varies between about 45 atomic percent and about 70 atomic percent. In a preferred embodiment, the nanosheet stack sacrificial layer 108 comprises a layer of SiGe having a germanium concentration of about 55 atomic percent. The higher concentration of germanium atoms allows the nanosheet stack sacrificial layer 108 to be selectively removed relative to the remaining alternating layers of the nanosheet stack 10, as described in more detail below. By way of example only, the nanosheet stack sacrificial layer 108 may be formed to have a thickness that varies between about 5 nm and about 20 nm, although thicknesses greater than 20 nm and less than 5 nm may also be used.

[0083] Generally, the layers in the nanosheet stack 10 (e.g., SiGe and Si layers) can be formed by epitaxial growth using the first semiconductor layer 106 as a seed layer. For example, the second sacrificial semiconductor layer 110 is formed by epitaxially growing a layer of SiGe. In this embodiment, the germanium concentration of the second sacrificial semiconductor layer 110 can vary from about 15 atomic percent to about 35 atomic percent. In one preferred embodiment, each of the second sacrificial semiconductor layers 110 includes a layer of SiGe having a germanium concentration of about 30 atomic percent.

[0084] Continuing with the construction of the nanosheet stack 10, the semiconductor channel layer 112 is formed by epitaxially growing a Si layer. As shown, the second sacrificial semiconductor layer 110 and the semiconductor channel layer 112 have substantially similar or identical thicknesses. The nanosheet stack 10 is grown by alternately forming (SiGe) sacrificial semiconductor layers 110 and (Si) semiconductor channel layers 112 on the nanosheet stack sacrificial layer 108. Thus, each of the second sacrificial semiconductor layers 110 and the semiconductor channel layers 112 in the nanosheet stack 10 can be formed to different thicknesses, for example, from about 6 nm to about 12 nm, using an epitaxial growth process similar to that described above, although other thicknesses are within the contemplated scope of the present invention.

[0085] Thus, each of the layers in the nanosheet stack 10 has nanoscale dimensions and can thus also be referred to as a nanosheet. Furthermore, as emphasized above, the (Si) semiconducting channel layer 112 in the nanosheet stack 10 is used to form the channel layer of the device. As a result, the dimensions of the semiconducting channel layer 112 dictate the dimensions of the channel region of the semiconductor structure 100.

[0086] As emphasized above, the goal is to create a stack of alternating layers of SiGe and Si (sacrificial and channel) on the wafer. The number of layers in the stack can be adapted depending on the particular application. Therefore, the configurations shown and described herein are merely examples intended to illustrate the present technology. For example, the nanosheet stack 10 can include more or fewer layers than shown in the figures.

[0087] The nanosheet stack 10 can be used to fabricate gate-all-around devices comprising vertically stacked nanosheets of semiconducting channel material for positive channel field effect transistor (hereinafter "PFET") or negative channel field effect transistor (hereinafter "NFET") devices.

[0088] In the illustrated embodiment, the semiconductor structure 100 further includes a hard mask layer 202 formed over the nanosheet stack 10 by depositing a hard mask material (e.g., silicon nitride) using, for example, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), or any suitable technique for dielectric deposition. By way of example only, the hard mask layer 202 may be formed to have a thickness varying from about 20 nm to about 200 nm, although thicknesses greater than 200 nm and less than 20 nm may also be used.

[0089] 3, there is shown a cross-sectional view of the semiconductor structure 100 after patterning the nanosheet stack 10 to form a plurality of nanosheet fins (hereinafter "nanosheet fins"), according to one embodiment of the present disclosure. In this embodiment, FIG. 3 is a cross-sectional view of the semiconductor structure 100 taken along Y1-Y1' as shown in FIG.

[0090] After depositing the hard mask layer 202 shown in FIG. 2 , photolithographic patterning is then performed on the deposited hard mask layer 202 to form a plurality of individual fin hard masks. According to an exemplary embodiment, reactive ion etching (RIE) can be used to etch the nanosheet stack 10 to form the nanosheet fins 302. The etching process can be continued until upper portions of the first semiconductor layer 106 located between adjacent nanosheet fins 302 are removed to form a plurality of trenches (not shown). The plurality of trenches (not shown) formed during the photolithographic patterning process are then filled with an insulating material to form shallow trench isolation (STI) regions 310, as shown.

[0091] The process for forming the STI regions 310 is standard and well known in the art and typically involves depositing an insulating material to substantially fill multiple trenches (not shown) created after removing portions of the first semiconductor layer 106 located between adjacent nano-sheet fins 302. According to one embodiment, the STI regions 310 electrically isolate the nano-sheet fins 302. The STI regions 310 may be formed, for example, by CVD of a dielectric material. Non-limiting examples of dielectric materials for forming the STI regions 310 include silicon oxide, silicon nitride, hydrogenated silicon carbon oxide, silicon-based low-k dielectrics, flowable oxides, porous dielectrics, or organic dielectrics, including porous organic dielectrics. After the formation of the STI regions 310, the hard mask layer 202 ( FIG. 2 ) can be removed from the semiconductor structure 100 using any suitable etching technique.

[0092] 4A-4C, cross-sectional views of the semiconductor structure 100 are shown after depositing a dummy gate 410 and a sacrificial hard mask 420, according to one embodiment of the present disclosure. In this embodiment, FIG. 4A is a cross-sectional view of the semiconductor structure 100 taken along line Y1-Y1′ shown in FIG. 1; FIG. 4B is a cross-sectional view of the semiconductor structure 100 taken along line Y2-Y2′ shown in FIG. 1; and FIG. 4C is a cross-sectional view of the semiconductor structure 100 taken along line X-X′ shown in FIG. 1.

[0093] The dummy gate 410 and the sacrificial hard mask 420 form a sacrificial gate structure for the semiconductor structure 100. The processes for forming the dummy gate 410 and the sacrificial hard mask 420 are typical and well known in the art. In one or more embodiments, the dummy gate 410 is formed from amorphous silicon (a-Si) and the sacrificial hard mask 420 is formed from silicon nitride (SiN), silicon oxide, an oxide / nitride stack, or similar materials and configurations.

[0094] After depositing the dummy gate 410 and sacrificial hard mask 420 on the semiconductor structure 100, the dummy gate 410 and sacrificial hard mask 420 are patterned as shown. As known to those skilled in the art, the process of patterning the dummy gate 410 typically involves exposing a pattern on a photoresist layer (not shown) and transferring the pattern to the sacrificial hard mask 420 and dummy gate 410 using known lithography and RIE processes, as shown in FIG. 4C . The dummy gate 410 is formed and patterned on top of the semiconductor channel layer 112 and along the sidewalls of the nanosheet fin 302. As shown in FIG. 4C , patterning the dummy gate 410 exposes portions of the top semiconductor channel layer 112 located between the sacrificial gate structures. As mentioned above, the cross-sectional view of FIG. 4A is taken along line Y1-Y1′ shown in FIG. 1, and therefore FIG. 4A does not show the sacrificial gate structure formed by dummy gate 410 and sacrificial hard mask 420.

[0095] 5A-5C, cross-sectional views of the semiconductor structure 100 are shown after removing the nanosheet stack sacrificial layer 108 (FIGS. 4A-4C), according to one embodiment of the present disclosure. In this embodiment, FIG. 5A is a cross-sectional view of the semiconductor structure 100 taken along line Y1-Y1′ shown in FIG. 1; FIG. 5B is a cross-sectional view of the semiconductor structure 100 taken along line Y2-Y2′ shown in FIG. 1; and FIG. 5C is a cross-sectional view of the semiconductor structure 100 taken along line X-X′ shown in FIG. 1.

[0096] As shown in the illustrated embodiment, removal of the nanosheet stack sacrificial layer 108 ( FIGS. 4A-4C ) creates a first opening 502 in the area of ​​the semiconductor structure 100 where the nanosheet stack sacrificial layer 108 ( FIGS. 4A-4C ) was removed. According to one embodiment, the nanosheet stack sacrificial layer 108 is removed selectively relative to the first semiconductor layer 106, the second sacrificial semiconductor layer 110, the semiconductor channel layer 112, the dummy gate 410, and the sacrificial hard mask 420. For example, a highly selective dry etching process can be used to selectively remove the nanosheet stack sacrificial layer 108 ( FIGS. 4A-4C ).

[0097] 6A-6C, cross-sectional views of the semiconductor structure 100 after forming sidewall spacers 610 are shown, according to one embodiment of the present disclosure. In this embodiment, FIG. 6A is a cross-sectional view of the semiconductor structure 100 taken along line Y1-Y1′ shown in FIG. 1; FIG. 6B is a cross-sectional view of the semiconductor structure 100 taken along line Y2-Y2′ shown in FIG. 1; and FIG. 6C is a cross-sectional view of the semiconductor structure 100 taken along line X-X′ shown in FIG. 1.

[0098] In this embodiment, a spacer material is deposited on the semiconductor structure 100. As shown in FIG. 6C, the spacer material is deposited along the sidewalls of the dummy gate 410 and the sacrificial hard mask 420 to form sidewall spacers 610. The spacer material forming the sidewall spacers 610 substantially fills the first openings 502 shown in FIGS. 5A-5C. The sidewall spacers 610 can be formed using a spacer pull-down formation process. The sidewall spacers 610 can also be formed using a sidewall image transfer (SIT) spacer formation process, which includes spacer material deposition followed by directional RIE of the deposited spacer material. In one or more embodiments, the spacer material deposited between the lower surface of the nanosheet fin 302 and the substrate 102 may be referred to as a lower dielectric isolation layer 620. In some embodiments, the lower dielectric isolation layer 620 and the sidewall spacers 610 may be composed of different materials.

[0099] Non-limiting examples of various spacer materials for forming sidewall spacers 610 and lower dielectric isolation layer 620 may include conventional low-k materials such as SiO, SiOC, SiOCN, or SiBCN. Typically, the thickness of sidewall spacers 610 may vary from about 5 nm to about 20 nm and ranges therebetween.

[0100] 7A-7C, cross-sectional views of the semiconductor structure 100 are shown after recessing the nanosheet fins 302 and forming inner spacers 720, according to one embodiment of the present disclosure. In this embodiment, FIG. 7A is a cross-sectional view of the semiconductor structure 100 taken along line Y1-Y1′ shown in FIG. 1; FIG. 7B is a cross-sectional view of the semiconductor structure 100 taken along line Y2-Y2′ shown in FIG. 1; and FIG. 7C is a cross-sectional view of the semiconductor structure 100 taken along line X-X′ shown in FIG. 1.

[0101] As known to those skilled in the art, the sidewall spacers 610 can be used as a mask for the recessed portions of the nanosheet fin 302 that are not covered by the sidewall spacers 610 and the dummy gate 410, as shown in FIG. 7C. For example, an RIE process may be used to recess the portions of the nanosheet fin 302 that are not under the sidewall spacers 610 and the dummy gate 410. According to one embodiment, the nanosheet fin 302 may be recessed until it reaches the upper portion of the lower dielectric isolation layer 620. As shown in FIGS. 7A and 7C, recessing the nanosheet fin 302 forms a second opening (or source / drain recess) 730 in the semiconductor structure 100.

[0102] Continuing with reference to FIGS. 7A-7C, each outer portion of the second sacrificial semiconductor layer 110 is selectively recessed using a selective etching process, such as, for example, a hydrogen chloride (HCl) gas etch. Preferably, the etching process selected for recessing the second sacrificial semiconductor layer 110 is capable of etching silicon germanium without attacking silicon. The inner spacers 720 may be formed within the recessed cavities (not shown) formed after etching the second sacrificial semiconductor layer 110. The inner spacers 720 may be formed, for example, by conformal deposition of an inner spacer dielectric material that pinches off the recessed cavities (not shown) formed after recessing the second sacrificial semiconductor layer 110. The inner spacers 720 may be formed using any suitable dielectric material, such as silicon dioxide, silicon nitride, SiOC, SiOCN, or SiBCN, and may include a single layer or multiple layers of dielectric material. An isotropic etch may then be performed to remove excess inner spacer material from other regions of the semiconductor structure 100.

[0103] As shown in FIG. 7C, the outer sidewalls of the inner spacers 720 are vertically aligned with the semiconductor channel layer 112 and thus with the upper portions of the sidewall spacers 610 located on the opposing sidewalls of the dummy gate 410.

[0104] 8A-8C, cross-sectional views of the semiconductor structure 100 are shown after forming a nanosheet protection layer 802 and performing back contact patterning, according to one embodiment of the present disclosure. In this embodiment, FIG. 8A is a cross-sectional view of the semiconductor structure 100 taken along line Y1-Y1′ shown in FIG. 1; FIG. 8B is a cross-sectional view of the semiconductor structure 100 taken along line Y2-Y2′ shown in FIG. 1; and FIG. 8C is a cross-sectional view of the semiconductor structure 100 taken along line X-X′ shown in FIG. 1.

[0105] According to one embodiment, the nanosheet protection layer 802 is formed on opposing sides of the sidewall spacer 610 within the second opening 730 (FIGS. 6A-6C), as shown in FIGS. 8A and 8C. In an exemplary embodiment, the nanosheet protection layer 802 may be composed of SiN, TiOx, AlOx, SiO2, SiOCN, SiC, and equivalent materials. To form the nanosheet protection layer 802 as configured in FIGS. 8A and 8C, an ALD deposition process followed by an anisotropic etching process can be used. In particular, the nanosheet protection layer 802 is formed in such a way that only the portions of the nanosheet protection layer 802 perpendicular to the substrate 102 remain on the semiconductor structure 100. The thickness of the nanosheet protection layer 802 may vary from about 1 nm to about 3 nm and ranges therebetween. As the name suggests, the nanosheet protection layer 802 may protect the integrity of the sidewall spacer 610 and the nanosheet fin 302 during subsequent etching processes.

[0106] After forming the nanosheet protection layer 802, an organic planarization layer (OPL), or simply planarization layer 804, may be deposited on the semiconductor structure 100. The planarization layer 804 may be made of any organic planarization material capable of effectively preventing damage to the underlying layer during a subsequent etching process. The planarization layer 804 may include, but is not limited to, an organic polymer containing C, H, and N. In one embodiment, the organic planarization material may be free of silicon (Si). In another embodiment, the organic planarization material may be free of Si and fluorine (F). As defined herein, a material is free of an atom if the level of that atom is at or below a trace level detectable by analytical methods available in the art. Non-limiting examples of organic planarization materials for forming the planarization layer 804 may include JSR HM8006, JSR HM8014, AZ UM10M2, Shin Etsu ODL102, or other similar commercially available materials. The planarization layer 804 may be deposited by, for example, spin coating.

[0107] 8A-8C , a lithography process followed by an etching process is performed on the semiconductor structure 100 to etch the planarization layer 804 and remove a portion of the first semiconductor layer 106 to form a third opening 810, as shown in Figures 8A and 8C. In some embodiments, etching the planarization layer 804 can be performed by OPL RIE including trace point detection, for example. Removal of the portion of the first semiconductor layer 106 can be performed by the same or a different etching process selective to the nanosheet protection layer 802, the STI region 310, and the bottom dielectric isolation layer 620.

[0108] In one or more embodiments, the location of the third opening 810 can be selected based on the desired location of the subsequently formed back metal contact.

[0109] 9A-9C, cross-sectional views of the semiconductor structure 100 after sigma etching the first semiconductor layer 106 are shown, according to one embodiment of the present disclosure. In this embodiment, FIG. 9A is a cross-sectional view of the semiconductor structure 100 taken along line Y1-Y1′ shown in FIG. 1; FIG. 9B is a cross-sectional view of the semiconductor structure 100 taken along line Y2-Y2′ shown in FIG. 1; and FIG. 9C is a cross-sectional view of the semiconductor structure 100 taken along line X-X′ shown in FIG. 1.

[0110] In the illustrated embodiment, a sigma etch process is performed on the first semiconductor layer 106 to further increase the size of the third opening 810 and expose an upper portion of the first sacrificial layer 104. As would be known to one skilled in the art, sigma etching is synonymous with the terms "crystallographic etching" and "anisotropic etching along crystal planes." Sigma etching involves utilizing a chemical etchant. Examples of chemical etchants that can be used for sigma etching include, but are not limited to, potassium hydroxide, tetraethylammonium hydroxide, or an aqueous solution of ethylenediamine and pyrocatechol.

[0111] A sigma etch is an etch that creates a sigma shape that cleaves a portion of the first semiconductor layer 106. As shown in Figure 9C, a sigma shape 902 is formed in the first semiconductor layer 106 after performing the sigma etch process.

[0112] 10A-10C, cross-sectional views of the semiconductor structure 100 are shown after forming a placeholder layer 1020 and removing the planarization layer 804 (FIGS. 9A-9C), according to one embodiment of the present disclosure. In this embodiment, FIG. 10A is a cross-sectional view of the semiconductor structure 100 taken along line Y1-Y1′ shown in FIG. 1; FIG. 10B is a cross-sectional view of the semiconductor structure 100 taken along line Y2-Y2′ shown in FIG. 1; and FIG. 10C is a cross-sectional view of the semiconductor structure 100 taken along line X-X′ shown in FIG. 1.

[0113] According to one embodiment, a layer of any suitable material may be deposited within the third opening 810 to form the placeholder layer 1020. In one or more embodiments, the material forming the placeholder layer 1020 may include, for example, SiGe, AlOx, TiOx, and the like. Specifically, the material forming the placeholder layer 1020 substantially fills the sigma-shaped third opening 810 as shown. In some embodiments, the top surface of the placeholder layer 1020 may be coplanar with the top surface of the lower dielectric isolation layer 620. The placeholder layer 1020, as suggested by its name, acts as a placeholder for a subsequently formed backside metal contact.

[0114] After forming the placeholder layer 1020, the planarization layer 804 may be removed from the semiconductor structure 100. Exemplary techniques suitable for removing the planarization layer 804 (FIGS. 9A-9C) from the semiconductor structure 100 may include, but are not limited to, oxygen plasma, nitrogen plasma, hydrogen plasma, or other carbon removal or ashing processes that cause minimal or no damage to the underlying layers. Removal of the planarization layer 804 exposes the lower dielectric isolation layer 620, the STI region 310, and the upper surface of the nanosheet protection layer 802.

[0115] 11A-11C, cross-sectional views of the semiconductor structure 100 are shown after removing the nanosheet protection layer 802 (FIGS. 10A-10C), according to one embodiment of the present disclosure. In this embodiment, FIG. 11A is a cross-sectional view of the semiconductor structure 100 taken along line Y1-Y1′ shown in FIG. 1; FIG. 11B is a cross-sectional view of the semiconductor structure 100 taken along line Y2-Y2′ shown in FIG. 1; and FIG. 11C is a cross-sectional view of the semiconductor structure 100 taken along line X-X′ shown in FIG. 1.

[0116] Exemplary techniques suitable for removing the nanosheet protection layer 802 (FIGS. 10A-10C) from the semiconductor structure 100 may include, but are not limited to, selective wet or dry etching processes that may cause minimal or no damage to the underlying layers. Removal of the nanosheet protection layer 802 (FIGS. 10A-10C) exposes the sidewall spacers 610, the lower dielectric isolation layer 620, the STI regions 310, the inner spacers 720, and the upper surface of the semiconductor channel layer 112, as shown.

[0117] 12A-12C, cross-sectional views of a semiconductor structure 100 after completing front-end (FEOL) processing steps are shown, according to one embodiment of the present disclosure. In this embodiment, FIG. 12A is a cross-sectional view of the semiconductor structure 100 taken along line Y1-Y1' shown in FIG. 1; FIG. 12B is a cross-sectional view of the semiconductor structure 100 taken along line Y2-Y2' shown in FIG. 1; and FIG. 12C is a cross-sectional view of the semiconductor structure 100 taken along line X-X' shown in FIG. 1.

[0118] Known semiconductor manufacturing operations are used to form the semiconductor structure 100 shown in Figures 12A-12C. Accordingly, conventional techniques related to the fabrication of semiconductor devices and integrated circuits (ICs) may or may not be described in detail herein. Furthermore, various tasks and process steps described herein may be incorporated into more comprehensive procedures or processes having additional steps or functions not described in detail herein. In particular, because the various steps in the fabrication of semiconductor devices and semiconductor-based ICs are well known, for the sake of brevity, many conventional steps are only briefly mentioned herein or omitted entirely without providing well-known process details.

[0119] Generally, at this stage in the fabrication process, source / drain regions 1220 may be formed in semiconductor structure 100. As known to those skilled in the art, source / drain regions are formed in NFET and PFET regions 12, 16 (shown in FIG. 1 ) of semiconductor structure 100 using methods well known in the art. For example, source / drain regions 1220 may be formed using an epitaxial layer growth process on the exposed ends of semiconductor channel layer 112.

[0120] The source / drain regions 1220 can be formed on opposing sides of the nanosheet fin 302 in direct contact with the edges of the semiconducting channel layer 112 and the edges of the inner spacer 720. The upper portions of the source / drain regions 1220 can include a diamond shape as a result of different growth rates during the epitaxial deposition process specific to each crystal orientation plane of the material forming the source / drain regions 1220. In other embodiments, the source / drain regions 1220 can have shapes other than the diamond shape shown in FIG. 12A .

[0121] After forming the source / drain regions 1220, an interlevel dielectric layer 1230 can be formed to fill the gaps in the semiconductor structure 100. The interlevel dielectric layer 1230 can be formed, for example, by CVD of a dielectric material. Non-limiting examples of dielectric materials for forming the interlevel dielectric layer 1230 may include silicon oxide, silicon nitride, hydrogenated silicon carbon oxide, silicon-based low-k dielectrics, flowable oxides, porous dielectrics, or organic dielectrics, including porous organic dielectrics.

[0122] As known to those skilled in the art, after depositing the interlevel dielectric layer 1230, the semiconductor structure 100 may be subjected to a planarization process (e.g., CMP), which may expose the top surface of the dummy gate 410 in preparation for a replacement metal gate process described in detail below.

[0123] 13A-13C, cross-sectional views of a semiconductor structure 100 are shown after performing a replacement metal gate process, performing middle-of-line (MOL) contact patterning and metallization, and forming a back-end (BEOL) interconnect level 1320 and a carrier wafer 1322, according to one embodiment of the present disclosure. In this embodiment, FIG. 13A is a cross-sectional view of the semiconductor structure 100 taken along line Y1-Y1′ shown in FIG. 1; FIG. 13B is a cross-sectional view of the semiconductor structure 100 taken along line Y2-Y2′ shown in FIG. 1; and FIG. 13C is a cross-sectional view of the semiconductor structure 100 taken along line X-X′ shown in FIG. 1.

[0124] According to one embodiment, the dummy gate 410 is removed from the semiconductor structure 100. As known in the art, in a gate-last manufacturing process, the removed dummy gate 410 is then replaced with a high-k metal gate structure, or replacement gate 1310. According to one embodiment, the second sacrificial semiconductor layer 110 (FIGS. 12A-12B) can now be removed from the semiconductor structure 100 using known etching processes, for example, including RIE, wet etching, or dry gas (HCl). The removal of the sacrificial semiconductor layer 110 (FIGS. 12A-12B) creates cavities (not shown) between the inner spacers 720, which are then filled with a corresponding gate dielectric and work function metal to form the high-k metal gate structure, or replacement gate 1310, as shown in FIGS. 13B-13C.

[0125] The replacement gate 1310 includes a gate dielectric, such as hafnium oxide (HfO), zirconium dioxide (ZrO), hafnium aluminum oxide (HfAlOx), or hafnium lanthanum oxide (HfLaOx), and one or more work function metals, including, but not limited to, titanium nitride (TiN), tantalum nitride (TaN), titanium carbide (TiC), titanium aluminum carbide (TiAlC), and conductive metals, such as aluminum (Al), tungsten (W), or cobalt (Co). As can be seen in FIG. 13B, the replacement gate 1310 surrounds the (stacked) semiconductor channel layer 112. In one or more embodiments, a gate cap (not shown) may be formed on the replacement gate 1310.

[0126] After forming the replacement gate 1310, chemical mechanical polishing (CMP) may be performed to remove excess material and polish the upper surface of the semiconductor structure 100.

[0127] In one or more embodiments, a gate cut process can be performed on the semiconductor structure 100 to isolate gate structures from different CMOS cells. During the process, as shown in FIG. 13B, either before or after the replacement metal gate (RMG), a gate cut region 1315 can be formed and then filled with a dielectric, such as SiO, SiN, SiBCN, SiOCN, SiOC, SiC, and the like.

[0128] 13A-13C , a plurality of conductive structures, including metal contacts 1312, are formed in the semiconductor structure 100 to electrically connect the FEOL devices to subsequently formed metal levels. The process for forming the metal contacts 1312 is standard and well known in the art. Typically, the process involves forming trenches (not shown) in the interlevel dielectric layer 1230 and then filling the trenches with a conductive material or combination of conductive materials to form the metal contacts 1312. In one or more embodiments, the conductive material filling the metal contacts 1312 may include a silicide liner (e.g., titanium (Ti), nickel (Ni), nickel-platinum (NiPt) alloy, etc.), a metal deposition liner (e.g., titanium nitride (TiN)), and a conductive metal (e.g., aluminum (Al), tungsten (W), copper (Co), ruthenium (Ru), or any combination thereof).

[0129] The conductive material may be deposited by a suitable deposition process, such as CVD, PECVD, PVD, plating, thermal or electron beam evaporation, or sputtering. A planarization process, such as CMP, may be performed to remove any conductive material from the upper surface of semiconductor structure 100. Specifically, in the illustrated example, metal contacts 1312 may include source / drain contacts (CA) that extend to the top surface of source / drain regions 1220, as shown in Figures 13A and 13C, and a gate contact (CB) to replacement gate 1310, as shown in Figure 13B.

[0130] According to one embodiment, a BEOL interconnect level 1320 is formed above and electrically connected to the FEOL device level 30 of semiconductor structure 100. Although not shown in the figures, as would be known to one skilled in the art, BEOL interconnect level 1320 typically includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-package connections. As mentioned above, the various stages in the fabrication of semiconductor devices and semiconductor-based ICs are well known, and therefore, for the sake of brevity, many conventional stages are only briefly mentioned herein or omitted entirely without providing details of the well-known processes.

[0131] According to one embodiment, after forming the BEOL interconnect level 1320, the semiconductor structure 100 (i.e., the semiconductor wafer) is bonded to a carrier wafer (or support substrate) 1322. The carrier wafer 1322 may act as a stiffening substrate to provide mechanical strength during processing (e.g., thinning) of the semiconductor wafer. The process of bonding the semiconductor wafer to the carrier wafer 1322 can be accomplished by conventional wafer bonding processes, such as dielectric-to-dielectric bonding or Cu-Cu bonding.

[0132] Thus, the carrier wafer 1322 may include a silicon oxide layer, or a SiCN layer, or any other layer that is amenable to direct bonding techniques applied in conventional packaging technologies. Bonding of the device wafer to the carrier wafer 1322 is performed by such known direct bonding techniques, thus resulting in the assembly shown in Figures 13A-13C. Although not shown, after bonding the device wafer to the carrier wafer 1322, the wafers are flipped.

[0133] 14A-14C, cross-sectional views of the semiconductor structure 100 after removing the substrate 102 (FIGS. 13A-13C) are shown, according to one embodiment of the present disclosure. In this embodiment, FIG. 14A is a cross-sectional view of the semiconductor structure 100 taken along line Y1-Y1′ shown in FIG. 1; FIG. 14B is a cross-sectional view of the semiconductor structure 100 taken along line Y2-Y2′ shown in FIG. 1; and FIG. 14C is a cross-sectional view of the semiconductor structure 100 taken along line X-X′ shown in FIG. 1.

[0134] In the illustrated embodiment, after the wafer is flipped (not shown), the substrate 102 (FIGS. 13A-13C) can be removed using conventional grinding, CMP, and selective etching processes, including wet or dry etching techniques. In one or more embodiments, the grinding process is performed until the substrate 102 is substantially removed from the semiconductor structure 100, leaving only a few microns of Si. An optional CMP process can then be further used to reduce thickness variations, and finally a highly selective Si etching process is used to remove the remaining substrate 102 from the semiconductor structure 100. In the illustrated embodiment, the first sacrificial layer 104 acts as an etch stop during the highly selective Si removal process to prevent excessive Si etching, which could damage the replacement gate 1310 and the source / drain regions 1220.

[0135] 15A-15C, cross-sectional views of the semiconductor structure 100 are shown after removing the first sacrificial layer 104 and etching a portion of the first semiconductor layer 106 to expose the placeholder layer 1020, according to one embodiment of the present disclosure. In this embodiment, FIG. 15A is a cross-sectional view of the semiconductor structure 100 taken along line Y1-Y1′ shown in FIG. 1; FIG. 15B is a cross-sectional view of the semiconductor structure 100 taken along line Y2-Y2′ shown in FIG. 1; and FIG. 15C is a cross-sectional view of the semiconductor structure 100 taken along line X-X′ shown in FIG. 1.

[0136] In the illustrated embodiment, any suitable etching technique may be used to remove the first sacrificial layer 104 (FIGS. 14A-14C). In embodiments in which the first sacrificial layer 104 (FIGS. 14A-14C) is made of SiGe, a high-temperature SC1 or dry HCl etch may be used to remove the first sacrificial layer 104. In embodiments in which the first sacrificial layer 104 (FIGS. 14A-14C) is made of SiO2, a DHF wet clean may be used to remove the first sacrificial layer 104. As shown in FIGS. 15A and 15C, a portion of the placeholder layer 1020 may also be etched during removal of the sacrificial layer 104.

[0137] 16A-16C, cross-sectional views of the semiconductor structure 100 are shown after removing the remaining Si-containing area, i.e., the first semiconductor layer 106 shown in Figures 15A-15C, according to one embodiment of the present disclosure. In this embodiment, Figure 16A is a cross-sectional view of the semiconductor structure 100 taken along line Y1-Y1' shown in Figure 1; Figure 16B is a cross-sectional view of the semiconductor structure 100 taken along line Y2-Y2' shown in Figure 1; and Figure 16C is a cross-sectional view of the semiconductor structure 100 taken along line X-X' shown in Figure 1.

[0138] In this embodiment, a process similar to that described in Figures 14A-14C for removing substrate 102 can be performed to remove first semiconductor layer 106 (Figures 15A-15C) from semiconductor structure 100. Selective removal of first semiconductor layer 106 (Figures 15A-15C) exposes placeholder layer 1020. As can be seen in Figures 16A and 16C, a first or lower surface of placeholder layer 1020 contacts a first or lower surface of source / drain regions 1220.

[0139] 17A-17C, cross-sectional views of the semiconductor structure 100 are shown after forming a first backside interlayer dielectric (BILD) 1702, according to one embodiment of the present disclosure. In this embodiment, FIG. 17A is a cross-sectional view of the semiconductor structure 100 taken along line Y1-Y1′ shown in FIG. 1; FIG. 17B is a cross-sectional view of the semiconductor structure 100 taken along line Y2-Y2′ shown in FIG. 1; and FIG. 17C is a cross-sectional view of the semiconductor structure 100 taken along line X-X′ shown in FIG. 1.

[0140] The first BILD 1702 is formed using standard methods and materials, such as those used to form the interlevel dielectric layer 1230 described above with reference to FIGS. 12A-12C. As shown in FIGS. 17B-17C, the first BILD 1702 is disposed on the lower dielectric isolation layer 620. In exemplary embodiments, the thickness of the first BILD 1702 can vary between about 40 nm and about 300 nm, and ranges therebetween. In one or more embodiments, after forming the first BILD 1702, a planarization process (e.g., CMP) can be performed on the semiconductor structure 100. After the planarization process, the exposed second or top surface of the placeholder layer 1020 opposite the first surface of the placeholder layer is substantially coplanar with the first BILD 1702 and the STI region 310.

[0141] 18A-18C, cross-sectional views of the semiconductor structure 100 are shown after selectively removing the placeholder layer 1020 (FIGS. 17A-17C), according to one embodiment of the present disclosure. In this embodiment, FIG. 18A is a cross-sectional view of the semiconductor structure 100 taken along line Y1-Y1′ shown in FIG. 1; FIG. 18B is a cross-sectional view of the semiconductor structure 100 taken along line Y2-Y2′ shown in FIG. 1; and FIG. 18C is a cross-sectional view of the semiconductor structure 100 taken along line X-X′ shown in FIG. 1.

[0142] Removal of placeholder layer 1020 (FIGS. 17A-17C) creates a fourth opening 1820 in semiconductor structure 100. Fourth opening 1820 (i.e., a backside contact via) exposes one or more of source / drain regions 1220, as shown in FIGS. 18A and 18C. An exemplary technique suitable for removing placeholder layer 1020 (FIGS. 17A-17C) in semiconductor structure 100 may include, but is not limited to, a dry HCl etch, which may cause minimal or no damage to underlying layers.

[0143] As can be seen in Figures 18A and 18C, at least one of the fourth openings 1820 exposes the upper surface of a source / drain region 1220 adjacent to another source / drain region 1220 that is in electrical contact with a metal contact 1312.

[0144] 19A-19C, cross-sectional views of the semiconductor structure 100 after depositing backside metal 1920 are shown, according to one embodiment of the present disclosure. In this embodiment, FIG. 19A is a cross-sectional view of the semiconductor structure 100 taken along line Y1-Y1′ shown in FIG. 1; FIG. 19B is a cross-sectional view of the semiconductor structure 100 taken along line Y2-Y2′ shown in FIG. 1; and FIG. 19C is a cross-sectional view of the semiconductor structure 100 taken along line X-X′ shown in FIG. 1.

[0145] The backside metal 1920 substantially fills the fourth opening 1820 (FIGS. 18A-18C). A layer of backside metal 1920 is further deposited over the filled fourth opening 1820, over the first BILD 1702, and over the STI regions 310, as shown. It should be noted that the backside metal 1920 that substantially fills the fourth opening 1820 (FIGS. 18A-18C) provides a backside metal contact 1930 to the source / drain regions 1220. According to one embodiment, the backside contact 1930 may electrically connect the semiconductor structure 100 to a subsequently formed backside power rail (BPR), as described in more detail below.

[0146] The backside metal 1920 may be formed using a similar conductive material and a similar deposition process as used to form the metal contact 1102. In some embodiments, the conductive metal for forming the backside metal 1920 may be selected depending on the structure of the backside power rail to be subsequently formed. In such cases, the backside metal 1920 may be formed by depositing a silicide liner such as Ti, Ni, NiPt, an adhesion metal liner such as TiN, and a layer of a low-resistivity metal such as Ru, Co, W, or Cu.

[0147] The thickness of the layer of backside material extending over the first BILD 1702 and STI regions 310 may vary from about 30 nm to about 200 nm and ranges therebetween.

[0148] In one or more embodiments, a backside contact 1930 may be formed between adjacent source / drain regions 1220 located in the NFET (i.e., N2N space) region 12 (FIG. 1) or the PFET (i.e., P2P space) region 16 (FIG. 1) of the semiconductor structure 100. In the illustrated embodiment, the backside metal contact 1930 is formed to directly contact a first or bottom surface of at least one source / drain region 1220.

[0149] 20A-20C, cross-sectional views of the semiconductor structure 100 after backside power rail patterning are shown, according to one embodiment of the present disclosure. In this embodiment, FIG. 20A is a cross-sectional view of the semiconductor structure 100 taken along line Y1-Y1' as shown in FIG. 1; FIG. 20B is a cross-sectional view of the semiconductor structure 100 taken along line Y2-Y2' as shown in FIG. 1; and FIG. 20C is a cross-sectional view of the semiconductor structure 100 taken along line X-X' as shown in FIG. 1.

[0150] In the illustrated embodiment, backside power rails (BPRs) 2010, 2012 are formed in the semiconductor structure 100 by patterning the backside metal 1920 (FIGS. 19A-19C) using subtractive metal etching. Specifically, hybrid damascene and subtractive metal patterning can be used to pattern the layer of backside metal 1920 (FIGS. 19A-19C) that extends over the first BILD 1702 and STI regions 310 to form the BPRs 2010, 2012 shown in the figures. Thus, this embodiment may be capable of simultaneously forming backside metal contacts (e.g., backside contact 1930) and backside power rails (e.g., BPRs 2010, 2012).

[0151] More particularly, in one embodiment, the semiconductor structure 100 includes an NFET device. In such an embodiment, the BPR 2012 includes a VSS rail embedded in the NFET region of the semiconductor structure 100 for electrically connecting to the N-type source / drain regions 1220 through backside contacts 1930 (located between adjacent N-type source / drain regions 1220). In other embodiments, the semiconductor structure 100 includes a PFET device, in which the BPR 2010 may include a VDD rail embedded in the PFET region of the semiconductor structure 100 for electrically connecting to the (P-type) source / drain regions 1220 through backside contacts 1930 (located between adjacent P-type source / drain regions 1220).

[0152] It should be noted that the source / drain regions 1220 routed to the backside power rails (i.e., BPRs 2010, 2012) are not connected to the BEOL interconnect level 1320. More specifically, as shown, at least one backside power rail (i.e., BPRs 2010, 2012) is electrically connected to the transistor source / drain regions 1220 through backside contacts 1930, and the lower dielectric isolation layer 620, first BILD 1702, and / or STI regions 310 contact the remaining source / drain regions 1220 and electrically isolate the at least one backside power rail from the source / drain regions 1220 that are not electrically connected to the backside contacts 1930.

[0153] After patterning the BPRs 2010, 2012, gaps within the semiconductor structure may be filled by depositing a dielectric material substantially similar to the first BILD 1702. Thus, for simplicity, another layer of the first BILD 1702 is deposited within the semiconductor structure 100 to fill any remaining gaps and electrically isolate the BPRs 2010, 2012, as shown in Figures 21A-21C below. After depositing another layer of the first BILD 1702, a planarization process may be performed on the semiconductor structure 100.

[0154] 21A-21C, cross-sectional views of the semiconductor structure 100 are shown after forming a backside power delivery network (BSPDN) 2130, according to one embodiment of the present disclosure. In this embodiment, FIG. 21A is a cross-sectional view of the semiconductor structure 100 taken along line Y1-Y1′ shown in FIG. 1; FIG. 21B is a cross-sectional view of the semiconductor structure 100 taken along line Y2-Y2′ shown in FIG. 1; and FIG. 21C is a cross-sectional view of the semiconductor structure 100 taken along line X-X′ shown in FIG. 1.

[0155] In one or more embodiments, the structure of the BSPDN 2130 can be fabricated according to known techniques. Depending on the exact function of the transistor configuration, multiple source / drain regions 1220 may be connected to a backside power supply and ground via backside contacts 1930. As mentioned above, the backside contacts 1930 are metal areas located between P-type source / drain regions (P2P spaces) and N-type source / drain regions (N2N spaces), i.e., source / drain regions of like polarity. According to one embodiment, the backside contacts 1930 contact the lower surface of the BPR 2010 or 2012 (depending on the polarity of the device) and are embedded within intermediate STI regions 310 (located between regions of like polarity).

[0156] It should be noted that the BEOL interconnect level 1320 in the semiconductor structure 100 fabricated by the disclosed technology is separated from the BSPDN 2130, thereby increasing routing resources within the semiconductor structure 100 for signal wiring at the BEOL level.

[0157] According to one embodiment, by performing a sigma etch process, the back contact via, and therefore the back metal contact 1930, exhibits a first (positive) taper profile including a first taper angle, as shown in FIG. 21C , such that a first or top critical dimension (CD1) of the back metal contact 1930 is less than a second or bottom critical dimension (CD2) of the back metal contact 1930. Similarly, the BPRs 2010, 2012 are formed to have a second (negative) taper profile that differs from the first taper profile of the back metal contact 1930. The second taper profile includes a second taper angle, such that a third or top critical dimension (CD3) of the BPRs 2010, 2012 is greater than a fourth or bottom critical dimension (CD4) of each of the BPRs 2010, 2012.

[0158] Thus, the previously described embodiments provide a semiconductor device including a field effect transistor (FET) and a backside contact 1930. The backside contact 1930 is electrically connected to the source / drain regions 1220 of the FET and electrically connected to a backside power rail 2010, 2012. The backside contact 1930 has a first width adjacent to the source / drain regions 1220 and a second width adjacent to the backside power rail 2010, 2012. The second width of the backside contact 1930 is greater than the first width of the backside contact 1930. According to one embodiment, the backside power rail 2010, 2012 has a third width adjacent to the backside contact 1930 and a fourth width at an opposing side of the backside contact 1930. The third width of the backside power rail 2010, 2012 is greater than the fourth width of the backside power rail 2010, 2012.

[0159] Methods such as those described above are used in the manufacture of integrated circuit chips. The resulting integrated circuit chips may be provided by the manufacturer in raw wafer (i.e., as a single wafer with multiple unpackaged chips), bare die form, or packaged form. In the latter case, the chips are mounted in a single-chip package (such as a plastic carrier with leads that are secured to a motherboard or other higher-level carrier) or in a multi-chip package (such as a ceramic carrier with either surface interconnects or embedded interconnects, or both). In either case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product such as a motherboard, or (b) a final product. The final product can be any product containing integrated circuit chips, ranging from toys and other low-cost applications to sophisticated computer products with displays, keyboards or other input devices, and central processors.

[0160] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will be further understood that the terms "comprise" and / or "comprising," as used herein, specify the presence of stated features, integers, steps, operations, elements, or components or combinations thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups or combinations thereof. "Optional" or "optionally" means that the subsequently described event or circumstance may or may not occur, and that the description includes instances in which the event occurs as well as instances in which it does not occur.

[0161] Spatially relative terms such as "inside," "outside," "below," "belower," "lower side," "upper," "upper," "top," "lower," etc. may be used herein to describe the relationship of one element or feature to another element or feature, as shown in the figures, for ease of description. Spatially relative terms may be intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. For example, if a device in the figures is turned over, elements described as "below" or "below" other elements or features may then be oriented "above" the other elements or features. Thus, the example term "below" can encompass both an upward and downward orientation. A device may be oriented differently (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0162] As used herein throughout the specification and claims, approximation may be applied to modify any quantitative expression that may vary appreciably without resulting in a change in the basic function to which it relates. Accordingly, values ​​modified by terms such as "about," "approximately," and "substantially" should not be limited to the exact value specified. In at least some cases, approximation may correspond to the precision of the instrument measuring the value. Here, and throughout the specification and claims, range limitations may be combined and / or interchangeable, and such ranges are specified and include all subranges contained therein unless the context or language indicates otherwise. "About," as applied to a particular value in a range, applies to both values ​​and may indicate + / - 10% of the stated value, unless otherwise dependent on the precision of the instrument measuring the value.

[0163] The description of various embodiments of the present invention has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used herein have been selected to best explain the principles of the embodiments, practical applications, or technical improvements beyond those found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. multiple source / drain regions in a field effect transistor; a back metal contact electrically connected to at least one source / drain region of the plurality of source / drain regions, the back metal contact having a first tapered profile; and a backside power rail electrically connected to the at least one source / drain region through the backside metal contact, the backside power rail having a second taper profile, the second taper profile being different from the first taper profile; 1. A semiconductor structure comprising:

2. a front-end level having the field effect transistor, the front-end level electrically connected to a back-end interconnect level located on a first side of the front-end level; a plurality of shallow trench isolation regions located between adjacent field effect transistors; a backside interlayer dielectric surrounding the backside power rail and located on a second side of the front-end level opposite the first side of the front-end level; and a metal contact in the interlevel dielectric layer, said metal contact electrically contacting a lower portion of at least another source / drain region; The semiconductor structure of claim 1 further comprising:

3. 2. The semiconductor structure of claim 1, wherein the first tapered profile of the back metal contact comprises a first critical dimension of the back metal contact that is less than a second critical dimension of the back metal contact.

4. 4. The semiconductor structure of claim 3, wherein the first critical dimension is a top critical dimension of the back metal contact and the second critical dimension is a bottom critical dimension of the back metal contact.

5. 2. The semiconductor structure of claim 1, wherein the second tapered profile includes a third critical dimension of the backside power rail that is greater than a fourth critical dimension of the backside power rail.

6. 6. The semiconductor structure of claim 5, wherein the third critical dimension is a top critical dimension of the backside power rail and the fourth critical dimension is a bottom critical dimension of the backside power rail.

7. 10. The semiconductor structure of claim 1, wherein said back metal contact and said back power rail are comprised of a conductive material including at least one of Ru, Cu, Co, W, and Al.

8. a power distribution network over and in electrical contact with said backside power rail; The semiconductor structure of claim 1 further comprising:

9. a carrier wafer in contact with a surface of the back-end interconnect level opposite the plurality of source / drain regions and the metal contacts; The semiconductor structure of claim 2 further comprising:

10. 10. The semiconductor structure of claim 1, wherein the field effect transistor comprises at least one of a P-type field effect transistor and an N-type field effect transistor, and the field effect transistor comprises a nanosheet field effect transistor.

11. forming a plurality of source / drain regions in the field effect transistor; forming a back metal contact electrically connected to at least one source / drain region of the plurality of source / drain regions, the back metal contact having a first tapered profile; and forming a backside power rail electrically connected to the at least one source / drain region through the backside metal contact, the backside power rail having a second taper profile, the second taper profile being different from the first taper profile; 1. A method for forming a semiconductor structure, comprising:

12. forming a front-end level having the field effect transistor, the front-end level electrically connected to a back-end interconnect level located on a first side of the front-end level; forming a plurality of shallow trench isolation regions between adjacent field effect transistors; forming a backside interlayer dielectric on a second side of the front-end level surrounding the backside power rail and opposite the first side of the front-end level; and forming a metal contact in the interlevel dielectric layer, the metal contact electrically contacting a lower portion of at least another source / drain region; The method of claim 11 further comprising:

13. 12. The method of claim 11, wherein the first tapered profile of the back metal contact comprises a first critical dimension of the back metal contact that is smaller than a second critical dimension of the back metal contact.

14. 14. The method of claim 13, wherein the first critical dimension is a top critical dimension of the back metal contact and the second critical dimension is a bottom critical dimension of the back metal contact.

15. 12. The method of claim 11, wherein the second tapered profile includes a third critical dimension of the backside power rail that is greater than a fourth critical dimension of the backside power rail.

16. 16. The method of claim 15, wherein the third critical dimension is a top critical dimension of the backside power rail and the fourth critical dimension is a bottom critical dimension of the backside power rail.

17. 12. The method of claim 11, wherein the back metal contact and the back power rail are comprised of a conductive material including at least one of Ru, Cu, Co, W, and Al.

18. forming a power distribution network over and in electrical contact with said backside power rail; The method of claim 11 further comprising:

19. forming a carrier wafer contacting a surface of the back-end interconnect level opposite the plurality of source / drain regions and the metal contacts; The method of claim 12 further comprising:

20. 12. The method of claim 11, wherein the field effect transistor comprises at least one of a P-type field effect transistor and an N-type field effect transistor, and the field effect transistor comprises a nanosheet field effect transistor.

21. 21. A computer program comprising a program code adapted to perform the steps of the method according to any of claims 11 to 20, when the computer program is run on a computer.

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