Display substrate and manufacturing method thereof, display device

Abstract

A display substrate and a manufacturing method thereof, and a display device, the display substrate includes a plurality of first circuit regions 210 and a plurality of second circuit regions 220 arranged alternately along a second direction, the first circuit region 210 includes a plurality of repeat units RU and a plurality of blank units KB arranged alternately along the first direction, the repeat units RU include a plurality of circuit units Q, the circuit units Q include pixel driving circuits and data signal lines DataI connected to the pixel driving circuits, the second circuit region 220 includes at least one gate unit G, the gate unit Q includes at least one gate driving circuit, and the orthogonal projection of the gate driving circuit on the display substrate plane does not overlap with the orthogonal projection of the data signal line DataI on the display substrate plane.

Description

[Technical Field]

[0001] The present disclosure relates to the field of display technology, but is not limited thereto, and more particularly to a display substrate and a manufacturing method thereof, and a display device. [Background technology]

[0002] Semiconductor light-emitting diode (LED) technology has been developing for nearly 30 years, laying a solid foundation for a wide range of applications, from the first solid-state lighting power source to the backlight source for display areas and even LED displays. With the development of chip manufacturing and packaging technology, mini light-emitting diode (Mini LED) displays and micro light-emitting diode (Micro LED) displays have gradually become a hotspot in display panels, and can be applied in fields such as AR / VR, TV, and outdoor displays.

[0003] The current display market is dominated by two technologies: Liquid Crystal Display (LCD) and Organic Light Emitting Diode (OLED). However, due to limitations in substrate size, manufacturing equipment, and processes, it is difficult for both LCD and OLED to realize large-screen displays, especially those over 110 inches. In contrast, Micro LED displays / Mini LED displays can realize large-screen displays using a splice method, breaking through size limitations. LEDs have advantages such as self-luminance, wide viewing angles, fast response, simple structure, small volume, thin and lightweight, energy-saving, high efficiency, long life, and bright light, making them easy to achieve high resolution (Pixels Per Inch, PPI) and considered the most competitive next-generation display technology. Summary of the Invention [Means for solving the problem]

[0004] The following is a summary of the subject matter described in detail in the text, which is not intended to limit the scope of protection of the claims.

[0005] In one aspect, an embodiment of the present disclosure provides a display substrate, comprising: a plurality of first circuit regions and a plurality of second circuit regions alternately arranged along a second direction; the first circuit region comprises a plurality of repeat units and a plurality of blank units alternately arranged along the first direction; the first direction and the second direction intersect; the repeat unit comprises a plurality of circuit units, each circuit unit including a pixel driving circuit and a data signal line and a driving signal line connected to the pixel driving circuit; the second circuit region comprises at least one gate unit, each gate unit including at least one gate driving circuit, the gate driving circuit connected to the driving signal line in an adjacent circuit unit; and orthogonal projections of the gate driving circuits on a plane of the display substrate do not overlap with orthogonal projections of the data signal lines on the plane of the display substrate.

[0006] In an exemplary embodiment, at least one second circuit area has a reference line, which is a straight line that equally divides the second circuit area in the second direction and extends along the first direction, and an orthogonal projection of at least one gate drive circuit on the reference line at least partially overlaps with an orthogonal projection of at least one blank unit on the reference line.

[0007] In an exemplary embodiment, at least one gate driving circuit is further connected to a clock signal line, a high voltage line, and a low voltage line, and in the first direction, the clock signal line is disposed between the high voltage line and the low voltage line, and the orthogonal projection of the clock signal line on the display substrate plane does not overlap with the orthogonal projection of the data signal line on the display substrate plane.

[0008] In an exemplary embodiment, in the first direction, the data signal line is located on the side of the high voltage line away from the clock signal line, or the data signal line is located on the side of the low voltage line away from the clock signal line.

[0009] In an exemplary embodiment, in the first direction, there is a first distance between an edge of the high-voltage line closer to the data signal line and an edge of the data signal line closer to the high-voltage line, and there is a second distance between an edge of the low-voltage line closer to the data signal line and an edge of the data signal line closer to the low-voltage line, the second distance being greater than the first distance.

[0010] In an exemplary embodiment, the first distance is greater than or equal to 25 μm and the second distance is greater than or equal to 25 μm.

[0011] In an exemplary embodiment, the clock signal lines include a first clock signal line and a second clock signal line, the second clock signal line being located on a side of the first clock signal line away from the low voltage line, a third distance being between an edge of the first clock signal line closer to the low voltage line and an edge of the low voltage line closer to the first clock signal line, and a fourth distance being between an edge of the second clock signal line closer to the high voltage line and an edge of the high voltage line closer to the second clock signal line, the third distance being greater than the fourth distance.

[0012] In an exemplary embodiment, at least one drive signal line is connected to one gate drive circuit, the gate drive circuit is provided in a first midline region of the second circuit region, the gate drive circuit is connected to a first midpoint region of the drive signal line via an output line, the first midline region is a region including a first midpoint, the first midline region and the first midpoint region are a region including a first midpoint, the widths of the first midline region and the first midpoint region in the first direction are 1% to 10% of the width of the display substrate, the first midline is a straight line that equally divides the second circuit region in the first direction and extends along the second direction, the first midpoint is a point that equally divides the drive signal line in the first direction, and the width of the display substrate is the dimension of the display substrate in the first direction.

[0013] In an exemplary embodiment, at least one driving signal line is respectively connected to a first gate driving circuit and a second gate driving circuit, the first gate driving circuit is provided in a second midline region of the second circuit region and is connected to a second midpoint region of the driving signal line via an output line, the second gate driving circuit is provided in a third midline region of the second circuit region and is connected to a third midpoint region of the driving signal line via an output line, the second midline region is a region including a second midline, the third midline region is a region including a third midline, the second midpoint region is a region including a second midpoint, and the third midpoint region is a region including a third midpoint, and the widths of the second midline region, the third midline region, the second midpoint region, and the third midpoint region in the first direction X are the second circuit area includes a first midline that equally divides the second circuit area in the first direction and extends along the second direction, the first midline divides the second circuit area into a first area and a second area, the second midline is a straight line that equally divides the first area in the first direction and extends along the second direction, the third midline is a straight line that equally divides the second area in the first direction and extends along the second direction, the drive signal line includes a first midpoint that equally divides the drive signal line in the first direction, the first midpoint divides the drive signal line into a first line segment and a second line segment, the second midpoint is a point that equally divides the first line segment in the first direction, and the third midpoint is a point that equally divides the second line segment in the first direction.

[0014] In an exemplary embodiment, at least one second circuit area has a reference line, which is a straight line that equally divides the second circuit area in the second direction and extends along the first direction, and the pixel driving circuits in the first circuit areas on both sides of the second circuit area in the second direction are mirror-symmetric with respect to the reference line.

[0015] In an exemplary embodiment, the at least one second circuit area further includes at least one first mark, and an orthogonal projection of the at least one first mark on the reference line at least partially overlaps with an orthogonal projection of the at least one blank unit on the reference line.

[0016] In an exemplary embodiment, the at least one second circuit area further includes at least one second mark, and an orthogonal projection of the at least one second mark on the reference line at least partially overlaps with an orthogonal projection of the at least one blank unit on the reference line.

[0017] In an exemplary embodiment, the orthogonal projection of the second mark onto the display substrate plane does not overlap with the orthogonal projection of the data signal lines, drive signal lines and clock signal lines onto the display substrate plane.

[0018] In an exemplary embodiment, in a plane perpendicular to the display substrate, the display substrate includes a first gate metal layer, a second gate metal layer, a first source / drain metal layer, and a second source / drain metal layer sequentially disposed on a base, the driving signal line being disposed on the second gate metal layer, and the data signal line and the clock signal line being disposed on the first source / drain metal layer.

[0019] In an exemplary embodiment, the at least one second circuit region further includes at least one first mark and at least one second mark, the first mark being disposed in the first source-drain metal layer and the second mark being disposed in the second source-drain metal layer.

[0020] In an exemplary embodiment, the display substrate further includes a first planar layer and a first passivation layer, wherein the first planar layer is disposed on a side of the first source / drain metal layer away from the base, the first passivation layer is disposed on a side of the first planar layer away from the base, the second source / drain metal layer is disposed on a side of the first passivation layer away from the base, the first planar layer has a first mark hole exposing the first mark, an orthogonal projection of the first mark hole on the plane of the base includes an orthogonal projection of the first mark on the plane of the base, and the first passivation layer covers the first mark in the first mark hole.

[0021] In an exemplary embodiment, the display substrate further includes a second passivation layer and a second planar layer, the second passivation layer being disposed on a side of the second source / drain metal layer away from the base, the second planar layer being disposed on a side of the second passivation layer away from the base, the second planar layer being provided with a second mark hole and a third mark hole, the second mark hole exposing the second passivation layer covering the second mark, the orthogonal projection of the second mark hole on the plane of the base including the orthogonal projection of the second mark on the plane of the base, the third mark hole exposing the second passivation layer covering the first mark, and the orthogonal projection of the third mark hole on the plane of the base including the orthogonal projection of the first mark on the plane of the base.

[0022] In another aspect, the present disclosure further provides a display device comprising a display substrate as described above.

[0023] In yet another aspect, the present disclosure further provides a method for manufacturing a display substrate, the display substrate including a plurality of first circuit areas and a plurality of second circuit areas alternately arranged along a second direction, the first circuit area including a plurality of repeating units and a plurality of blank units alternately arranged along the first direction, the repeating units including a plurality of circuit units, the second circuit area including at least one gate unit, the first direction and the second direction intersect, the manufacturing method including: forming a pixel driving circuit and data signal lines and driving signal lines connected to the pixel driving circuit in the circuit unit, and forming at least one gate driving circuit and a clock signal line connected to the gate driving circuit in the gate unit, wherein the gate driving circuit is connected to the driving signal lines in an adjacent circuit unit, and the orthogonal projection of the data signal lines on the display substrate plane does not overlap with the orthogonal projection of the clock signal lines on the display substrate plane.

[0024] Other aspects will be understood after reading and understanding the drawings and detailed description. [Brief explanation of the drawings]

[0025] [Figure 1]FIG. 1 is a structural schematic diagram of a display device. [Figure 2] FIG. 2 is a schematic plan view of a light-emitting structure layer on a display substrate. [Figure 3] FIG. 2 is a schematic plan view of a driving structure layer on a display substrate. [Figure 4] FIG. 2 is an equivalent circuit diagram of a pixel driving circuit. [Figure 5] FIG. 2 is a structural schematic diagram of a gate driver; [Figure 6] FIG. 2 is an equivalent circuit diagram of a gate drive circuit. [Figure 7] FIG. 2 is a schematic planar structural view of a display substrate according to an exemplary embodiment of the present disclosure; [Figure 8] FIG. 2 is a schematic diagram of wiring of a gate drive circuit according to an exemplary embodiment of the present disclosure. [Figure 9] FIG. 2 is a schematic diagram illustrating the layout of a gate unit according to an exemplary embodiment of the present disclosure. [Figure 10] FIG. 10 is a schematic diagram illustrating the layout of another gate unit according to an exemplary embodiment of the present disclosure. [Figure 11] FIG. 2 is a schematic planar structural view of a display substrate according to an exemplary embodiment of the present disclosure; [Figure 12] FIG. 2 is a schematic planar structural view of a display substrate according to an exemplary embodiment of the present disclosure; [Figure 13] 3 is a schematic diagram of a display substrate according to the present disclosure after a first conductive layer pattern has been formed. FIG. [Figure 14] 3 is a schematic diagram of a display substrate according to the present disclosure after a first conductive layer pattern has been formed. FIG. [Figure 15] 3 is a schematic diagram of a display substrate according to the present disclosure after a first conductive layer pattern has been formed. FIG. [Figure 16] 3 is a schematic diagram of a display substrate according to the present disclosure after a semiconductor layer pattern is formed on the display substrate. FIG. [Figure 17] 3 is a schematic diagram of a display substrate according to the present disclosure after a semiconductor layer pattern is formed on the display substrate. FIG. [Figure 18] 3 is a schematic diagram of a display substrate according to the present disclosure after a semiconductor layer pattern is formed on the display substrate. FIG. [Figure 19] 3 is a schematic diagram of a display substrate according to the present disclosure after a second conductive layer pattern has been formed. FIG. [Figure 20]3 is a schematic diagram of a display substrate according to the present disclosure after a second conductive layer pattern has been formed. FIG. [Figure 21] 3 is a schematic diagram of a display substrate according to the present disclosure after a second conductive layer pattern has been formed. FIG. [Figure 22] 10 is a schematic diagram of the display substrate of the present disclosure after a third insulating layer pattern has been formed. FIG. [Figure 23] 10 is a schematic diagram of the display substrate of the present disclosure after a third insulating layer pattern has been formed. FIG. [Figure 24] 10 is a schematic diagram of the display substrate of the present disclosure after a third insulating layer pattern has been formed. FIG. [Figure 25] 10 is a schematic diagram of a display substrate according to the present disclosure after a third conductive layer pattern has been formed. FIG. [Figure 26] 10 is a schematic diagram of a display substrate according to the present disclosure after a third conductive layer pattern has been formed. FIG. [Figure 27] 10 is a schematic diagram of a display substrate according to the present disclosure after a third conductive layer pattern has been formed. FIG. [Figure 28] 10 is a schematic diagram of a display substrate according to the present disclosure after a third conductive layer pattern has been formed. FIG. [Figure 29] 3 is a schematic diagram of a display substrate according to the present disclosure after a first flat layer pattern is formed on the display substrate. FIG. [Figure 30] 3 is a schematic diagram of a display substrate according to the present disclosure after a first flat layer pattern is formed on the display substrate. FIG. [Figure 31] 3 is a schematic diagram of a display substrate according to the present disclosure after a first flat layer pattern is formed on the display substrate. FIG. [Figure 32] 10 is a schematic diagram of the display substrate of the present disclosure after a fourth conductive layer pattern has been formed. FIG. [Figure 33] 10 is a schematic diagram of the display substrate of the present disclosure after a fourth conductive layer pattern has been formed. FIG. [Figure 34] 3 is a schematic diagram of a display substrate according to the present disclosure after a second flat layer pattern is formed on the display substrate. FIG. [Figure 35] 3 is a schematic diagram of a display substrate according to the present disclosure after a second flat layer pattern is formed on the display substrate. FIG. [Figure 36] FIG. 10 is a schematic diagram of wiring of another gate drive circuit according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0026] The drawings are intended to provide a further understanding of the technical solution of the present disclosure, to be a part of the specification, and to interpret the technical solution of the present disclosure together with the embodiments of the present disclosure, but are not intended to limit the technical solution of the present disclosure. The shape and size of one or more parts in the drawings do not reflect actual proportions and are intended to schematically explain the contents of the present disclosure.

[0027] To clarify the objectives, technical solutions, and advantages of the present disclosure, the following detailed description of the embodiments of the present disclosure will be given with reference to the accompanying drawings. It should be noted that the embodiments can be implemented in many different forms. As those skilled in the art can easily understand, the manner and content of the present disclosure can be transformed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited to the following embodiments. Where there is no conflict, the embodiments and features of the embodiments of the present disclosure can be combined with each other.

[0028] The proportions in the drawings in this disclosure may be used as a reference for actual processes, but are not limited thereto. For example, the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line may be adjusted according to actual needs. The number of pixels on the display substrate and the number of subpixels in each pixel are also not limited to the numbers shown in the drawings. The drawings described in this disclosure are merely structural schematic diagrams, and one aspect of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0029] In this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of components and are not intended to limit the number of components.

[0030] For convenience, the positions of components in this specification are described with reference to the drawings using terms indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer." However, this is intended to simplify and explain the specification, and is not intended to indicate or suggest that the described devices or elements have a specific orientation or must be configured and operated in a specific orientation. Therefore, it is not intended to limit the present disclosure. The positional relationships of components may be appropriately changed depending on the direction in which each component is described. Therefore, the terms described in the specification may not be limited and may be appropriately changed as the case may be.

[0031] In this specification, unless otherwise clearly specified and limited, the terms "attached," "coupled," and "connected" should be understood in a broad sense. For example, they may be fixedly connected, detachably connected, or integrally connected. They may be mechanically connected or connected. They may be directly connected, indirectly connected via a linker, or internal communication between two elements. Those skilled in the art can understand the specific meanings of the above terms in the present disclosure according to the specific circumstances.

[0032] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and a current can flow through the drain electrode, channel region, and source electrode. In this specification, the channel region refers to a region through which a current mainly flows.

[0033] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. When using a transistor with opposite polarity, or when the current direction during operation in a circuit changes, the functions of "source electrode" and "drain electrode" may be interchangeable. Therefore, in this specification, "source electrode" and "drain electrode" may be interchangeable, and "source terminal" and "drain terminal" may be interchangeable.

[0034] In this specification, "connection" includes cases where components are connected via an element having a certain electrical function. The "element having a certain electrical function" is not particularly limited as long as it can transmit and receive electrical signals between the connected components. Examples of the "element having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0035] In this specification, "parallel" refers to a state in which the angle formed by two straight lines is between -10° and 10°, and includes a state in which the angle is between -5° and 5°. "Perpendicular" refers to a state in which the angle formed by two straight lines is between 80° and 100°, and includes a state in which the angle is between 85° and 95°.

[0036] In this specification, the terms "film" and "layer" are interchangeable. For example, a "conductive layer" may be changed to a "conductive thin film." Similarly, an "insulating film" may be changed to an "insulating layer."

[0037] In this disclosure, the terms "thickness" and "height" refer to the vertical distance from the surface of the membrane layer away from the base to the surface of the membrane layer closer to the base.

[0038] The triangles, rectangles, trapezoids, pentagons, hexagons, etc. in this specification are not intended to be exact, and may be approximate triangles, rectangles, trapezoids, pentagons, hexagons, etc., and may have small variations due to tolerances, chamfers, arc edges, and variations.

[0039] In this disclosure, "about" refers to a case where the boundary is not precisely defined, but rather allows for a numerical value within the tolerances of process and measurement.

[0040] FIG. 1 is a structural schematic diagram of a display device. As shown in FIG. 1, the main body structure of a large-screen display device may include a plurality of display substrates 200 mounted on a motherboard 100, with the plurality of display substrates 200 closely connected to display images. In a plane perpendicular to the display substrates, at least one display substrate 200 may include at least a driving circuit layer 20 mounted on a base 10 and a light-emitting structure layer 30 mounted on the side of the driving circuit layer 20 away from the base. In a plane parallel to the display substrates, the driving circuit layer 20 may include a plurality of circuit units, at least one of which may include a pixel driving circuit and a plurality of signal lines connected to the pixel driving circuit, and the pixel driving circuit is configured to receive a data voltage and output a corresponding current under the control of the signal lines. The light-emitting structure layer 30 may include a plurality of light-emitting units, at least one of which may include a light-emitting diode 40, and the light-emitting diodes 40 in the plurality of light-emitting units are correspondingly connected to pixel driving circuits in the plurality of circuit units, and the light-emitting diodes 40 are configured to emit light rays of corresponding brightness under the driving of the output current of the corresponding pixel driving circuit.

[0041] In an exemplary embodiment, the circuit unit described in the present disclosure refers to an area divided into each pixel driving circuit, and the light-emitting unit described in the present disclosure refers to an area divided into each light-emitting diode. In an exemplary embodiment, the positions of both the light-emitting unit and the circuit unit may correspond to each other, or may not correspond to each other, and the present disclosure is not limited thereto.

[0042] 2 is a schematic diagram of the planar structure of a light-emitting structure layer on a display substrate. As shown in FIG. 2, the light-emitting structure layer may include, in a plane parallel to the display substrate, a first light-emitting unit P1 that emits a first color light, a second light-emitting unit P2 that emits a second color light, and a third light-emitting unit P3 that emits a third color light. In an exemplary embodiment, the first light-emitting unit P1 may be a red light-emitting unit that emits red light and form a red (R) subpixel, the second light-emitting unit P2 may be a green light-emitting unit that emits green light and form a green (G) subpixel, and the third light-emitting unit P3 may be a blue light-emitting unit that emits blue light and form a blue (B) subpixel.

[0043] In an exemplary embodiment, a red subpixel, a blue subpixel, and a green subpixel may constitute one pixel unit P. The shape of the subpixel may be rectangular, rhombic, pentagonal, or hexagonal, and the three subpixels in one pixel unit P may be arranged in a horizontal array, vertical array, or square shape, etc., and the present disclosure is not limited thereto.

[0044] In an exemplary embodiment, a pixel unit includes four sub-pixels, and the four sub-pixels may be arranged in a manner such as a horizontal array, a vertical array, a square or a diamond shape.

[0045] In an exemplary embodiment, the light emitting diode 40 may be a mini light emitting diode (Mini LED) or a micro light emitting diode (Micro LED).

[0046] 3 is a schematic plan view of the driving structure layer on the display substrate, showing a structure in which a gate driving circuit is installed in the display area (Gate Driver In AA, abbreviated as GIA). As shown in FIG. 3, in a plane parallel to the display substrate, the driving structure layer may include at least a first circuit area 210 and a second circuit area 220. The second circuit area 220 may have an elongated shape extending along the second direction Y. The second circuit area 220 may be installed on the first direction X side or the opposite side of the first direction X from the first circuit area 210, and the first direction X and the second direction Y intersect.

[0047] In an exemplary embodiment, the first circuit region 210 may include a plurality of circuit units Q forming a plurality of unit rows and a plurality of unit columns, where the unit rows may include a plurality of circuit units Q arranged sequentially along a first direction X, and the unit columns may include a plurality of circuit units Q arranged sequentially along a second direction Y. At least one circuit unit Q may include at least a pixel driving circuit, where the plurality of pixel driving circuits in a unit row are connected to driving signal lines in the unit row, and the pixel driving circuit is configured to receive a data voltage under the control of the driving signal line and output a current corresponding to the connected light emitting diode.

[0048] In an exemplary embodiment, the second circuit region 220 may include at least a gate driver, which may include at least a plurality of gate units G sequentially arranged and cascaded along the second direction Y, at least one gate unit G may include at least one gate driver circuit, the gate driver circuit is connected to a driver signal line in a corresponding unit row, and the gate driver circuit is configured to output a row driver signal to the driver signal line in the corresponding unit row.

[0049] In an exemplary embodiment, the driving signal lines may include at least scanning signal lines and light-emitting signal lines, and the gate unit G may include at least a first gate driving circuit (GOA circuit) and a second gate driving circuit (EOA circuit), where the first gate driving circuit may be connected to the scanning signal lines and the second gate driving circuit may be connected to the light-emitting signal lines.

[0050] FIG. 4 is an equivalent circuit diagram of a pixel driving circuit, showing the structure of an 11T3C pixel driving circuit. In an exemplary embodiment, the multiple light-emitting diodes on the display substrate may be driven using a current mode. Current-mode light-emitting diodes can suffer from color coordinate drift and reduced external quantum efficiency when driven at low current densities, resulting in poor brightness uniformity, making it difficult to accurately represent low gray scales by simply controlling the current amplitude. The pixel driving circuit used on the display substrate includes at least two types of data terminals: a current data terminal and a time length data terminal. The current data terminal is configured to supply current signals with different amplitudes to the light-emitting diodes, and the time length data terminal is configured to supply the time length of the current signal to the light-emitting diodes.

[0051] 4, the pixel driving circuit may include at least a current control sub-circuit DK and a time length control sub-circuit SK. The current control sub-circuit DK may include at least a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor Cs, and the time length control sub-circuit SK may include at least an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a first capacitor C1, and a second capacitor C2.

[0052] In an exemplary embodiment, the pixel driving circuit may include at least a first node N1, a second node N2, a third node N3, a fourth node N4, a fifth node N5, a sixth node N6, and a seventh node N7. The first node N1 is connected to the gate electrode of the sixth node N6, the second pole of the ninth transistor T9, and the second pole of the eleventh transistor T11, respectively. The second node N2 is connected to the second pole of the sixth transistor T6, the second pole of the seventh transistor T7, and the anode of the light-emitting diode EL, respectively. The third node N3 is connected to the second pole of the first transistor T1, the first pole of the second transistor T2, the gate electrode of the third transistor T3, and the first end of the storage capacitor Cs, respectively. The fourth node N4 is connected to the second pole of the second transistor T2, the second pole of the third transistor T3, and the first pole of the sixth transistor T6, respectively. The fifth node N5 is connected to the first pole of the third transistor T3, the second pole of the fourth transistor T4, and the second pole of the fifth transistor T5, respectively. The sixth node N6 is connected to the second pole of the eighth transistor T8, the gate electrode of the ninth transistor T9, and the first terminal of the first capacitor C1, and the seventh node N7 is connected to the second pole of the tenth transistor T10, the gate electrode of the eleventh transistor T11, and the first terminal of the second capacitor C2, respectively.

[0053] In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the second scanning signal line S2, the first pole of the first transistor T1 is connected to the initial signal line Vint, and the second pole of the first transistor T1 is connected to the third node N3.

[0054] In an exemplary embodiment, the gate electrode of the second transistor T2 is connected to the first scanning signal line S1, the first pole of the second transistor T2 is connected to the third node N3, and the second pole of the second transistor T2 is connected to the fourth node N4.

[0055] In an exemplary embodiment, the gate electrode of the third transistor T3 is connected to the third node N3, the first pole of the third transistor T3 is connected to the fifth node N5, and the second pole of the third transistor T3 is connected to the fourth node N4.

[0056] In an exemplary embodiment, the gate electrode of the fourth transistor T4 is connected to the first scanning signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line DataI, and the second electrode of the fourth transistor T4 is connected to the fifth node N5.

[0057] In an exemplary embodiment, the gate electrode of the fifth transistor T5 is connected to the light emitting signal line EM, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the fifth node N5.

[0058] In an exemplary embodiment, the gate electrode of the sixth transistor T6 is connected to the first node N1, the first pole of the sixth transistor T6 is connected to the fourth node N4, and the second pole of the sixth transistor T6 is connected to the second node N2.

[0059] In an exemplary embodiment, the gate electrode of the seventh transistor T7 is connected to the second scanning signal line S2, the first pole of the seventh transistor T7 is connected to the initial signal line Vint, and the second pole of the seventh transistor T7 is connected to the second node N2.

[0060] In an exemplary embodiment, the gate electrode of the eighth transistor T8 is connected to the first control line CT1, the first electrode of the eighth transistor T8 is connected to the time-length signal line DataT, and the second electrode of the eighth transistor T8 is connected to the sixth node N6.

[0061] In an exemplary embodiment, the gate electrode of the ninth transistor T9 is connected to the sixth node N6, the first electrode of the ninth transistor T9 is connected to the light emission signal line EM, and the second electrode of the ninth transistor T9 is connected to the first node N1.

[0062] In an exemplary embodiment, the gate electrode of the tenth transistor T10 is connected to the second control line CT2, the first electrode of the tenth transistor T10 is connected to the time-length signal line DataT, and the second electrode of the tenth transistor T10 is connected to the seventh node N7.

[0063] In an exemplary embodiment, the gate electrode of the eleventh transistor T11 is connected to the seventh node N7, the first pole of the eleventh transistor T11 is connected to the high-frequency signal line Hf, and the second pole of the eleventh transistor T11 is connected to the first node N1.

[0064] In the exemplary embodiment, a first end of the storage capacitor Cs is connected to the third node N3, and a second end of the storage capacitor Cs is connected to the first power supply rail VDD.

[0065] In the exemplary embodiment, a first end of the first capacitor C1 is connected to the sixth node N6, and a second end of the first capacitor C1 is connected to the initial signal line Vint.

[0066] In the exemplary embodiment, a first end of the second capacitor C2 is connected to the seventh node N7, and a second end of the second capacitor C2 is connected to the initial signal line Vint.

[0067] In an exemplary embodiment, the first transistor T1, the second transistor T2, the fourth transistor T4 to the eleventh transistor T11 may be switching transistors, and the third transistor T3 may be a driving transistor.

[0068] In an exemplary embodiment, the light emitting diode EL may be a Mini LED or a Micro LED. A first pole of the light emitting diode EL is connected to the second node N2, and a second pole of the light emitting diode EL is connected to a second power supply line VSS, and the signal of the second power supply line VSS is a continuously provided low-level signal, such as a DC low voltage. The signal of the first power supply line VDD is a continuously provided high-level signal, such as a DC high voltage.

[0069] In an exemplary embodiment, the first transistor T1 to the eleventh transistor T11 may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the processing difficulty of the display panel, and improve the yield rate of the product. In some possible embodiments, the first transistor T1 to the eleventh transistor T11 may include P-type transistors and N-type transistors.

[0070] In an exemplary embodiment, the first transistor T1 to the eleventh transistor T11 may be low-temperature polysilicon transistors, oxide transistors, or both low-temperature polysilicon transistors and metal oxide transistors. The active layer of the low-temperature polysilicon transistors is low-temperature polysilicon (abbreviated as LTPS), and the active layer of the metal oxide transistors is metal oxide semiconductor (oxide). The low-temperature polysilicon transistors have advantages such as high mobility and fast charging, while the oxide transistors have advantages such as low leakage current. By integrating the low-temperature polysilicon transistors and the metal oxide transistors on one display substrate to form a low-temperature polycrystalline oxide (abbreviated as LTPO) display substrate, the advantages of both can be utilized to realize low-frequency driving, reduce power consumption, and improve display properties.

[0071] In an exemplary embodiment, taking the pixel driving circuit shown in FIG. 4 as an example in which the first transistor T1 and the eleventh transistor T11 are both P-type transistors, the operation process of the pixel driving circuit may include the following:

[0072] In an exemplary embodiment, when the gray scale displayed by the light emitting diode connected to the pixel driving circuit is greater than a threshold gray scale, the operation process of the pixel driving circuit may include an initialization stage, a writing stage, and an emission stage, and the initialization stage may include a first sub-stage and a second sub-stage.

[0073] In the first and second sub-phases, the signals on the first scanning signal line S1 and the light-emitting signal line EM are high, the signal on the second scanning signal line S2 is low, and the first transistor T1 and the seventh transistor T7 are turned on. When the first transistor T1 is turned on, the signal on the initial signal line Vint is written to the third node N3, initializing (resetting) the storage capacitor Cs and clearing any existing charge on the storage capacitor Cs. Because the first end of the storage capacitor Cs is low, the third transistor T3 is turned on. When the seventh transistor T7 is turned on, the signal on the initial signal line Vint is written to the second node N2, initializing (resetting) the first pole of the light-emitting diode EL and clearing the voltage previously stored therein, completing the initialization and ensuring that the light-emitting diode EL does not emit light.

[0074] In the first sub-phase, the signal on the time-long signal line DataT is high, the signal on the second control line CT2 is low, and the tenth transistor T10 is turned on, so that the signal on the time-long signal line DataT is written to the seventh node N7 and charges the second capacitor C2. At this time, because the signal on the time-long signal line DataT is high, the eleventh transistor T11 is turned off, and the signal on the high-frequency signal line Hf is not written to the first node N1.

[0075] In the second sub-phase, the signal on the time-long signal line DataT is low, the signal on the first control line CT1 is low, and the eighth transistor T8 is turned on, so that the signal on the time-long signal line DataT is written to the sixth node N6 and charges the first capacitor C1. At this time, because the signal on the time-long signal line DataT is low, the ninth transistor T9 is turned on, and the signal on the light-emitting signal line EM is written to the first node N1.

[0076] In the write phase, the data signal line DataI outputs a data voltage, the signals on the second scan signal line S2 and the light-emitting signal line E are high, the signal on the first scan signal line S1 is low, and the second transistor T2 and the fourth transistor T4 are turned on. With the second transistor T2 and the fourth transistor T4 turned on, the data voltage output from the data signal line DataI is supplied to the third node N3 via the fifth node N5, the turned-on third transistor T3, the fourth node N4, and the turned-on second transistor T2. The difference between the data voltage Vd output from the data signal line DataI and the threshold voltage Vth of the third transistor T3 is stored in the storage capacitor Cs, and the voltage at the first end (third node N3) of the storage capacitor Cs is Vd-|Vth|. The first capacitor C1 maintains the potential of the signal at the sixth node N6 constant, the ninth transistor T9 remains turned on, and the signal on the light-emitting signal line EM is written to the first node N1.

[0077] In the light-emitting stage, the signal on the light-emitting signal line EM is a low-level signal, the fifth transistor T5 is turned on, the first capacitor C1 maintains the potential of the signal on the sixth node N6, the ninth transistor T9 remains turned on, the signal on the light-emitting signal line EM is written to the first node N1, and the sixth transistor T6 is turned on. The power supply voltage output from the first power supply line VDD supplies a driving voltage to the first electrode of the light-emitting diode EL via the fifth transistor T5, the third transistor T3, and the sixth transistor T6, which are turned on, to drive the light-emitting diode EL to emit light.

[0078] In an exemplary embodiment, when the gray scale displayed by the light emitting diode connected to the pixel driving circuit is smaller than the threshold gray scale, the operation process of the pixel driving circuit includes an initialization stage, a writing stage and an emission stage, and the initialization stage may include a first sub-stage and a second sub-stage.

[0079] In the first and second sub-phases, the signals on the first scanning signal line S1 and the light-emitting signal line EM are high, the signal on the second scanning signal line S2 is low, and the first transistor T1 and the seventh transistor T7 are turned on. When the first transistor T1 is turned on, the signal on the initial signal line Vint is written to the third node N3, initializing (resetting) the storage capacitor Cs and clearing any existing charge on the storage capacitor Cs. Because the first end of the storage capacitor Cs is low, the third transistor T3 is turned on. When the seventh transistor T7 is turned on, the signal on the initial signal line Vint is written to the second node N2, initializing (resetting) the first pole of the light-emitting diode EL and clearing the voltage previously stored therein, completing the initialization and ensuring that the light-emitting diode EL does not emit light.

[0080] In the first sub-phase, the signal on the time-long signal line DataT is low, the signal on the second control line CT2 is low, and the tenth transistor T10 is turned on, so that the signal on the time-long signal line DataT is written to the seventh node N7 and charges the second capacitor C2. At this time, because the signal on the time-long signal line DataT is low, the eleventh transistor T11 is turned on, so that the signal on the high-frequency signal line Hf is written to the first node N1.

[0081] In the second sub-phase, the signal on the time-long signal line DataT is high, the signal on the first control line CT1 is low, the eighth transistor T8 is turned on, and the signal on the time-long signal line DataT is written to the sixth node N6 to charge the first capacitor C1. At this time, because the signal on the time-long signal line DataT is high, the ninth transistor T9 is turned off, and the signal on the light-emitting signal line EM is not written to the first node N1.

[0082] During the write phase, the data signal line DataI outputs a data voltage, the signals on the second scan signal line S2 and the light-emitting signal line E are high, the signal on the first scan signal line S1 is low, and the second transistor T2 and the fourth transistor T4 are turned on. With the second transistor T2 and the fourth transistor T4 turned on, the data voltage output from the data signal line DataI is supplied to the third node N3 via the fifth node N5, the turned-on third transistor T3, the fourth node N4, and the turned-on second transistor T2. The difference between the data voltage Vd output from the data signal line DataI and the threshold voltage Vth of the third transistor T3 is stored in the storage capacitor Cs, and the voltage at the first end (third node N3) of the storage capacitor Cs is Vd - |Vth|. The second capacitor C2 maintains the potential of the signal at the seventh node N7 constant, the eleventh transistor T11 is always turned on, and the signal on the high-frequency signal line Hf is written to the first node N1.

[0083] In the light-emitting stage, the signal on the light-emitting signal line EM is a low-level signal, the fifth transistor T5 is turned on, the second capacitor C2 maintains the potential of the signal at the seventh node N7 constant, the eleventh transistor T11 is always turned on, the signal on the high-frequency signal line Hf is written to the first node N1, and the sixth transistor T6 is turned on. The power supply voltage output from the first power supply line VDD supplies a driving voltage to the first electrode of the light-emitting diode EL via the fifth transistor T5, the third transistor T3, and the sixth transistor T6, which are turned on, to drive the light-emitting diode EL to emit light.

[0084] In the exemplary embodiment, during the light-emitting stage, the driving current output by the third transistor T3 in the pixel driving circuit is only related to the voltage of the data signal line and the voltage of the first power supply line, without being affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring the uniformity of the display brightness of the display product, and improving the display effect.

[0085] In an exemplary embodiment, when the gray scale displayed by the light emitting diode connected to the pixel driving circuit is greater than a threshold gray scale, a control signal is supplied to the first node N1 via the light emitting signal line, thereby controlling the gray scale of the light emitting diode by the driving current.When the gray scale displayed by the light emitting diode connected to the pixel driving circuit is less than the threshold gray scale, a control signal is supplied to the first node N1 via the high-frequency signal line, thereby controlling the gray scale of the light emitting diode by the driving current and the light emitting time length.

[0086] In an exemplary embodiment, the signal on the high-frequency signal line Hf is a pulse signal, and the signal on the high-frequency signal line Hf has multiple pulses within one image frame. In an exemplary embodiment, the frequency of the signal on the high-frequency signal line Hf may be greater than the frequency of the signal on the light-emitting signal line EM. For example, the frequency of the signal on the high-frequency signal line Hf may be between 3,000 Hz and 60,000 Hz, and the frequency of the light-emitting signal line EM may be between 60 Hz and 120 Hz. In the present disclosure, the high-frequency pulse signal on the high-frequency signal line controls the light-emitting duration, dispersing short light-emitting durations within one frame time. This reduces flashing that occurs when the grayscale displayed by the light-emitting diodes connected to the pixel driving circuit is smaller than the threshold grayscale, thereby improving the display effect of display products.

[0087] FIG. 5 is a structural schematic diagram of a gate driver. In an exemplary embodiment, the gate driver may include at least a plurality of cascaded GOA circuits (first gate driver circuits). As shown in FIG. 5, the plurality of GOA circuits may include a first-stage GOA circuit, a second-stage GOA circuit, a third-stage GOA circuit, ..., an i-th stage GOA circuit.... The first-stage GOA circuit may generate a scan signal G(1) for the pixel driver circuit of the first unit row based on an initial signal provided from an initial signal line STV, clock signals provided from a first clock signal line CLK and a second clock signal line CLKB, etc. The i-th stage GOA circuit may generate a scan signal G(i) for the pixel driver circuit of the i-th unit row based on a scan signal G(i-1) generated by the i-1-th stage GOA circuit, a scan signal G(i+1) generated by the i+1-th stage GOA circuit, clock signals provided from the first clock signal line CLK and a second clock signal line CLKB, etc., where i is a positive integer greater than 1.

[0088] 6 is an equivalent circuit diagram of the gate drive circuit, showing the 8T2C GOA circuit structure. As shown in FIG. 6, in an exemplary embodiment, the gate drive circuit may include eight transistors (the 21st transistor T21 to the 28th transistor T28) and two capacitors (the third capacitor C3 and the fourth capacitor C4), and the gate drive circuits are respectively connected to six signal lines (the first clock signal line CLK, the second clock signal line CLKB, the high voltage line VGH, the low voltage line VGL, the upper stage signal output line G(n-1), and the main stage signal output line G(n)).

[0089] In an exemplary embodiment, the gate drive circuit may include at least an eleventh node N11, a twelfth node N12, a thirteenth node N13, and a fourteenth node N14. The eleventh node N11 is connected to the second pole of the first transistor T21, the gate electrode of the second transistor T22, the second pole of the seventh transistor T27, and the first pole of the eighth transistor T28, respectively. The twelfth node N12 is connected to the second pole of the third transistor T23, the second pole of the second transistor T22, the gate electrode of the fourth transistor T24, the gate electrode of the sixth transistor T26, and the first terminal of the fourth capacitor C4, respectively. The thirteenth node N13 is connected to the second pole of the sixth transistor T26 and the first pole of the seventh transistor T27, respectively. The fourteenth node N14 is connected to the gate electrode of the fifth transistor T25, the second pole of the eighth transistor T28, and the first terminal of the third capacitor C3, respectively.

[0090] In an exemplary embodiment, the gate electrode of the twenty-first transistor T21 is connected to the first clock signal line CLK, the first electrode of the twenty-first transistor T21 is connected to the upper stage signal output line G(n-1), and the second electrode of the twenty-first transistor T21 is connected to the eleventh node N11.

[0091] In an exemplary embodiment, the gate electrode of the 22nd transistor T22 is connected to the 11th node N11, the first pole of the 22nd transistor T22 is connected to the first clock signal line CLK, and the second pole of the 22nd transistor T22 is connected to the 12th node N12.

[0092] In an exemplary embodiment, the gate electrode of the 23rd transistor T23 is connected to the first clock signal line CLK, the first electrode of the 23rd transistor T23 is connected to the low voltage line VGL, and the second electrode of the 23rd transistor T23 is connected to the 12th node N12.

[0093] In an exemplary embodiment, the gate electrode of the twenty-fourth transistor T24 is connected to the twelfth node N12, the first electrode of the twenty-fourth transistor T24 is connected to the high voltage rail VGH, and the second electrode of the twenty-fourth transistor T24 is connected to the main stage signal output line G(n).

[0094] In an exemplary embodiment, a gate electrode of the 25th transistor T25 is connected to the 14th node N14, a first electrode of the 25th transistor T25 is connected to the second clock signal line CLKB, and a second electrode of the 25th transistor T25 is connected to the main stage signal output line G(n).

[0095] In an exemplary embodiment, the gate electrode of the twenty-sixth transistor T26 is connected to the twelfth node N12, the first electrode of the twenty-sixth transistor T26 is connected to the high voltage rail VGH, and the second electrode of the twenty-sixth transistor T26 is connected to the thirteenth node N13.

[0096] In an exemplary embodiment, the gate electrode of the 27th transistor T27 is connected to the second clock signal line CLKB, the first electrode of the 27th transistor T27 is connected to the 13th node N13, and the second electrode of the 27th transistor T27 is connected to the 11th node N11.

[0097] In an exemplary embodiment, the gate electrode of the 28th transistor T28 is connected to the low voltage rail VGL, the first electrode of the 28th transistor T28 is connected to the 11th node N11, and the second electrode of the 28th transistor T28 is connected to the 14th node N14.

[0098] In the exemplary embodiment, the first end of the third capacitor C3 is connected to the fourteenth node N14, the second end of the third capacitor C3 is connected to the main stage signal output line G(n), the first end of the fourth capacitor C4 is connected to the twelfth node N12, and the second end of the fourth capacitor C4 is connected to the high voltage line VGH.

[0099] In an exemplary embodiment, when the level of the first clock signal line CLK is at an active level, the level of the second clock signal line CLKB is at an inactive level, and when the level of the second clock signal line CLKB is at an active level, the level of the first clock signal line CLK is at an inactive level, the high voltage line VGH continuously supplies a high level signal, and the low voltage line VGL continuously supplies a low level signal.

[0100] In an exemplary embodiment, the pulse duration of the active level signal on the first clock signal line CLK may be essentially equal to the pulse duration of the active level signal on the second clock signal line CLKB.

[0101] In an exemplary embodiment, the 21st transistor T21 to the 28th transistor T28 may all be N-type thin film transistors or all P-type thin film transistors, which can unify the process flow, reduce process steps, and contribute to improving product yield. Considering that low-temperature polysilicon thin film transistors have small leakage currents, the 21st transistor T21 to the 28th transistor T28 may be low-temperature polysilicon thin film transistors, and the thin film transistors may have a bottom-gate structure or a top-gate structure.

[0102] An embodiment of the present disclosure provides a display substrate, in an exemplary embodiment, the display substrate includes a plurality of first circuit regions and a plurality of second circuit regions alternately arranged along a second direction, the first circuit regions include a plurality of repeat units and a plurality of blank units alternately arranged along the first direction, the first direction and the second direction intersect, the repeat units include a plurality of circuit units, each circuit unit including a pixel driving circuit and a data signal line and a driving signal line connected to the pixel driving circuit, the second circuit region includes at least one gate unit, each gate unit including at least one gate driving circuit, the gate driving circuit connected to the driving signal line in an adjacent circuit unit, and orthogonal projections of the gate driving circuit on the display substrate plane do not overlap with orthogonal projections of the data signal lines on the display substrate plane.

[0103] In an exemplary embodiment, at least one second circuit area has a reference line, which is a straight line that equally divides the second circuit area in the second direction and extends along the first direction, and an orthogonal projection of at least one gate drive circuit on the reference line at least partially overlaps with an orthogonal projection of at least one blank unit on the reference line.

[0104] In an exemplary embodiment, at least one gate driving circuit is further connected to a clock signal line, a high voltage line, and a low voltage line, and in the first direction, the clock signal line is disposed between the high voltage line and the low voltage line, and the orthogonal projection of the clock signal line on the display substrate plane does not overlap with the orthogonal projection of the data signal line on the display substrate plane.

[0105] In an exemplary embodiment, in the first direction, the data signal line is located on the side of the high voltage line away from the low voltage line, or the data signal line is located on the side of the low voltage line away from the high voltage line.

[0106] In an exemplary embodiment, at least one second circuit area further includes at least one first mark, and the installation position of the at least one first mark in the second circuit area corresponds to the installation position of at least one blank unit in the first circuit area.

[0107] In an exemplary embodiment, at least one second circuit area further includes at least one second mark, and the installation position of the at least one second mark in the second circuit area corresponds to the installation position of at least one blank unit in the first circuit area.

[0108] In an exemplary embodiment, in a plane perpendicular to the display substrate, the display substrate includes a first gate metal layer, a second gate metal layer, a first source / drain metal layer, and a second source / drain metal layer sequentially disposed on a base, the driving signal line being disposed on the second gate metal layer, and the data signal line and the clock signal line being disposed on the first source / drain metal layer.

[0109] In an exemplary embodiment, the at least one second circuit region further includes at least one first mark and at least one second mark, the first mark being disposed in the first source-drain metal layer and the second mark being disposed in the second source-drain metal layer.

[0110] FIG. 7 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure, illustrating the planar structure of a driving structure layer on the display substrate. In a plane perpendicular to the display substrate, the display substrate 200 may include at least a driving structure layer disposed on the substrate and a light-emitting structure layer disposed on a side of the driving structure layer away from the base. In a plane parallel to the display substrate, the driving structure layer may include at least a plurality of first circuit regions 210 and a plurality of second circuit regions 220. As shown in FIG. 7 , each of the first circuit regions 210 and the second circuit regions 220 may have an elongated shape extending along the first direction X, and the plurality of first circuit regions 210 and the plurality of second circuit regions 220 may be alternately arranged along the second direction Y. In an exemplary embodiment, the first circuit region may be referred to as a pixel circuit region, and the second circuit region may be referred to as a gate circuit region.

[0111] In an exemplary embodiment, the first circuit region 210 may include a plurality of repeat units RU and a plurality of blank units KB, and the plurality of repeat units RU and the plurality of blank units KB may be alternately arranged along the first direction X. At least one repeat unit RU may include m1*m2 circuit units Q, where m1 may be the number of unit columns included in the repeat unit RU, and m2 may be the number of unit columns included in the repeat unit RU, and m1 and m2 may be positive integers greater than or equal to 2. For example, the repeat unit RU may include two unit rows and three unit columns, and the repeat unit RU forms a 2*3 circuit unit array. Also, for example, the repeat unit RU may include two unit rows and six unit columns, and the repeat unit RU forms a 2*6 circuit unit array.

[0112] In an exemplary embodiment, the repeat unit RU may be an area where a pixel driving circuit is provided, and the blank unit KB may be an area where a pixel driving circuit is not provided. In an exemplary embodiment, some of the blank units KB may be wiring areas for gate drivers to reduce interference between signal lines. Some of the blank units KB may be light-transmitting areas of the display substrate to allow external light to pass through the display substrate to form a transparent display. In an exemplary embodiment, the width of the blank unit KB may be larger than the width between adjacent circuit units Q in the first direction X within the repeat unit RU, and the width may be a dimension in the first direction X.

[0113] In an exemplary embodiment, at least one circuit unit Q may include at least a pixel driving circuit, a driving signal line extending along a first direction X and a data signal line extending along a second direction Y, the pixel driving circuit being connected to the driving signal line and the data signal line respectively, and configured to receive a data voltage of the data signal line under the control of the driving signal line and output a corresponding current to a connected light emitting diode. The light emitting structure layer may include a plurality of light emitting units, each of which may include at least a light emitting diode, and the light emitting diodes in the plurality of light emitting units are correspondingly connected to the pixel driving circuits in the plurality of circuit units, so that the light emitting diodes emit light of corresponding brightness when driven by the output current of the corresponding pixel driving circuit.

[0114] In an exemplary embodiment, the second circuit area 220 may include at least one gate unit G, and the at least one gate unit G may include a gate drive circuit, which is connected to a drive signal line in the adjacent first circuit area 210, and which is configured to output a row drive signal to the drive signal line to which it is connected.

[0115] In an exemplary embodiment, the at least one second circuit area 220 may have a reference line O1, which may be a straight line that equally divides the second circuit area 220 in the second direction Y and extends along the first direction X. In an exemplary embodiment, the installation position of the at least one gate driving circuit in the second circuit area 220 may basically correspond to the installation position of the at least one blank unit KB in the first circuit area 210, and the orthogonal projection of the at least one gate driving circuit on the reference line O1 at least partially overlaps with the orthogonal projection of the at least one blank unit KB on the reference line O1.

[0116] In an exemplary embodiment, at least one second circuit area 220 may further include at least one first mark MARK1, and the first mark MARK1 may be located on one edge or both edges of the second circuit area 220 in the first direction X. The first mark MARK1 is configured as a splice mark, and positioning is performed via the first mark MARK1 when performing a splice connection of the display substrate.

[0117] In an exemplary embodiment, the shape of the first mark MARK1 may be cross-shaped, the installation position of at least one first mark MARK1 in the second circuit area 220 may basically correspond to the installation position of at least one blank unit KB in the first circuit area 210, and the orthogonal projection of the at least one first mark MARK1 on the reference line O1 at least partially overlaps with the orthogonal projection of the at least one blank unit KB on the reference line O1.

[0118] In an exemplary embodiment, at least one second circuit region 220 may further include at least one second mark MARK2, which may be located on one edge or both edges of the second circuit region 220 in the first direction X and on a side closer to the gate unit G than the first mark MARK1. The second mark MARK2 is configured as a binding mark, and positioning is performed via the second mark MARK2 when binding connection of the light-emitting diode.

[0119] In an exemplary embodiment, the shape of the second mark MARK2 may be circular, the installation position of at least one second mark MARK2 in the second circuit area 220 may basically correspond to the installation position of at least one blank unit KB in the first circuit area 210, and the orthogonal projection of the at least one second mark MARK2 on the reference line O1 at least partially overlaps with the orthogonal projection of the at least one blank unit KB on the reference line O1.

[0120] 8 is a schematic diagram of the wiring of a gate driving circuit in an exemplary embodiment of the present disclosure. As shown in FIG. 8, a driving signal line HL and a data signal line DataI are connected to the pixel driving circuit in a circuit unit Q. The driving signal line HL may be a linear shape extending along a first direction X, and the driving signal line HL is configured to be connected to multiple pixel driving circuits in one unit row. The data signal line DataI may be a linear shape extending along a second direction Y, and the data signal line DataI is configured to be connected to multiple pixel driving circuits in one unit column. The gate driving circuit in a gate unit G is connected to a first clock signal line CLK, a second clock signal line CLKB, a high-voltage line VGH, and a low-voltage line VGL, and the gate driving circuit is connected to the driving signal line HL in an adjacent unit column via an output line OUT.

[0121] In an exemplary embodiment, the first clock signal line CLK, the second clock signal line CLKB, the high voltage line VGH, and the low voltage line VGL may have a linear shape extending along the second direction Y and be arranged sequentially along the first direction X. The first clock signal line CLK, the second clock signal line CLKB, the high voltage line VGH, and the low voltage line VGL are configured to supply a first clock signal, a second clock signal, a high voltage signal, and a low voltage signal to the connected gate drive circuits, respectively, and the first clock signal line CLK and the second clock signal line CLKB constitute the clock signal lines of the present disclosure.

[0122] In an exemplary embodiment, the orthogonal projection of the gate driving circuit in gate unit G on the display substrate plane does not overlap with the orthogonal projection of the data signal line DataI on the display substrate plane, and the gate driving circuit may include transistors 21 to 28, a third capacitor, and a fourth capacitor.

[0123] In an exemplary embodiment, the orthogonal projection of the first clock signal line CLK onto the display substrate plane does not overlap with the orthogonal projection of the data signal line DataI onto the display substrate plane, and the orthogonal projection of the second clock signal line CLKB onto the display substrate plane does not overlap with the orthogonal projection of the data signal line DataI onto the display substrate plane.

[0124] In an exemplary embodiment, the first clock signal line CLK may be essentially parallel to the data signal line DataI, and the second clock signal line CLKB may be essentially parallel to the data signal line DataI, or the orthogonal projection of the first clock signal line CLK on the display substrate plane may be essentially parallel to the orthogonal projection of the data signal line DataI on the display substrate plane, and the orthogonal projection of the second clock signal line CLKB on the display substrate plane may be essentially parallel to the orthogonal projection of the data signal line DataI on the display substrate plane.

[0125] In an exemplary embodiment, along the second direction Y, the repeating units RU of the multiple first circuit areas 210 may form a repeating unit string extending along a single second direction Y, and the blank units KB of the multiple first circuit areas 210 may form a blank unit string extending along a single second direction Y, and the data signal line DataI may be installed in the area where the repeating unit string is located, and the first clock signal line CLK and the second clock signal line CLKB may be installed in the area where the blank unit string is located, so that the data signal line DataI does not overlap with the first clock signal line CLK and the second clock signal line CLKB.

[0126] In an exemplary embodiment, the first clock signal line CLK and the second clock signal line CLKB may be disposed between the high voltage line VGH and the low voltage line VGL along the first direction X, whereby the data signal line DataI is located on the side of the high voltage line VGH away from the first clock signal line CLK, and the data signal line DataI is located on the side of the low voltage line VGL away from the second clock signal line CLKB, and the high voltage line VGH and the low voltage line VGL transmitting constant voltage signals may serve as a shield, effectively reducing the coupling capacitance between the clock signal lines and the data signal lines.

[0127] In an exemplary embodiment, a first distance L1 is present between the edge of the high voltage line VGH closer to the data signal line DataI and the edge of the data signal line DataI closer to the high voltage line VGH, and a second distance L2 is present between the edge of the low voltage line VGL closer to the data signal line DataI and the edge of the data signal line DataI closer to the low voltage line VGL, where the second distance L2 may be greater than the first distance L1, and the first distance L1 and the second distance L2 may be dimensions in the first direction X.

[0128] In an exemplary embodiment, the first distance L1 may be 25 μm or greater, and the second distance L2 may be 25 μm or greater.

[0129] In an exemplary embodiment, the second clock signal line CLKB may be provided on a side of the first clock signal line CLK that is away from the low voltage line VGL, i.e., the low voltage line VGL, the first clock signal line CLK, the second clock signal line CLKB, and the high voltage line VGH may be provided sequentially along the first direction X. A third distance L3 may be provided between an edge of the first clock signal line CLK that is closer to the low voltage line VGL and an edge of the low voltage line VGL that is closer to the first clock signal line CLK, and a fourth distance L4 may be provided between an edge of the second clock signal line CLKB that is closer to the high voltage line VGH and an edge of the high voltage line VGH that is closer to the second clock signal line CLKB, the third distance L3 may be greater than the fourth distance L4, and the third distance L3 and the fourth distance L4 may be dimensions in the first direction X.

[0130] In an exemplary embodiment, in at least one repeat unit RU, the space between adjacent data signal lines DataI may have a first width D1, and at least one blank unit KB may have a second width D2, which may be larger than the first width D1, and the first width D1 and the second width D2 may be dimensions in the first direction X.

[0131] In an exemplary embodiment, at least one gate unit G may have a third width D3 between the first clock signal line CLK and the second clock signal line CLKB, the first width D1 may be greater than the third width D3, and the third width D3 may be a dimension in the first direction X.

[0132] 9 is a schematic diagram of the layout of gate units in an exemplary embodiment of the present disclosure. As shown in FIG. 9, in the exemplary embodiment, each gate circuit region may include one gate unit G, that is, the gate driving circuit in one gate unit G is connected to the driving signal line HL in one unit row via the output line OUT, and the gate unit G may be disposed in a central region of the display substrate.

[0133] In an exemplary embodiment, the gate drive circuit in one gate unit G is connected to the drive signal line HL in one unit row via the output line OUT, which means that the drive signal line in one unit row includes a scanning signal line and an emission signal line, one gate unit G includes a GOA circuit and an EOA circuit, the scanning signal line in one unit row is connected to one GOA circuit via a scanning output line, and the emission signal line in one unit row is connected to one EOA circuit via an emission output line.

[0134] In an exemplary embodiment, at least one gate driving circuit may be provided in a first midline region of the second circuit region 220, and the gate driving circuit may be connected to a first midpoint region of the driving signal line HL via an output line OUT. The second circuit region 220 may have a first midline, and the driving signal line HL may have a first midpoint. The first midline may be a straight line that equally divides the second circuit region 220 in the first direction X and extends along the second direction Y, and the first midpoint may be a point that equally divides the driving signal line HL in the first direction X. The first midline region may be a region that includes the first midline, and the width of the first midline region in the first direction X may be about 1% to 10% of the width of the display substrate. The first midpoint region may be a region that includes the first midpoint, and the width of the first midline region in the first direction X may be about 1% to 10% of the width of the display substrate, and the width of the display substrate may be the dimension of the display substrate in the first direction X.

[0135] Research has shown that when the gate unit G is installed on one side (e.g., the left side) of the display substrate, the row driving signals are transmitted from the left side of the display substrate (the tip of the driving signal line) to the right side of the display substrate (the tip of the driving signal line). If the transmission distance of the row driving signals is L, the RC delay at the tip of the driving signal line is equal to the RC delay of the entire length of the driving signal line. In the present disclosure, the gate unit G is installed in the central region of the display substrate. The row driving signals are transmitted from the central position of the display substrate (the tip of the driving signal line) to both sides of the display substrate (the tip of the driving signal line). The transmission distance of the row driving signals is L / 2. This reduces the RC delay at the tip of the driving signal line in this disclosure by half compared to the RC delay of the entire length of the driving signal line, thereby effectively reducing the RC delay and lengthening the charging time. Furthermore, installing the gate unit G in the central region of the display substrate avoids the wiring pads and anti-static circuits on both sides of the display substrate, effectively avoiding mutual interference between the gate driving circuit and the anti-static circuit.

[0136] 10 is a schematic diagram of another gate unit layout in an exemplary embodiment of the present disclosure. As shown in FIG. 10, in the exemplary embodiment, each gate circuit region may include two gate units G, that is, the gate driving circuits in the two gate units G are simultaneously connected to the driving signal lines HL in one unit row via output lines OUT, and the two gate units G may be respectively disposed in the 1 / 4 position region and the 3 / 4 position region of the display substrate.

[0137] In an exemplary embodiment, the gate drive circuits in two gate units G are connected to the drive signal lines in one unit row, meaning that one gate unit G includes a first gate drive circuit and the other gate unit G includes a second gate drive circuit, and the drive signal lines in one unit row are respectively connected to the first gate drive circuit and the second gate drive circuit via output lines.

[0138] In an exemplary embodiment, the first gate drive circuit may be provided in a second midline region of the second circuit region 220, and the first gate drive circuit is connected to the second midpoint region of the drive signal line HL via an output line, and the second gate drive circuit may be provided in a third midline region of the second circuit region 220, and the second gate drive circuit is connected to the third midpoint region of the drive signal line HL via an output line. The second circuit region 220 may have a first midline that equally divides the second circuit region 220 in the first direction X and extends along the second direction Y, and the first midline divides the second circuit region 220 into a first region and a second region. The second midline may be a straight line that equally divides the first region in the first direction X and extends along the second direction Y, and the third midline may be a straight line that equally divides the second region in the first direction X and extends along the second direction Y. The second midline region may be a region including the second midline, and the width of the second midline region in the first direction X may be about 1% to 10% of the width of the display substrate, and the third midline region may be a region including the third midline, and the width of the third midline region in the first direction X may be about 1% to 10% of the width of the display substrate. The drive signal line HL may have a point that equally divides the drive signal line HL in the first direction X, and the first midpoint may divide the drive signal line HL into a first line segment and a second line segment, the second midpoint may be a point that equally divides the first line segment in the first direction X, and the third midpoint may be a point that equally divides the second line segment in the first direction X. The second midpoint region may be a region that includes the second midpoint, and the width of the second midpoint region in the first direction X may be approximately 1% to 10% of the width of the display substrate. The third midpoint region may be a region that includes the third midpoint, and the width of the third midpoint region in the first direction X may be approximately 1% to 10% of the width of the display substrate.

[0139] In the present disclosure, two gate units G are installed in the 1 / 4 position region and the 3 / 4 position region of the display substrate, and the transmission distance of the row driving signal is L / 4, so that the RC delay at the end of the driving signal line can be reduced to 1 / 4 of the RC delay of the entire length of the driving signal line, thereby further reducing the RC delay and further extending the charging time.

[0140] 11 and 12 are schematic diagrams of the planar structure of a display substrate according to an exemplary embodiment of the present disclosure, in which Fig. 11 shows the planar structure of region A in Fig. 7 and Fig. 12 shows the planar structure of region B in Fig. 7, in which the circuit unit includes the pixel driving circuit shown in Fig. 4, and the gate unit includes the gate driving circuit shown in Fig. 6. As shown in Fig. 11 and 12, the first circuit region 210 may include a plurality of repeat units RU and a plurality of blank units KB, which may be alternately arranged along the first direction X. The second circuit region 220 may include at least one gate driving circuit. At least one repeat unit RU includes 12 circuit units forming two unit rows and six unit columns, and each unit row may include a first circuit unit Q1, a second circuit unit Q2, and a third circuit unit Q3 periodically arranged along a first direction X, wherein the first circuit unit Q1 may include at least a first pixel driving circuit, the second circuit unit Q2 may include at least a second pixel driving circuit, and the third circuit unit Q3 may include at least a third pixel driving circuit, wherein the first pixel driving circuit is configured to be connected to a red light emitting diode, the second pixel driving circuit is configured to be connected to a green light emitting diode, and the third pixel driving circuit is configured to be connected to a blue light emitting diode.

[0141] As shown in FIG. 11 , in an exemplary embodiment, the pixel driving circuit of at least one circuit unit may include at least a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a storage capacitor Cs, a first capacitor C1, and a second capacitor C2, and the pixel driving circuit may be respectively connected to a first scanning signal line S1, a second scanning signal line S2, an emission signal line EM, an initial signal line Vint, a data signal line DataI, and a high-frequency signal line Hf. The first scanning signal line S1, the second scanning signal line S2, the light-emitting signal line EM, and the initial signal line Vint may have a linear shape extending along a first direction X, and the data signal line DataI and the high-frequency signal line Hf may have a linear shape extending along a second direction Y. The pixel driving circuit is configured to receive a data voltage of the data signal line and an initial voltage of the initial signal line Vint under the control of the first scanning signal line S1, the second scanning signal line S2, the light-emitting signal line EM, and the high-frequency signal line Hf, and output a current of a duration corresponding to the connected light-emitting diode.

[0142] In an exemplary embodiment, at least one second circuit area 220 may have a reference line O1, which is a straight line that equally divides the second circuit area 220 in the second direction Y and extends along the first direction X. The pixel driving circuits in the first circuit areas 210 on either side of the second circuit area 220 in the second direction Y may be mirror-symmetric with respect to the reference line O1.

[0143] In an exemplary embodiment, the gate drive circuit may include a first transistor T21, a second transistor T22, a third transistor T23, a fourth transistor T24, a fifth transistor T25, a sixth transistor T26, a seventh transistor T27, a eighth transistor T28, a third capacitor C3, and a fourth capacitor C4, and the gate drive circuit may be connected to a first clock signal line CLK, a second clock signal line CLKB, a high voltage line VGH, and a low voltage line VGL, respectively. In an exemplary embodiment, one gate unit may include a first GOA circuit, a second GOA circuit, and an EOA circuit, and the first GOA circuit may be connected to a first scanning signal line S1 via an output line, the second GOA circuit may be connected to a second scanning signal line S2 via an output line, and the EOA circuit may be connected to an emission signal line EM via an output line. FIG. 12 only shows the structure of the second GOA circuit.

[0144] In an exemplary embodiment, the installation position of the gate driving circuit may basically correspond to the installation position of at least one blank unit KB in the first circuit area 210, and the orthogonal projection of the gate driving circuit on the reference line O1 at least partially overlaps with the orthogonal projection of the at least one blank unit KB on the reference line O1.

[0145] In an exemplary embodiment, the orthogonal projection of the gate driving circuit on the display substrate plane does not overlap with the orthogonal projection of the data signal line DataI on the display substrate plane.

[0146] In an exemplary embodiment, the first clock signal line CLK, the second clock signal line CLKB, the high voltage line VGH, and the low voltage line VGL may have a linear shape extending along the second direction Y and may be arranged sequentially along the first direction X.

[0147] In an exemplary embodiment, the orthogonal projections of the first clock signal line CLK and the second clock signal line CLKB onto the display substrate plane do not overlap with the orthogonal projections of the data signal line DataI onto the display substrate plane.

[0148] In an exemplary embodiment, the first clock signal line CLK may be essentially parallel to the data signal line DataI, and the second clock signal line CLKB may be essentially parallel to the data signal line DataI, or the orthogonal projection of the first clock signal line CLK on the display substrate plane may be essentially parallel to the orthogonal projection of the data signal line DataI on the display substrate plane, and the orthogonal projection of the second clock signal line CLKB on the display substrate plane may be essentially parallel to the orthogonal projection of the data signal line DataI on the display substrate plane.

[0149] In an exemplary embodiment, the orthogonal projections of the first clock signal line CLK and the second clock signal line CLKB onto the display substrate plane do not overlap with the orthogonal projections of the gate drive circuits onto the display substrate plane.

[0150] In an exemplary embodiment, the first clock signal line CLK and the second clock signal line CLKB may be disposed between the high voltage line VGH and the low voltage line VGL, whereby the high voltage line VGH and the low voltage line VGL transmitting constant voltage signals may act as a shield, and may effectively reduce the coupling capacitance between the clock signal line and the data signal line.

[0151] In an exemplary embodiment, a first distance L1 is present between the edge of the high voltage line VGH closer to the data signal line DataI and the edge of the data signal line DataI closer to the high voltage line VGH, and a second distance L2 is present between the edge of the low voltage line VGL closer to the data signal line DataI and the edge of the data signal line DataI closer to the low voltage line VGL, where the second distance L2 may be greater than the first distance L1, and the first distance L1 and the second distance L2 may be dimensions in the first direction X.

[0152] In an exemplary embodiment, the first distance L1 may be 25 μm or greater, and the second distance L2 may be 25 μm or greater.

[0153] In an exemplary embodiment, a third distance L3 is provided between the edge of the first clock signal line CLK closer to the low voltage line VGL and the edge of the low voltage line VGL closer to the first clock signal line CLK, and a fourth distance L4 is provided between the edge of the second clock signal line CLKB closer to the high voltage line VGH and the edge of the high voltage line VGH closer to the second clock signal line CLKB, and the third distance L3 may be greater than the fourth distance L4, and the third distance L3 and the fourth distance L4 may be dimensions in the first direction X.

[0154] 12, in an exemplary embodiment, the second circuit region 220 may further include at least one first mark MARK1 and at least one second mark MARK2. The first mark MARK1 may have a cross shape, and the second mark MARK2 may have a circular shape.

[0155] In an exemplary embodiment, the installation position of the first mark MARK1 in the second circuit area 220 may basically correspond to the installation position of the at least one blank unit KB in the first circuit area 210, and the orthogonal projection of the at least one first mark MARK1 on the reference line O1 at least partially overlaps with the orthogonal projection of the at least one blank unit KB on the reference line O1.

[0156] In an exemplary embodiment, the installation position of the second mark MARK2 in the second circuit area 220 may basically correspond to the installation position of the at least one blank unit KB in the first circuit area 210, and the orthogonal projection of the at least one second mark MARK2 on the reference line O1 at least partially overlaps with the orthogonal projection of the at least one blank unit KB on the reference line O1.

[0157] In an exemplary embodiment, the orthogonal projections of the first mark MARK1 and the second mark MARK2 onto the display substrate plane do not overlap with the orthogonal projections of the first scanning signal line S1, the second scanning signal line S2, the light emitting signal line EM, the high frequency signal line Hf, the initial signal line Vint, the data signal line DataI, the first clock signal line CLK, the second clock signal line CLKB, the high voltage line VGH, and the low voltage line VGL onto the display substrate plane.

[0158] In an exemplary embodiment, in a plane perpendicular to the display substrate, the display substrate may include a first gate metal layer, a second gate metal layer, a first source / drain metal layer, and a second source / drain metal layer sequentially disposed on a base, one electrode plate of a plurality of capacitors may be disposed on the first gate metal layer, the first scanning signal line S1, the second scanning signal line S2, the light emitting signal line EM, and the other electrode plates of the plurality of capacitors may be disposed on the second gate metal layer, the data signal line DataI, the high frequency signal line Hf, the first clock signal line CLK, the second clock signal line CLKB, the high voltage line VGH, and the low voltage line VGL may be disposed on the first source / drain metal layer, and the high voltage power line and the low voltage power line may be disposed on the second source / drain metal layer.

[0159] In an exemplary embodiment, the first mark MARK1 may be provided in a first source-drain metal layer, and the second mark MARK2 may be provided in a second source-drain metal layer.

[0160] In this disclosure, structure A extending along direction B means that structure A includes a main body portion and a secondary portion connected to the main body portion, the main body portion is elongated and extends along approximately one direction, the shape of the secondary portion is not limited, the main body portion accounts for at least 60% of structure A, the main body portion extends along direction B, and the size of the main body portion extending along direction B is larger than the size of the secondary portion extending along another direction. In the following description, "structure A extending along direction B" always means "the main body portion of structure A extends along direction B."

[0161] The manufacturing process of a display substrate is described below by way of example. The "patterning process" described in this disclosure includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping for metal, inorganic, or transparent conductive materials, and organic material coating, mask exposure, and development for organic materials. The deposition may be performed by one or more of sputtering, evaporation coating, and chemical vapor deposition. The coating may be performed by one or more of spray coating, spin coating, and inkjet printing. The etching may be performed by one or more of dry etching and wet etching. This disclosure is not limited thereto. A "thin film" refers to a thin film layer fabricated on a base material by deposition, coating, or other process. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be referred to as a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is referred to as a "thin film" before the patterning process and as a "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern." In the present disclosure, "A and B are disposed on the same layer" means that A and B are formed simultaneously by the same patterning process. The "thickness" of a film layer is the size of the film layer in a direction perpendicular to the display substrate. In an exemplary embodiment of the present disclosure, "the orthogonal projection of B is within the range of the orthogonal projection of A" or "the orthogonal projection of A includes the orthogonal projection of B" means that the boundary of the orthogonal projection of B is within the boundary range of the orthogonal projection of A, or the boundary of the orthogonal projection of A overlaps the boundary of the orthogonal projection of B.

[0162] In an exemplary embodiment, the manufacturing process for the display substrate may include the following operations.

[0163] (1) Forming a first conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 13, 14, and 15, forming the first conductive layer pattern may include depositing a first conductive thin film on a base and patterning the first conductive thin film by a patterning process to form a first conductive layer pattern disposed on the base. FIG. 13 is a structure of region A in FIG. 7, FIG. 14 is an enlarged view of one circuit unit in FIG. 13, and FIG. 15 is an enlarged view of one gate driving circuit in FIG. 13. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0164] As shown in Figures 13 and 14, in an exemplary embodiment, the first conductive layer pattern of each circuit unit may include at least a first electrode plate CF1, a second electrode plate CF2, a third electrode plate CF3, and a third bottom gate electrode Gate3-B.

[0165] In an exemplary embodiment, the first plate CF1, the second plate CF2, and the third plate CF3 may have a rectangular shape, and the corners of the rectangle may be chamfered. In the first direction X, the first plate CF1 may be disposed on the first direction X side of the second plate CF2. In the second direction Y, the first plate CF1 and the second plate CF2 may be disposed on the second direction Y side of the circuit unit, and the third plate CF3 may be disposed on the other side of the circuit unit in the second direction Y.

[0166] In an exemplary embodiment, the first electrode plate CF1 may be one electrode plate of a first capacitor in a pixel driving circuit, the second electrode plate CF2 may be one electrode plate of a second capacitor in a pixel driving circuit, and the third electrode plate CF3 may be one electrode plate of a storage capacitor in a pixel driving circuit, and the positions, shapes and sizes of the first electrode plate CF1, the second electrode plate CF2 and the third electrode plate CF3 in the first circuit unit Q1, the second circuit unit Q2 and the third circuit unit Q3 may be basically the same.

[0167] In an exemplary embodiment, a plate electrode connecting line is connected to the third plate CF3 on the first direction X side or the side opposite to the first direction X, and the shape of the plate electrode connecting line may be elongated and extending along the first direction X. A first end of the plate electrode connecting line is connected to the third plate CF3 of the present circuit unit, and a second end of the plate electrode connecting line extends along the first direction X or the direction opposite to the first direction X and is then connected to the third plate CF3 of the adjacent circuit unit, thereby connecting the third plates CF3 in one unit row.

[0168] In an exemplary embodiment, the third plates CF3 and the plate electrode connecting lines in one unit row may be connected to each other in an integrated structure. In the exemplary embodiment, the third plates CF3 in each circuit unit are connected to a high-voltage power supply line to be formed later, so that the third plates CF3 of adjacent circuit units are connected to each other in an integrated structure, and the integrated third plates CF3 can also be used as high-voltage power supply signal lines, ensuring that the third plates CF3 in one unit row have the same potential, contributing to improving the uniformity of the panel, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0169] In an exemplary embodiment, the third bottom gate electrode Gate3-B may be a bottom gate electrode of a third transistor (drive transistor). The third bottom gate electrode Gate3-B may have an L-shape, and may be located on a side of the third plate CF3 that is away from the first plate CF1 and the second plate CF2 in the second direction Y.

[0170] In an exemplary embodiment, the positions, shapes and sizes of the third bottom gate electrodes Gate3-B in the first circuit unit Q1, the second circuit unit Q2 and the third circuit unit Q3 may be basically the same.

[0171] In an exemplary embodiment, the first conductive layer patterns located on both sides of the second circuit area 220 in the second direction Y may be mirror-symmetric with respect to a reference line, and the reference line may be a straight line that equally divides the second circuit area 220 in the second direction Y and extends along the first direction X.

[0172] As shown in FIGS. 13 and 15, in an exemplary embodiment, the first conductive layer pattern of each gate drive circuit may include at least an eleventh plate CF11 and a twelfth plate CF12.

[0173] In an exemplary embodiment, the eleventh plate CF11 and the twelfth plate CF12 may have a rectangular shape, and the corners of the rectangle may be chamfered. The twelfth plate CF12 may be disposed on the first direction X side of the eleventh plate CF11. The eleventh plate CF11 may be one plate of a third capacitor in the gate drive circuit, and the twelfth plate CF12 may be one plate of a fourth capacitor in the gate drive circuit.

[0174] (2) Forming a semiconductor layer pattern. In an exemplary embodiment, as shown in Figures 16, 17, and 18, forming the semiconductor layer pattern may include sequentially depositing a first insulating thin film and a first semiconductor thin film on a base, and patterning the first semiconductor thin film by a patterning process to form a first insulating layer covering the first conductive layer and a semiconductor layer pattern provided on the first insulating layer. Figure 16 shows the structure of region A in Figure 7, Figure 17 is an enlarged view of one circuit unit in Figure 16, and Figure 18 is an enlarged view of one gate driving circuit in Figure 16.

[0175] As shown in FIGS. 16 and 17, in the exemplary embodiment, the semiconductor layer pattern of each circuit unit may include at least a first active layer AT1 to an eleventh active layer AT11.

[0176] In an exemplary embodiment, the first active layer AT1 may be the active layer of the first transistor T1, the second active layer AT2 may be the active layer of the second transistor T2, the third active layer AT3 may be the active layer of the third transistor T3, the fourth active layer AT4 may be the active layer of the fourth transistor T4, the fifth active layer AT5 may be the active layer of the fifth transistor T5, the sixth active layer AT6 may be the active layer of the sixth transistor T6, the seventh active layer AT7 may be the active layer of the seventh transistor T7, the eighth active layer AT8 may be the active layer of the eighth transistor T8, the ninth active layer AT9 may be the active layer of the ninth transistor T9, the tenth active layer AT10 may be the active layer of the tenth transistor T10, and the eleventh active layer AT11 may be the active layer of the eleventh transistor T11.

[0177] In an exemplary embodiment, the first active layer AT1, the second active layer AT2, the fourth active layer AT4, the seventh active layer AT7, the eighth active layer AT8, the ninth active layer AT9, and the tenth active layer AT10 may have an elongated shape extending along the first direction X, and the third active layer AT3, the fifth active layer AT5, the sixth active layer AT6, and the eleventh active layer AT11 may have a rectangular shape.

[0178] In an exemplary embodiment, the second active layer AT2 to the sixth active layer AT6 may be located on the side of the third electrode plate CF3 away from the first electrode plate CF1, and the first active layer AT1 and the seventh active layer AT7 to the eleventh active layer AT11 may be located between the first electrode plate CF1 and the third electrode plate CF3.

[0179] In an exemplary embodiment, the third active layer AT3 may be located on a side of the third electrode plate CF3 away from the first electrode plate CF1, and an orthogonal projection of the third active layer AT3 at a base thereof at least partially overlaps with an orthogonal projection of the third bottom gate electrode Gate3-B at a base thereof. The second active layer AT2 may be located on a side of the third active layer AT3 in the first direction X, and the fourth active layer AT4 may be located on an opposite side of the third active layer AT3 in the first direction X. The fifth active layer AT5 and the sixth active layer AT6 may be located between the third electrode plate CF3 and the third active layer AT3, and the sixth active layer AT6 may be located on a side of the fifth active layer AT5 in the first direction X.

[0180] In an exemplary embodiment, the tenth active layer AT10 may be located on a side of the first electrode plate CF1 that is closer to the third electrode plate CF3, the eighth active layer AT8 may be located on a side of the tenth active layer AT10 that is closer to the third electrode plate CF3, the eleventh active layer AT11 may be located on a side of the tenth active layer AT10 that is closer to the third electrode plate CF3, the first active layer AT1 and the seventh active layer AT7 may be located on the side of the eighth active layer AT8 in the first direction X, the first active layer AT1 and the seventh active layer AT7 may be an integral structure that is connected to each other, and the ninth active layer AT9 may be located on the side of the eleventh active layer AT11 in the first direction X.

[0181] In an exemplary embodiment, the width of the third active layer AT3 in the first circuit unit Q1 may be larger than the width of the third active layer AT3 in the second circuit unit Q2 and the third circuit unit Q3, and the width may be a dimension in the first direction X, so that the aspect ratio of the driving transistor (third transistor T3) in the first circuit unit Q1 is larger than the aspect ratio of the driving transistor in the second circuit unit Q2 and the third circuit unit Q3.

[0182] In an exemplary embodiment, the first active layer AT1 to the eleventh active layer AT11 may each include a first region, a second region, and a channel region located between the first and second regions, and the first and second regions of the multiple active layers may each be provided separately, and the first region of the first active layer AT1 and the first region of the seventh active layer AT7 may be connected to each other.

[0183] In an exemplary embodiment, the semiconductor layer patterns located on both sides of the second circuit region 220 in the second direction Y may be mirror-symmetric with respect to the reference line.

[0184] As shown in FIGS. 16 and 18, in the exemplary embodiment, the semiconductor layer pattern of each gate driving circuit may include at least a 21st active layer AT21 to a 28th active layer AT28.

[0185] In an exemplary embodiment, the twenty-first active layer AT21 may be the active layer of the twenty-first transistor T21, the twenty-second active layer AT22 may be the active layer of the twenty-second transistor T22, the twenty-third active layer AT23 may be the active layer of the twenty-third transistor T23, the twenty-fourth active layer AT24 may be the active layer of the twenty-fourth transistor T24, the twenty-fifth active layer AT25 may be the active layer of the twenty-fifth transistor T25, the twenty-sixth active layer AT26 may be the active layer of the twenty-sixth transistor T26, the twenty-seventh active layer AT27 may be the active layer of the twenty-seventh transistor T27, and the twenty-eighth active layer AT28 may be the active layer of the twenty-eighth transistor T28.

[0186] In an exemplary embodiment, the 21st active layer AT21, the 22nd active layer AT22, the 23rd active layer AT23, the 26th active layer AT26, the 27th active layer AT27, and the 28th active layer AT28 may have an elongated shape extending along the second direction Y, and the 24th active layer AT24 and the 25th active layer AT25 may have a parallel connection structure having multiple elongated shapes extending along the second direction Y.

[0187] In an exemplary embodiment, the 24th active layer AT24 may be located on the opposite side of the 11th electrode plate CF11 in the second direction Y, and the 25th active layer AT25 may be located on the side of the 11th electrode plate CF11 in the second direction Y. The 26th active layer AT26 and the 27th active layer AT27 may be an integral structure connected to each other and may be located on the side of the 12th electrode plate CF12 in the second direction Y, and the 21st active layer AT21 may be located on the side of the 27th active layer AT27 in the second direction Y. The 28th active layer AT28 may be located on the side of the 11th electrode plate CF11 in the first direction X, the 23rd active layer AT23 may be located on the side of the 28th active layer AT28 in the first direction X, and the 22nd active layer AT22 may be located on the side of the 23rd active layer AT23 in the first direction X.

[0188] In an exemplary embodiment, each of the 21st active layer AT21 to the 28th active layer AT28 may include a first region, a second region, and a channel region located between the first and second regions, and the first and second regions of the multiple active layers may be provided separately, and the second region of the 26th active layer AT26 and the first region of the 27th active layer AT27 may be connected to each other.

[0189] (3) Forming a second conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 19, 20, and 21, forming the second conductive layer pattern may include sequentially depositing a second insulating thin film and a second conductive thin film on the base on which the above-mentioned pattern is formed, and patterning the second conductive thin film by a patterning process to form a second insulating layer covering the semiconductor layer and a second conductive layer pattern provided on the second insulating layer. FIG. 19 shows the structure of region A in FIG. 7, FIG. 20 is an enlarged view of one circuit unit in FIG. 19, and FIG. 21 is an enlarged view of one gate driving circuit in FIG. 19. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0190] As shown in Figures 19 and 20, in an exemplary embodiment, the second conductive layer pattern of each circuit unit includes at least a fourth electrode plate CF4, a fifth electrode plate CF5, a sixth electrode plate CF6, a first scanning signal line S1, a second scanning signal line S2, an emission signal line EM, a second control line CT2, an initial signal line Vint, a high-frequency connecting line Hf-C, a high-voltage connecting line VDD-C, a low-voltage connecting line VSS-C, a plurality of gate electrodes and a plurality of connecting electrodes.

[0191] In an exemplary embodiment, the fourth plate CF4, the fifth plate CF5, and the sixth plate CF6 may have a rectangular shape with a notch at one corner. The orthogonal projection of the fourth plate CF4 at the base at least partially overlaps with the orthogonal projection of the first plate CF1 at the base, and the fourth plate CF4 may be the other plate of a first capacitor, and the first plate CF1 and the fourth plate CF4 form one first capacitor of the pixel driving circuit. The orthogonal projection of the fifth plate CF5 at the base at least partially overlaps with the orthogonal projection of the second plate CF2 at the base, and the fifth plate CF5 may be the other plate of a second capacitor, and the second plate CF2 and the fifth plate CF5 form one second capacitor of the pixel driving circuit. The orthogonal projection at the base of the sixth plate CF6 at least partially overlaps with the orthogonal projection at the base of the third plate CF3, and the sixth plate CF6 may be the other plate of a storage capacitor, and the third plate CF3 and the sixth plate CF6 constitute one storage capacitor of the pixel driving circuit.

[0192] In an exemplary embodiment, the positions, shapes and sizes of the fourth electrode plate CF4, the fifth electrode plate CF5 and the sixth electrode plate CF6 in the first circuit unit Q1, the second circuit unit Q2 and the third circuit unit Q3 may be essentially the same.

[0193] In an exemplary embodiment, the first scanning signal line S1, the second scanning signal line S2, the emission signal line EM, the second control line CT2, the initial signal line Vint, the high-frequency connecting line Hf-C, the high-voltage connecting line VDD-C, and the low-voltage connecting line VSS-C may have a linear or polygonal shape with their main bodies extending along the first direction X. The first scanning signal line S1 may be located on a side of the sixth plate CF6 away from the fourth plate CF4 and the fifth plate CF5, the high-frequency connecting line Hf-C and the low-voltage connecting line VSS-C may be located on a side of the fourth plate CF4 and the fifth plate CF5 away from the sixth plate CF6, and the second scanning signal line S2, the emission signal line EM, the second control line CT2, the initial signal line Vint, and the high-voltage connecting line VDD-C may be located between the fourth plate CF4 and the sixth plate CF6.

[0194] In an exemplary embodiment, the low-voltage connection line VSS-C may be located on the side of the fourth plate CF4 and the fifth plate CF5 away from the sixth plate CF6, and the high-frequency connection line Hf-C may be located on the side of the low-voltage connection line VSS-C away from the fourth plate CF4 and the fifth plate CF5.

[0195] In an exemplary embodiment, one of the first circuit areas 210 located on either side of the second circuit area 220 in the second direction Y may be provided with a high-frequency connecting line Hf-C, and the other first circuit area 210 may not be provided with a high-frequency connecting line Hf-C.

[0196] In an exemplary embodiment, one of the low-voltage connecting lines VSS-C located on both sides of the second circuit area 220 in the second direction Y may be provided with a bent portion, and the bent portion may be located in the area where the blank unit KB is located, and the bent portion is bent in a direction away from the second circuit area 220 to leave a corresponding space for the gate driving circuit.

[0197] In an exemplary embodiment, a plurality of connection bars may be provided on one side of the low-voltage connecting line VSS-C located on both sides of the second circuit area 220 in the second direction Y, with first ends of the plurality of connection bars connected to the low-voltage connecting line VSS-C and second ends of the plurality of connection bars extending along the second direction Y toward the second circuit area 220.

[0198] In an exemplary embodiment, the initial signal line Vint may be located on the side of the fourth plate CF4 and the fifth plate CF5 that is closer to the sixth plate CF6, the second control line CT2 may be located on the side of the initial signal line Vint that is closer to the sixth plate CF6, the second scanning signal line S2 may be located on the side of the second control line CT2 that is closer to the sixth plate CF6, the high voltage connecting line VDD-C may be located on the side of the second scanning signal line S2 that is closer to the sixth plate CF6, and the emission signal line EM may be located on the side of the high voltage connecting line VDD-C that is closer to the sixth plate CF6.

[0199] In an exemplary embodiment, the second scan signal line S2 may also be used as a first control line to control the turning on and off of the eighth transistor T8.

[0200] In an exemplary embodiment, the high-voltage connection line VDD-C is configured to be connected to a later-formed high-voltage power supply line to form a net-like interconnection structure, the low-voltage connection line VSS-C is configured to be connected to a later-formed low-voltage power supply line to form a net-like interconnection structure, and the high-frequency connection line Hf-C is configured to be connected to a later-formed high-frequency signal line to form a net-like interconnection structure.

[0201] In an exemplary embodiment, the multiple gate electrodes of each circuit unit may include at least a first gate electrode Gate1, a second gate electrode Gate2, a third top gate electrode Gate3-T, a fourth gate electrode Gate4, a fifth gate electrode Gate5, a sixth gate electrode Gate6, a seventh gate electrode Gate7, an eighth gate electrode Gate8, a ninth gate electrode Gate9, a tenth gate electrode Gate10 and an eleventh gate electrode Gate11.

[0202] In an exemplary embodiment, the second gate electrode Gate2 and the fourth gate electrode Gate4 may be disposed on a side of the first scanning signal line S1 closer to the sixth electrode plate CF6. The second gate electrode Gate2 is the gate electrode of the second transistor T2, and the orthogonal projection of the second gate electrode Gate2 at the base at least partially overlaps with the orthogonal projection of the base of the second active layer. The fourth gate electrode Gate4 is the gate electrode of the fourth transistor T4, and the orthogonal projection of the fourth gate electrode Gate4 at the base at least partially overlaps with the orthogonal projection of the base of the fourth active layer. In an exemplary embodiment, the first scanning signal line S1, the second gate electrode Gate2, and the fourth gate electrode Gate4 may be an integral structure connected to each other.

[0203] In an exemplary embodiment, the first gate electrode Gate1, the seventh gate electrode Gate7, and the eighth gate electrode Gate8 may be disposed on a side of the second scanning signal line S2 away from the initial signal line Vint. The first gate electrode Gate1 is the gate electrode of the first transistor T1, and the orthogonal projection of the first gate electrode Gate1 at the base at least partially overlaps with the orthogonal projection of the base of the first active layer. The seventh gate electrode Gate7 is the gate electrode of the seventh transistor T7, and the orthogonal projection of the seventh gate electrode Gate7 at the base at least partially overlaps with the orthogonal projection of the base of the seventh active layer. The eighth gate electrode Gate8 is the gate electrode of the eighth transistor T8, and the orthogonal projection of the eighth gate electrode Gate8 at the base at least partially overlaps with the orthogonal projection of the base of the eighth active layer. In an exemplary embodiment, the second scanning signal line S2, the first gate electrode Gate1, the seventh gate electrode Gate7, and the eighth gate electrode Gate8 may be an integral structure connected to each other.

[0204] In an exemplary embodiment, the tenth gate electrode Gate10 may be disposed on a side of the second control line CT2 closer to the initial signal line Vint. The tenth gate electrode Gate10 is the gate electrode of the tenth transistor T10, and the orthogonal projection of the tenth gate electrode Gate10 at the base at least partially overlaps with the orthogonal projection of the tenth active layer at the base. In an exemplary embodiment, the second control line CT2 and the tenth gate electrode Gate10 may be an integral structure connected to each other.

[0205] In an exemplary embodiment, the third top gate electrode Gate3-T may be a top gate electrode of the third transistor T3, wherein the orthogonal projection of the third top gate electrode Gate3-T at the base at least partially overlaps with the orthogonal projection of the third top gate electrode Gate3-T at the base of the third active layer, and the orthogonal projection of the third top gate electrode Gate3-T at the base at least partially overlaps with the orthogonal projection of the third bottom gate electrode Gate3-B at the base.

[0206] In an exemplary embodiment, the fifth gate electrode Gate5 may be a gate electrode of the fifth transistor T5, and the orthogonal projection of the fifth gate electrode Gate5 at the base at least partially overlaps with the orthogonal projection of the base of the fifth active layer. The fifth gate electrode Gate5 may be located between the emission signal line EM and the third top gate electrode Gate3-T, and the shape of the fifth gate electrode Gate5 may be comb-like.

[0207] In an exemplary embodiment, the sixth gate electrode Gate6 may be a gate electrode of the sixth transistor T6, and the orthogonal projection of the sixth gate electrode Gate6 at the base at least partially overlaps with the orthogonal projection of the base of the sixth active layer. The sixth gate electrode Gate6 may be located between the emission signal line EM and the third top gate electrode Gate3-T, and the sixth gate electrode Gate6 may have a comb-like shape.

[0208] In an exemplary embodiment, the ninth gate electrode Gate9 may be the gate electrode of the ninth transistor T9, and the orthogonal projection of the base of the ninth gate electrode Gate9 at least partially overlaps with the orthogonal projection of the base of the ninth active layer. The ninth gate electrode Gate9 may be located between the second scanning signal line S2 and the high-voltage connecting line VDD-C, and the shape of the ninth gate electrode Gate9 may be rectangular.

[0209] In an exemplary embodiment, the eleventh gate electrode Gate11 may be the gate electrode of the eleventh transistor T11, and the orthogonal projection of the base of the eleventh gate electrode Gate11 at least partially overlaps with the orthogonal projection of the base of the eleventh active layer. The eleventh gate electrode Gate11 may be located between the second scanning signal line S2 and the high-voltage connecting line VDD-C, and the shape of the eleventh gate electrode Gate11 may be elongated.

[0210] In an exemplary embodiment, the multiple connection electrodes of each circuit unit include at least a first connection electrode CO1, a second connection electrode CO2, a third connection electrode CO3, a fourth connection electrode CO4, a fifth connection electrode CO, a sixth connection electrode CO6, a seventh connection electrode CO7, and an eighth connection electrode CO8.

[0211] In an exemplary embodiment, the first connecting electrode CO1 may have an elongated shape extending along the first direction X and may be installed between the second scanning signal line S2 and the high-voltage connecting line VDD-C, and the first connecting electrode CO1 is configured to be connected to the high-frequency signal line Hf and the 24th connecting electrode to be formed later.

[0212] In an exemplary embodiment, the second connecting electrode CO2 may have an elongated shape extending along the first direction X and may be located between the second scanning signal line S2 and the high-voltage connecting line VDD-C, and the second connecting electrode CO2 is configured to be connected to the 22nd connecting electrode and the 23rd connecting electrode that will be formed later.

[0213] In an exemplary embodiment, the third connecting electrode CO3 may be rectangular in shape and may be located on the side of the second connecting electrode CO2 closer to the second scanning signal line S2, and the third connecting electrode CO3 is configured to be connected to the 25th connecting electrode to be formed later.

[0214] In an exemplary embodiment, the fourth connection electrode CO4 may have a polygonal line shape extending along the second direction Y and may be disposed on a side of the third top gate electrode Gate3-T closer to the sixth plate CF6, with a first end of the fourth connection electrode CO4 connected to the third top gate electrode Gate3-T and a second end of the fourth connection electrode CO4 connected to the sixth plate CF6. In an exemplary embodiment, the third top gate electrode Gate3-T, the sixth plate CF6, and the fourth connection electrode CO4 may be an integral structure connected to each other.

[0215] In an exemplary embodiment, the fifth connection electrode CO5 may have an elongated shape extending along the second direction Y and may be disposed on a side of the fifth gate electrode Gate5 that is closer to the light-emitting signal line EM, with a first end of the fifth connection electrode CO5 connected to the fifth gate electrode Gate5 and a second end of the fifth connection electrode CO5 connected to the light-emitting signal line EM, thereby realizing that the light-emitting signal line EM controls the turning on or off of the fifth transistor T5. In an exemplary embodiment, the light-emitting signal line EM, the fifth gate electrode Gate5, and the fifth connection electrode CO5 may be an integral structure that is connected to each other.

[0216] In an exemplary embodiment, the sixth connection electrode CO6 may have an elongated shape extending along the second direction Y, and may be located on the side of the sixth gate electrode Gate6 closer to the light-emitting signal line EM, with a first end of the sixth connection electrode CO6 connected to the sixth gate electrode Gate6 and a second end of the sixth connection electrode CO6 closer to the light-emitting signal line EM, and the sixth connection electrode CO6 connected to the 23rd connection electrode to be formed later.

[0217] In an exemplary embodiment, the seventh connecting electrode CO7 may have an elongated shape extending along the first direction X, and may be disposed between the second scanning signal line S2 and the high-voltage connecting line VDD-C, and the seventh connecting electrode CO7 and the ninth gate electrode Gate9 may be connected to form an integral structure.

[0218] In an exemplary embodiment, the eighth connecting electrode CO8 may have an elongated shape extending along the first direction X, and may be disposed between the second scanning signal line S2 and the high-voltage connecting line VDD-C, and the eighth connecting electrode CO8 and the eleventh gate electrode Gate11 may be connected to each other as an integral structure.

[0219] In an exemplary embodiment, some circuit units may further include a first anode connecting line 11, which is connected to an anode connecting block to be formed later.

[0220] In an exemplary embodiment, except for the low voltage connecting line VSS-C, the high frequency connecting line Hf-C and the first anode connecting line 11, the second conductive layer patterns located on both sides of the second circuit area 220 in the second direction Y may be basically mirror symmetrical with respect to the reference line.

[0221] As shown in FIGS. 19 and 21, in an exemplary embodiment, the second conductive layer pattern of each gate driving circuit may include at least a thirteenth electrode plate CF13, a fourteenth electrode plate CF14, an upper stage output signal line G(n-1), a main stage output signal line G(n), a plurality of gate electrodes, and a plurality of gate blocks.

[0222] In an exemplary embodiment, the thirteenth plate CF13 and the fourteenth plate CF14 may be rectangular in shape. An orthogonal projection of the thirteenth plate CF13 at the base at least partially overlaps with an orthogonal projection of the eleventh plate CF11 at the base, and the thirteenth plate CF13 may be the other plate of a third capacitor, and the eleventh plate CF11 and the thirteenth plate CF13 constitute the third capacitor of the gate drive circuit. An orthogonal projection of the fourteenth plate CF14 at the base at least partially overlaps with an orthogonal projection of the twelfth plate CF12 at the base, and the fourteenth plate CF14 may be the other plate of a fourth capacitor, and the twelfth plate CF12 and the fourteenth plate CF14 constitute the fourth capacitor of the gate drive circuit.

[0223] In an exemplary embodiment, the upper-stage output signal line G(n-1) and the main-stage output signal line G(n) may have a linear or polygonal shape with their main bodies extending along the first direction X. The upper-stage output signal line G(n-1) is configured to be connected to at least the first scanning signal line in the (n-1)th row, and the main-stage output signal line G(n) is configured to be connected to at least the first scanning signal line in the nth row. In the first direction X, the upper-stage output signal line G(n-1) may be located on the first direction X side of the fourteenth electrode plate CF14, and the main-stage output signal line G(n) may be located on the opposite side of the thirteenth electrode plate CF13 in the first direction X. In the second direction Y, the upper-stage output signal line G(n-1) and the main-stage output signal line G(n) may be located on the second direction Y side of the thirteenth electrode plate CF13 and the fourteenth electrode plate CF14.

[0224] In an exemplary embodiment, the multiple gate electrodes of the gate drive circuit may include a 21st gate electrode Gate21, a 22nd gate electrode Gate22, a 23rd gate electrode Gate23, a 24th gate electrode Gate24, a 25th gate electrode Gate25, a 26th gate electrode Gate26, a 27th gate electrode Gate27 and a 28th gate electrode Gate28.

[0225] In an exemplary embodiment, the 24th gate electrode Gate24 may be provided on the opposite side of the 14th electrode plate CF14 in the first direction X, the 24th gate electrode Gate24 being the gate electrode of the 24th transistor T24, and the orthogonal projection of the 24th gate electrode Gate24 at the base at least partially overlaps with the orthogonal projection of the 24th active layer at the base.

[0226] In an exemplary embodiment, the 24th gate electrode Gate24 may include a plurality of sub-electrodes, each of which may have an elongated shape extending along the first direction X, and the plurality of sub-electrodes may be spaced apart along the second direction Y to form a comb-like structure and connected to the 14th electrode plate CF14.

[0227] In an exemplary embodiment, the twenty-fourth gate electrode Gate24 and the fourteenth electrode plate CF14 may be an integral structure connected to each other.

[0228] In an exemplary embodiment, the 25th gate electrode Gate25 may be installed on the second direction Y side of the 13th electrode plate CF13, and the 25th gate electrode Gate25 is the gate electrode of the 25th transistor T25, and the orthogonal projection of the base of the 25th gate electrode Gate25 at least partially overlaps with the orthogonal projection of the base of the 25th active layer.

[0229] In an exemplary embodiment, the 25th gate electrode Gate25 may include a plurality of sub-electrodes, each of which may have an elongated shape extending along the first direction X, and the plurality of sub-electrodes may be spaced apart along the second direction Y to form a comb-like structure and connected to the 13th electrode plate CF13.

[0230] In an exemplary embodiment, the twenty-fifth gate electrode Gate25 and the thirteenth electrode plate CF13 may be an integral structure connected to each other.

[0231] In an exemplary embodiment, the 26th gate electrode Gate26 may be disposed on the second direction Y side of the 14th electrode plate CF14 and connected to the 14th electrode plate CF14. The 26th gate electrode Gate26 is the gate electrode of the 26th transistor T26, and the orthogonal projection of the 26th gate electrode Gate26 at the base at least partially overlaps with the orthogonal projection of the 26th active layer at the base.

[0232] In an exemplary embodiment, the twenty-fourth gate electrode Gate24, the twenty-sixth gate electrode Gate26, and the fourteenth electrode plate CF14 may be an integral structure connected to each other.

[0233] In an exemplary embodiment, the 27th gate electrode Gate27 may be installed on the second direction Y side of the 26th gate electrode Gate26, and the 27th gate electrode Gate27 serves as the gate electrode of the 27th transistor T27, and the orthogonal projection of the base of the 27th gate electrode Gate27 at least partially overlaps with the orthogonal projection of the base of the 27th active layer.

[0234] In an exemplary embodiment, the 22nd gate electrode Gate22 may be located on the second direction Y side of the 27th gate electrode Gate27, and the 22nd gate electrode Gate22 is the gate electrode of the 22nd transistor T22, and the orthogonal projection of the base of the 22nd gate electrode Gate22 at least partially overlaps with the orthogonal projection of the base of the 22nd active layer.

[0235] In an exemplary embodiment, the 21st gate electrode Gate21 and the 23rd gate electrode Gate23 may be disposed on the second direction Y side of the 22nd gate electrode Gate22 and may be an integral structure connected to each other. The 21st gate electrode Gate21 is the gate electrode of the 21st transistor T21, and the orthogonal projection of the 21st gate electrode Gate21 at the base at least partially overlaps with the orthogonal projection of the 21st gate electrode Gate21 at the base of the 21st active layer. The 23rd gate electrode Gate23 is the gate electrode of the 23rd transistor T23, and the orthogonal projection of the 23rd gate electrode Gate23 at the base at least partially overlaps with the orthogonal projection of the 23rd gate electrode Gate23 at the base of the 23rd active layer.

[0236] In an exemplary embodiment, the 28th gate electrode Gate28 may be installed on the second direction Y side of the 22nd gate electrode Gate22, the 28th gate electrode Gate28 is the gate electrode of the 28th transistor T28, and the orthogonal projection of the base of the 28th gate electrode Gate28 at least partially overlaps with the orthogonal projection of the base of the 28th active layer.

[0237] In an exemplary embodiment, the multiple gate blocks of the gate drive circuit may include a first gate block GK1, a second gate block GK2, a third gate block GK3, and a fourth gate block GK4.

[0238] In an exemplary embodiment, the first gate block GK1 may be rectangular in shape and may be located on the first direction X side of the 21st gate electrode Gate21, the first gate block GK1 and the 21st gate electrode Gate21 are an integral structure connected to each other, and the first gate block GK1 is configured to be connected to a first clock signal line to be formed later.

[0239] In an exemplary embodiment, the second gate block GK2 may be rectangular in shape and may be located on the first direction X side of the 27th gate electrode Gate27, the second gate block GK2 and the 27th gate electrode Gate27 are an integral structure connected to each other, and the second gate block GK2 is configured to be connected to a second clock signal line that will be formed later.

[0240] In an exemplary embodiment, the third gate block GK3 may have an elongated shape extending along the first direction X and may be installed on the first direction X side of the fourteenth electrode plate CF14, and the third gate block GK3 is configured to be connected to a high voltage line to be formed later.

[0241] In an exemplary embodiment, the fourth gate block GK4 may be rectangular in shape and may be located on the first direction X side of the 28th gate electrode Gate28, the fourth gate block GK4 and the 28th gate electrode Gate28 are an integral structure connected to each other, and the fourth gate block GK4 is configured to be connected to a low voltage line that will be formed later.

[0242] In an exemplary embodiment, after forming the second conductive layer pattern, the semiconductor layer can be made conductive by using the second conductive layer as a shield. The semiconductor layer in the region blocked by the second conductive layer forms the channel regions of the first transistor T1 through the twelfth transistor T12. The semiconductor layer in the region not blocked by the first conductive layer is made conductive, i.e., the first and second regions of the first transistor T1 through the eleventh transistor T11 and the twenty-first transistor T2 through the twenty-eighth transistor T28 are all made conductive.

[0243] (4) Forming a third insulating layer pattern. In an exemplary embodiment, as shown in Figures 22, 23, and 24, forming the third insulating layer pattern may include depositing a third insulating thin film on the base on which the above-mentioned pattern is formed, and patterning the third insulating thin film by a patterning process to form a third insulating layer covering the second conductive layer, and providing a plurality of vias in the third insulating layer. Figure 22 shows the structure of region A in Figure 7, Figure 23 is an enlarged view of one circuit unit in Figure 22, and Figure 24 is an enlarged view of one gate driving circuit in Figure 22.

[0244] As shown in FIGS. 22 and 23, in the exemplary embodiment, the plurality of vias in each circuit unit include at least an eleventh via V11 to a fifty-fourth via V54.

[0245] In an exemplary embodiment, the orthogonal projection at the base of the 11th via V11 is located within the range of the orthogonal projection at the base of the first region of the first active layer, the third insulating layer and the second insulating layer within the 11th via V11 are etched to expose the surface of the first region of the first active layer, and the 11th via V11 is configured to connect the 11th connection electrode to be formed later through the via.

[0246] In an exemplary embodiment, the orthogonal projection at the base of the 12th via V12 is located within the range of the orthogonal projection at the base of the second region of the first active layer, the third insulating layer and the second insulating layer within the 12th via V12 are etched to expose the surface of the second region of the first active layer, and the 12th via V12 is configured to connect a later-formed 14th connection electrode to the second region of the first active layer through the via.

[0247] In an exemplary embodiment, the orthogonal projection at the base of the 13th via V13 is located within the range of the orthogonal projection at the base of the first region of the second active layer, the third insulating layer and the second insulating layer within the 13th via V13 are etched to expose the surface of the first region of the second active layer, and the 13th via V13 is configured to connect a later-formed 15th connection electrode through the via to the first region of the second active layer.

[0248] In an exemplary embodiment, the orthogonal projection at the base of the 14th via V14 is located within the range of the orthogonal projection at the base of the second region of the second active layer, the third insulating layer and the second insulating layer within the 14th via V14 are etched to expose the surface of the second region of the second active layer, and the 14th via V14 is configured to connect a later-formed 16th connection electrode through the via to the second region of the second active layer.

[0249] In an exemplary embodiment, the orthogonal projection at the base of the 15th via V15 is located within the range of the orthogonal projection at the base of the first region of the third active layer, the third insulating layer and the second insulating layer within the 15th via V15 are etched to expose the surface of the first region of the third active layer, and the 15th via V15 is configured to connect a later-formed 17th connection electrode through the via to the first region of the third active layer.

[0250] In an exemplary embodiment, the orthogonal projection at the base of the 16th via V16 is located within the range of the orthogonal projection at the base of the second region of the third active layer, the third insulating layer and the second insulating layer within the 16th via V16 are etched to expose the surface of the second region of the third active layer, and the 16th via V16 is configured to connect a later-formed 16th connection electrode through the via to the second region of the third active layer.

[0251] In an exemplary embodiment, the orthogonal projection at the base of the 17th via V17 is located within the range of the orthogonal projection at the base of the first region of the fourth active layer, the third insulating layer and the second insulating layer within the 17th via V17 are etched to expose the surface of the first region of the fourth active layer, and the 17th via V17 is configured to connect a data signal line to be formed later through the via to the first region of the fourth active layer.

[0252] In an exemplary embodiment, the orthogonal projection at the base of the 18th via V18 is located within the range of the orthogonal projection at the base of the second region of the fourth active layer, the third insulating layer and the second insulating layer within the 18th via V18 are etched to expose the surface of the second region of the fourth active layer, and the 18th via V18 is configured to connect a later-formed 17th connection electrode through the via to the second region of the fourth active layer.

[0253] In an exemplary embodiment, the orthogonal projection at the base of the 19th via V19 is located within the range of the orthogonal projection at the base of the first region of the fifth active layer, the third insulating layer and the second insulating layer within the 19th via V19 are etched to expose the surface of the first region of the fifth active layer, and the 19th via V19 is configured to connect a later-formed 18th connection electrode through the via to the first region of the fifth active layer.

[0254] In an exemplary embodiment, the orthogonal projection at the base of the 20th via V20 is located within the range of the orthogonal projection at the base of the second region of the fifth active layer, the third insulating layer and the second insulating layer within the 20th via V20 are etched to expose the surface of the second region of the fifth active layer, and the 20th via V20 is configured to connect a later-formed 17th connection electrode through the via to the second region of the fifth active layer.

[0255] In the exemplary embodiment, the nineteenth vias V19 and the twentieth vias V20 are both plural, and the plural nineteenth vias V19 and the plural twentieth vias V20 are alternately arranged in the second direction Y.

[0256] In an exemplary embodiment, the orthogonal projection at the base of the 21st via V21 is located within the range of the orthogonal projection at the base of the first region of the sixth active layer, the third insulating layer and the second insulating layer within the 21st via V21 are etched to expose the surface of the first region of the sixth active layer, and the 20th via V20 is configured to connect a later-formed 16th connection electrode through the via to the first region of the sixth active layer.

[0257] In an exemplary embodiment, the orthogonal projection at the base of the 22nd via V22 is located within the range of the orthogonal projection at the base of the second region of the sixth active layer, the third insulating layer and the second insulating layer within the 22nd via V22 are etched to expose the surface of the second region of the sixth active layer, and the 22nd via V22 is configured to connect a later-formed 26th connection electrode through the via to the second region of the sixth active layer.

[0258] In the exemplary embodiment, there are a plurality of the 21st vias V21 and a plurality of the 22nd vias V22, and the plurality of the 21st vias V21 and the plurality of the 22nd vias V22 are arranged alternately in the second direction Y.

[0259] In the exemplary embodiment, the orthogonal projection of the base of the via V23 is located within the range of the orthogonal projection of the base of the first region of the seventh active layer, the third insulating layer and the second insulating layer in the via V23 are etched to expose the surface of the seventh region of the seventh active layer, and the via V23 is configured to connect the eleventh connecting electrode to be formed later to the first region of the seventh active layer through the via. Because the first region of the first active layer and the first region of the seventh active layer are connected to each other, the via V11 and the via V23 are a common via.

[0260] In an exemplary embodiment, the orthogonal projection at the base of the 24th via V24 is located within the range of the orthogonal projection at the base of the second region of the seventh active layer, the third insulating layer and the second insulating layer within the 24th via V24 are etched to expose the surface of the second region of the seventh active layer, and the 24th via V24 is configured to connect a later-formed 26th connection electrode through the via to the second region of the seventh active layer.

[0261] In an exemplary embodiment, the orthogonal projection at the base of the 25th via V25 is located within the range of the orthogonal projection at the base of the first region of the eighth active layer, the third insulating layer and the second insulating layer in the 25th via V25 are etched to expose the surface of the 9th region of the eighth active layer, and the 25th via V25 is configured to connect a data signal line to be formed later through the via to the first region of the eighth active layer.

[0262] In an exemplary embodiment, the orthogonal projection at the base of the 26th via V26 is located within the range of the orthogonal projection at the base of the second region of the eighth active layer, the third insulating layer and the second insulating layer within the 26th via V26 are etched to expose the surface of the second region of the eighth active layer, and the 26th via V26 is configured to connect the later-formed 20th connection electrode through the via to the second region of the eighth active layer.

[0263] In an exemplary embodiment, the orthogonal projection at the base of the 27th via V27 is located within the range of the orthogonal projection at the base of the first region of the 9th active layer, the third insulating layer and the second insulating layer within the 27th via V27 are etched to expose the surface of the first region of the 9th active layer, and the 27th via V27 is configured to connect the later-formed 25th connection electrode through the via to the first region of the 9th active layer.

[0264] In an exemplary embodiment, the orthogonal projection at the base of the 28th via V28 is located within the range of the orthogonal projection at the base of the second region of the 9th active layer, the third insulating layer and the second insulating layer within the 28th via V28 are etched to expose the surface of the second region of the 9th active layer, and the 28th via V28 is configured to connect a later-formed 22nd connection electrode through the via to the second region of the 9th active layer.

[0265] In an exemplary embodiment, the orthogonal projection at the base of the 29th via V29 is located within the range of the orthogonal projection at the base of the first region of the 10th active layer, the third insulating layer and the second insulating layer within the 29th via V29 are etched to expose the surface of the first region of the 10th active layer, and the 29th via V29 is configured to connect a later-formed data signal line to the first region of the 10th active layer through the via.

[0266] In an exemplary embodiment, the orthogonal projection at the base of the 30th via V30 is located within the range of the orthogonal projection at the base of the second region of the 10th active layer, the third insulating layer and the second insulating layer within the 30th via V30 are etched to expose the surface of the second region of the 10th active layer, and the 30th via V30 is configured to connect a later-formed 21st connection electrode through the via to the second region of the 10th active layer.

[0267] In an exemplary embodiment, the orthogonal projection at the base of the 31st via V31 is located within the range of the orthogonal projection at the base of the first region of the 11th active layer, the third insulating layer and the second insulating layer within the 31st via V31 are etched to expose the surface of the first region of the 11th active layer, and the 31st via V31 is configured to connect a later-formed 24th connection electrode through the via to the first region of the 11th active layer.

[0268] In an exemplary embodiment, the orthogonal projection at the base of the 32 via V32 is located within the range of the orthogonal projection at the base of the second region of the 11th active layer, the third insulating layer and the second insulating layer within the 32 via V32 are etched to expose the surface of the second region of the 11th active layer, and the 32 via V32 is configured to connect a later-formed 22nd connection electrode through the via to the second region of the 11th active layer.

[0269] In an exemplary embodiment, the orthogonal projection at the base of the 33rd via V33 is located within the range of the orthogonal projection at the base of the first electrode plate CF1, the third insulating layer, the second insulating layer and the first insulating layer within the 33rd via V33 are etched to expose the surface of the first electrode plate CF1, and the 33rd via V33 is configured to connect a later-formed seventh electrode plate to the first electrode plate CF1 through the via.

[0270] In an exemplary embodiment, the orthogonal projection at the base of the 34th via V34 is located within the range of the orthogonal projection at the base of the second electrode plate CF2, the third insulating layer, the second insulating layer and the first insulating layer within the 34th via V34 are etched to expose the surface of the second electrode plate CF2, and the 34th via V34 is configured to connect a later-formed eighth electrode plate to the second electrode plate CF2 through the via.

[0271] In an exemplary embodiment, the orthogonal projection at the base of the 35th via V35 is located within the range of the orthogonal projection at the base of the third electrode plate CF3, the third insulating layer, the second insulating layer, and the first insulating layer in the 35th via V35 are etched to expose the surface of the third electrode plate CF3, and the 35th via V35 is configured to connect a later-formed ninth electrode plate to the third electrode plate CF3 through the via.

[0272] In an exemplary embodiment, the orthogonal projection at the base of the 36th via V36 is located within the range of the orthogonal projection at the base of the fourth electrode plate CF4, the third insulating layer in the 36th via V36 is etched to expose the surface of the fourth electrode plate CF4, and the 36th via V36 is configured to connect the later-formed 19th connection electrode to the fourth electrode plate CF4 through the via.

[0273] In an exemplary embodiment, the orthogonal projection at the base of the 37th via V37 is located within the range of the orthogonal projection at the base of the fifth electrode plate CF5, the third insulating layer in the 37th via V37 is etched to expose the surface of the fifth electrode plate CF5, and the 37th via V37 is configured to connect the later-formed 21st connection electrode to the fifth electrode plate CF5 through the via.

[0274] In the exemplary embodiment, the orthogonal projection at the base of the 38th via V38 is located within the range of the orthogonal projection at the base of the sixth electrode plate CF6, the third insulating layer in the 38th via V38 is etched to expose the surface of the sixth electrode plate CF6, and the 38th via V38 is configured to connect to the 14th connection electrode to be formed later and the sixth electrode plate CF6.

[0275] In an exemplary embodiment, the orthogonal projection at the base of the 39th via V39 is located within the range of the orthogonal projection at the base of the high-voltage connection line VDD-C, the third insulating layer in the 39th via V39 is etched to expose the surface of the high-voltage connection line VDD-C, and the 39th via V39 is configured to connect a later-formed 13th connection electrode to the high-voltage connection line VDD-C through the via.

[0276] In an exemplary embodiment, the orthogonal projection at the base of the 40th via V40 is located within the range of the orthogonal projection at the base of the high-frequency connection line Hf-C, the third insulating layer in the 40th via V40 is etched to expose the surface of the high-frequency connection line Hf-C, and the 40th via V40 is configured to connect a later-formed high-frequency signal line to the high-frequency connection line Hf-C through the via.

[0277] In an exemplary embodiment, the orthogonal projection at the base of the 41st via V41 is located within the range of the orthogonal projection at the base of the light-emitting signal line EM, the third insulating layer in the 41st via V41 is etched to expose the surface of the light-emitting signal line EM, and the 41st via V41 is configured to connect the 25th connection electrode to be formed later to the light-emitting signal line EM through the via.

[0278] In an exemplary embodiment, the orthogonal projections at the bases of the 42nd via V42 and the 43rd via V43 are each located within the range of the orthogonal projection at the base of the initial signal line Vint, the third insulating layer in the 42nd via V42 and the 43rd via V43 is etched to expose the surface of the initial signal line Vint, and the 42nd via V42 and the 43rd via V43 are configured to connect the 11th and 12th connection electrodes to be formed later to the initial signal line Vint, respectively, through the vias.

[0279] In an exemplary embodiment, the orthogonal projection at the base of the 44th via V44 is located within the range of the orthogonal projection at the base of the first end of the first connection electrode CO1, the third insulating layer in the 44th via V44 is etched to expose the surface of the first end of the first connection electrode CO1, and the 44th via V44 is configured to connect a later-formed high-frequency connection line to the first connection electrode CO1 through the via.

[0280] In an exemplary embodiment, the orthogonal projection at the base of the 45th via V45 is located within the range of the orthogonal projection at the base of the second end of the first connection electrode CO1, the third insulating layer in the 45th via V45 is etched to expose the surface of the second end of the first connection electrode CO1, and the 45th via V45 is configured to connect the later-formed 24th connection electrode through the via to the second end of the first connection electrode CO1.

[0281] In an exemplary embodiment, the orthogonal projection at the base of the 46th via V46 is located within the range of the orthogonal projection at the base of the first end of the second connection electrode CO2, the third insulating layer within the 46th via V46 is etched to expose the surface of the first end of the second connection electrode CO2, and the 46th via V46 is configured to connect a later-formed 22nd connection electrode through the via to the first end of the second connection electrode CO2.

[0282] In an exemplary embodiment, the orthogonal projection at the base of the 47th via V47 is located within the range of the orthogonal projection at the base of the second end of the second connection electrode CO2, the third insulating layer in the 47th via V47 is etched to expose the surface of the second end of the second connection electrode CO2, and the 47th via V47 is configured to connect a later-formed 23rd connection electrode through the via to the second end of the second connection electrode CO2.

[0283] In an exemplary embodiment, the orthogonal projection at the base of the 48th via V48 is located within the range of the orthogonal projection at the base of the third connection electrode CO3, the third insulating layer within the 48th via V48 is etched to expose the surface of the third connection electrode CO3, and the 48th via V48 is configured to connect the later-formed 25th connection electrode to the third connection electrode CO3 through the via.

[0284] In an exemplary embodiment, the orthogonal projection at the base of the 49th via V49 is located within the range of the orthogonal projection at the base of the fourth connection electrode CO4, the third insulating layer within the 49th via V49 is etched to expose the surface of the fourth connection electrode CO4, and the 49th via V49 is configured to connect the later-formed 15th connection electrode to the fourth connection electrode CO4 through the via.

[0285] In an exemplary embodiment, the orthogonal projection at the base of the 50th via V50 is located within the range of the orthogonal projection at the base of the third bottom gate electrode Gate3-B, the third insulating layer, the second insulating layer and the first insulating layer in the 50th via V50 are etched to expose the surface of the third bottom gate electrode Gate3-B, and the 50th via V50 is configured to connect a later-formed 15th connection electrode to the third bottom gate electrode Gate3-B through the via.

[0286] In an exemplary embodiment, the orthogonal projection at the base of the 51st via V51 is located within the range of the orthogonal projection at the base of the 6th connection electrode CO6, the third insulating layer in the 51st via V51 is etched to expose the surface of the 6th connection electrode CO6, and the 51st via V51 is configured to connect the 23rd connection electrode to be formed later to the 6th connection electrode CO6 through the via.

[0287] In an exemplary embodiment, the orthogonal projection at the base of the 52nd via V52 is located within the range of the orthogonal projection at the base of the first end of the seventh connecting electrode CO7, the third insulating layer in the 52nd via V52 is etched to expose the surface of the first end of the seventh connecting electrode CO7, and the 52nd via V52 is configured to connect the later-formed 20th connecting electrode through the via to the first end of the seventh connecting electrode CO7.

[0288] In an exemplary embodiment, the orthogonal projection at the base of the 53rd via V53 is located within the range of the orthogonal projection at the base of the second end of the seventh connecting electrode CO7, the third insulating layer in the 53rd via V53 is etched to expose the surface of the second end of the seventh connecting electrode CO7, and the 53rd via V53 is configured to connect the later-formed 19th connecting electrode through the via to the second end of the seventh connecting electrode CO7.

[0289] In an exemplary embodiment, the orthogonal projection at the base of the 54th via V54 is located within the range of the orthogonal projection at the base of the 8th connection electrode CO8, the third insulating layer within the 54th via V54 is etched to expose the surface of the 8th connection electrode CO8, and the 54th via V54 is configured to connect the 21st connection electrode to be formed later to the 8th connection electrode CO8 through the via.

[0290] In an exemplary embodiment, some circuit units may further include a 55th via V55. The orthogonal projection of the base of the 55th via V55 is located within the range of the orthogonal projection of the base of the low-voltage connecting line VSS-C, the third insulating layer in the 55th via V55 is etched to expose the surface of the low-voltage connecting line VSS-C, and the 55th via V55 is configured to connect a 27th connecting electrode to be formed later to the low-voltage connecting line VSS-C through the via.

[0291] In an exemplary embodiment, some circuit units may further include a plurality of connection line vias, which may be installed at both ends of the first anode connection line 11, and the connection line vias 11 are configured to connect the anode connection block to be formed later to the first anode connection line 11 through the vias.

[0292] In an exemplary embodiment, the first scanning signal line S1, the second scanning signal line S2 and the light-emitting signal line EM located in the blank unit area are further provided with gate line vias (not shown), and the gate line vias are configured to be connected to corresponding output signal lines that will be formed later.

[0293] As shown in FIGS. 22 and 24, in an exemplary embodiment, the plurality of vias of each gate drive circuit may include at least a 61st via V61 to a 90th via V90.

[0294] In an exemplary embodiment, the orthogonal projection at the base of the 61st via V61 is located within the range of the orthogonal projection at the base of the first region of the 21st active layer, the third insulating layer and the second insulating layer within the 61st via V61 are etched to expose the surface of the first region of the 21st active layer, and the 61st via V61 is configured to connect a later-formed 31st connection electrode through the via to the first region of the 21st active layer.

[0295] In an exemplary embodiment, the orthogonal projection at the base of the 62nd via V62 is located within the range of the orthogonal projection at the base of the second region of the 21st active layer, the third insulating layer and the second insulating layer within the 62nd via V62 are etched to expose the surface of the second region of the 21st active layer, and the 62nd via V62 is configured to connect a later-formed 32nd connection electrode through the via to the second region of the 21st active layer.

[0296] In an exemplary embodiment, the orthogonal projection at the base of the 63rd via V63 is located within the range of the orthogonal projection at the base of the first region of the 22nd active layer, the third insulating layer and the second insulating layer within the 63rd via V63 are etched to expose the surface of the first region of the 22nd active layer, and the 63rd via V63 is configured to connect a later-formed 33rd connection electrode through the via to the first region of the 22nd active layer.

[0297] In an exemplary embodiment, the orthogonal projection at the base of the 64th via V64 is located within the range of the orthogonal projection at the base of the second region of the 22nd active layer, the third insulating layer and the second insulating layer within the 64th via V64 are etched to expose the surface of the second region of the 22nd active layer, and the 64th via V64 is configured to connect a later-formed 34th connection electrode through the via to the second region of the 22nd active layer.

[0298] In an exemplary embodiment, the orthogonal projection at the base of the 65th via V65 is located within the range of the orthogonal projection at the base of the first region of the 23rd active layer, the third insulating layer and the second insulating layer within the 65th via V65 are etched to expose the surface of the first region of the 23rd active layer, and the 65th via V65 is configured to connect a later-formed low-voltage line through the via to the first region of the 23rd active layer.

[0299] In an exemplary embodiment, the orthogonal projection at the base of the 66th via V66 is located within the range of the orthogonal projection at the base of the second region of the 23rd active layer, the third insulating layer and the second insulating layer within the 66th via V66 are etched to expose the surface of the second region of the 23rd active layer, and the 66th via V66 is configured to connect the later-formed 34th connection electrode through the via.

[0300] In an exemplary embodiment, the orthogonal projection at the base of the 67th via V67 is located within the range of the orthogonal projection at the base of the first region of the 24th active layer, and the third insulating layer and the second insulating layer within the 67th via V67 are etched to expose the surface of the first region of the 24th active layer and are configured to connect the later-formed 37th connection electrode to the first region of the 24th active layer through the via.

[0301] In an exemplary embodiment, the orthogonal projection at the base of the 68th via V68 is located within the range of the orthogonal projection at the base of the second region of the 24th active layer, the third insulating layer and the second insulating layer within the 68th via V68 are etched to expose the surface of the second region of the 24th active layer, and the 68th via V68 is configured to connect the later-formed 38th connection electrode through the via.

[0302] In an exemplary embodiment, the orthogonal projection at the base of the 69th via V69 is located within the range of the orthogonal projection at the base of the first region of the 25th active layer, the third insulating layer and the second insulating layer within the 69th via V69 are etched to expose the surface of the first region of the 25th active layer, and the 69th via V69 is configured to connect the later-formed 39th connection electrode through the via to the first region of the 25th active layer.

[0303] In an exemplary embodiment, the orthogonal projection at the base of the 70th via V70 is located within the range of the orthogonal projection at the base of the second region of the 25th active layer, the third insulating layer and the second insulating layer within the 70th via V70 are etched to expose the surface of the second region of the 25th active layer, and the 70th via V70 is configured to connect the later-formed 38th connection electrode through the via to the second region of the 25th active layer.

[0304] In an exemplary embodiment, the orthogonal projection at the base of the 71st via V71 is located within the range of the orthogonal projection at the base of the first region of the 26th active layer, the third insulating layer and the second insulating layer within the 71st via V71 are etched to expose the surface of the first region of the 26th active layer, and the 71st via V71 is configured to connect the later-formed 35th connection electrode through the via to the first region of the 26th active layer.

[0305] In an exemplary embodiment, the orthogonal projection at the base of the 72nd via V72 is located within the range of the orthogonal projection at the base of the second region of the 26th active layer, the third insulating layer and the second insulating layer within the 72nd via V72 are etched to expose the surface of the second region of the 26th active layer, and the 72nd via V72 is configured to connect the later-formed 36th connection electrode through the via to the second region of the 26th active layer.

[0306] In an exemplary embodiment, the orthogonal projection of the via V73 at the base is located within the range of the orthogonal projection of the base of the first region of the 27th active layer, the third insulating layer and the second insulating layer in the via V73 are etched to expose the surface of the first region of the 27th active layer, and the via V73 is configured to connect the 36th connecting electrode to be formed later to the first region of the 27th active layer through the via. Since the second region of the 26th active layer and the first region of the 27th active layer are connected to each other, the via V72 and the via V73 are common.

[0307] In an exemplary embodiment, the orthogonal projection at the base of the 74th via V74 is located within the range of the orthogonal projection at the base of the second region of the 27th active layer, the third insulating layer and the second insulating layer within the 74th via V74 are etched to expose the surface of the second region of the 27th active layer, and the 74th via V74 is configured to connect a later-formed 32nd connection electrode through the via to the second region of the 27th active layer.

[0308] In an exemplary embodiment, the orthogonal projection at the base of the 75th via V75 is located within the range of the orthogonal projection at the base of the first region of the 28th active layer, the third insulating layer and the second insulating layer within the 75th via V75 are etched to expose the surface of the first region of the 28th active layer, and the 75th via V75 is configured to connect the later-formed 40th connection electrode CO40 to the first region of the 28th active layer through the via.

[0309] In an exemplary embodiment, the orthogonal projection at the base of the 76th via V76 is located within the range of the orthogonal projection at the base of the second region of the 28th active layer, the third insulating layer and the second insulating layer within the 76th via V76 are etched to expose the surface of the second region of the 28th active layer, and the 76th via V76 is configured to connect the later-formed 41st connection electrode through the via.

[0310] In an exemplary embodiment, the orthogonal projection at the base of the 77th via V77 is located within the range of the orthogonal projection at the base of the 22nd gate electrode Gate22, the third insulating layer in the 77th via V77 is etched to expose the surface of the 22nd gate electrode Gate22, and the 77th via V77 is configured to connect the 40th connection electrode to be formed later to the 22nd gate electrode Gate22 through the via.

[0311] In an exemplary embodiment, the orthogonal projection at the base of the 78th via V78 is located within the range of the orthogonal projection at the base of the 23rd gate electrode Gate23, the third insulating layer in the 78th via V78 is etched to expose the surface of the 23rd gate electrode Gate23, and the 78th via V78 is configured to connect the 33rd connection electrode to be formed later to the 23rd gate electrode Gate23 through the via.

[0312] In an exemplary embodiment, the orthogonal projection at the base of the 79th via V79 is located within the range of the orthogonal projection at the base of the 25th gate electrode Gate25, the third insulating layer in the 79th via V79 is etched to expose the surface of the 25th gate electrode Gate25, and the 79th via V79 is configured to connect the 41st connection electrode to be formed later to the 25th gate electrode Gate25 through the via.

[0313] In an exemplary embodiment, the orthogonal projection at the base of the 80th via V80 is located within the range of the orthogonal projection at the base of the 26th gate electrode Gate26, the third insulating layer in the 80th via V80 is etched to expose the surface of the 26th gate electrode Gate26, and the 80th via V80 is configured to connect the 34th connection electrode to be formed later to the 26th gate electrode Gate26 through the via.

[0314] In an exemplary embodiment, the orthogonal projection at the base of the 81st via V81 is located within the range of the orthogonal projection at the base of the 27th gate electrode Gate27, the third insulating layer in the 81st via V81 is etched to expose the surface of the 27th gate electrode Gate27, and the 81st via V81 is configured to connect the 39th connection electrode to be formed later to the 27th gate electrode Gate27 through the via.

[0315] In an exemplary embodiment, the orthogonal projection at the base of the 82nd via V82 is located within the range of the orthogonal projection at the base of the 11th electrode plate CF11, the third insulating layer, the second insulating layer and the first insulating layer in the 82nd via V82 are etched to expose the surface of the 11th electrode plate CF11, and the 82nd via V82 is configured to connect the 38th connection electrode to the 11th electrode plate CF11 through the via.

[0316] In the exemplary embodiment, the orthogonal projection of the 83rd via V83 at the base is located within the range of the orthogonal projection of the 12th electrode plate CF12 at the base, and the third insulating layer, the second insulating layer, and the first insulating layer in the 83rd via V83 are etched to expose the surface of the 12th electrode plate CF12. In the exemplary embodiment, the 83rd via V83 may be provided in two locations, and the two 83rd vias V83 are configured to connect the 35th and 37th connection electrodes CO37, which will be formed later, to the 12th electrode plate CF12, respectively.

[0317] In an exemplary embodiment, the orthogonal projection at the base of the 84th via V84 is located within the range of the orthogonal projection at the base of the first end of the third gate block GK3, the third insulating layer in the 84th via V84 is etched to expose the surface of the first end of the third gate block GK3, and the 84th via V84 is configured to connect the 35th connection electrode to be formed later to the first end of the third gate block GK3 through the via.

[0318] In an exemplary embodiment, the orthogonal projection at the base of the 85th via V85 is located within the range of the orthogonal projection at the base of the first gate block GK1, the third insulating layer in the 85th via V85 is etched to expose the surface of the first gate block GK1, and the 85th via V85 is configured to connect a first clock signal line to be formed later to the first gate block GK1 through the via.

[0319] In an exemplary embodiment, the orthogonal projection at the base of the 86th via V86 is located within the range of the orthogonal projection at the base of the second gate block GK2, the third insulating layer within the 86th via V86 is etched to expose the surface of the second gate block GK2, and the 86th via V86 is configured to connect a second clock signal line to be formed later to the second gate block GK2 through the via.

[0320] In an exemplary embodiment, the orthogonal projection at the base of the 87th via V87 is located within the range of the orthogonal projection at the base of the second end of the third gate block GK3, the third insulating layer in the 87th via V87 is etched to expose the surface of the second end of the third gate block GK3, and the 87th via V87 is configured to connect a later-formed high-voltage line through the via to the second end of the third gate block GK3.

[0321] In the exemplary embodiment, the orthogonal projection at the base of the 88th via V88 is located within the range of the orthogonal projection at the base of the fourth gate block GK4, the third insulating layer in the 88th via V88 is etched to expose the surface of the fourth gate block GK4, and the 88th via V88 is configured to connect a low-voltage line to be formed later to the fourth gate block GK4 through the via.

[0322] In an exemplary embodiment, the orthogonal projection at the base of the 89th via V89 is located within the range of the orthogonal projection at the base of the upper stage signal output line G(n-1), the third insulating layer in the 89th via V89 is etched to expose the surface of the upper stage signal output line G(n-1), and the 89th via V89 is configured to connect the 31st connection electrode to be formed later to the upper stage signal output line G(n-1) through the via.

[0323] In an exemplary embodiment, the orthogonal projection at the base of the 90th via V90 is located within the range of the orthogonal projection at the base of the main stage signal output line G(n), the third insulating layer in the 90th via V90 is etched to expose the surface of the main stage signal output line G(n), and the 90th via V90 is configured to connect the 38th connection electrode to be formed later to the main stage signal output line G(n) through the via.

[0324] (5) Forming a third conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 25, 26, 27, and 28, forming the third conductive layer pattern may include depositing a third conductive thin film on the base on which the above-mentioned pattern is formed, and patterning the third conductive thin film by a patterning process to form a third conductive layer pattern provided on the third insulating layer. FIG. 25 is a structure of region A in FIG. 7, FIG. 26 is an enlarged view of one circuit unit in FIG. 25, FIG. 27 is an enlarged view of one gate drive circuit in FIG. 25, and FIG. 28 is a structure of region B in FIG. 7. In an exemplary embodiment, the third conductive layer may be referred to as a first source-drain metal (SD1) layer.

[0325] As shown in Figures 25 and 26, in an exemplary embodiment, the third conductive layer pattern of each circuit unit includes at least a data signal line DataI, a high-frequency signal line Hf, a seventh electrode plate CF7, an eighth electrode plate CF8, a ninth electrode plate CF9, an anode connection block 13, and a plurality of connection electrodes.

[0326] In an exemplary embodiment, the data signal line DataI may have a linear shape with its main body extending along the second direction Y, and may be located on the opposite side of the circuit unit in the first direction X. The data signal line DataI is connected to the first region of the fourth active layer through the seventeenth via V17 on the one hand, the first region of the eighth active layer through the twenty-fifth via V25 on the other hand, and the first region of the tenth active layer through the twenty-ninth via V29 on the other hand, so that the data signal line DataI writes data signals to the first pole of the fourth transistor T4, the first pole of the eighth transistor T8, and the first pole of the tenth transistor T10, respectively.

[0327] In an exemplary embodiment, the data signal line DataI may also be used as a time-length signal line DataT. The data signal line DataI is used to provide a time-length signal to the first pole of the eighth transistor T8 and the first pole of the tenth transistor T10, respectively.

[0328] In an exemplary embodiment, the high-frequency signal line Hf may have a linear shape with its main body extending along the second direction Y, and may be located on the opposite side of the data signal line DataI in the first direction X. On the one hand, the high-frequency signal line Hf is connected to the first end of the first connection electrode CO1 through the 44th via V44, and on the other hand, the high-frequency signal line Hf is connected to the high-frequency connecting line Hf-C through the 40th via V40. This realizes connection between the high-frequency connecting line Hf-C extending along the first direction X and the high-frequency signal line Hf extending along the second direction Y, forming a net-like communication structure for transmitting high-frequency signals.

[0329] In an exemplary embodiment, the seventh plate CF7 may be rectangular in shape, and the orthogonal projection of the seventh plate CF7 at the base at least partially overlaps the orthogonal projection of the fourth plate CF4 at the base. The seventh plate CF7 is connected to the first plate CF1 through via V33. The seventh plate CF7 may be another plate of a first capacitor, and the fourth plate CF4 and the seventh plate CF7 constitute another first capacitor of the pixel driving circuit. Because the seventh plate CF7 is connected to the first plate CF1 through the via, the first plate CF1 and the seventh plate CF7 have the same initial signal potential, so that the first plate CF1, the fourth plate CF4, and the third plate 97 constitute a first capacitor in a parallel connection structure, with the first plate CF1 and the fourth plate CF4 constituting one first capacitor of the pixel driving circuit and the fourth plate CF4 and the seventh plate CF7 constituting the other first capacitor of the pixel driving circuit, and the two first capacitors being connected in parallel.

[0330] In an exemplary embodiment, the eighth plate CF8 may be rectangular in shape, and the orthogonal projection of the eighth plate CF8 at the base at least partially overlaps the orthogonal projection of the fifth plate CF5 at the base. The eighth plate CF8 is connected to the second plate CF2 through the via V34. The eighth plate CF8 may be an additional plate of a second capacitor, and the fifth plate CF5 and the eighth plate CF8 constitute another second capacitor of the pixel driving circuit. Because the eighth plate CF8 is connected to the second plate CF2 through the via, the second plate CF2 and the eighth plate CF8 have the same initial signal potential, so that the second plate CF2, the fifth plate CF5, and the eighth plate CF8 constitute a second capacitor in a parallel connection structure, with the second plate CF2 and the fifth plate CF5 constituting one second capacitor of the pixel driving circuit and the fifth plate CF5 and the eighth plate CF8 constituting the other second capacitor of the pixel driving circuit, and the two second capacitors being connected in parallel.

[0331] In an exemplary embodiment, the ninth plate CF9 may be rectangular in shape, and the orthogonal projection of the ninth plate CF9 at the base at least partially overlaps the orthogonal projection of the sixth plate CF6 at the base. The ninth plate CF9 is connected to the third plate CF3 through the via V35. The ninth plate CF9 may be an additional plate of a storage capacitor, with the sixth plate CF6 and the ninth plate CF9 constituting another storage capacitor of the pixel driving circuit. Because the ninth plate CF9 is connected to the third plate CF3 through the via, the third plate CF3 and the ninth plate CF9 have the same first power supply potential, thereby constituting a parallel-connected storage capacitor structure, with the third plate CF3 and the sixth plate CF6 constituting one storage capacitor of the pixel driving circuit and the sixth plate CF6 and the ninth plate CF9 constituting the other storage capacitor of the pixel driving circuit, and the two storage capacitors being connected in parallel.

[0332] In an exemplary embodiment, the plurality of connection electrodes in each circuit unit may include at least an eleventh connection electrode CO11 to a twenty-sixth connection electrode CO26.

[0333] In an exemplary embodiment, the shape of the 11th connecting electrode CO11 may be elongated extending along the second direction Y, and the first end of the 11th connecting electrode CO11 is connected to the first region of the first active layer (which is also the first region of the seventh active layer) through the 11th via V11, and the second end of the 11th connecting electrode CO11 is connected to the initial signal line Vint through the 42nd via V42, thereby realizing the initial signal line Vint to write the initial signal to the first pole of the first transistor T1 and the first pole of the seventh transistor T7, respectively.

[0334] In the exemplary embodiment, the eleventh connection electrode CO11 is further connected to the seventh plate CF7, and the first plate CF1 and the seventh plate CF7 are connected through a via, so that the initial signal line Vint writes the initial signal to the first plate CF1 and the seventh plate CF7 of the first capacitor.

[0335] In an exemplary embodiment, the eleventh connection electrode CO11 and the seventh electrode plate CF7 may be an integral structure connected to each other.

[0336] In an exemplary embodiment, the twelfth connecting electrode CO12 may have an elongated shape extending along the second direction Y, with a first end of the twelfth connecting electrode CO12 connected to the initial signal line Vint through a via hole V43 and a second end of the twelfth connecting electrode CO12 connected to the eighth plate CF8. The second plate CF2 and the eighth plate CF8 are connected through vias, thereby enabling the initial signal line Vint to write an initial signal to the second plate CF2 and the eighth plate CF8 of the second capacitor.

[0337] In an exemplary embodiment, the twelfth connection electrode CO12 and the eighth electrode plate CF8 may be an integral structure connected to each other.

[0338] In an exemplary embodiment, the thirteenth connecting electrode CO13 may have an elongated shape extending along the second direction Y, with a first end of the thirteenth connecting electrode CO13 connected to the high-voltage connecting line VDD-C through the ninth via V39 and a second end of the thirteenth connecting electrode CO13 connected to the ninth electrode plate CF9. The third electrode plate CF3 and the ninth electrode plate CF9 are connected through vias, so that the high-voltage connecting line VDD-C is configured to be connected to a high-voltage power supply line, and the high-voltage power supply line realizes writing a high-voltage signal to the third electrode plate CF3 and the ninth electrode plate CF9 of the storage capacitor.

[0339] In an exemplary embodiment, the thirteenth connecting electrode CO13 and the ninth electrode plate CF9 may be an integral structure connected to each other.

[0340] In an exemplary embodiment, the shape of the fourteenth connecting electrode CO14 may be a broken line extending along the second direction Y, a first end of the fourteenth connecting electrode CO14 is connected to the second region of the first active layer through the twelfth via V12, and a second end of the fourteenth connecting electrode CO14 is connected to the sixth electrode plate CF6 through the thirty-eighth via V38, and the fourteenth connecting electrode CO14 causes the second electrode of the first transistor T1 and the sixth electrode plate CF6 to have the same potential.

[0341] In an exemplary embodiment, the shape of the fifteenth connecting electrode CO15 may be a polygonal line, with a first end of the fifteenth connecting electrode CO15 connected to the first region of the second active layer through the thirteenth via V13, a second end of the fifteenth connecting electrode CO15 connected to the fourth connecting electrode CO4 through the forty-ninth via V49, and a portion of the fifteenth connecting electrode CO15 between the first and second ends connected to the third bottom gate electrode Gate3-B through the fiftieth via V50. In an exemplary embodiment, since the fourth connecting electrode CO4 is connected to the third top gate electrode Gate3-T and the sixth electrode plate CF6, respectively, the fifteenth connecting electrode CO15 not only connects the third top gate electrode Gate3-T and the third bottom gate electrode Gate3-B to each other, but also causes the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the sixth electrode plate CF6 to have the same potential.

[0342] In an exemplary embodiment, on the one hand, the sixth plate CF6 is connected to the first pole of the second transistor T2 and the gate electrode of the third transistor T3, and on the other hand, the sixth plate CF6 is connected to the second pole of the first transistor T1, so that, through the fourteenth connecting electrode CO14 and the fifteenth connecting electrode CO15, the second pole of the first transistor T1, the first pole of the second transistor T2, the gate electrode of the third transistor T3 and the sixth plate CF6 have the same potential (i.e., the third node N3 of the pixel driving circuit).

[0343] In the illustrative embodiment, the shape of the sixteenth connecting electrode CO16 is a broken line, a first end of the sixteenth connecting electrode CO16 is connected to the second region of the second active layer through the fourteenth via V14, a second end of the sixteenth connecting electrode CO16 is connected to the second region of the third active layer through the sixteenth via V16, and a portion between the first and second ends of the sixteenth connecting electrode CO16 is connected to the first region of the sixth active layer through the twenty-first via V21, and the sixteenth connecting electrode CO16 causes the second pole of the second transistor T2, the second pole of the third transistor T3, and the first pole of the sixth transistor T6 to have the same potential (i.e., the fourth node N4 of the pixel driving circuit).

[0344] In an exemplary embodiment, the shape of the 17th connecting electrode CO17 may be a polygonal line, with a first end of the 17th connecting electrode CO17 connected to the first region of the third active layer via the 15th via V15, a second end of the 17th connecting electrode CO17 connected to the second region of the fifth active layer via the 20th via V20, and a portion of the 17th connecting electrode CO17 between the first and second ends connected to the second region of the fourth active layer via the 18th via V18, and the 17th connecting electrode CO17 causing the first pole of the third transistor T3, the second pole of the fourth transistor T4, and the second pole of the fifth transistor T5 to have the same potential (i.e., the fifth node N5 of the pixel driving circuit).

[0345] In an exemplary embodiment, the eighteenth connecting electrode CO18 may have a polygonal shape, a first end of the eighteenth connecting electrode CO18 connected to the first region of the fifth active layer through the nineteenth via V19, and a second end of the eighteenth connecting electrode CO18 connected to the ninth electrode plate CF9, such that the first electrode of the fifth transistor T5 and the ninth electrode plate CF9 have the same potential through the eighteenth connecting electrode CO18. The ninth electrode plate CF9 is connected to the thirteenth connecting electrode CO13, which is connected to the high-voltage connecting line VDD-C, which is connected to a high-voltage power supply line, so that the high-voltage power supply line writes a high-voltage signal to the first electrode of the fifth transistor T5 of each circuit unit.

[0346] In an exemplary embodiment, the eighteenth connecting electrode CO18 and the ninth electrode plate CF9 may be an integral structure connected to each other.

[0347] In an exemplary embodiment, the 19th connecting electrode CO19 may have an elongated shape extending along the second direction Y, and a first end of the 19th connecting electrode CO19 is connected to a second end of the 7th connecting electrode CO7 through the 53rd via V53, and a second end of the 19th connecting electrode CO19 is connected to the 4th electrode CF4 through the 36th via V36, so that the gate electrode of the 9th transistor T9 and the 4th electrode CF4 have the same potential due to the 19th connecting electrode CO19.

[0348] In an exemplary embodiment, the 20th connecting electrode CO20 may have an elongated shape extending along the first direction X, with a first end of the 20th connecting electrode CO20 connected to the second region of the eighth active layer through the 26th via V26 and a second end of the 20th connecting electrode CO20 connected to a first end of the seventh connecting electrode CO7 through the 52nd via V52. Because the seventh connecting electrode CO7 is connected to the ninth gate electrode Gate9, the 19th connecting electrode CO19 and the 20th connecting electrode CO12 cause the second electrode of the eighth transistor T8, the gate electrode of the ninth transistor T9, and the fourth plate CF4 to have the same potential (i.e., the sixth node N6 of the pixel driving circuit).

[0349] In an exemplary embodiment, the shape of the twenty-first connecting electrode CO21 may be elongated along the second direction Y, with a first end of the twenty-first connecting electrode CO21 connected to the eighth connecting electrode CO8 through the fifty-fourth via V54, a second end of the twenty-first connecting electrode CO21 connected to the fifth electrode CF5 through the thirty-seventh via V37, and a portion of the twenty-first connecting electrode CO21 between the first and second ends connected to the second region of the tenth active layer through the thirty-eighth via V30. Because the eighth connecting electrode CO8 is connected to the eleventh gate electrode Gate11, the twenty-first connecting electrode CO21 causes the second electrode of the tenth transistor T10, the gate electrode of the eleventh transistor T11, and the fifth electrode CF5 to have the same potential (i.e., the seventh node N7 of the pixel driving circuit).

[0350] In an exemplary embodiment, the shape of the 22nd connecting electrode CO22 may be a broken line extending along the first direction X, a first end of the 22nd connecting electrode CO22 is connected to the second region of the 11th active layer via the 32nd via V32, a second end of the 22nd connecting electrode CO22 is connected to the first end of the second connecting electrode CO2 via the 46th via V46, a portion of the 22nd connecting electrode CO22 between the first and second ends is connected to the second region of the 9th active layer via the 28th via V28, and the 22nd connecting electrode CO22 connects the second pole of the 9th transistor T9 and the second pole of the 11th transistor T11 to each other.

[0351] In an exemplary embodiment, the shape of the 23rd connecting electrode CO23 may be elongated along the second direction Y, with a first end of the 23rd connecting electrode CO23 connected to a second end of the second connecting electrode CO2 via a 47th via V47 and a second end of the 23rd connecting electrode CO23 connected to the sixth connecting electrode CO6 via a 51st via V51. The 22nd connecting electrode CO22 is connected to the 23rd connecting electrode CO23 via the second connecting electrode CO2, and the sixth connecting electrode CO6 is connected to the sixth gate electrode Gate6. Therefore, the 22nd connecting electrode CO22 and the 23rd connecting electrode CO23 cause the sixth gate electrode Gate6, the second pole of the ninth transistor T9, and the second pole of the eleventh transistor T11 to have the same potential (i.e., the first node N1 of the pixel driving circuit).

[0352] In an exemplary embodiment, the connecting electrode CO24 may be L-shaped, with a first end connected to the first region of the active layer through the via V31 and a second end connected to the second end of the connecting electrode CO1 through the via V45. The first end of the connecting electrode CO1 is connected to the high-frequency signal line Hf through the via, thereby enabling the high-frequency signal line Hf to write a high-frequency signal to the first pole of the transistor T11.

[0353] In an exemplary embodiment, the shape of the 25th connecting electrode CO25 may be L-shaped, a first end of the 25th connecting electrode CO25 is connected to the first region of the 9th active layer through the 27th via V27, a second end of the 25th connecting electrode CO25 is connected to the light-emitting signal line EM through the 41st via V41, and the portion between the first and second ends of the 25th connecting electrode CO25 is connected to the third connecting electrode CO3 through the 48th via V48, so that the light-emitting signal line EM writes the light-emitting signal to the first pole of the 9th transistor T9.

[0354] In an exemplary embodiment, the shape of the 26th connecting electrode CO26 may be elongated extending along the second direction Y, and a first end of the 26th connecting electrode CO26 is connected to the second region of the sixth active layer via the 22nd via V22, and a second end of the 26th connecting electrode CO26 is connected to the second region of the seventh active layer via the 24th via V24, so that the 26th connecting electrode CO26 causes the second pole of the sixth transistor T6 and the second pole of the seventh transistor T7 to have the same potential (i.e., the second node N2 of the pixel driving circuit).

[0355] In an exemplary embodiment, the third conductive layer may further include a 27th connecting electrode CO27. The 27th connecting electrode CO27 may have an elongated shape extending along the second direction Y, and may be provided on some of the circuit units. The 27th connecting electrode CO27 is connected to the low-voltage connecting line VSS-C through the 55th via V55, and is configured to be connected to a low-voltage power supply line that will be formed later.

[0356] In an exemplary embodiment, some circuit units may further include a second anode connecting line 12 and an anode connecting block 13 .

[0357] In an exemplary embodiment, a first end of the second anode connecting wire 12 is configured to be connected to the first anode connecting wire 11 through a connecting wire via, and a second end of the second anode connecting wire 12 is configured to be directly connected to the anode connecting block 13. The anode connecting blocks 13 of some circuit units are directly connected to the 26th connecting electrode CO26, and the anode connecting blocks 13 of some circuit units are connected to the anode connecting block 13 through the first anode connecting wire 11 and the second anode connecting wire 12, thereby realizing the connection between the anode connecting block 13 and the 26th connecting electrode CO26 in each circuit unit, and the present disclosure is not limited thereto.

[0358] As shown in FIGS. 25 and 27, in an exemplary embodiment, the third conductive layer pattern of each gate driving circuit includes at least a first clock signal line CLK, a second clock signal line CLKB, a high voltage line VGH, a low voltage line VG, and a plurality of connecting electrodes.

[0359] In an exemplary embodiment, the first clock signal line CLK may have a linear body extending along the second direction Y, may be located on the side of the fourteenth electrode plate CF14 away from the thirteenth electrode plate CF13, and is connected to the first gate block GK1 through the eighth via hole V85. The first gate block GK1 is connected to the twenty-first gate electrode Gate21, which is connected to the twenty-third gate electrode Gate23, thereby realizing that the first clock signal line CLK can control the turn-on and turn-off of the twenty-first transistor T21 and the twenty-third transistor T23.

[0360] In an exemplary embodiment, the second clock signal line CLKB may have a linear body extending along the second direction Y, and may be located on the side of the first clock signal line CLK away from the fourteenth electrode plate CF14. The second clock signal line CLKB is connected to the second gate block GK2 through the 86th via V86. The second gate block GK2 is connected to the 27th gate electrode Gate27, so that the second clock signal line CLKB can control the turn-on and turn-off of the 27th transistor T27.

[0361] In an exemplary embodiment, the high voltage line VGH may have a linear shape with its main body extending along the second direction Y, and the high voltage line VGH may be located on the side of the second clock signal line CLKB away from the 14th electrode plate CF14, and the high voltage line VGH is connected to the second end of the third gate block GK3 through the 87th via V87.

[0362] In an exemplary embodiment, the low-voltage line VGL may have a linear shape with its main body extending along the second direction Y, and may be located between the thirteenth electrode plate CF13 and the fourteenth electrode plate CF14. The low-voltage line VGL is connected to the fourth gate block GK4 through the via V88 on one side and to the first region of the twenty-third active layer through the via V90 on the other side. The fourth gate block GK4 is connected to the twenty-eighth gate electrode Gate28, so that the low-voltage line VGL controls the turning on and off of the twenty-eighth transistor T28 and realizes that a low-voltage signal can be written to the first electrode of the twenty-third transistor T23.

[0363] In an exemplary embodiment, the orthogonal projection of the gate driving circuit on the display substrate plane does not overlap with the orthogonal projection of the data signal line DataI on the display substrate plane.

[0364] In an exemplary embodiment, the first clock signal line CLK and the second clock signal line CLKB are disposed in the area where the blank columns are located, and the data signal line DataI may be disposed in the area where the repeating unit columns are located, so that the data signal line DataI does not overlap with the first clock signal line CLK and the second clock signal line CLKB, the orthogonal projection of the first clock signal line CLK on the display substrate plane does not overlap with the data signal line DataI on the display substrate plane, and the orthogonal projection of the second clock signal line CLKB on the display substrate plane does not overlap with the data signal line DataI on the display substrate plane.

[0365] In an exemplary embodiment, the first clock signal line CLK may be essentially parallel to the data signal line DataI, and the second clock signal line CLKB may be essentially parallel to the data signal line DataI, or the orthogonal projection of the first clock signal line CLK on the display substrate plane may be essentially parallel to the orthogonal projection of the data signal line DataI on the display substrate plane, and the orthogonal projection of the second clock signal line CLKB on the display substrate plane may be essentially parallel to the orthogonal projection of the data signal line DataI on the display substrate plane.

[0366] In an exemplary embodiment, the first clock signal line CLK and the second clock signal line CLKB may be disposed between the high voltage line VGH and the low voltage line VGL along the first direction X, whereby the data signal line DataI is located on the side of the high voltage line VGH away from the first clock signal line CLK, and the data signal line DataI is located on the side of the low voltage line VGL away from the second clock signal line CLKB, and the high voltage line VGH and the low voltage line VGL transmitting constant voltage signals may serve as a shield, effectively reducing the coupling capacitance between the clock signal lines and the data signal lines.

[0367] In an exemplary embodiment, a first distance L is provided between the edge of the high voltage line VGH closer to the data signal line DataI and the edge of the data signal line DataI closer to the high voltage line VGH, and a second distance L2 is provided between the edge of the low voltage line VGL closer to the data signal line DataI and the edge of the data signal line DataI closer to the low voltage line VGL, and the second distance L2 may be greater than the first distance L1.

[0368] In an exemplary embodiment, the first distance L1 may be 25 μm or more, and the second distance L2 may be 25 μm or more. For example, the first distance L1 may be approximately 28.5 μm.

[0369] In an exemplary embodiment, a third distance L3 is provided between the edge of the first clock signal line CLK closer to the low voltage line VGL and the edge of the low voltage line VGL closer to the first clock signal line CLK, and a fourth distance L4 is provided between the edge of the second clock signal line CLKB closer to the high voltage line VGH and the edge of the high voltage line VGH closer to the second clock signal line CLKB, and the third distance L3 may be greater than the fourth distance L4.

[0370] In an exemplary embodiment, a fifth distance L5 between an edge of the gate drive circuit closer to the data signal line DataI and an edge of the data signal line DataI closer to the gate drive circuit may be 50 μm or more, for example, the fifth distance L5 may be approximately 55.5 μm. The fifth distance L5 may be a dimension in the first direction X.

[0371] In an exemplary embodiment, the plurality of connection electrodes of each gate drive circuit may include at least a 31st connection electrode CO31 to a 41st connection electrode CO41.

[0372] In an exemplary embodiment, the 31st connecting electrode CO31 may have an elongated shape, a first end of the 31st connecting electrode CO31 is connected to the first region of the 21st active layer through the 61st via V61, and a second end of the 31st connecting electrode CO31 is connected to the upper output signal line G(n-1) through the 89th via V89, so that the upper output signal transmitted through the upper output signal line G(n-1) can be written to the first pole of the 21st transistor T21.

[0373] In an exemplary embodiment, the 32nd connecting electrode CO32 may have an elongated shape, and a first end of the 32nd connecting electrode CO32 is connected to the second region of the 21st active layer via the 62nd via V62, and a second end of the 32nd connecting electrode CO32 is connected to the second region of the 27th active layer via the 74th via V74, thereby connecting the second pole of the 21st transistor T21 and the second pole of the 27th transistor T27 to each other (the 11th node N11 of the gate drive circuit).

[0374] In an exemplary embodiment, the connecting electrode CO33 may have an elongated shape, a first end of the connecting electrode CO33 is connected to the first region of the active layer through the via V63, and a second end of the connecting electrode CO33 is connected to the gate electrode Gate23 through the via V78. The gate electrode Gate23 is connected to the first clock signal line CLK, so that the first clock signal line CLK can write the first clock signal to the first electrode of the transistor T22.

[0375] In an exemplary embodiment, the shape of the 34th connecting electrode CO34 may be a polygonal line, with a first end of the 34th connecting electrode CO34 connected to the 26th gate electrode Gate26 through the 80th via V80, a second end of the 34th connecting electrode CO34 connected to the second region of the 23rd active layer through the 66th via V66, and a portion of the 34th connecting electrode CO34 between the first and second ends connected to the second region of the 22nd active layer through the 64th via V64. The 26th gate electrode Gate26 is connected to the 14th electrode plate CF14, and the 14th electrode plate CF14 is connected to the 24th gate electrode Gate24. Therefore, the 34th connecting electrode CO34 causes the second pole of the 22nd transistor T22, the second pole of the 23rd transistor T23, the gate electrode of the 24th transistor T24, the gate electrode of the 26th transistor T26, and the 14th electrode plate CF14 to have the same potential (the 11th node N12 of the gate drive circuit).

[0376] In an exemplary embodiment, the connecting electrode CO35 may have an elongated shape, a first end of the connecting electrode CO35 connected to the first region of the active layer through the via V71, and a second end of the connecting electrode CO35 connected to the twelfth electrode plate CF12 through the via V83 and to a first end of the third gate block GK3 through the via V84. The third gate block GK3 is connected to the high voltage line VGH, so that the high voltage line VGH writes a high voltage signal to the first electrode of the transistor T26, and the twelfth electrode plate CF12 and the voltage line VGH have the same potential.

[0377] In an exemplary embodiment, the shape of the 36th connecting electrode CO36 may be rectangular, and the 36th connecting electrode CO36 is connected to the second region of the 26th active layer (which is also the first region of the 27th active layer) through the 72nd via V72 (which is also the 73rd via V73), realizing the connection between the second pole of the 26th transistor T26 and the first pole of the 27th transistor T27 (the 13th node N13 of the gate driving circuit).

[0378] In an exemplary embodiment, the shape of the connecting electrode CO37 may be comb-shaped, and on the one hand, the connecting electrode CO37 is connected to the first region of the twenty-fourth active layer through the via V67, and on the other hand, the connecting electrode CO37 is connected to the twelfth electrode plate CF12 through the via V83. The twelfth electrode plate CF12 is connected to the high voltage line VGH, so that the high voltage line VGH writes a high voltage signal to the first electrode of the twenty-fourth transistor T24.

[0379] In an exemplary embodiment, the shape of the 38th connecting electrode CO38 may be comb-like, and on the one hand, the 38th connecting electrode CO38 is connected to the second region of the 24th active layer through the 68th via V68, and on the other hand, the 38th connecting electrode CO38 is connected to the second region of the 25th active layer through the 70th via V70, and on the other hand, the 38th connecting electrode CO38 is connected to the main stage output signal line G(n) through the 90th via V90, and on the other hand, the 38th connecting electrode CO38 is connected to the 11th electrode plate CF11 through the 82nd via V82, thereby realizing that the second pole of the 24th transistor T24, the second pole of the 25th transistor T25, and the 11th electrode plate CF11 have the same potential. In an exemplary embodiment, the 38th connecting electrode CO38 may be the output line of this stage, and one end of the 38th connecting electrode CO38 away from the gate driving circuit extends to the first circuit area and is then connected to the second scanning signal line S2 (or the first scanning signal line S1, the light-emitting signal line EM) through a gate line via.

[0380] In an exemplary embodiment, the shape of the thirty-ninth connecting electrode CO39 may be comb-shaped, and on the one hand, the thirty-ninth connecting electrode CO39 is connected to the first region of the twenty-fifth active layer through the sixty-ninth via V69, and on the other hand, the thirty-ninth connecting electrode CO39 is connected to the twenty-seventh gate electrode Gate27 through the eighth via V81. The twenty-seventh gate electrode Gate27 is connected to the second clock signal line CLKB, so that the second clock signal line CLKB writes the second clock signal to the first electrode of the twenty-fifth transistor T25.

[0381] In an exemplary embodiment, the 40th connection electrode CO40 may have an elongated shape, and on the one hand, the 40th connection electrode CO40 is connected to the first region of the 28th active layer through the 75th via V75, and on the other hand, the 40th connection electrode CO40 is connected to the 22nd gate electrode Gate22 through the 77th via V77, thereby connecting the gate electrode of the 22nd transistor T22 and the first pole of the 28th transistor T28 to each other (the 11th node N11 of the gate drive circuit).

[0382] In an exemplary embodiment, the shape of the forty-first connecting electrode CO41 may be elongated, and on the one hand, the forty-first connecting electrode CO41 is connected to the second region of the twenty-eighth active layer through the seventy-sixth via V76, and on the other hand, the forty-first connecting electrode CO41 is connected to the twenty-fifth gate electrode Gate25 through the seventy-ninth via V79. Since the twenty-fifth gate electrode Gate25 is connected to the thirteenth electrode plate CF13, the gate electrode of the twenty-fifth transistor T25, the second electrode of the twenty-eighth transistor T28, and the thirteenth electrode plate CF13 have the same potential (the fourteenth node N14 of the gate drive circuit).

[0383] 28 , in an exemplary embodiment, the third conductive layer pattern of the second circuit region 220 may further include a first mark MARK1, which may be located at one edge or both edges in the first direction X of the second circuit region 220. The first mark MARK1 is configured as a splice mark, and positioning is performed via the first mark MARK1 when performing a splice connection of the display substrate.

[0384] In an exemplary embodiment, the shape of the first mark MARK1 may be cross-shaped, and the installation position of at least one first mark MARK1 in the second circuit area 220 may basically correspond to the installation position of at least one blank unit KB in the first circuit area 210, i.e., the first mark MARK1 may be installed in the area where the blank row is located, and the orthogonal projection of at least one first mark MARK1 on the reference line O1 at least partially overlaps with the orthogonal projection of at least one blank unit KB on the reference line O1.

[0385] In an exemplary embodiment, the data signal lines and high frequency connection lines near the first mark MARK1 may be provided with bends, which are bent in a direction away from the first mark MARK1, leaving a corresponding space for the first mark MARK1.

[0386] In the illustrative embodiment, the pixel driving circuit and its corresponding signal line, and the gate driving circuit and its corresponding signal line all avoid the first mark MARK1, the orthogonal projection of the first mark MARK1 at its base does not overlap with the orthogonal projection of the pixel driving circuit and the gate driving circuit at their bases, and the orthogonal projection of the first mark MARK1 at its base does not overlap with the orthogonal projection of the first scanning signal line, the second scanning signal line, the light-emitting signal line, the high-frequency signal line, the initial signal line, the data signal line, the first clock signal line, the second clock signal line, the high-voltage line, and the low-voltage line, etc.

[0387] (6) Forming a fourth insulating layer and a first flat layer pattern. In an exemplary embodiment, as shown in FIGS. 29, 30, and 31, forming the fourth insulating layer and the first flat layer pattern may include applying a first flat thin film to the base on which the above-mentioned pattern is formed, patterning the first flat thin film by a patterning process, then depositing a fourth insulating thin film, and patterning the fourth insulating thin film by a patterning process to form a first flat layer covering the third conductive layer pattern and a fourth insulating layer located on the side of the first flat layer away from the base, and multiple vias are provided in the fourth insulating layer and the first flat layer. FIG. 29 shows the structure of region A in FIG. 7, FIG. 30 is an enlarged view of one circuit unit in FIG. 29, and FIG. 31 shows the structure of region B in FIG. 7.

[0388] As shown in FIGS. 29 and 30, in an exemplary embodiment, the plurality of vias in each circuit unit may include at least a 91st via V91.

[0389] In an exemplary embodiment, the orthogonal projection at the base of the 91st via V91 is located within the range of the orthogonal projection at the base of the anode connection block 13, the fourth insulating thin film and the first flat thin film in the 91st via V91 are removed to expose the surface of the anode connection block 13, and the 91st via V91 is configured to connect a later-formed anode connection electrode to the anode connection block 13 through the via.

[0390] In an exemplary embodiment, some circuit units may further include a 92nd via V92. The orthogonal projection of the base of the 92nd via V92 is located within the range of the orthogonal projection of the base of the 27th connecting electrode CO27, the fourth insulating thin film and the first flat thin film in the 92nd via V92 are removed to expose the surface of the 27th connecting electrode CO27, and the 92nd via V92 is configured to connect a low-voltage power line to be formed later to the 27th connecting electrode CO27 through the via.

[0391] In an exemplary embodiment, some circuit units may further include a via V93. The orthogonal projection of the base of the via V93 is located within the range of the orthogonal projection of the base of the connecting electrode CO13, the fourth insulating thin film and the first flat thin film in the via V93 are removed to expose the surface of the connecting electrode CO13, and the via V93 is configured to connect a high-voltage power line to be formed later to the connecting electrode CO13.

[0392] In an exemplary embodiment, no vias are provided in the fourth insulating layer and the first planar layer in the area where the gate drive circuit is located.

[0393] As shown in FIG. 31, in the exemplary embodiment, a first mark hole B1 is provided in the first flat layer in the region where the first mark MARK1 is located.

[0394] In an exemplary embodiment, during the process of forming the first planar layer by a patterning process, a first mark hole B1 is provided in the region where the first mark MARK1 is located, and the first planar layer in the first mark hole B1 is removed to expose the first mark MARK1. The shape of the first mark hole B1 may be rectangular, and the orthogonal projection of the first mark hole B1 at its base may include the orthogonal projection of the first mark MARK1 at its base. During the process of forming the fourth insulating layer, the region where the first mark hole B1 is located is covered by the fourth insulating layer, so that the fourth insulating layer covers the first mark MARK1, i.e., the first mark MARK1 is covered only by the fourth insulating layer (also referred to as a first passivation layer) to protect the first mark MARK1.

[0395] (7) Forming a fourth conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 32 and 33, forming the fourth conductive layer pattern may include depositing a fourth conductive thin film on the base on which the above-mentioned pattern is formed, and patterning the fourth conductive thin film by a patterning process to form a fourth conductive layer pattern disposed on the fourth insulating layer. FIG. 32 shows the structure of region A in FIG. 7, and FIG. 33 shows the structure of region B in FIG. 7. In an exemplary embodiment, the fourth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0396] As shown in FIG. 32, in an exemplary embodiment, the fourth conductive layer pattern of each circuit unit may include at least an anode connecting electrode 14, a high-voltage power supply line VDD, and a low-voltage power supply line VSS, where the high-voltage power supply line may be referred to as the first power supply line, and the low-voltage power supply line may be referred to as the second power supply line.

[0397] In an exemplary embodiment, the anode connecting electrode 14 may have a rectangular shape and is connected to the anode connecting block 13 through the 91st via V91. The anode connecting electrode 14 is configured to be bound-connected to the first pole of the light-emitting diode. The anode connecting block 13 is connected to the 26th connecting electrode CO26, which is connected to the second region of the sixth active layer and the second region of the seventh active layer, respectively. This allows the anode connecting electrode 14 to be connected to the second pole of the sixth transistor T6 and the second pole of the seventh transistor T7, and the pixel driving circuit can drive the light-emitting diode to emit light.

[0398] In an exemplary embodiment, the high-voltage power line VDD may have a linear shape extending along the second direction Y, and the high-voltage power line VDD is connected to the thirteenth connecting electrode CO13 through the 93rd via V93 in some circuit units. The thirteenth connecting electrode CO13 is connected to the high-voltage connecting line VDD-C through the via, so that the high-voltage connecting line VDD-C extending along the first direction X and the high-voltage power line VDD extending along the second direction Y form a net-like communication structure, which not only minimizes the resistance of the power transmission line but also reduces the drop in power supply voltage, effectively improving the uniformity of the power supply voltage on the display substrate, effectively improving the uniformity within the signal plane, effectively improving display uniformity, and improving display attributes and display quality.

[0399] In an exemplary embodiment, some of the low-voltage power lines VSS may have a linear shape extending along the second direction Y, and other low-voltage power lines VSS may have a T-shape. The low-voltage power line VSS is connected to the 27th connecting electrode CO27 through the 92nd via V92. The 27th connecting electrode CO27 is connected to the low-voltage connecting line VSS-C through the via, so that the low-voltage connecting line VSS-C extending along the first direction X and the low-voltage power line VSS extending along the second direction Y form a net-like communication structure, which not only minimizes the resistance of the power transmission line but also reduces the drop in power supply voltage, effectively improving the uniformity of the power supply voltage on the display substrate, effectively improving the uniformity in the signal plane, effectively improving display uniformity, and improving display attributes and display quality.

[0400] 33 , in an exemplary embodiment, the fourth conductive layer pattern of the second circuit region 220 may further include a second mark MARK2, which may be located at one edge or both edges of the second circuit region 220 in the first direction X and on the side closer to the gate driving circuit than the first mark MARK1. The second mark MARK2 is configured as a binding mark, and is used for positioning when performing binding connection of the light-emitting diode.

[0401] In an exemplary embodiment, the shape of the second mark MARK2 may be circular, and the installation position of at least one second mark MARK2 in the second circuit area 220 may basically correspond to the installation position of at least one blank unit KB in the first circuit area 210, that is, the second mark MARK2 may be installed in the area where the blank unit row is located.

[0402] In the exemplary embodiment, the pixel driving circuit and its corresponding signal line, and the gate driving circuit and its corresponding signal line all avoid the second mark MARK2, and the orthogonal projection of the second mark MARK2 at its base does not overlap with the orthogonal projection of the pixel driving circuit and the gate driving circuit at their bases, and the orthogonal projection of the second mark MARK2 at its base does not overlap with the orthogonal projection of the first scanning signal line, the second scanning signal line, the light-emitting signal line, the high-frequency signal line, the initial signal line, the data signal line, the first clock signal line, the second clock signal line, the high-voltage line, and the low-voltage line, etc.

[0403] (8) Forming a fifth insulating layer and a second planar layer pattern. In an exemplary embodiment, as shown in FIGS. 34 and 35, forming the fifth insulating layer and the second planar layer pattern may include depositing a fifth insulating thin film on the base on which the above-mentioned pattern is formed, patterning the fifth insulating thin film by a patterning process to form a fifth insulating layer covering the fourth conductive layer pattern, applying a second planar thin film, and patterning the second planar thin film by a patterning process to form a second planar layer provided on the side of the fifth insulating layer away from the base, and providing a plurality of vias in the fifth insulating layer and the second planar layer. FIG. 34 shows the structure of region A in FIG. 7, and FIG. 35 shows the structure of region B in FIG. 7.

[0404] As shown in FIG. 34, in the exemplary embodiment, the fifth insulating layer and the second planar layer are provided with a first binding via K1 and a second binding via K2.

[0405] In an exemplary embodiment, the first binding via K1 may have a rectangular shape, the orthogonal projection at the base of the first binding via K1 is located within the range of the orthogonal projection at the base of the anode connecting electrode 14, the second planar thin film and the fifth insulating thin film in the first binding via K1 are removed to expose the surface of the anode connecting electrode 14, and the area of ​​the anode connecting electrode 14 exposed by the first binding via K1 may be an anode pad, and the first binding via K1 is configured to connect the first pole of the light-emitting diode to the anode connecting electrode 14 through the binding via.

[0406] In an exemplary embodiment, the second binding via K2 may have a rectangular shape, the orthogonal projection at the base of the second binding via K2 is located within the range of the orthogonal projection at the base of the low-voltage power supply line VSS, the second flat thin film and the fifth insulating thin film in the second binding via K2 are removed to expose the surface of the low-voltage power supply line VSS, and the area of ​​the low-voltage power supply line VSS exposed by the second binding via K2 may be a cathode pad, and the second binding via K2 is configured to connect the second pole of the light-emitting diode to the low-voltage power supply line VSS through the binding via.

[0407] As shown in FIG. 35, in the exemplary embodiment, a second mark hole B2 and a third mark hole B3 are provided in the second flat layer in the region where the first mark MARK1 and the second mark MARK2 are located.

[0408] In an exemplary embodiment, during the process of forming the fifth insulating layer, the fifth insulating layer covers the second mark MARK2 on one hand, and covers the fourth insulating layer located under the first mark MARK1 on the other hand. During the process of forming the second flat layer by a patterning process, a second mark hole B2 is provided in the area where the second mark MARK2 is located, a third mark hole B3 is provided in the area where the first mark MARK1 is located, and the second flat layer at the second mark MARK2 and the third mark hole B3 is removed to expose the fifth insulating layer covering the first mark MARK1 and the second mark MARK2, respectively. In an exemplary embodiment, to protect the first mark MARK1 and the second mark MARK2, the fourth insulating layer and the fifth insulating layer are respectively covered over the first mark MARK1 and the second mark MARK2, and the fifth insulating layer is covered over the second mark MARK2 (also referred to as a second passivation layer).

[0409] In an exemplary embodiment, the second mark hole B2 may be circular in shape, and the orthogonal projection at the base of the second mark hole B2 may include the orthogonal projection at the base of the second mark MARK2.

[0410] In an exemplary embodiment, the third mark hole B3 may be rectangular in shape, and the orthogonal projection at the base of the third mark hole B3 may include the orthogonal projection at the base of the first mark MARK1.

[0411] Thus, the driving circuit layer of this exemplary embodiment is fabricated and completed. In a plane parallel to the display substrate, the driving circuit layer may include at least a plurality of circuit units, each of which may include a pixel driving circuit, a first scanning signal line, a second scanning signal line, a light-emitting signal line, a primary signal line, a high-frequency signal line, a data signal line, and a high-voltage power supply line connected to the pixel driving circuit. In a plane perpendicular to the display substrate, the driving circuit layer may include at least a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a first planar layer, a fourth insulating layer, a fourth conductive layer, a fifth insulating layer, and a second planar layer, which are sequentially disposed on a base.

[0412] In exemplary embodiments, the base may be a flexible base or a rigid base. The rigid base may include, but is not limited to, one or more of glass and quartz. The flexible base may include, but is not limited to, one or more of polyethylene terephthalate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyaryl ester, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.

[0413] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer may be made of a metal material, such as one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may have a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer may be made of one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be made of a single layer, multi-layer, or composite layer. The first and second planar layers may be made of an organic material, such as a resin. The semiconductor layer may be made of one or more materials, such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, polythiophene, etc. That is, the present disclosure is applicable to transistors fabricated based on oxide technology, silicon technology, and organic technology. For example, the material of the semiconductor layer may be polycrystalline silicon (p-Si).

[0414] In an exemplary embodiment, the subsequent manufacturing flow may include first using a dispenser to add a binding material (e.g., solder paste) to the plurality of first binding vias and the plurality of second binding vias, and then using a transfer die bonding process to bind-connect first electrodes of the plurality of light-emitting diodes to anode connecting electrodes through the first binding vias and bind-connect second electrodes of the plurality of light-emitting diodes to low-voltage power supply lines through the second binding vias, thereby completing the connection between the light-emitting diodes and corresponding pixel driving circuits. Then, a cover thin film is applied to the base on which the above structure is formed to form a cover layer, and the cover layer covers the plurality of light-emitting diodes. In an exemplary embodiment, the plurality of light-emitting diodes and the cover layer may constitute a light-emitting structure layer.

[0415] As can be seen from the above-described structure and manufacturing process of the display substrate, the display substrate according to the exemplary embodiment of the present disclosure has the first and second clock signal lines positioned in the blank column area. Therefore, the orthogonal projections of the first and second clock signal lines on the plane of the display substrate do not overlap with the orthogonal projections of the data signal lines on the plane of the display substrate. This effectively avoids the occurrence of overlapping capacitance between the clock signal lines and the data signal lines. The overlapping capacitance between the two signal lines can be essentially zero, effectively avoiding data voltage jumps on the data signal lines and improving display quality. In the exemplary embodiment of the present disclosure, the high-voltage and low-voltage lines are positioned outside the first and second clock signal lines, which is equivalent to providing a shielding line between the clock signal lines and the data signal lines, effectively reducing the side-to-side capacitance between the clock signal lines and the data signal lines. For a clock signal line and a data signal line with a width of 10 μm and a length of 715 μm, when the distance between the two signal lines is 5 μm, the side-to-side capacitance between the two signal lines is approximately 2.8 fF. When one high-voltage or low-voltage wire is used as a shield between two signal wires, the side-to-side capacitance between the two signal wires is approximately 3.3*10 -5 fF.

[0416] In the present disclosure, the positioning of the gate driver circuit not only effectively reduces RC delay and extends charging time, but also avoids the wiring pads and anti-static circuits on both sides of the display substrate, effectively avoiding mutual interference between the gate driver circuit and the anti-static circuit. In the present disclosure, the parallel-connected first capacitor, second capacitor, and storage capacitor minimize the space occupied by the first capacitor, second capacitor, and storage capacitor while ensuring capacitance, which is advantageous for achieving high-resolution display. In the present disclosure, the high-voltage and low-voltage power lines are formed with a net-like interconnect structure, which minimizes the resistance of the power transmission line and reduces power supply voltage drop, effectively improving power supply voltage uniformity on the display substrate, effectively improving signal plane uniformity, effectively improving display uniformity, and improving display attributes and display quality. The manufacturing process of the present disclosure is highly compatible with conventional manufacturing processes, is simple and easy to implement, has high production efficiency, low production costs, and a high yield rate.

[0417] It should be noted that the structures and manufacturing processes shown in the exemplary embodiments of the present disclosure are merely examples, and the corresponding structures can be modified or patterning processes can be added or removed according to actual needs, and the embodiments of the present disclosure are not specifically limited here.

[0418] The display substrate according to the exemplary embodiments of the present disclosure can be applied to any LED driving pixel circuit, including P-type PAM, P-type PAM+PWM, N-type PAM, N-type PAM+PWM, LTPO-type PAM and PAM+PWM circuits, etc.

[0419] 36 is a schematic diagram of wiring of another gate driving circuit in an exemplary embodiment of the present disclosure. As shown in Fig. 36, the pixel driving circuit of circuit unit Q is connected to a data signal line and a driving signal line, and the gate driving circuit of gate unit G is connected to a first clock signal line, a second clock signal line, a high voltage line, and a low voltage line.

[0420] In an exemplary embodiment, the first clock signal line CLK, the second clock signal line CLKB, the high voltage line VGH, and the low voltage line VGL may have a linear shape extending along the second direction Y, the data signal line DataI may have a linear shape extending along the second direction Y, the orthogonal projection of the first clock signal line CLK and the second clock signal line CLKB on the display substrate plane may not overlap with the orthogonal projection of the data signal line DataI on the display substrate plane, and the first clock signal line CLK and the second clock signal line CLKB may be basically parallel to the data signal line DataI.

[0421] In an exemplary embodiment, the driving signal lines of one unit row in the first circuit area 210 may include at least a first scanning signal line S1, a second scanning signal line S2 and an emission signal line EM, and the gate driving circuit in one gate unit G may include at least a first GOA circuit G1, a second GOA circuit G2 and an EOA circuit G3, where the first GOA circuit G1 is connected to the first scanning signal line S1 via a first output line OUT1, the second GOA circuit G2 is connected to the second scanning signal line S2 via a second output line OUT2, and the EOA circuit G3 is connected to the emission signal line EM via a third output line OUT3.

[0422] In an exemplary embodiment, the first GOA circuit G1, the second GOA circuit G2 and the EOA circuit G3 in one gate unit G may be sequentially arranged along the first direction X, and are respectively connected to the first clock signal line CLK via the first clock connection line CK1, and respectively connected to the second clock signal line CLKB via the second clock connection line CK2.

[0423] In an exemplary embodiment, the orthogonal projection of the first GOA circuit G1, the second GOA circuit G2 and / or the EOA circuit G3 on the reference line O1 at least partially overlaps with the orthogonal projection of at least one pixel driving circuit on the reference line O1.

[0424] In an exemplary embodiment, the orthogonal projection of the first GOA circuit G1, the second GOA circuit G2 and / or the EOA circuit G3 on the display substrate plane does not overlap with the orthogonal projection of the data signal line DataI on the display substrate plane.

[0425] In an exemplary embodiment, the orthogonal projection of the first GOA circuit G1, the second GOA circuit G2 and / or the EOA circuit G3 on the display substrate plane does not overlap with the orthogonal projection of the data signal line DataI on the display substrate plane.

[0426] In an exemplary embodiment, the first clock connection line CK1 and the second clock connection line CK2 may have a linear shape extending along the first direction X, and the orthogonal projection of the first clock connection line CK1 and the second clock connection line CK2 on the display substrate plane at least partially overlaps with the orthogonal projection of the data signal line DataI on the display substrate plane.

[0427] In an exemplary embodiment, the first clock connection line CK1 and the second clock connection line CK2 transmit clock signals, so there is overlap capacitance between the clock signal line and the data signal line in this embodiment. The voltage change of the clock signal line is VGH / VGL, and the coupling capacitance between the clock signal line and the data signal line is C ck_cp and the load capacitance of the data signal line is C data Then, the voltage jump of the data signal line affected by the clock signal line coupling is ΔV data is.

[0428] [ka]

[0429] After filling the gamma curve, the voltage jump ΔV data are the voltage levels of two adjacent grayscales, V step If the voltage jump is smaller than , there will be no gray scale difference, i.e., the following formula is satisfied:

[0430] [ka]

[0431] In an exemplary embodiment, V stepis usually about 2mV to 3mV, and the VGH-VGL difference is usually about 20V. ck_cp is C data It should be less than / 10fF.

[0432] In an exemplary embodiment of the present disclosure, it is proposed to divide the gate unit so that it can be applied to a situation where the space of the second circuit area is limited, etc. In this proposal, although there is overlap capacitance between the clock signal line and the data signal line, the coupling capacitance C ck_cp C data As long as the setting requirement of less than / 10fF is met, the jump of the data voltage on the data signal line can be effectively avoided and the display attributes can be guaranteed.

[0433] An exemplary embodiment of the present disclosure further provides a method for manufacturing the above-mentioned display substrate, wherein the display substrate includes a plurality of first circuit regions and a plurality of second circuit regions alternately arranged along a second direction, the first circuit region includes a plurality of repeat units and a plurality of blank units alternately arranged along the first direction, the repeat units include a plurality of circuit units, the second circuit region includes at least one gate unit, the first direction and the second direction intersect, and the manufacturing method includes: The method may include forming a pixel driving circuit and data signal lines and driving signal lines connected to the pixel driving circuit in the circuit unit, and forming at least one gate driving circuit and a clock signal line connected to the gate driving circuit in the gate unit, wherein the gate driving circuit is connected to the driving signal lines in an adjacent circuit unit, and orthogonal projections of the data signal lines on the display substrate plane do not overlap with orthogonal projections of the clock signal lines on the display substrate plane.

[0434] An exemplary embodiment of the present disclosure further provides a display device, comprising the display substrate of the above embodiment. The display device may be a product or component with a display function, such as a mobile phone, a tablet, a television, a monitor, a laptop, a digital frame, or a navigation device.

[0435] The drawings in this disclosure only relate to the structures disclosed herein, and other structures may refer to conventional designs. Where there is no conflict, the embodiments and features of the embodiments in this disclosure may be combined with each other to obtain new embodiments. As will be understood by those skilled in the art, modifications or equivalent substitutions may be made to the technical solutions of this disclosure without departing from the spirit and scope of the technical solutions of this disclosure. Any such modifications or equivalent substitutions should be included within the scope of the claims of this disclosure. [Explanation of symbols]

[0436] AT1: first active layer, AT2: second active layer, AT3: third active layer, AT4: 4th active layer, AT5: 5th active layer, AT6: 6th active layer, AT7: 7th active layer, AT8: 8th active layer, AT9: 9th active layer, AT10: 10th active layer, AT11: 11th active layer, AT21: 21st active layer, AT22: 22nd active layer, AT23: 23rd active layer, AT24: 24th active layer, AT25: 25th active layer, AT26: 26th active layer, AT27: 27th active layer, AT28: 28th active layer, CF1: 1st electrode plate, CF2: 2nd electrode plate, CF3: 3rd pole plate, CF4: 4th pole plate, CF5: 5th pole plate, CF6: 6th pole plate, CF7: 7th pole plate, CF8: 8th pole plate, CF9: 9th electrode plate, CF11: 11th electrode plate, CF12: 12th electrode plate, CF13: 13th electrode plate, CF14: 14th electrode plate, Cs: storage capacitor, C1: first capacitor, C2: second capacitor, CT1: first control line, CT2: second control line, CLK: first clock signal line, CLKB: second clock signal line, DataI: data signal line, DataT: time length signal line, EM: light emission signal line, Gate1: first gate electrode, Gate2: second gate electrode, Gate3-B: third bottom gate electrode, Gate3-T: third top gate electrode, Gate4: fourth gate electrode, Gate5: fifth gate electrode, Gate6: sixth gate electrode, Gate7: seventh gate electrode, and Gate8: eighth gate electrode. Gate9: ninth gate electrode, Gate10: tenth gate electrode, Gate11: eleventh gate electrode, Gate21: 21st gate electrode, Gate22: 22nd gate electrode, Gate23: 23rd gate electrode, Gate24: 24th gate electrode, Gate25: 25th gate electrode, Gate26: 26th gate electrode, Gate27: 27th gate electrode, Gate28: 28th gate electrode, Hf: high frequency signal line, Hf-C: High frequency connection line, MARK1: First mark, MARK2: Second mark, S1: first scanning signal line, S2: second scanning signal line, VDD: high voltage power supply line, VDD-C: High voltage connection line, VSS: Low voltage power supply line, VSS-C: Low voltage connection line, Vint: initial signal line, VGH: high voltage line, VGL: low voltage line, 10: base, 11: first anode connecting wire, 12: second anode connecting wire, 13: anode connection block; 14: anode connection electrode; 20: driving structure layer; 30: light-emitting structure layer, 40: light-emitting diode, 100: motherboard, 200: Display board, 210: First circuit area, 220: Second circuit area.

Claims

1. a display substrate including a plurality of first circuit regions and a plurality of second circuit regions alternately arranged along a second direction, the first circuit region including a plurality of repeat units and a plurality of blank units alternately arranged along a first direction, the first direction and the second direction intersect, the repeat unit including a plurality of circuit units, the circuit unit including a pixel driving circuit and a data signal line and a driving signal line connected to the pixel driving circuit, the second circuit region including at least one gate unit, the gate unit including at least one gate driving circuit, the gate driving circuit connected to the driving signal line in an adjacent circuit unit, and orthogonal projections of the gate driving circuit on a plane of the display substrate do not overlap with orthogonal projections of the data signal lines on the plane of the display substrate.

2. 2. The display substrate of claim 1, wherein at least one second circuit area has a reference line, the reference line being a straight line that equally divides the second circuit area in the second direction and extends along the first direction, and an orthogonal projection of at least one gate driving circuit on the reference line at least partially overlaps an orthogonal projection of at least one blank unit on the reference line.

3. 3. The display substrate of claim 2, wherein at least one gate driving circuit is further connected to a clock signal line, a high-voltage line, and a low-voltage line, wherein in the first direction, the clock signal line is disposed between the high-voltage line and the low-voltage line, and an orthogonal projection of the clock signal line on the display substrate plane does not overlap with an orthogonal projection of the data signal line on the display substrate plane.

4. 4. The display substrate of claim 3, wherein, in the first direction, the data signal lines are disposed on the side of the high-voltage lines away from the clock signal lines, or the data signal lines are disposed on the side of the low-voltage lines away from the clock signal lines.

5. 5. The display substrate of claim 4, wherein in the first direction, there is a first distance between an edge of the high-voltage line closer to the data signal line and an edge of the data signal line closer to the high-voltage line, and there is a second distance between an edge of the low-voltage line closer to the data signal line and an edge of the data signal line closer to the low-voltage line, the second distance being greater than the first distance.

6. The display substrate of claim 5 , wherein the first distance is equal to or greater than 25 μm and the second distance is equal to or greater than 25 μm.

7. 4. The display substrate of claim 3, wherein the clock signal lines include a first clock signal line and a second clock signal line, the second clock signal line being disposed on a side of the first clock signal line away from the low-voltage line, a third distance being between an edge of the first clock signal line closer to the low-voltage line and an edge of the low-voltage line closer to the first clock signal line, and a fourth distance being between an edge of the second clock signal line closer to the high-voltage line and an edge of the high-voltage line closer to the second clock signal line, the third distance being greater than the fourth distance.

8. 2. The display substrate of claim 1, wherein at least one drive signal line is connected to one gate drive circuit, the gate drive circuit is provided in a first midline region of the second circuit region, the gate drive circuit is connected to a first midpoint region of the drive signal line via an output line, the first midline region is a region including a first midline, the first midpoint region is a region including a first midpoint, widths of the first midline region and the first midpoint region in the first direction are 1% to 10% of the width of the display substrate, the first midline is a straight line that equally divides the second circuit region in the first direction and extends along the second direction, the first midpoint is a point that equally divides the drive signal line in the first direction, and the width of the display substrate is a dimension of the display substrate in the first direction.

9. at least one driving signal line is connected to a first gate driving circuit and a second gate driving circuit, the first gate driving circuit is provided in a second midline region of the second circuit region and is connected to a second midpoint region of the driving signal line via an output line, the second gate driving circuit is provided in a third midline region of the second circuit region and is connected to a third midpoint region of the driving signal line via an output line, the second midline region is a region including the second midline, the third midline region is a region including the third midline, the second midpoint region is a region including the second midpoint, and the third midpoint region is a region including the third midpoint, the widths of the second midline region, the third midline region, the second midpoint region and the third midpoint region in the first direction X are 1% to 10% of the width of the display substrate, 2. The display substrate of claim 1, wherein the second circuit region includes a first midline that equally divides the second circuit region in the first direction and extends along the second direction, the first midline divides the second circuit region into a first region and a second region, the second midline is a straight line that equally divides the first region in the first direction and extends along the second direction, the third midline is a straight line that equally divides the second region in the first direction and extends along the second direction, the drive signal lines include a first midpoint that equally divides the drive signal lines in the first direction, the first midpoint divides the drive signal lines into first line segments and second line segments, the second midpoint is a point that equally divides the first line segment in the first direction, and the third midpoint is a point that equally divides the second line segment in the first direction.

10. 3. The display substrate of claim 2, wherein at least one second circuit area has a reference line, the reference line being a straight line that equally divides the second circuit area in the second direction and extends along the first direction, and pixel driving circuits in first circuit areas on both sides of the second circuit area in the second direction are mirror-symmetric with respect to the reference line.

11. 3. The display substrate of claim 2, wherein at least one second circuit region further includes at least one first mark, and an orthogonal projection of the at least one first mark on the reference line at least partially overlaps with an orthogonal projection of the at least one blank unit on the reference line.

12. 3. The display substrate of claim 2, wherein at least one second circuit region further includes at least one second mark, and an orthogonal projection of the at least one second mark on the reference line at least partially overlaps with an orthogonal projection of the at least one blank unit on the reference line.

13. 13. The display substrate of claim 1, wherein, in a plane perpendicular to the display substrate, the display substrate includes a first gate metal layer, a second gate metal layer, a first source / drain metal layer, and a second source / drain metal layer sequentially disposed on a base, the driving signal lines being disposed on the second gate metal layer, and the data signal lines and the clock signal lines being disposed on the first source / drain metal layer.

14. 14. The display substrate of claim 13, wherein at least one second circuit region further includes at least one first mark and at least one second mark, the first mark being disposed in the first source / drain metal layer, and the second mark being disposed in the second source / drain metal layer.

15. 15. The display substrate of claim 14, further comprising a first planar layer and a first passivation layer, wherein the first planar layer is disposed on a side of the first source / drain metal layer away from the base, the first passivation layer is disposed on a side of the first planar layer away from the base, the second source / drain metal layer is disposed on a side of the first passivation layer away from the base, the first planar layer has a first mark hole exposing the first mark, an orthogonal projection of the first mark hole on the plane of the base includes an orthogonal projection of the first mark on the plane of the base, and the first passivation layer covers the first mark in the first mark hole.

16. 15. The display substrate of claim 14, further comprising a second passivation layer and a second planar layer, wherein the second passivation layer is disposed on a side of the second source / drain metal layer away from the base, the second planar layer is disposed on a side of the second passivation layer away from the base, the second planar layer is disposed with a second mark hole and a third mark hole, the second mark hole exposes the second passivation layer covering the second mark, an orthogonal projection of the second mark hole on the plane of the base includes an orthogonal projection of the second mark on the plane of the base, and the third mark hole exposes the second passivation layer covering the first mark, and an orthogonal projection of the third mark hole on the plane of the base includes an orthogonal projection of the first mark on the plane of the base.

17. A display device comprising the display substrate according to any one of claims 1 to 16.

18. A method for manufacturing a display substrate, the display substrate including a plurality of first circuit regions and a plurality of second circuit regions alternately arranged along a second direction, the first circuit region including a plurality of repeat units and a plurality of blank units alternately arranged along the first direction, the repeat units including a plurality of circuit units, the second circuit region including at least one gate unit, the first direction and the second direction intersect, the manufacturing method comprising: forming a pixel driving circuit and data signal lines and driving signal lines connected to the pixel driving circuit in the circuit unit, and forming at least one gate driving circuit and a clock signal line connected to the gate driving circuit in the gate unit, wherein the gate driving circuit is connected to the driving signal lines in an adjacent circuit unit, and orthogonal projections of the data signal lines on the plane of the display substrate do not overlap with orthogonal projections of the clock signal lines on the plane of the display substrate.

Images