Radio frequency power amplifier with off-mode output impedance control and process for implementing same

Abstract

The device may include an input port, an RF output port, an RF amplifier device, and an off-mode output impedance control.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Application No. 18 / 061,246, filed December 2, 2022, which is incorporated by reference in its entirety for all purposes as if fully set forth herein.

[0002] The present disclosure relates to a radio frequency power amplifier that implements off-mode output impedance control. Additionally, the present disclosure relates to a process for implementing a radio frequency power amplifier that implements off-mode output impedance control. [Background technology]

[0003] Radio frequency (RF) power amplifiers are used in a variety of applications, such as base stations for wireless communication systems, wireless communication devices, and / or the like. RF power amplifiers typically include a transistor die to amplify RF signals. These devices typically have a relatively low characteristic impedance (e.g., 2 ohms or less). Input and output impedance matching circuits are typically used to match the RF power amplifier to external transmission lines that provide RF signals to and from the RF power amplifier. These external transmission lines typically have a characteristic impedance that is approximately 50 ohms. However, the characteristic impedance can be any value as determined by the designer, as required for a particular application and / or system, and / or the like. The input and output matching circuits typically include inductive and capacitive elements used to provide impedance matching between the input and output of the RF power amplifier.

[0004] Due to the nature of RF power amplifiers, one or more scattering parameters or S-parameters, such as S22, are typically not control parameters for achieving amplifier performance such as efficiency, power, gain, and / or the like. In particular, the S22 parameter, which may also be referred to as output impedance, is typically not a control parameter for achieving amplifier performance such as efficiency, power, gain, and / or the like. In this regard, the S22 parameter is the output port voltage reflection coefficient. For RF power amplifiers where gain is the only concern, the S22 parameter is typically controlled and close to a target impedance in the ON mode, also referred to as the operating mode or bias mode.

[0005] However, some specific applications require RF power amplifiers to present close to a 50 ohm impedance in the OFF mode, also known as the non-operating or unbiased mode. Such a specification is often referred to as the OFF mode S22.

[0006] Amplifying devices such as field-effect transistors (FETs), bipolar devices such as gallium nitride (GaN) devices, metal-oxide-semiconductor field-effect transistor (MOSFET) devices, laterally diffused MOSFET (LDMOS) devices, complementary metal-oxide-semiconductor (CMOS) devices, and / or the like, have dramatically different impedances in ON and OFF modes. In this regard, in many cases, in OFF mode, the impedance of the device is actually closer to the outer edge of the Smith chart. For example, the S22 parameter is typically about -1 dB, while the target is approximately less than -10 dB. Therefore, without specific impedance control, it is impossible to meet the OFF mode impedance, other amplifier specifications described herein, and / or the like.

[0007] Current technology typically does not implement OFF mode impedance control, however, it is sometimes possible to slightly modify this particular OFF mode S22 parameter by sacrificing other parameters, without completely achieving the desired OFF mode S22 parameter.

[0008] Circulators are sometimes used when both ON-mode and OFF-mode impedances are important. Due to their size, circulators cannot be practically implemented within a module. Furthermore, because circulators are typically implemented within the line, they also introduce some loss, degradation, and / or the like. When a transmit / receive (T / R) switch is used, such as in a time-division duplex (TDD) system, the S22 parameter OFF-mode impedance is equal to the Rx input impedance. This provides a suitable OFF-mode impedance, but also includes losses. In this regard, it is important to ensure that the transmit / receive (T / R) switch is appropriately sized so as not to degrade the overall amplifier third-order intercept (IP3).

[0009] Therefore, there is a need to implement an RF power amplifier that is configured to provide OFF mode impedance control that has limited impact on RF power amplifier performance. Summary of the Invention

[0010] In one general aspect, the RF power amplifier circuit includes an input port. The RF power amplifier circuit additionally includes an RF output port. The RF power amplifier circuit further includes an RF amplifier device. The RF power amplifier circuit also includes an off-mode output impedance control.

[0011] In one general aspect, a process includes providing an input port. The process additionally includes providing an RF output port. The process includes providing an RF amplifier device. The process also includes providing an off-mode output impedance control.

[0012] In one general aspect, an RF power amplifier circuit includes an input port. The RF power amplifier circuit additionally includes an RF output port. The RF power amplifier circuit includes an RF amplifier device. The RF power amplifier circuit also includes an output impedance control section, which may include an impedance circuit and at least one switch circuit.

[0013] In one general aspect, the process includes providing an input port. The process additionally includes providing an RF output port. The process includes providing an RF amplifier device. The process further includes providing an output impedance control, which may also include an impedance circuit and at least one switch circuit.

[0014]

[0013] Additional features, advantages, and aspects of the present disclosure may be set forth in or apparent from a consideration of the following detailed description, drawings, and claims. Moreover, both the foregoing summary of the present disclosure and the following detailed description are exemplary and intended to provide further explanation without limiting the scope of the disclosure as claimed.

[0015] The accompanying drawings, which are included to provide a further understanding of the present disclosure, are incorporated in and constitute a part of this specification, illustrate aspects of the disclosure, and together with the detailed description, serve to explain the principles of the disclosure. No attempt is made to show structural details of the disclosure in more detail than may be necessary for a basic understanding of the disclosure and the various ways in which it may be practiced. [Brief explanation of the drawings]

[0016] [Figure 1]FIG. 1 is a functional block diagram of an RF power amplifier circuit according to the present disclosure. [Figure 2] FIG. 10 illustrates simulation results for an off-mode power amplifier implemented without the off-mode output impedance controller of the present disclosure. [Figure 3] FIG. 10 illustrates simulation results of an off-mode power amplifier implemented with the off-mode output impedance controller of the present disclosure. [Figure 4] FIG. 1 illustrates an exemplary embodiment of an off-mode output impedance control section according to aspects of the present disclosure. [Figure 5] FIG. 1 illustrates an exemplary embodiment of an off-mode output impedance control section according to aspects of the present disclosure. [Figure 6] FIG. 1 illustrates an exemplary embodiment of an off-mode output impedance control section according to aspects of the present disclosure. [Figure 7] FIG. 1 illustrates an exemplary embodiment of an off-mode output impedance control section according to aspects of the present disclosure. [Figure 8] FIG. 1 illustrates an exemplary embodiment of an off-mode output impedance control section according to aspects of the present disclosure. [Figure 9] FIG. 10 illustrates an exemplary embodiment of an impedance circuit in an off-mode output impedance control section according to aspects of the present disclosure. [Figure 10] FIG. 10 illustrates an exemplary embodiment of an impedance circuit in an off-mode output impedance control section according to aspects of the present disclosure. [Figure 11] FIG. 10 illustrates an exemplary embodiment of an impedance circuit in an off-mode output impedance control section according to aspects of the present disclosure. [Figure 12] FIG. 10 illustrates an exemplary embodiment of an impedance circuit in an off-mode output impedance control section according to aspects of the present disclosure. [Figure 13] FIG. 1 illustrates various regions in which the S22 parameter of a power amplifier may operate. [Figure 14A] FIG. 1 illustrates an exemplary embodiment of an off-mode output impedance control section according to aspects of the present disclosure. [Figure 14B] FIG. 1 illustrates an exemplary embodiment of an off-mode output impedance control section according to aspects of the present disclosure. [Figure 14C] FIG. 1 illustrates an exemplary embodiment of an off-mode output impedance control section according to aspects of the present disclosure. [Figure 14D] FIG. 1 illustrates an exemplary embodiment of an off-mode output impedance control section according to aspects of the present disclosure. [Figure 14E] FIG. 1 illustrates an exemplary embodiment of an off-mode output impedance control section according to aspects of the present disclosure. [Figure 14F] FIG. 1 illustrates an exemplary embodiment of an off-mode output impedance control section according to aspects of the present disclosure. [Figure 15] 1 is an enlarged partial layout diagram of an exemplary embodiment of an RF amplifying transistor device according to the present disclosure. [Figure 16] FIG. 16 is a schematic cross-sectional view taken along line XX in FIG. 15. [Figure 17] FIG. 1 illustrates a process for implementing a package according to the present disclosure. [Figure 18] FIG. 10 illustrates simplified S22 parameters for a power amplifier without an implementation of an off-mode output impedance controller according to the present disclosure. [Figure 19] FIG. 10 illustrates rotated S22 parameters for a power amplifier without a full implementation of the off-mode output impedance control in accordance with the present disclosure. [Figure 20] FIG. 10 illustrates S22 parameters of a power amplifier with an implementation of an off-mode output impedance controller according to the present disclosure. [Figure 21A] 2 is a block diagram of an exemplary embodiment of the RF power amplifier circuit according to FIG. 1 implemented as a multi-stage Doherty power amplifier module (PAM). [Figure 21B] FIG. 1 illustrates an exemplary embodiment of a massive multiple-input multiple-output (MMIMO) simplified front-end antenna architecture according to aspects of the present disclosure. [Figure 21C]2 is a block diagram of an exemplary embodiment of the RF power amplifier circuit according to FIG. 1 implemented as a single-pass multi-stage amplifier. [Figure 21D] 2 is a block diagram of an exemplary embodiment of the RF power amplifier circuit according to FIG. 1 implemented as a multi-stage amplifier, the final stage of which is a Doherty. [Figure 21E] 2 is a block diagram of an exemplary embodiment of the RF power amplifier circuit according to FIG. 1 implemented as a multi-stage amplifier, the final stage being either a quadrature stage or a balanced stage. [Figure 22A] 14E is a graph of power handling of at least one switch circuit of FIG. 14E implementing off-mode S22 correction according to an embodiment of the present disclosure. [Figure 22B] 14F is a graph of power handling of at least one switch circuit of FIG. 14F implementing off mode S22 correction according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0017] Aspects of the present disclosure and their various features and advantageous details will be more fully described with reference to non-limiting embodiments and examples illustrated and / or depicted in the accompanying drawings and detailed in the following description. It should be noted that the features illustrated in the drawings are not necessarily drawn to scale, and that features of one embodiment may be used with other embodiments, as would be understood by those skilled in the art, even if not explicitly stated herein. Descriptions of well-known components and processing techniques may be omitted so as not to unnecessarily obscure aspects of the present disclosure. The examples used herein are intended only to facilitate an understanding of how the present disclosure may be practiced and to further enable those skilled in the art to practice aspects of the present disclosure. Therefore, the examples and embodiments herein should not be construed as limiting the scope of the present disclosure, which is defined solely by the appended claims and applicable law. Furthermore, it should be noted that like reference numerals represent like parts throughout the several views.

[0018] Terms such as first, second, etc. may be used herein to describe various elements, but it should be understood that these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0019] When an element such as a layer, region, or substrate is referred to as being "on" or extending "onto" another element, it is understood that it may be directly on or extending directly onto the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements. Similarly, when an element such as a layer, region, or substrate is referred to as being "over" or extending "over" another element, it is understood that it may be directly on or extending directly onto the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly over" or extending "directly onto" another element, there are no intervening elements. When an element is referred to as being "connected" or "coupled" to another element, it should be understood that it may be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0020] Relative terms such as "bottom" or "top" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe the relationship of one element, layer, or region to another, as illustrated in the figures. It should be understood that these terms, and those discussed above, are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0021] The terminology used herein is for the purpose of describing particular aspects only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should be further understood that the terms "comprises," "comprising," "includes," and / or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0022] Unless otherwise specified, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms used herein should be interpreted as having a meaning consistent with their meaning in the context of the present specification and the related art, and should not be interpreted in an idealized or overly formal sense, unless expressly defined as such in the present specification.

[0023] Aspects of the present disclosure may be implemented in any RF power amplifier for which an S22 parameter specification in OFF mode exists, is beneficial, is required, and / or is similar. For example, the S22 parameter OFF mode specification may relate to a need within a system for partially shutting down and / or partially operating one or more power amplifiers. In this regard, this may relate to multiple-input multiple-output (MIMO) systems, massive MIMO (mMIMO) systems, 5G systems, and / or the like. Furthermore, this may relate to the coexistence of one or more power amplifiers within a wireless device. A "wireless device" is intended to encompass any compatible mobile technology computing device capable of connecting to a wireless communications network, such as a mobile phone, mobile device, mobile station, user equipment, mobile phone, smartphone, handset, wireless dongle, remote alert device, Internet of Things (IoT)-based wireless device, or other mobile computing device that may be supported by a wireless network. The OFF mode S22 parameter is often an issue when there is coexistence of several amplifiers within a system.

[0024] Embodiments of the present disclosure may provide OFF mode control using an additional OFF mode switch that performs impedance compensation. Embodiments of the present disclosure may implement a switch circuit, such as a field effect transistor (FET) switch circuit. Embodiments of the present disclosure may implement a switch at the output of a module, amplifier, and / or the like. Embodiments of the present disclosure may be implemented without a circulator. Embodiments of the present disclosure may be implemented such that the S22 parameter in OFF mode is significantly closer to 50 ohms.

[0025] FIG. 1 illustrates a functional block diagram of an RF power amplifier circuit according to the present disclosure.

[0026] 1 illustrates an RF power amplifier circuit 100. The RF power amplifier circuit 100 may include an input port 102, an RF output port 104, and a reference potential port 106. The RF power amplifier circuit 100 may additionally include an RF amplifier device 108, an output impedance matching network 147, and an off-mode output impedance control section 190. In an aspect, the RF power amplifier circuit 100 may additionally include an input impedance matching network 146, although the embodiment of the input impedance matching network 146 is not necessarily directly related to the disclosed embodiment of the off-mode output impedance control section 190. In an aspect, the RF power amplifier circuit 100 may be implemented in a system in which the RF power amplifier circuit 100 may operate in an on mode, and the RF power amplifier circuit 100 may be implemented in a system in which the RF power amplifier circuit 100 may also be configured in an off mode.

[0027] In an aspect, the RF power amplifier circuit 100 configured with the off-mode output impedance control unit 190 may be an embodiment in which an S22 parameter specification in the OFF mode exists, is beneficial, is required, and / or is the same. For example, the S22 parameter OFF-mode specification may relate to a need within a system implementing the RF power amplifier circuit 100 to partially shut down and / or only partially operate one or more embodiments of the RF power amplifier circuit 100. In this regard, the RF power amplifier circuit 100 configured with the off-mode output impedance control unit 190 may be implemented in one or more of a multiple-input multiple-output (MIMO) system, a massive MIMO (mMIMO) system, a 5G system, and / or the like. Furthermore, the RF power amplifier circuit 100 configured with the off-mode output impedance control unit 190 may be implemented to coexist with one or more other power amplifiers within a wireless device, as defined herein.

[0028] In embodiments, an RF power amplifier circuit 100 configured with an off-mode output impedance control unit 190 may address the off-mode S22 parameter, which can often be problematic when several amplifiers coexist in a system. Embodiments of the present disclosure may implement an RF power amplifier circuit 100 configured with an off-mode output impedance control unit 190 without a circulator. Embodiments of the present disclosure may implement an RF power amplifier circuit 100 configured with an off-mode output impedance control unit 190 such that the S22 parameter in the OFF mode is significantly closer to 50 ohms.

[0029] In an embodiment, the off mode output impedance control unit 190 may control the associated S22 parameter of the RF power amplifier circuit 100 in the off mode so that the S22 parameter of the RF power amplifier circuit 100 in the off mode is less than −7 dB, less than −10 dB, less than −15 dB, less than −20 dB, or less than −25 dB. In an embodiment, the off mode output impedance control unit 190 may control the associated S22 parameter of the RF power amplifier circuit 100 in the off mode so that the output impedance of the RF power amplifier circuit 100 in the off mode is 17 ohms to 150 ohms, 25 ohms to 100 ohms, 33 ohms to 75 ohms, or 45 ohms to 55 ohms.

[0030] The RF amplifier device 108 may have an input terminal 110 electrically coupled to the input port 102 through an input impedance matching network 146. The RF amplifier device 108 may include an output terminal 112 electrically coupled to the RF output port 104, and a reference potential terminal 114 electrically coupled to the reference potential port 106. Additionally, the RF power amplifier circuit 100 may further include an off-mode output impedance control section 190 electrically coupled between the output terminal 112 and the RF output port 104.

[0031] In one or more embodiments, the off-mode output impedance control unit 190 may be integrated into the RF power amplifier circuit 100, the off-mode output impedance control unit 190 may be integrated into a package that houses the RF power amplifier circuit 100, the off-mode output impedance control unit 190 may be implemented within the RF power amplifier circuit 100 that is separate from the system that implements the RF power amplifier circuit 100, and / or the like.

[0032] In embodiments, input impedance matching network 146 and output impedance matching network 147 may be implemented using various circuit combinations of one or more capacitors, one or more inductors, and / or the like.

[0033] FIG. 2 illustrates simulation results of an off-mode power amplifier implemented without the off-mode output impedance control of the present disclosure.

[0034] In particular, Figure 2 illustrates simulation results of the S22 parameter for an off-mode power amplifier implemented without the off-mode output impedance control 190 of the present disclosure. The S22 parameter is indicated by a dashed line. More specifically, Figure 2 illustrates simulation results of the S22 parameter for an off-mode power amplifier implemented without the off-mode output impedance control 190 of the present disclosure, the amplifier implemented using 40 dBm at 2.5 to 2.7 GHz. As illustrated by Figure 2, the S22 parameter of the power amplifier is approximately -1.5 dB and approximately 4 ohms, which is unsatisfactory for many systems.

[0035] FIG. 3 illustrates simulation results of an off-mode power amplifier implemented with the off-mode output impedance controller of the present disclosure.

[0036] In particular, FIG. 3 illustrates simulation results of the S22 parameter of an off-mode power amplifier implemented with the off-mode output impedance control 190 of the present disclosure. The S22 parameter is indicated by a dashed line. More specifically, FIG. 3 illustrates simulation results of the S22 parameter of an off-mode power amplifier implemented with the off-mode output impedance control 190 of the present disclosure, the amplifier implemented with 40 dBm at 2.5 to 2.7 GHz. As illustrated by FIG. 3, the S22 parameter of the power amplifier is approximately −10 dB or better, and an output impedance of 25 to 100 ohms, which is satisfactory for many systems where the system impedance is 50 ohms and the impedance can vary by a factor of two.

[0037] FIG. 4 illustrates an exemplary embodiment of an off-mode output impedance control section according to aspects of the present disclosure.

[0038] In particular, FIG. 4 illustrates an exemplary embodiment of an off-mode output impedance control section 190. The aspect of FIG. 4 may include any other aspect as disclosed herein, and further, the aspect of FIG. 4 may be implemented in other aspects described herein. The off-mode output impedance control section 190 may include a main line 202, an impedance circuit 204, and at least one switch circuit 206. The main line 202 may extend between the output terminal 112 and the RF output port 104 of the RF power amplifier circuit 100. Additionally, the impedance circuit 204 and the at least one switch circuit 206 may connect to the main line 202, and the impedance circuit 204 and the at least one switch circuit 206 may connect to ground 208. Furthermore, the at least one switch circuit 206 may include a control input 210. As illustrated in FIG. 4, the impedance circuit 204 may be connected in series with the at least one switch circuit 206 between ground 208 and the main line 202.

[0039] In an embodiment, the at least one switch circuit 206 may be active when the RF power amplifier circuit 100 is inactive, and vice versa. In this regard, the control input 210 may control the at least one switch circuit 206 to be active when the RF power amplifier circuit 100 is inactive, and the control input 210 may control the at least one switch circuit 206 to be inactive when the RF power amplifier circuit 100 is active. In an embodiment, the control input 210 may be implemented at a system level using an additional input associated with the RF power amplifier circuit 100, such as an input pin, to receive a signal and provide the signal as the control input 210 to the at least one switch circuit 206. In an embodiment, the control input 210 may be implemented in a controller associated with the RF power amplifier circuit 100, such as a controller chip, to provide the signal as the control input 210 to the at least one switch circuit 206. In a particular embodiment, the controller may implement four controls used for a driver device, a carrier device, and a peaker device. Thus, the fourth control may be utilized to provide a control input 210 to at least one switch circuit 206 .

[0040] Embodiments of off-mode output impedance control 190 may implement OFF-mode control using at least one switch circuit 206 implemented as an OFF-mode switch that implements impedance compensation. Impedance circuit 204 may be configured in off-mode output impedance control 190 to provide impedance compensation. In embodiments, at least one switch circuit 206 may be implemented with multiple switching devices in series. In embodiments, at least one switch circuit 206 may be implemented as a FET. However, at least one switch circuit 206 may be implemented with any type of transistor switch, including a CMOS switch, a GaAs FET switch, a GaN FET switch, a bipolar switch, a solid-state relay, an optocoupler, and / or the like.

[0041] In an aspect, the at least one switch circuit 206 may be implemented as a FET. However, the at least one switch circuit 206 and / or the off-mode output impedance control section 190 may further include support components not illustrated, such as decoupling circuits, biasing circuits, and / or the like. The switch device embodiment of the at least one switch circuit 206 may need to be biased, and the breakdown voltage of the switch device embodiment of the at least one switch circuit 206 may be essential to functionality as it relates to the amount of power being transferred.

[0042] In this regard, the switch device embodiment of the at least one switch circuit 206 may be implemented as a stack of switch devices, such as FETs, to handle the total voltage excursion of the output power of the RF power amplifier circuit 100. A typical maximum excursion in a linear implementation of a power amplifier is usually Z0=50, equal to sqrt(8*Pmax*Z0). For ultra-high power amplifiers, the switch device embodiment of the at least one switch circuit 206 may utilize GaN devices due to their high breakdown and good heat dissipation. There are other considerations for the switch device embodiment of the at least one switch circuit 206, such as an adequate margin to avoid breakdown. For example, in implementing FETs for the switch device embodiment of the at least one switch circuit 206, the FET size needs to be considered to avoid any degradation in linearity. Therefore, the number of FETs implemented by the at least one switch circuit 206 may need to be increased accordingly. Because breakdown voltage is not a variable in each process, the switch device embodiment of the at least one switch circuit 206, such as FETs, is typically stacked.

[0043] In an embodiment, operation of the off-mode output impedance control section 190 to provide impedance compensation for the RF power amplifier circuit 100 may be implemented by closing at least one switch circuit 206 to close a circuit between ground 208 and the main line 202 and provide the impedance compensation provided by the impedance circuit 204. In an embodiment, the closing of the at least one switch circuit 206 may be in response to receiving a signal at a control input 210. In an embodiment, the at least one switch circuit 206 may be a transistor, and the control input 210 may provide an input to control the switch (the control terminal of the switch may be a gate as in a FET device, a base as in a bipolar device, a logic input as in an optocoupler, etc.).

[0044] 4, the impedance circuit 204 may be connected to the main line 202, and the at least one switch circuit 206 may be connected to ground 208. In an embodiment, the impedance circuit 204 may be connected directly to the main line 202, and the at least one switch circuit 206 may be connected directly to ground 208.

[0045] FIG. 5 illustrates an exemplary embodiment of an off-mode output impedance control section according to aspects of the present disclosure.

[0046] In particular, Figure 5 illustrates an example embodiment of off-mode output impedance control section 190. The aspects of Figure 5 may include any other aspects as disclosed herein, and further, the aspects of Figure 5 may be implemented with other aspects described herein.

[0047] 5, at least one switch circuit 206 may be connected to the main line 202, and the impedance circuit 204 may be connected to ground 208. In an embodiment, at least one switch circuit 206 may be connected directly to the main line 202, and the impedance circuit 204 may be connected directly to ground 208.

[0048] FIG. 6 illustrates an exemplary embodiment of an off-mode output impedance control section according to aspects of the present disclosure.

[0049] In particular, Figure 6 illustrates an example embodiment of off-mode output impedance control section 190. The aspects of Figure 6 may include any other aspects as disclosed herein, and further, the aspects of Figure 6 may be implemented with other aspects described herein.

[0050] 6, the off-mode output impedance control section 190 may further include a rotation circuit 212. The rotation circuit 212 may be disposed in line on the main line 202. In embodiments, the rotation circuit 212 may provide the required amount of phase rotation around 50 ohms (or any other system characteristic impedance). In embodiments, the rotation circuit 212 may be implemented using transmission lines of the same characteristic impedance, discrete component equivalents, and / or the like. Referring to FIG. 6, the impedance circuit 204 may be connected to the main line 202, and the at least one switch circuit 206 may be connected to ground 208. In embodiments, the impedance circuit 204 may be directly connected to the main line 202, and the at least one switch circuit 206 may be directly connected to ground 208.

[0051] FIG. 7 illustrates an exemplary embodiment of an off-mode output impedance control section according to aspects of the present disclosure.

[0052] In particular, Figure 7 illustrates an example embodiment of off-mode output impedance control section 190. The aspects of Figure 7 may include any other aspects as disclosed herein, and furthermore, the aspects of Figure 7 may be implemented with other aspects described herein.

[0053] 7, the off-mode output impedance control section 190 may further include a rotation circuit 212. The rotation circuit 212 may be disposed in line on the main line 202. In an embodiment, the rotation circuit 212 may provide approximately 50 ohms of rotation. Referring to FIG. 7, the impedance circuit 204 may be connected to the main line 202, and the at least one switch circuit 206 may be connected to ground 208. In an embodiment, the impedance circuit 204 may be directly connected to the main line 202, and the at least one switch circuit 206 may be directly connected to ground 208.

[0054] FIG. 8 illustrates an exemplary embodiment of an off-mode output impedance control section according to aspects of the present disclosure.

[0055] In particular, FIG. 8 illustrates an exemplary embodiment of the off-mode output impedance control section 190. The embodiment of FIG. 8 may include any other embodiment as disclosed herein, and further, the embodiment of FIG. 8 may be implemented in other embodiments described herein. As illustrated in FIG. 8, the off-mode output impedance control section 190 may implement two or more separate embodiments of the at least one switch circuit 206 and two or more separate embodiments of the impedance circuit 204. The embodiments of the at least one switch circuit 206 and the impedance circuit 204 are not limited to the arrangement in FIG. 8 and may be arranged and structured according to other embodiments as described herein. In this regard, the embodiment of FIG. 8 may implement different types of impedance circuit 204. Thus, the RF power amplifier circuit 100 may be configured to implement one or more desired embodiments of the impedance circuit 204 as needed. A variety of impedance circuits 204 may be useful, for example, to cover large or diverse operating bandwidths.

[0056] FIG. 9 illustrates an exemplary embodiment of an impedance circuit in an off-mode output impedance control section according to aspects of the present disclosure.

[0057] In particular, Figure 9 illustrates an example embodiment of off-mode output impedance control section 190. The aspects of Figure 9 may include any other aspects as disclosed herein, and further, the aspects of Figure 9 may be implemented in other aspects described herein. As illustrated in Figure 9, impedance circuit 204 may be implemented with one or more capacitors, which may be connected to main line 202, impedance circuit 204, and ground 208, as illustrated in other aspects of the present disclosure.

[0058] FIG. 10 illustrates an exemplary embodiment of an impedance circuit in an off-mode output impedance control section according to aspects of the present disclosure.

[0059] In particular, Figure 10 illustrates an example embodiment of off-mode output impedance control section 190. The aspects of Figure 10 may include any other aspects as disclosed herein, and further, the aspects of Figure 10 may be implemented in other aspects described herein. As illustrated in Figure 10, impedance circuit 204 may be implemented with one or more capacitors in parallel with one or more resistors, which may be connected to main line 202, impedance circuit 204, and ground 208, as illustrated in other aspects of the present disclosure.

[0060] FIG. 11 illustrates an exemplary embodiment of an impedance circuit in an off-mode output impedance control section according to aspects of the present disclosure.

[0061] In particular, Figure 11 illustrates an example embodiment of off-mode output impedance control section 190. The aspects of Figure 11 may include any other aspects as disclosed herein, and further, the aspects of Figure 11 may be implemented in other aspects described herein. As illustrated in Figure 11, impedance circuit 204 may be implemented with one or more inductors, which may be connected to main line 202, impedance circuit 204, and ground 208, as illustrated in other aspects of the present disclosure.

[0062] FIG. 12 illustrates an exemplary embodiment of an impedance circuit in an off-mode output impedance control section according to aspects of the present disclosure.

[0063] In particular, Figure 12 illustrates an example embodiment of off-mode output impedance control section 190. The aspects of Figure 12 may include any other aspects as disclosed herein, and further, the aspects of Figure 12 may be implemented in other aspects described herein. As illustrated in Figure 12, impedance circuit 204 may be implemented with one or more inductors in parallel with one or more resistors, which may be connected to main line 202, impedance circuit 204, and ground 208, as illustrated in other aspects of the present disclosure.

[0064] FIG. 13 illustrates various regions in which the S22 parameter of a power amplifier may occur.

[0065] In this regard, without the implementation of the off-mode output impedance control 190 implemented by the RF power amplifier circuit 100, the S22 parameter of the power amplifier in the off mode may fall into Region 2, Region 3, Region 6, Region 5, and / or Region 4. Conversely, embodiments of the RF power amplifier circuit 100 using the off-mode output impedance control 190 provide the S22 parameter of the power amplifier within Region 1.

[0066] In an embodiment, when the power amplifier operates such that the S22 parameter of the power amplifier is within region 6, the off-mode output impedance control section 190 may be configured for implementation of the rotation circuit 212 as illustrated in FIGS. 6 and 7.

[0067] In an embodiment, when the power amplifier operates such that the S22 parameter of the power amplifier is within zone 2 or zone 6, the off-mode output impedance control section 190 may be configured for implementation of the impedance circuit 204 as illustrated in FIG. 9.

[0068] In an embodiment, when the power amplifier operates such that the S22 parameter of the power amplifier is within region 4, the off-mode output impedance control section 190 may be configured for implementation of an impedance circuit 204 as illustrated in FIG. 10.

[0069] In an embodiment, when the power amplifier operates such that the S22 parameter of the power amplifier is within region 3, the off-mode output impedance control section 190 may be configured for implementation of an impedance circuit 204 as illustrated in FIG. 11.

[0070] In an embodiment, when the power amplifier operates such that the S22 parameter of the power amplifier is within region 5, the off-mode output impedance control section 190 may be configured for implementation of the impedance circuit 204 as illustrated in FIG. 12.

[0071] In an aspect, when the power amplifier operates such that its S22 parameter is in one of multiple zones, the off-mode output impedance control section 190 may be configured to implement multiple embodiments of the impedance circuit 204 as illustrated in Figure 8. Thus, depending on the operating zone, the desired implementation of the impedance circuit 204 may be switched by a respective implementation of at least one switch circuit 206 to ensure that the off-mode output impedance control section 190 provides the desired impedance control for the RF power amplifier circuit 100.

[0072] FIG. 14A illustrates an exemplary embodiment of an off-mode output impedance control section according to aspects of the present disclosure.

[0073] In particular, Figure 14A illustrates an exemplary embodiment of off-mode output impedance control 190. The aspects of Figure 14A may include any other aspects as disclosed herein, and further, the aspects of Figure 14A may be implemented in other aspects described herein. Furthermore, the off-mode output impedance control 190 illustrated in Figure 14A is merely exemplary, and off-mode output impedance control 190 may be implemented in numerous other ways as described herein.

[0074] 14A, impedance circuit 204 may be implemented with one or more inductors or capacitors in parallel with one or more resistors, which may be connected to main line 202, impedance circuit 204, and ground 208 as illustrated in other aspects of the present disclosure. The elements in impedance circuit 204 are necessary elements for bringing S22 to area 1. Furthermore, as shown in at least one switch circuit 206, the switch may require either a resistor and / or an inductor for proper biasing of the gate and drain (these bias elements may additionally need to be isolated).

[0075] Additionally, the at least one switch circuit 206 may be implemented by a FET. However, as described herein, the switching device implemented by the at least one switch circuit 206 may be any type of switching device, and there may be any number of switching devices implemented by the at least one switch circuit 206. Additionally, the gates of the switching devices of the at least one switch circuit 206 may be connected to inductors in combination with or instead of resistors. These elements may be configured to receive a control input 210.

[0076] FIG. 14B illustrates an exemplary embodiment of an off-mode output impedance control section according to aspects of the present disclosure.

[0077] In particular, Figure 14B illustrates an exemplary embodiment of off-mode output impedance control 190. The aspects of Figure 14B may include any other aspects as disclosed herein, and further, the aspects of Figure 14B may be implemented in other aspects described herein. Furthermore, the off-mode output impedance control 190 illustrated in Figure 14B is merely exemplary, and off-mode output impedance control 190 may be implemented in numerous other ways as described herein.

[0078] 14B, the impedance circuit 204 may be implemented with one or more inductors or capacitors in parallel with one or more resistors, which may be connected to the main line 202, the impedance circuit 204, and ground 208 as illustrated in other aspects of the present disclosure. Additionally, one or more inductors and / or one or more resistors may be connected to bias the exemplary FET switch at the gate and drain. One or more of these elements may typically be required to bias the switch and further isolate it. Their presence or absence is determined during the design process.

[0079] In Figure 14B, switch 206 is configured with two FETs connected. This configuration roughly expands switch power handling by a factor of four (or 6 dB) in theory. In this regard, Figure 14B is exemplary; multiplying the FETs can further expand power capabilities. Three FETs would expand power capabilities by a factor of eight (or 9 dB), and so on.

[0080] FIG. 14C illustrates an exemplary embodiment of an off-mode output impedance control section according to aspects of the present disclosure.

[0081] In particular, Figure 14C illustrates an exemplary embodiment of off-mode output impedance control 190. The aspects of Figure 14C may include any other aspects as disclosed herein, and further, the aspects of Figure 14C may be implemented in other aspects described herein. Furthermore, the off-mode output impedance control 190 illustrated in Figure 14C is merely exemplary, and off-mode output impedance control 190 may be implemented in numerous other ways as described herein.

[0082] As illustrated in FIG. 14C , the off-mode output impedance control section 190 may receive a control input 210 from a controller 300. Note that the controller 300 is not required for embodiments of the present disclosure. In this regard, aspects of the controller 300 may be implemented using a simple toggle voltage. Additionally, the RF power amplifier circuit 100 and / or the off-mode output impedance control section 190 may include a gate driver 310. The controller 300 may generate a signal to activate the off-mode output impedance control section 190 and / or the at least one switch circuit 206. The signal may be provided to the gate driver 310. The gate driver 310 may then generate a gate drive signal and provide the gate drive signal to the at least one switch circuit 206 to activate the at least one switch circuit 206. In this regard, the off-mode output impedance control section 190 may implement a shunt switch and matched switching method. In an aspect, the signal generated by the controller 300 may be 0 V or −8 V. In an embodiment, the gate drive signal generated by the gate driver 310 can be 0 V or −28 V. These values ​​are switch process dependent, so they are merely exemplary and not limiting.

[0083] FIG. 14D illustrates an exemplary embodiment of an off-mode output impedance control section according to aspects of the present disclosure.

[0084] In particular, Figure 14D illustrates an exemplary embodiment of off-mode output impedance control 190. The aspects of Figure 14D may include any other aspects as disclosed herein, and further, the aspects of Figure 14D may be implemented in other aspects described herein. Furthermore, the off-mode output impedance control 190 illustrated in Figure 14D is merely exemplary, and off-mode output impedance control 190 may be implemented in numerous other ways as described herein.

[0085] 14D , the off-mode output impedance control section 190 may receive a control input 210 from a controller 300. Additionally, the RF power amplifier circuit 100 and / or the off-mode output impedance control section 190 may include a level-down circuit 312. The controller 300 may generate a signal to activate the off-mode output impedance control section 190 and / or the at least one switch circuit 206. The signal may be provided to the level-down circuit 312. The level-down circuit 312 may then generate a signal and provide it to the at least one switch circuit 206 to activate the at least one switch circuit 206. In this regard, the off-mode output impedance control section 190 may implement a shunt switch and matched switching method. In an embodiment, one or more gates of the at least one switch circuit 206 may be grounded. The level-down circuit 312 may use an available source used within the power amplifier section of the RF power amplifier circuit 100 and therefore available there (an exemplary value for a GaN-based amplifier device is 50V) and may not require a complex gate driver to generate -28V. In embodiments, the level-down circuit 312 may use MOS or BJT transistors. In embodiments, the signal generated by the controller 300 may be 0V or 1.8V. In embodiments, the signal generated by the level-down circuit 312 may be 0V or 28V. In embodiments, the active at least one switch circuit 206 may implement a GaN transistor switch device.

[0086] FIG. 14E illustrates an exemplary embodiment of an off-mode output impedance control section according to aspects of the present disclosure.

[0087] In particular, Figure 14E illustrates an exemplary embodiment of off-mode output impedance control 190. The aspects of Figure 14E may include any other aspects as disclosed herein, and further, the aspects of Figure 14E may be implemented in other aspects described herein. Furthermore, the off-mode output impedance control 190 illustrated in Figure 14E is merely exemplary, and off-mode output impedance control 190 may be implemented in numerous other ways as described herein.

[0088] As illustrated in FIG. 14E , the off-mode output impedance control section 190 may receive a control input 210 from a controller 300. Additionally, the RF power amplifier circuit 100 and / or the off-mode output impedance control section 190 may include a gate driver 310. The controller 300 may generate a signal to activate the off-mode output impedance control section 190 and / or the at least one switch circuit 206. The signal may be provided to the gate driver 310. The gate driver 310 may then generate a gate drive signal and provide the gate drive signal to the at least one switch circuit 206 to activate the at least one switch circuit 206. In this regard, the off-mode output impedance control section 190 may implement a shunt switch and matched switching method. In an embodiment, the signal generated by the controller 300 may be 0 V or −8 V. In an embodiment, the gate drive signal generated by the gate driver 310 may be 0 V or −28 V.

[0089] FIG. 14E further illustrates exemplary details of an embodiment of the at least one switch circuit 206. In this regard, the gate driver 310 may be connected to the gates of the transistors of the at least one switch circuit 206. In an embodiment, the transistors of the at least one switch circuit 206 may be FETs. The connection between the gate driver 310 and the gates of the transistors of the at least one switch circuit 206 may include one or more resistors and one or more inductors. As illustrated in FIG. 14E, the gate driver 310 may connect to a resistor, and the signal may be split into two inductors that may be connected to the gates of the transistors of the at least one switch circuit 206. In an embodiment, the drains of the transistors of the at least one switch circuit 206 may be connected to a resistor and ground.

[0090] FIG. 14F illustrates an exemplary embodiment of an off-mode output impedance control section according to aspects of the present disclosure.

[0091] In particular, Figure 14F illustrates an exemplary embodiment of off-mode output impedance control 190. The aspects of Figure 14F may include any other aspects as disclosed herein, and further, the aspects of Figure 14F may be implemented in other aspects described herein. Furthermore, the off-mode output impedance control 190 illustrated in Figure 14F is merely exemplary, and off-mode output impedance control 190 may be implemented in numerous other ways as described herein.

[0092] As illustrated in FIG. 14F , the off-mode output impedance control section 190 may receive a control input 210 from a controller 300. Additionally, the RF power amplifier circuit 100 and / or the off-mode output impedance control section 190 may include a level-down circuit 312. The controller 300 may generate a signal to activate the off-mode output impedance control section 190 and / or the at least one switch circuit 206. The signal may be provided to the level-down circuit 312. The level-down circuit 312 may then generate a signal and provide it to the at least one switch circuit 206 to activate the at least one switch circuit 206. In this regard, the off-mode output impedance control section 190 may implement a shunt switch and matched switching method. In embodiments, one or more gates of the at least one switch circuit 206 may be grounded. The level-down circuit 312 may use an available 50V source used within the power amplifier section of the RF power amplifier circuit 100, eliminating the need for a complex gate driver to generate −28V. In embodiments, the level-down circuit 312 may use MOS or BJT transistors. In embodiments, the signal generated by the controller 300 may be 0 V or 1.8 V. In embodiments, the signal generated by the level-down circuit 312 may be 0 V or 28 V. In embodiments, the active at least one switch circuit 206 may implement a GaN transistor switch device.

[0093] 14F further illustrates exemplary details of an embodiment of at least one switch circuit 206. In an embodiment, a gate of a transistor of at least one switch circuit 206 may be tied to ground. In an embodiment, a drain of a transistor of at least one switch circuit 206 may be tied to a resistor and connected to a level-down circuit 312.

[0094] In an embodiment, the bottom source of the transistor of at least one switch circuit 206 may also be coupled to a resistor and level-down circuit 312. In particular, this resistor may be implemented as a supply source resistor having a value that determines power and linearity.

[0095] In embodiments, the bottom source of the transistor of at least one switch circuit 206 may also be tied to a capacitor and ground. In embodiments, this capacitor may allow the source to float. In embodiments, this capacitor may be an RF short, a DC block, a matching capacitor, and / or the like.

[0096] 14F further illustrates exemplary details of an embodiment of the level-down circuit 312. In an embodiment, the level-down circuit 312 may include a transistor, which may be implemented as a BJT, but may also be implemented as a CMOS device, a FET device, and / or the like, for the purpose of activating and deactivating a switch circuit. In particular, the level-down circuit 312 may receive a control input 210 from the controller 300 along a line that may include a resistor and provide the control input 210 to the base of a BJT. The BJT may be connected to at least one switch circuit 206 as well as ground. Additionally, the level-down circuit 312 may connect to a 50V source received through a first resistor, which may be connected to a second resistor that is connected to ground.

[0097] Additionally, the at least one switch circuit 206 may be implemented with two FETs in series. This particular aspect, although not always required, is relevant to increasing power by 6 dB as described above. However, as described herein, the switching device implemented by the at least one switch circuit 206 may be any type of switching device, and there may be any number of switching devices implemented by the at least one switch circuit 206. A resistor at the base of the BJT may be configured to receive a control input 210, such as an appropriate logic level, from a controller 300, which may use, for example, 1.8V, 3.3V, or 5V logic levels.

[0098] 14E, the embodiment of the aspect of the off-mode output impedance control section 190 illustrated in FIG. 14F may enable the use of a positive voltage to drive the at least one switch circuit 206. This may therefore eliminate any negative voltage requirement from the RF power amplifier circuit 100. This may be beneficial because generating a negative voltage may be cumbersome and may generate some spurious signals within the transmit chain of the RF power amplifier circuit 100. In particular, this may require the implementation of a DC-DC converter that is involved and has an LO frequency that may be upconverted to the system operating frequency.

[0099] The embodiment of the aspect of the off mode output impedance control section 190 illustrated in FIG. 14F allows for the power handling of the RF switch when OFF to be extended by appropriate selection of capacitor and resistor values ​​compared to the aspect illustrated in FIG. 14E, and the main line 202 can provide power as shown in FIGS. 22A and 22B.

[0100] In an aspect, the level-down circuit 312 may have a simplified circuit structure that may be configured and used to downshift a voltage, such as downshifting 50 V to 28 V, and further, the level-down circuit 312 may control the ON / OFF of the at least one switch circuit 206 using a small logic voltage of the controller 300. In an aspect, the level-down circuit 312 may be implemented because the at least one switch circuit 206 may operate on a 28 V rail, while the RF amplifier device 108 may operate on a 50 V rail. Thus, an embodiment of the level-down circuit 312 may enable the use of a single voltage, such as 50 V, for the RF power amplifier circuit 100. However, the present disclosure contemplates an embodiment in which the at least one switch circuit 206 may operate on the same voltage rail as the RF amplifier device 108. Additionally, the present disclosure contemplates embodiments of RF power amplifier circuit 100 having multiple voltages, such as 28 V and 50 V, and the present disclosure contemplates embodiments configured for operation consistent with such multiple voltage embodiments, with minor variations in the various circuits as described herein.

[0101] In an aspect, the RF power amplifier circuit 100 may be configured as a packaged embodiment of the RF power amplifier circuit 100 including a support and a housing.

[0102] In embodiments, the support may be a laminate, a flange, a metal flange, a metal submount, a support, a surface, a package support, a package surface, a package support surface, a heat sink, a source ground circuit support, a source ground circuit surface, a source ground circuit package support, a source ground circuit package surface, a source ground circuit package support surface, a source ground circuit flange, a source ground circuit heat sink, a lead frame, a metal lead frame, a substrate, and / or the like. The support may comprise an insulating material, a dielectric material, a conductive material, a metal deposition, and / or the like.

[0103] The various components of the RF power amplifier circuit 100, including the components of the input impedance matching network 146, the components of the off-mode output impedance control section 190, the RF amplifier device 108, and / or the like, may be implemented as one or more discrete components, surface-mounted device (SMD) components, integrated passive device (IPD) components, monolithic microwave integrated circuit (MMIC) components, and / or the like. In embodiments, one or more of the various components of the RF power amplifier circuit 100, including the components of the input impedance matching network 146, the components of the off-mode output impedance control section 190, the RF amplifier device 108, and / or the like, may be surface-mounted device (SMD) components, surface-mounted device (SMD) capacitors, ceramic capacitors, surface-mounted device (SMD) ceramic capacitors, inductors, surface-mounted device (SMD) inductors, resistors, surface-mounted device (SMD) resistors, and / or the like. One or more of the various components of the RF power amplifier circuit 100, including components of the input impedance matching network 146, components of the off-mode output impedance control section 190, the RF amplifier device 108, and / or the like, may be attached directly to the support or may be attached to the support by an intervening structure. In embodiments, one or more of the various components of the RF power amplifier circuit 100, including components of the input impedance matching network 146, the output impedance matching network 147, components of the off-mode output impedance control section 190, the RF amplifier device 108, and / or the like, may be attached to the support by adhesives, soldering, sintering, eutectic bonding, ultrasonic welding, clip components, and / or the like, as described herein.

[0104] Generally speaking, the term IPD refers to an integrated circuit, which may be semiconductor-based, that includes several passive devices integrally formed within and connected to the terminals of the IC. Custom circuit topologies can be provided by the IPD. A variety of different structures are fabricated within the device to provide the required frequency response of specified passive components (e.g., capacitors, inductors, etc.). Examples of these structures include parallel plate capacitors, radial stubs, transmission lines, etc.

[0105] Additionally, one or more of the various components of RF power amplifier circuit 100, including components of input impedance matching network 146, output impedance matching network 147, components of off-mode output impedance control section 190, RF amplifier device 108, and / or the like, may be connected with one or more interconnects by adhesives, solder, sintering, eutectic bonding, ultrasonic welding, clip components, and / or the like, as described herein. One or more interconnects may be implemented as one or more wires, wire bonds, leads, vias, edge plating, circuit traces, tracks, clips, and / or the like. In one embodiment, one or more interconnects may utilize the same type of connection. In one embodiment, one or more interconnects may utilize different types of connections.

[0106] In an aspect, the housing of the packaged embodiment may include an overmolded structure that may substantially enclose the RF amplifier device 108, which may be mounted on a support. The overmolded structure may be formed of a plastic or plastic polymer compound, which may be an injection molded material, around the support, the off-mode output impedance control section 190, the RF amplifier device 108, the input impedance matching network 146, the output impedance matching network 147, and / or the like, thereby providing protection from the outside environment.

[0107] The packaging embodiment may include conductive input leads or pads that may be located on a first side of the packaging embodiment and conductive output leads or pads that may be located on a second side of the packaging embodiment opposite the conductive input leads or pads. The conductive input leads or pads may provide and / or implement the input port 102 of the RF power amplifier circuit 100 as described herein, and the conductive output leads or pads may provide and / or implement the RF output port 104 of the RF power amplifier circuit 100 as described herein. In one aspect, the packaging embodiment may be implemented to include separate embodiments of DC bias leads or pads located on both sides of the packaging embodiment adjacent to the conductive output leads or pads.

[0108] The packaging embodiment may be implemented using an electrically insulating window frame embodiment of the housing. The electrically insulating window frame may be formed around the support. The electrically insulating window frame may insulate the conductive input leads and the conductive output leads from the support. A central portion of the housing may be exposed from the insulating window frame. This exposed portion of the housing may provide a conductive die pad for one or more components of the RF power amplifier circuit 100 thereon.

[0109] Packaging embodiments may implement a housing to include an open-cavity configuration suitable for use with the RF amplifier device 108, input impedance matching network 146, and / or off-mode output impedance control 190 of the present disclosure. In particular, the open-cavity configuration may utilize an open-cavity package design. In some aspects, the open-cavity configuration may include a lid or other enclosure to protect interconnects, circuit components, the RF amplifier device 108, input impedance matching network 146, output impedance matching network 147, off-mode output impedance control 190, and / or the like. Packaging embodiments may include a ceramic body, and / or the lid may be made of a ceramic material. In one aspect, the ceramic material may include aluminum oxide (Al2O3). In one aspect, the lid may be attached to an electrically insulating window frame with an adhesive. In one aspect, the adhesive may be epoxy-based.

[0110] Inside a packaged embodiment, the RF amplifier device 108, input impedance matching network 146, output impedance matching network 147, and / or off-mode output impedance control section 190 may be attached to a support via die attach material. The electrically insulating window frame may be configured to insulate the source, gate, and drain of the RF amplifier device 108. The electrically insulating window frame may be configured to be more cost-effective, to provide a better coefficient of thermal expansion (CTE) matching with metal flanges, and to allow for high flexibility in lead configurations for both straight-lead and surface-mount configurations. The electrically insulating window frame may also be configured to be rigid, and therefore more stable, and less susceptible to bending.

[0111] Packaged embodiments may include traces, such as traces etched from a copper plate that is laminated to, embedded in, and / or separately mounted to the support. The housing may be mounted to a perimeter region of the support. The support may dissipate heat generated by the RF amplifier device 108, the input impedance matching network 146, the output impedance matching network 147, and / or the off-mode output impedance control section 190.

[0112] In various embodiments, the RF amplifier device 108 and the RF power amplifier circuit 100 may be a 5G amplifier, a multi-carrier amplifier, a multi-band amplifier, an LTE (Long Term Evolution) compatible amplifier, a WCDMA (Wideband Code Division Multiple Access) compatible amplifier, an 802.11(x) compatible amplifier, and / or the like. The RF power amplifier circuit 100 may be used in or with base stations, wireless devices, cellular base station communication transmitters, cellular base station communication amplifiers, RF power amplifiers for various cellular bands, Wireless Fidelity (Wi-Fi) devices, multiple-input multiple-output (MIMO) devices, devices utilizing IEEE 802.11n (Wi-Fi), devices utilizing IEEE 802.11ac (Wi-Fi), devices implementing the Evolved High Speed ​​Packet Access (HSPA+) protocol, devices implementing the 3G protocol, devices implementing the Worldwide Interoperability for Microwave Access (WiMAX) protocol, devices implementing the 4G protocol, devices implementing the Long Term Evolution (LTE) protocol, devices implementing the 5G protocol, devices used in Internet of Things (IOT) systems, Class-A amplifier devices, Class-B amplifier devices, Class-C amplifier devices, Class-AB amplifier devices, Doherty amplifiers, and / or the like, and combinations thereof.

[0113] Generally speaking, the RF amplifier device 108 can be any device capable of amplifying an RF signal. In the depicted embodiment, the RF amplifier device 108 is a transistor device, with the input terminal 110 corresponding to the control or gate terminal of the transistor device, the output terminal 112 corresponding to the first load terminal, such as the drain, of the transistor device, and the reference potential terminal 114 corresponding to the second load terminal, such as the source terminal, of the transistor device.

[0114] The RF amplifier device 108 may be configured to amplify an RF signal over an RF frequency range between the input terminal 110 and the output terminal 112, spanning an RF frequency range that includes a fundamental RF frequency. According to one aspect, this frequency range may be a “wideband” frequency range. A “wideband” frequency range refers to a range of frequency values ​​for the RF signal that exceeds the coherent bandwidth of a single channel.

[0115] In one aspect, a packaged embodiment may contain and / or implement two of the RF power amplifier circuits 100 described herein disposed adjacent to one another. In another aspect, a packaged RF amplifier may contain and / or implement one of the RF power amplifier circuits 100.

[0116] In particular, the packaged RF amplifier may be implemented at least in part as a Doherty circuit with one of the RF power amplifier circuits 100 implemented as a carrier amplifier and another of the RF power amplifier circuits 100 implemented as a peaking amplifier. In particular, the packaged RF amplifier may include a carrier amplifier and a peaking amplifier, where the packaged RF amplifier is configured to power combine the outputs of the carrier amplifier and the peaking amplifier. In one embodiment, the two amplifiers may be biased differently. In one embodiment, the carrier amplifier may operate in conventional Class AB or Class B. In one embodiment, the peaking amplifier may operate in Class C. Other operating classes are similarly contemplated.

[0117] FIG. 15 is an enlarged partial layout view of an exemplary embodiment of an RF amplifying transistor device according to the present disclosure.

[0118] FIG. 16 is a schematic cross-sectional view taken along line XX in FIG.

[0119] 15 and 16 and their descriptions may be implemented in any other embodiment and / or diagram of the RF power amplifier circuit 100 as described herein. As shown in FIG. 15, the RF amplifier device 108 may include a gate bus 402 that may be connected to multiple gate fingers 406 that may extend parallel in a first direction (e.g., the x-direction shown in FIG. 15). A source bus 410 may be connected to multiple parallel ones of the source contacts 416. The source bus 410 may be connected to a ground voltage node below the RF amplifier device 108. A drain bus 420 may be connected to multiple drain contacts 426.

[0120] As shown in FIG. 15 , each gate finger 406 may extend along the X direction between adjacent pairs of source contacts 416 and drain contacts 426. The RF amplifier device 108 or RF amplifier device 108 may include a plurality of unit cells 430, each of which may include an individual transistor. One of the plurality of unit cells 430 is illustrated by a dashed box in FIG. 15 and includes a gate finger 406 that may extend between adjacent ones of the source contacts 416 and drain contacts 426. A “gate width” may refer to the distance that the gate finger 406 overlaps with associated ones of the source contacts 416 and drain contacts 426 in the X direction. That is, the “width” of the gate finger 406 refers to the dimension of the gate finger 406 that extends parallel to adjacent source contacts 416 / drain contacts 426 (the distance along the z direction). Each of the plurality of unit cells 430 may share one of the source contacts 416 and / or drain contacts 426 with one or more adjacent ones of the plurality of unit cells 430. Although a particular number of the plurality of unit cells 430 is illustrated in FIG. 15 , it should be understood that the RF amplifier device 108 may include more or fewer unit cells 430.

[0121] 16 , the RF amplifier device 108 may include a semiconductor structure 440 including a substrate 422, which may include, for example, 4H—SiC or 6H—SiC. A channel layer 490 may be disposed on the substrate 422, and a barrier layer 470 may be disposed on the channel layer 490, such that the channel layer 490 is between the substrate 422 and the barrier layer 470. The channel layer 490 and the barrier layer 470 may include III-nitride based materials, with the material of the barrier layer 470 having a higher bandgap than the material of the channel layer 490. For example, the channel layer 490 may include GaN, while the barrier layer 470 may include AlGaN.

[0122] Due to the bandgap difference between the barrier layer 470 and the channel layer 490 and the piezoelectric effect at the interface between the barrier layer 470 and the channel layer 490, a two-dimensional electron gas (2DEG) is induced in the channel layer 490 at the junction between the channel layer 490 and the barrier layer 470. The 2DEG acts as a highly conductive layer that enables conduction between the source and drain regions of the device, which may be directly underneath the source contact 416 and the drain contact 426, respectively. The source contact 416 and the drain contact 426 may be on the barrier layer 470. The gate finger 406 may be on the barrier layer 470 between the source contact 416 and the drain contact 426. Although the gate fingers 406 and the source and drain contacts 416, 426 are all shown in FIG. 15 as having the same "length," it should be understood that in practice the gate fingers 406 may have a length that is substantially less than the length of the source and drain contacts 416, 426, and it should also be understood that the source and drain contacts 416, 426 need not have the same length.

[0123] The material of the gate fingers 406 may be selected based on the composition of the barrier layer 470. However, in particular embodiments, Ni, Pt, NiSi x Materials that can make Schottky contacts to nitrogen-based semiconductor materials, such as Ni, Cu, Pd, Cr, W, and / or WSiN, can be used. The source contact 416 and drain contact 426 can include a metal, such as TiAlN, that can form an ohmic contact to GaN.

[0124] The RF amplifier device 108 may include a metallization layer located on the lower surface of the substrate 422. The metallization layer may be located in a plane generally parallel to the z-axis and / or the x-axis. In one embodiment, the metallization layer may be implemented as a full metal layer on the lower surface of the substrate 422. The RF amplifier device 108 may include features such as separate conductive lines, tracks, circuit traces, pads for connections, vias for passing connections between layers of aluminum, copper, silver, gold, and / or the like, and solid conductive areas for EM shielding or other purposes.

[0125] FIG. 17 illustrates a process for implementing a package according to the present disclosure.

[0126] The process illustrated in FIG. 17 and described below may include any one or more other features, components, arrangements, and / or the like as described herein. In particular, FIG. 17 illustrates a process for forming package 700 associated with a packaging embodiment as described herein. Note that aspects of the process for forming package 700 may be performed in a different order consistent with the aspects described herein. Additionally, note that portions of the process for forming package 700 may be performed in a different order consistent with the aspects described herein. Furthermore, the process for forming package 700 may be modified to have more or fewer processes consistent with various aspects disclosed herein.

[0127] Initially, the process of forming package 700 may include a process of forming support 702. More specifically, the support may be constructed, configured, and / or arranged as described herein. In embodiments, the support may be a laminate, a flange, a metal flange, a metal submount, a support, a surface, a package support, a package surface, a package support surface, a heat sink, a source ground circuit support, a source ground circuit surface, a source ground circuit package support, a source ground circuit package surface, a source ground circuit package support surface, a source ground circuit flange, a source ground circuit heat sink, a lead frame, a metal lead frame, a substrate, and / or the like. The support may include an insulating material, a dielectric material, a conductive material, a metal deposition, and / or the like.

[0128] The process of forming package 700 may include a process of forming one or more interconnects 704. More particularly, the one or more interconnects may be constructed, configured, and / or arranged as described herein. In one embodiment, the process of forming one or more interconnects 704 may include forming the one or more interconnects by forming one or more wires, leads, vias, edge plating, circuit traces, tracks, and / or the like on the support and / or between and to components of RF power amplifier circuit 100, including RF amplifier device 108, input impedance matching network 146, and / or off-mode output impedance control section 190.

[0129] The process of forming the package 700 may include a process of arranging components on the support 706. More specifically, the process of arranging components on the support 706 may include arranging the components of the RF power amplifier circuit 100, including the RF amplifier device 108, the input impedance matching network 146, and / or the off-mode output impedance control section 190, on the support, as described herein. Thereafter, the process of arranging components on the support 706 may further include mounting the components of the RF power amplifier circuit 100, including the RF amplifier device 108, the input impedance matching network 146, and / or the off-mode output impedance control section 190, on the support. In this regard, the components of the RF power amplifier circuit 100 may be attached to the top surface of the support by adhesive, solder, sintering, eutectic bonding, ultrasonic welding, and / or the like, as described herein.

[0130] The process of forming package 700 may include a process of closing package 708. More particularly, the packaging embodiments may be constructed, configured, and / or arranged as described herein. In aspects, the housing of the packaging embodiments may include an overmolded configuration, an electrically insulating window frame embodiment of the housing, where the housing may include an open cavity configuration, and / or the like.

[0131] FIG. 18 illustrates simplified S22 parameters of a power amplifier without an implementation of an off-mode output impedance control according to the present disclosure.

[0132] In particular, Figure 18 illustrates the S22 parameter of a power amplifier shown at a single frequency without implementation of an off-mode output impedance control 190 in accordance with the present disclosure. In this regard, Figure 18 illustrates RF power amplifier circuit 100 implemented without the off-mode S22 correction provided by off-mode output impedance control 190 in accordance with the present disclosure. Thus, RF power amplifier circuit 100 operates such that the S22 parameter is approximately 4 ohms and approximately -1.5 dB, which is not satisfactory for many systems.

[0133] FIG. 19 illustrates the rotated S22 parameters of a power amplifier without full implementation of the off-mode output impedance control according to the present disclosure.

[0134] 19 illustrates the S22 parameter of a power amplifier without the implementation of an off-mode output impedance control 190 according to the present disclosure and rotated by a 50 ohm line or equivalent circuit. In this regard, RF power amplifier circuit 100 is implemented without a switch. Thus, RF power amplifier circuit 100 operates such that the S22 parameter is approximately 4 ohms and approximately −1.5 dB, which is not satisfactory for many systems.

[0135] FIG. 20 illustrates the S22 parameter of a power amplifier with an implementation of an off-mode output impedance controller according to the present disclosure.

[0136] 20 illustrates the S22 parameter of a power amplifier with an implementation of the off-mode output impedance control section 190 according to the present disclosure. Thus, the RF power amplifier circuit 100 operates such that the S22 parameter is satisfactory for many systems.

[0137] 21A illustrates a block diagram of an exemplary embodiment of the RF power amplifier circuit according to FIG. 1 implemented as a multi-stage Doherty power amplifier module (PAM). (The output impedance matching network 147 and the off-mode output impedance control section 190 are not explicitly illustrated in the figure.)

[0138] FIG. 21B illustrates an exemplary embodiment of a massive multiple-input multiple-output (MMIMO) simplified front-end antenna architecture according to aspects of the present disclosure.

[0139] In particular, the aspects of FIG. 21A and FIG. 21B and their descriptions may be implemented in any other aspects and / or diagrams of RF power amplifier circuit 100 as described herein. FIG. 21A illustrates a block diagram of an exemplary embodiment of RF power amplifier circuit 100 implemented as a multi-stage Doherty power amplifier module (PAM) 810. In this regard, multi-stage Doherty power amplifier module (PAM) 810 may implement off-mode output impedance control section 190 (not illustrated) as described herein. As illustrated in FIG. 21A, multi-stage Doherty power amplifier module (PAM) 810 is implemented with two stages. However, the present disclosure contemplates any number of stages. In an aspect, multi-stage Doherty power amplifier module (PAM) 810 may be used in a massive multiple-input multiple-output (MMIMO) simplified front-end antenna architecture 820 illustrated in FIG. 21B.

[0140] 21A, a multi-stage Doherty power amplifier module (PAM) 810 may implement a driver stage. In particular, the multi-stage Doherty power amplifier module (PAM) 810 may include an embodiment of the RF amplifier device 108 that may be implemented as a driver stage 188. In certain aspects, the driver stage 188 may be implemented as a GaN driver stage.

[0141] Additionally, the multi-stage Doherty power amplifier module (PAM) 810 may include an embodiment of the RF amplifier device 108 that may be implemented as a peak Doherty amplifier device 182. In certain aspects, the peak Doherty amplifier device 182 may be implemented as a peak Doherty GaN amplifier device.

[0142] Additionally, the multi-stage Doherty power amplifier module (PAM) 810 may include an embodiment of the RF amplifier device 108 that may be implemented as a main (or carrier) Doherty amplifier device 184. In certain aspects, the main (or carrier) Doherty amplifier device 184 may be implemented as a main Doherty GaN amplifier device.

[0143] Additionally, the multi-stage Doherty power amplifier module (PAM) 810 may include an inter-stage matching / signal splitter 186. The output of the driver stage 188 may be input to the inter-stage matching / signal splitter 186. The output of the inter-stage matching / signal splitter 186 may be input to the main (or carrier) Doherty amplifier device 184 and the peak Doherty amplifier device 182.

[0144] Additionally, the multi-stage Doherty power amplifier module (PAM) 810 may include a combiner / output matching 840. The outputs from the main (or carrier) Doherty amplifier device 184 and the peak Doherty amplifier device 182 may be input to the combiner / output matching 840.

[0145] Additionally, multi-stage Doherty power amplifier module (PAM) 810 may implement input impedance matching network 146 and / or off-mode output impedance control section 190 as described herein. In this regard, input impedance matching network 146 and / or off-mode output impedance control section 190 may view the Doherty amplifiers of multi-stage Doherty power amplifier module (PAM) 810 as simple amplifiers, even though the Doherty amplifiers of multi-stage Doherty power amplifier module (PAM) 810 may be implemented using multiple transistors, such as driver stage 188, main (or carrier) Doherty amplifier device 184, and peak Doherty amplifier device 182 as illustrated in FIG. 21A .

[0146] 21B , a massively multiple-input, multiple-output (MMIMO) simplified front-end antenna architecture 820 may be implemented using a signal splitter 822 connected to an array of multiple embodiments of multi-stage Doherty power amplifier modules (PAMs) 810. In this regard, there may be 1 to n embodiments of the multi-stage Doherty power amplifier modules (PAMs) 810. Additionally, the massively multiple-input, multiple-output (MMIMO) simplified front-end antenna architecture 820 may include antenna elements 824. In an aspect, there may be 1 to n embodiments of the antenna elements 824 connected to 1 to n embodiments of the multi-stage Doherty power amplifier modules (PAMs) 810 forming an antenna array 826. In this regard, each amplifier embodiment of the multi-stage Doherty power amplifier module (PAM) 810 implemented in the massively multiple-input multiple-output (MMIMO) simplified front-end antenna architecture 820 of FIG. 21B may be implemented using the embodiment of the multi-stage Doherty power amplifier module (PAM) 810 illustrated in FIG. 21A.

[0147] In this regard, aspects of the present disclosure implementing off-mode output impedance control section 190 may be utilized with a single discrete amplifier, multiple parallel amplifier stages combined at the output, a Doherty amplifier in which peak and main RF signals are combined at the output, a single-pass multi-stage amplifier, and / or the like.

[0148] Referring to FIG. 21B, any power amplifier (particularly, but not exclusively, a single-path multistage amplifier 1000 and / or a multipath multistage amplifier 1100) may replace the multi-stage Doherty power amplifier module (PAM) 810 with a massively multiple-input multiple-output (MMIMO) architecture 820, all benefiting from the application of an off-mode output impedance control section 190.

[0149] FIG. 21C illustrates a block diagram of an exemplary embodiment of an RF power amplifier circuit according to FIG. 1 implemented as a single-pass multi-stage amplifier.

[0150] 21C illustrates a block diagram of an exemplary embodiment of the RF power amplifier circuit 100 according to FIG. 1 implemented as a single-path multi-stage amplifier 1000. In this regard, the single-path multi-stage amplifier 1000 may implement an off-mode output impedance control section 190 (not illustrated) as described herein.

[0151] 21C , a single-path multi-stage amplifier 1000 is illustrated schematically, including an electrically cascaded preamplifier 1010 and an output stage 1030. As shown in FIG. 21C , the single-path multi-stage amplifier 1000 may include the preamplifier 1010, an inter-stage impedance matching network 1020, and an output stage 1030. Additionally, the single-path multi-stage amplifier 1000 may implement an input impedance matching network 146 and / or an off-mode output impedance control 190 as described herein. (The output impedance matching network 147 and the off-mode output impedance control 190 are not explicitly illustrated in the figure.)

[0152] The inter-stage impedance matching network 1020 may include, for example, inductors and / or capacitors arranged in any suitable configuration to form a circuit that improves impedance matching between the output of the preamplifier 1010 and the input of the output stage 1030. An RF transistor amplifier according to an embodiment may be used to implement either or both of the preamplifier 1010 and the output stage 1030.

[0153] FIG. 21D is a block diagram of an exemplary embodiment of an RF power amplifier circuit according to FIG. 1 implemented as a multi-path multi-stage amplifier, the final stage of which is a Doherty.

[0154] 21D illustrates a block diagram of an exemplary embodiment of the RF power amplifier circuit 100 according to FIG. 1 implemented as a multi-path multi-stage amplifier 1100. In this regard, the multi-path multi-stage amplifier 1100 may implement an off-mode output impedance control section 190 (not illustrated) as described herein.

[0155] 21D , a multi-path multi-stage amplifier 1100 as schematically illustrated includes a preamplifier 1010, a pair of inter-stage impedance matching networks 1020-1, 1020-2, and a pair of main amplifiers 1030-1, 1030-2. A splitter 1003 and a combiner 1004 are also provided. The pair of main amplifiers 1030-1, 1030-2 output stages 1030 are electrically arranged in parallel, and the preamplifier 1010 output stage 1030 is electrically cascaded with the pair of main amplifiers 1030-1, 1030-2. Additionally, the multi-path multi-stage amplifier 1100 may implement an input impedance matching network 146 and / or an off-mode output impedance control 190 as described herein (the output impedance matching network 147 and the off-mode output impedance control 190 are not explicitly illustrated in the figure).

[0156] FIG. 21E illustrates a block diagram of an exemplary embodiment of an RF power amplifier circuit according to FIG. 1 implemented as a multi-path multi-stage amplifier, with the final stage being either a quadrature stage or a balanced stage.

[0157] 21E illustrates a block diagram of an exemplary embodiment of the RF power amplifier circuit 100 according to FIG. 1, implemented as another embodiment of a multi-path multistage amplifier 1100.

[0158] 21E, a multi-path multi-stage amplifier 1100 as schematically illustrated includes a preamplifier 1010, an impedance matching network 1020, and a pair of main amplifiers 1030-1, 1030-2. A splitter 1003 and a combiner 1004 are also provided. The pair of main amplifiers 1030-1, 1030-2 are electrically arranged in parallel, and the preamplifier 1010 is electrically cascaded with the pair of main amplifiers 1030-1, 1030-2. In this regard, the pair of main amplifiers 1030-1, 1030-2 may implement an off-mode output impedance control 190 (not illustrated) as described herein, and each of them may implement an input impedance matching network 14 (the output impedance matching network 147 and the off-mode output impedance control 190 are not explicitly illustrated in the figure).

[0159] FIG. 22A illustrates a graph of power handling of at least one switch circuit of FIG. 14E implementing off-mode S22 correction according to an embodiment of the present disclosure.

[0160] 22A illustrates a graph of the power handling of at least one switch circuit 206 of FIG. 14E implementing off-mode S22 correction according to an embodiment of the present disclosure. In this regard, the power handling of the FIG. 14E circuit, which may be associated with current switch control, exhibits a peak power at marker m73 at approximately 51 dBm.

[0161] FIG. 22B illustrates a graph of power handling of at least one switch circuit of FIG. 14F implementing off-mode S22 correction according to an embodiment of the present disclosure.

[0162] In particular, FIG. 22B illustrates a graph of the power handling of the at least one switch circuit 206 of FIG. 14F implementing off-mode S22 correction according to aspects of the present disclosure. In this regard, the power handling of the FIG. 14F circuit implementing the novel switch control configuration exhibits a peak power at marker m73 of approximately 55 dBm, which is 4 dB better than the current switch control illustrated in FIG. 22B and associated with the at least one switch circuit 206 of FIG. 14F. Additionally, aspects of the present disclosure implementing the off-mode output impedance control section 190 may provide increased power handling / linearity of the RF amplifier device 108, such as the embodiment illustrated in FIG. 22B.

[0163] In one embodiment, the RF amplifier device 108 may be implemented as a high-power transistor. In one embodiment, the RF amplifier device 108 may be implemented as a high-power laterally diffused MOSFET (LDMOS), a high-power gallium nitride (GaN) MOSFET, a high-power GaN laterally diffused MOSFET (LDMOS), a high-power GaN high-electron mobility transistor (HEMT), an HBT (heterojunction bipolar transistor), a CMOS (complementary metal-oxide-semiconductor) device, a device having materials such as GaAs (gallium arsenide), Si (silicon), SiGe (silicon germanium), GaN, and / or the like, and / or a high-power GaN metal-semiconductor field-effect transistor (MESFET) transistor, a bipolar transistor, a discrete device, a Doherty configuration, any device utilizing a bias supply, and the like. In one embodiment, the off-mode output impedance control section 190 of the present disclosure may be utilized by various embodiments of the present disclosure to control the OFF-mode output impedance (also referred to as S22) of the RF power amplifier circuit 100.

[0164] In one embodiment, the RF amplifier device 108 may be implemented as a high-frequency transistor. In one embodiment, the RF amplifier device 108 may be implemented as a high-frequency laterally diffused MOSFET (LDMOS), a high-frequency gallium nitride (GaN) MOSFET, a high-frequency GaN laterally diffused MOSFET (LDMOS), a high-frequency GaN high-electron mobility transistor (HEMT), an HBT (heterojunction bipolar transistor), a CMOS (complementary metal-oxide-semiconductor) device, a device having materials such as GaAs (gallium arsenide), Si (silicon), SiGe (silicon germanium), GaN, and / or the like, and / or a high-frequency GaN metal-semiconductor field-effect transistor (MESFET) transistor, a bipolar transistor, a discrete device, a Doherty configuration, any device utilizing a bias supply, and the like. In one embodiment, the off-mode output impedance control section 190 of the present disclosure may be utilized by various embodiments of the present disclosure to control the OFF-mode output impedance (also referred to as S22) of the RF power amplifier circuit 100 of other types of device technologies.

[0165] Additionally, two or more RF amplifier devices 108 may be mounted and connected in parallel within the RF power amplifier circuit 100. In this regard, multiple embodiments of the RF amplifier device 108 may utilize the same type of transistor, and / or multiple embodiments of the RF amplifier device 108 may utilize different types of transistor. In one aspect, the off-mode output impedance control section 190 of the present disclosure may be utilized by various aspects of the present disclosure to control the OFF-mode output impedance (also referred to as S22) of the RF power amplifier circuit 100.

[0166] In certain embodiments, the RF power amplifier circuit 100 includes an input port 102, an RF output port 104, an RF amplifier device 108, and an off-mode output impedance control unit 190. In certain embodiments, the RF power amplifier circuit 100 is configured to be implemented in a system in which the RF power amplifier circuit 100 is configured to operate in an on mode and also configured in an off mode. In certain embodiments, the off-mode output impedance control unit 190 is configured to correspond to an off-mode S22 parameter. In certain embodiments, the RF power amplifier circuit 100 is configured with an off-mode output impedance control unit 190 without a circulator. In certain embodiments, the off-mode output impedance control unit 190 is configured to control the S22 parameter in the off mode to be between 40 ohms and 60 ohms. In certain embodiments, the RF power amplifier circuit 100 includes a main line 202, an impedance circuit 204, and at least one switch circuit 206. In a particular embodiment, the RF power amplifier circuit 100 includes at least one switch circuit 206 configured to be active when the RF power amplifier circuit is inactive and at least one switch circuit 206 configured to be inactive when the RF power amplifier circuit is active. In a particular embodiment, the RF power amplifier circuit 100 includes at least one switch circuit 206 having a control input 210. In a particular embodiment, the control input 210 is configured to control the at least one switch circuit 206 to be inactive when the RF power amplifier circuit is active and the control input 210 is configured to control the at least one switch circuit 206 to be active when the RF power amplifier circuit 100 is inactive. In a particular embodiment, the RF power amplifier circuit 100 includes an RF power amplifier circuit 100, wherein the control input 210 is generated by a controller associated with the RF power amplifier circuit 100. In a particular embodiment, the RF power amplifier circuit 100 includes an off-mode output impedance control unit 190 configured to perform impedance compensation.In certain aspects, the RF power amplifier circuit 100 includes at least one switch circuit 206 implemented by multiple switching devices in series. In certain aspects, the RF power amplifier circuit 100 includes at least one switch circuit 206 implemented by at least one FET switch, at least one CMOS switch, at least one GaAs FET switch, and / or at least one GaN FET switch. In certain aspects, the RF power amplifier circuit 100 includes an off-mode output impedance control unit 190 configured to provide impedance compensation for the RF power amplifier circuit 100 by closing the at least one switch circuit 206 and providing the impedance compensation provided by the impedance circuit 204. In certain aspects, the RF power amplifier circuit 100 includes an off-mode output impedance control unit 190 further comprising a rotation circuit 212. In certain aspects, the RF power amplifier circuit 100 includes an off-mode output impedance control unit 190 configured to implement two or more separate embodiments of the at least one switch circuit 206 and two or more separate embodiments of the impedance circuit 204. In certain embodiments, the impedance circuit 204 comprises one of the following: one or more capacitors, one or more capacitors in parallel with one or more resistors, one or more inductors, and / or one or more inductors in parallel with one or more resistors, RF power amplifier circuit 100. In certain embodiments, the RF power amplifier circuit 100 further comprises an input impedance matching network 146, an output impedance matching network 147, and a reference potential port 106.

[0167] Below are some non-limiting examples of aspects of the present disclosure.

[0168] One embodiment includes an RF power amplifier circuit including an input port, the RF power amplifier circuit additionally including an RF output port, the RF power amplifier circuit further including an RF amplifier device, and the RF power amplifier circuit also including an off-mode output impedance control.

[0169] The above-described embodiments may further include any one or a combination of two or more of the following embodiments: The RF power amplifier circuit of the above-described embodiments, wherein the RF power amplifier circuit is configured to be implemented in a system in which the RF power amplifier circuit is configured to operate in an on mode and is also configured in an off mode; The RF power amplifier circuit of the above-described embodiments, wherein the off-mode output impedance control section is configured to correspond to an off-mode S22 parameter; The RF power amplifier circuit of the above-described embodiments, wherein the RF power amplifier circuit is configured using an off-mode output impedance control section without a circulator; The RF power amplifier circuit of the above-described embodiments, wherein the off-mode output impedance control section is configured to control the S22 parameter in the off mode to be between 40 ohms and 60 ohms; The RF power amplifier circuit of the above-described embodiments, wherein the off-mode output impedance control section may include a main line, an impedance circuit, and at least one switch circuit; The RF power amplifier circuit of the above-described embodiments, wherein the at least one switch circuit is configured to be active when the RF power amplifier circuit is inactive and to be inactive when the RF power amplifier circuit is active. The RF power amplifier circuit of any of the above-mentioned embodiments, wherein the at least one switch circuit may include a control input. The control input is configured to control the at least one switch circuit to be inactive when the RF power amplifier circuit is active, and the control input is configured to control the at least one switch circuit to be active when the RF power amplifier circuit is inactive. The RF power amplifier circuit of any of the above-mentioned embodiments, wherein the control input is generated by a controller associated with the RF power amplifier circuit. The RF power amplifier circuit of any of the above-mentioned embodiments, wherein the off-mode output impedance control section is configured to perform impedance compensation. The RF power amplifier circuit of any of the above-mentioned embodiments, wherein the at least one switch circuit is implemented by multiple switching devices in series.The RF power amplifier circuit of the above-mentioned example, wherein the at least one switch circuit is implemented by at least one FET switch, at least one CMOS switch, at least one GaAs FET switch, and / or at least one GaN FET switch. The RF power amplifier circuit of the above-mentioned example, wherein the off-mode output impedance control unit is configured to provide impedance compensation for the RF power amplifier circuit by closing the at least one switch circuit and providing the impedance compensation provided by the impedance circuit. The RF power amplifier circuit of the above-mentioned example, wherein the off-mode output impedance control unit is configured to implement two or more separate embodiments of the at least one switch circuit and two or more separate embodiments of the impedance circuit. The RF power amplifier circuit of the above-mentioned example, wherein the impedance circuit may include one of the following: one or more capacitors, one or more capacitors in parallel with one or more resistors, one or more inductors, and / or one or more inductors in parallel with one or more resistors. The RF power amplifier circuit of the above-mentioned example, wherein the off-mode output impedance control unit may further include a rotation circuit. The RF power amplifier circuit of the above-described embodiments may include an input impedance matching network, an output impedance matching network, and a reference potential port.

[0170] In one embodiment, a process includes providing an input port. The process additionally includes providing an RF output port. The process further includes providing an RF amplifier device. The process also includes providing an off-mode output impedance control.

[0171] The above-described embodiments may further include any one or a combination of two or more of the following embodiments: the process of the above-described embodiments, wherein the RF power amplifier circuit is configured to be implemented in a system in which the RF power amplifier circuit is configured to operate in an on mode and also configured in an off mode; the process of the above-described embodiments, wherein the off-mode output impedance control is configured to correspond to an off-mode S22 parameter; the process of the above-described embodiments, wherein the RF power amplifier circuit is configured using an off-mode output impedance control without a circulator; the process of the above-described embodiments, wherein the off-mode output impedance control is configured to control the S22 parameter in the off mode to be between 40 ohms and 60 ohms; the process of the above-described embodiments, wherein the off-mode output impedance control may include providing a main line, providing an impedance circuit, and providing at least one switch circuit; the process of the above-described embodiments, wherein the at least one switch circuit is configured to be active when the RF power amplifier circuit is inactive and the at least one switch circuit is configured to be inactive when the RF power amplifier circuit is active; the process of the above-described embodiments, wherein the at least one switch circuit may include a control input. The process of any of the above-mentioned embodiments, wherein the control input is configured to control the at least one switch circuit to be inactive when the RF power amplifier circuit is active, and the control input is configured to control the at least one switch circuit to be active when the RF power amplifier circuit is inactive. The process of any of the above-mentioned embodiments, wherein the control input is generated by a controller associated with the RF power amplifier circuit. The process of any of the above-mentioned embodiments, wherein the off-mode output impedance control section is configured to perform impedance compensation. The process of any of the above-mentioned embodiments, wherein the at least one switch circuit is implemented by multiple switching devices in series. The process of any of the above-mentioned embodiments, wherein the at least one switch circuit is implemented by at least one FET switch, at least one CMOS switch, at least one GaAs FET switch, and / or at least one GaN FET switch.The process of any of the above examples, wherein the off-mode output impedance control section is configured to provide impedance compensation for the RF power amplifier circuit by closing at least one switch circuit and providing impedance compensation provided by the impedance circuit. The process of any of the above examples, wherein the off-mode output impedance control section is configured to implement two or more separate embodiments of the at least one switch circuit and two or more separate embodiments of the impedance circuit. The process of any of the above examples, wherein the impedance circuit may include one of the following: one or more capacitors, one or more capacitors in parallel with one or more resistors, one or more inductors, and / or one or more inductors in parallel with one or more resistors. The process of any of the above examples, wherein the off-mode output impedance control section may further include a rotation circuit. The process of any of the above examples may include providing an input impedance matching network, an output impedance matching network, and a reference potential port.

[0172] Below are some non-limiting examples of aspects of the present disclosure.

[0173] One embodiment includes an RF power amplifier circuit including an input port. The RF power amplifier circuit additionally includes an RF output port. The RF power amplifier circuit further includes an RF amplifier device. The RF power amplifier circuit also includes an output impedance control section, which may include an impedance circuit and at least one switch circuit.

[0174] The above-described embodiments may further include any one or a combination of two or more of the following embodiments: The RF power amplifier circuit of the above-described embodiments, wherein the RF power amplifier circuit is configured to be implemented in a system in which the RF power amplifier circuit is configured to operate in an on mode and is also configured in an off mode; The RF power amplifier circuit of the above-described embodiments, wherein the output impedance control section is configured to correspond to an off-mode S22 parameter; The RF power amplifier circuit of the above-described embodiments, wherein the RF power amplifier circuit is configured using an output impedance control section without a circulator; The RF power amplifier circuit of the above-described embodiments, wherein the output impedance control section is configured to control the S22 parameter in the off mode to be between 40 ohms and 60 ohms; The RF power amplifier circuit of the above-described embodiments, wherein at least one switch circuit is configured to be active when the RF power amplifier circuit is inactive and at least one switch circuit is configured to be inactive when the RF power amplifier circuit is active; The RF power amplifier circuit of the above-described embodiments, wherein the at least one switch circuit may include a control input. The RF power amplifier circuit of any of the above-mentioned embodiments, wherein the control input is configured to control the at least one switch circuit to be inactive when the RF power amplifier circuit is active, and the control input is configured to control the at least one switch circuit to be active when the RF power amplifier circuit is inactive. The RF power amplifier circuit of any of the above-mentioned embodiments, wherein the control input is generated by a controller associated with the RF power amplifier circuit. The RF power amplifier circuit of any of the above-mentioned embodiments, wherein the output impedance control section is configured to perform impedance compensation. The RF power amplifier circuit of any of the above-mentioned embodiments, wherein the at least one switch circuit is implemented by multiple switching devices in series. The RF power amplifier circuit of any of the above-mentioned embodiments, wherein the at least one switch circuit is implemented by at least one FET switch, at least one CMOS switch, at least one GaAs FET switch, and / or at least one GaN FET switch.The RF power amplifier circuit of the above-mentioned example, wherein the output impedance control section is configured to provide impedance compensation for the RF power amplifier circuit by closing at least one switch circuit and providing impedance compensation provided by the impedance circuit. The RF power amplifier circuit of the above-mentioned example, wherein the output impedance control section may further include a rotation circuit. The RF power amplifier circuit of the above-mentioned example, wherein the output impedance control section is configured to implement two or more separate embodiments of the at least one switch circuit and two or more separate embodiments of the impedance circuit. The RF power amplifier circuit of the above-mentioned example, wherein the impedance circuit may include one of the following: one or more capacitors, one or more capacitors in parallel with one or more resistors, one or more inductors, and / or one or more inductors in parallel with one or more resistors. The RF power amplifier circuit of the above-mentioned example may include an input impedance matching network, an output impedance matching network, and a reference potential port.

[0175] In one embodiment, a process includes providing an input port. The process additionally includes providing an RF output port. The process further includes providing an RF amplifier device. The process also includes providing an output impedance control, which may include an impedance circuit and at least one switch circuit.

[0176] The above-described embodiments may further include any one or a combination of two or more of the following embodiments: the process of the above-described embodiments, wherein the RF power amplifier circuit is configured to be implemented in a system in which the RF power amplifier circuit is configured to operate in an on mode and is also configured in an off mode; the process of the above-described embodiments, wherein the output impedance control is configured to correspond to an off-mode S22 parameter; the process of the above-described embodiments, wherein the RF power amplifier circuit is configured with an output impedance control without a circulator; the process of the above-described embodiments, wherein the output impedance control is configured to control the S22 parameter in the off mode to be between 40 ohms and 60 ohms; the process of the above-described embodiments, wherein at least one switch circuit is configured to be active when the RF power amplifier circuit is inactive and at least one switch circuit is configured to be inactive when the RF power amplifier circuit is active; the process of the above-described embodiments, wherein the at least one switch circuit may include a control input. The process of any of the above-mentioned embodiments, wherein the control input is configured to control the at least one switch circuit to be inactive when the RF power amplifier circuit is active, and the control input is configured to control the at least one switch circuit to be active when the RF power amplifier circuit is inactive. The process of any of the above-mentioned embodiments, wherein the control input is generated by a controller associated with the RF power amplifier circuit. The process of any of the above-mentioned embodiments, wherein the output impedance control unit is configured to perform impedance compensation. The process of any of the above-mentioned embodiments, wherein the at least one switch circuit is implemented by multiple switching devices in series. The process of any of the above-mentioned embodiments, wherein the at least one switch circuit is implemented by at least one FET switch, at least one CMOS switch, at least one GaAs FET switch, and / or at least one GaN FET switch. The process of any of the above-mentioned embodiments, wherein the output impedance control unit is configured to provide impedance compensation for the RF power amplifier circuit by closing the at least one switch circuit and providing the impedance compensation provided by the impedance circuit.The process of any of the above examples, wherein the output impedance control section may further include a rotation circuit. The process of any of the above examples, wherein the output impedance control section is configured to implement two or more separate embodiments of the at least one switch circuit and two or more separate embodiments of the impedance circuit. The process of any of the above examples, wherein the impedance circuit may include one of the following: one or more capacitors, one or more capacitors in parallel with one or more resistors, one or more inductors, and / or one or more inductors in parallel with one or more resistors. The process of any of the above examples may include providing an input impedance matching network, an output impedance matching network, and providing a reference potential port.

[0177] In particular, connections as described herein may include bonds or connections that may include leads as described herein, wire bonding, adhesives, solder, sintering, eutectic bonding, thermocompression bonding, ultrasonic bonding / welding, clip components, and / or the like. The connections may be through intervening structures or components, or the connections may be direct connections.

[0178] The adhesives of the present disclosure can be used in adhesive bonding processes that may include applying an intermediate layer to connect surfaces to be connected. The adhesive can be organic or inorganic, and the adhesive can be deposited on one or both surfaces of the surfaces to be connected. The adhesive can be used in adhesive bonding processes that may include applying an adhesive material having a specific coating thickness at a specific bonding temperature for a specific processing time while in an environment that may include applying a specific tool pressure. In one embodiment, the adhesive can be a conductive adhesive, an epoxy adhesive, a conductive epoxy adhesive, and / or the like.

[0179] The solder of the present disclosure can be utilized to form a solder interface that can include and / or be formed from solder. The solder can be any fusible metal alloy that can be used to form a bond between surfaces to be joined. The solder can be lead-free solder, lead solder, eutectic solder, or the like. Lead-free solder can contain tin, copper, silver, bismuth, indium, zinc, antimony, trace amounts of other metals, and / or the like. Lead solder can contain lead and other metals such as tin, silver, and / or the like. The solder can further include a flux, if desired.

[0180] Sintering of the present disclosure may utilize a process of compressing and forming a solid mass of material through heat and / or pressure. The sintering process may operate without melting the material to its liquidus point. The sintering process may include sintering of metal powders. The sintering process may include sintering in a vacuum. The sintering process may include sintering with the use of a protective gas.

[0181] The eutectic bonding of the present disclosure may utilize a bonding process involving an intermediate metal layer that can form a eutectic system. The eutectic system may be used between the surfaces to be joined. Eutectic bonding may utilize a eutectic metal, which may be an alloy that changes from a solid to a liquid state or from a liquid to a solid state at a specific composition and temperature without passing through two-phase equilibrium. The eutectic alloy may be deposited by sputtering, dual-source evaporation, electroplating, and / or the like.

[0182] Ultrasonic welding of the present disclosure may utilize a process in which high frequency ultrasonic acoustic vibrations are applied locally to components being held together under pressure. Ultrasonic welding may create a solid weld between the surfaces to be joined. In one embodiment, ultrasonic welding may include applying a sonication force.

[0183] In certain embodiments, RF power amplifier circuit 100 and / or RF amplifiers of the present disclosure may be utilized in a wireless base station that connects to a wireless device. In further embodiments, RF power amplifier circuit 100 and / or RF amplifiers of the present disclosure may be utilized in an amplifier implemented by a wireless base station that connects to a wireless device. In further embodiments, RF power amplifier circuit 100 and / or RF amplifiers of the present disclosure may be utilized in a wireless device. In still further embodiments, RF power amplifier circuit 100 and / or RF amplifiers of the present disclosure may be utilized in an amplifier implemented within a wireless device.

[0184] It should be understood that in this disclosure, references to wireless devices are intended to encompass electronic devices such as mobile phones, tablet computers, gaming systems, MP3 players, personal computers, PDAs, user equipment (UE), and the like. A "wireless device" is intended to encompass any compatible mobile technology computing device capable of connecting to a wireless communications network, such as a mobile phone, mobile device, mobile station, user equipment, mobile phone, smartphone, handset, wireless dongle, remote alert device, Internet of Things (IoT)-based wireless device, or other mobile computing device that may be supported by a wireless network. A wireless device may utilize wireless communications technologies such as GSM, CDMA, wireless local loop, Wi-Fi, WiMAX, other wide area network (WAN) technologies, 3G technology, 4G technology, 5G technology, LTE technology, and / or the like.

[0185] In this disclosure, references to wireless base stations are intended to encompass base transceiver stations (BTSs), Node B devices, base station (BS) devices, evolved Node B devices, and the like that facilitate wireless communication between wireless devices and a network. The wireless base stations and / or networks may utilize wireless communication technologies such as GSM, CDMA, wireless local loop, Wi-Fi, WiMAX, other wide area network (WAN) technologies, 3G technologies, 4G technologies, 5G technologies, LTE technologies, and / or the like. However, aspects of the present disclosure are applicable to other embodiments as well.

[0186] While the present disclosure has been described with reference to exemplary embodiments, those skilled in the art will recognize that the present disclosure can be practiced with modification within the spirit and scope of the appended claims. These examples provided above are merely illustrative and are not intended to be an exhaustive list of all possible designs, embodiments, applications, or modifications of the present disclosure.

Claims

1. An input port; an RF output port; an RF amplifier device; Off-mode output impedance control section An RF power amplifier circuit comprising:

2. 10. The RF power amplifier circuit of claim 1, wherein the RF power amplifier circuit is configured to be implemented in a system in which the RF power amplifier circuit is configured to operate in an on mode and is also configured in an off mode.

3. The RF power amplifier circuit of claim 1 , wherein the off-mode output impedance control section is configured to correspond to an off-mode S22 parameter.

4. The RF power amplifier circuit of claim 1 , wherein the RF power amplifier circuit is configured using the off-mode output impedance control section without a circulator.

5. 2. The RF power amplifier circuit of claim 1, wherein the off-mode output impedance control section is configured to control the S22 parameter in the off-mode to be between 40 ohms and 60 ohms.

6. The RF power amplifier circuit of claim 1 , wherein the off-mode output impedance control section comprises a main line, an impedance circuit, and at least one switch circuit.

7. 7. The RF power amplifier circuit of claim 6, wherein the at least one switch circuit is configured to be active when the RF power amplifier circuit is inactive, and the at least one switch circuit is configured to be inactive when the RF power amplifier circuit is active.

8. The RF power amplifier circuit of claim 6 , wherein the at least one switch circuit comprises a control input.

9. 9. The RF power amplifier circuit of claim 8, wherein the control input is configured to control the at least one switch circuit to be inactive when the RF power amplifier circuit is active, and the control input is configured to control the at least one switch circuit to be active when the RF power amplifier circuit is inactive.

10. The RF power amplifier circuit of claim 8 , wherein the control input is generated by a controller associated with the RF power amplifier circuit.

11. The RF power amplifier circuit of claim 6 , wherein the off-mode output impedance control section is configured to perform impedance compensation.

12. The RF power amplifier circuit of claim 6 , wherein the at least one switch circuit is implemented by a plurality of switching devices in series.

13. 7. The RF power amplifier circuit of claim 6, wherein the at least one switch circuit is implemented by at least one FET switch, at least one CMOS switch, at least one GaAs FET switch, and / or at least one GaN FET switch.

14. 7. The RF power amplifier circuit of claim 6, wherein the off-mode output impedance control section is configured to provide impedance compensation for the RF power amplifier circuit by closing the at least one switch circuit and providing impedance compensation provided by the impedance circuit.

15. The RF power amplifier circuit of claim 1 , wherein the off-mode output impedance control section further comprises a rotation circuit.

16. 7. The RF power amplifier circuit of claim 6, wherein the off-mode output impedance control section is configured to implement two or more separate embodiments of the at least one switch circuit and two or more separate embodiments of the impedance circuit.

17. 7. The RF power amplifier circuit of claim 6, wherein the impedance circuit comprises one of the following: one or more capacitors, one or more capacitors in parallel with one or more resistors, one or more inductors, and / or one or more inductors in parallel with one or more resistors.

18. The RF power amplifier circuit of claim 6 , wherein the off-mode output impedance control section is configured to receive a control input from a controller.

19. 20. The RF power amplifier circuit of claim 18, wherein the off-mode output impedance control section further comprises a gate driver configured to be responsive to the controller.

20. 20. The RF power amplifier circuit of claim 18, wherein the off-mode output impedance control section further comprises a level-down circuit configured to be responsive to the controller.

21. 21. The RF power amplifier circuit of claim 20, wherein the level-down circuit is configured to limit the generation of spurious signals in a transmit chain of the RF power amplifier circuit.

22. 21. The RF power amplifier circuit of claim 20, wherein the level-down circuit is configured to control on / off of the at least one switch circuit.

23. 21. The RF power amplifier circuit of claim 20, wherein the RF power amplifier circuit is configured to generate a single voltage, and the level-down circuit is configured to be implemented using the single voltage.

24. The RF power amplifier circuit of claim 1 , further comprising an input impedance matching network and a reference potential port.

25. providing an input port; providing an RF output port; Providing an RF amplifier device; providing an off-mode output impedance control section; 1. A process for implementing an RF power amplifier circuit, comprising:

26. 26. The process for implementing an RF power amplifier circuit of claim 25, wherein the RF power amplifier circuit is configured to be implemented in a system in which the RF power amplifier circuit is configured to operate in an on mode and is also configured in an off mode.

27. 26. The process for implementing an RF power amplifier circuit of claim 25, wherein the off-mode output impedance control section is configured to correspond to an off-mode S22 parameter.

28. 26. The process for implementing an RF power amplifier circuit of claim 25, wherein the RF power amplifier circuit is configured with the off-mode output impedance control section without a circulator.

29. 26. The process for implementing an RF power amplifier circuit of claim 25, wherein the off-mode output impedance control section is configured to control the S22 parameter in the off-mode to be between 40 ohms and 60 ohms.

30. The off mode output impedance control section Providing the main line, providing an impedance circuit; providing at least one switch circuit; 26. A process for implementing the RF power amplifier circuit of claim 25, comprising:

31. 31. The process for implementing an RF power amplifier circuit of claim 30, wherein the at least one switch circuit is configured to be active when the RF power amplifier circuit is inactive, and the at least one switch circuit is configured to be inactive when the RF power amplifier circuit is active.

32. 31. The process for implementing an RF power amplifier circuit of claim 30, wherein the at least one switch circuit comprises a control input.

33. 33. The process for implementing an RF power amplifier circuit of claim 32, wherein the control input is configured to control the at least one switch circuit to be inactive when the RF power amplifier circuit is active, and the control input is configured to control the at least one switch circuit to be active when the RF power amplifier circuit is inactive.

34. 33. The process for implementing an RF power amplifier circuit of claim 32, wherein the control input is generated by a controller associated with the RF power amplifier circuit.

35. 31. The process for implementing an RF power amplifier circuit of claim 30, wherein the off-mode output impedance control section is configured to perform impedance compensation.

36. 31. The process for implementing an RF power amplifier circuit of claim 30, wherein the at least one switch circuit is implemented by a plurality of switching devices in series.

37. 31. The process for implementing an RF power amplifier circuit of claim 30, wherein the at least one switch circuit is implemented with at least one FET switch, at least one CMOS switch, at least one GaAs FET switch, and / or at least one GaN FET switch.

38. 31. The process for implementing an RF power amplifier circuit of claim 30, wherein the off-mode output impedance control section is configured to provide impedance compensation for the RF power amplifier circuit by closing the at least one switch circuit and providing impedance compensation provided by the impedance circuit.

39. 26. The process for implementing an RF power amplifier circuit of claim 25, wherein the off-mode output impedance control section further comprises a rotation circuit.

40. 31. The process for implementing an RF power amplifier circuit of claim 30, wherein the off-mode output impedance control section is configured to implement two or more separate embodiments of the at least one switch circuit and two or more separate embodiments of the impedance circuit.

41. 31. The process for implementing an RF power amplifier circuit of claim 30, wherein the impedance circuit comprises one of the following: one or more capacitors, one or more capacitors in parallel with one or more resistors, one or more inductors, and / or one or more inductors in parallel with one or more resistors.

42. 31. The process for implementing an RF power amplifier circuit of claim 30, wherein the off-mode output impedance control section is configured to receive a control input from a controller.

43. 43. The process for implementing an RF power amplifier circuit of claim 42, wherein the off-mode output impedance control section further comprises a gate driver configured to be responsive to the controller.

44. 43. The process for implementing an RF power amplifier circuit of claim 42, wherein the off-mode output impedance control section further comprises a level-down circuit configured to be responsive to the controller.

45. 45. The process for implementing an RF power amplifier circuit of claim 44, wherein the level-down circuit is configured to limit the generation of spurious signals in a transmit chain of the RF power amplifier circuit.

46. 45. The process for implementing an RF power amplifier circuit of claim 44, wherein the level-down circuit is configured to control the on / off of the at least one switch circuit.

47. 45. The process of implementing an RF power amplifier circuit of claim 44, wherein the RF power amplifier circuit is configured to generate a single voltage and the level-down circuit is configured to be implemented using the single voltage.

48. providing an input impedance matching network; Providing a reference potential port; 26. A process for implementing the RF power amplifier circuit of claim 25, further comprising:

49. An input port; an RF output port; an RF amplifier device; Output impedance control section wherein the output impedance control section includes an impedance circuit and at least one switch circuit.

50. 50. The RF power amplifier circuit of claim 49, wherein the RF power amplifier circuit is configured to be implemented in a system in which the RF power amplifier circuit is configured to operate in an on mode and is also configured in an off mode.

51. 50. The RF power amplifier circuit of claim 49, wherein the output impedance control section is configured to correspond to an off-mode S22 parameter.

52. 50. The RF power amplifier circuit of claim 49, wherein the RF power amplifier circuit is configured with the output impedance control section without a circulator.

53. 50. The RF power amplifier circuit of claim 49, wherein the output impedance control section is configured to control the S22 parameter in off mode to be between 40 ohms and 60 ohms.

54. 50. The RF power amplifier circuit of claim 49, wherein the at least one switch circuit is configured to be active when the RF power amplifier circuit is inactive, and the at least one switch circuit is configured to be inactive when the RF power amplifier circuit is active.

55. 50. The RF power amplifier circuit of claim 49, wherein the at least one switch circuit comprises a control input.

56. 56. The RF power amplifier circuit of claim 55, wherein the control input is configured to control the at least one switch circuit to be inactive when the RF power amplifier circuit is active, and the control input is configured to control the at least one switch circuit to be active when the RF power amplifier circuit is inactive.

57. 56. The RF power amplifier circuit of claim 55, wherein the control input is generated by a controller associated with the RF power amplifier circuit.

58. 50. The RF power amplifier circuit of claim 49, wherein the output impedance control section is configured to perform impedance compensation.

59. 50. The RF power amplifier circuit of claim 49, wherein the at least one switch circuit is implemented by a plurality of switching devices in series.

60. 50. The RF power amplifier circuit of claim 49, wherein the at least one switch circuit is implemented with at least one FET switch, at least one CMOS switch, at least one GaAs FET switch, and / or at least one GaN FET switch.

61. 50. The RF power amplifier circuit of claim 49, wherein the output impedance control section is configured to provide impedance compensation for the RF power amplifier circuit by closing the at least one switch circuit and providing impedance compensation provided by the impedance circuit.

62. 50. The RF power amplifier circuit of claim 49, wherein the output impedance control section further comprises a rotation circuit.

63. 50. The RF power amplifier circuit of claim 49, wherein the output impedance control section is configured to implement two or more separate embodiments of the at least one switch circuit and two or more separate embodiments of the impedance circuit.

64. 50. The RF power amplifier circuit of claim 49, wherein the impedance circuit comprises one of the following: one or more capacitors, one or more capacitors in parallel with one or more resistors, one or more inductors, and / or one or more inductors in parallel with one or more resistors.

65. 50. The RF power amplifier circuit of claim 49, wherein the output impedance control section is configured to receive a control input from a controller.

66. 66. The RF power amplifier circuit of claim 65, wherein the output impedance control section further comprises a gate driver configured to be responsive to the controller.

67. 66. The RF power amplifier circuit of claim 65, wherein the output impedance control section further comprises a level-down circuit configured to be responsive to the controller.

68. 68. The RF power amplifier circuit of claim 67, wherein the level-down circuit is configured to limit the generation of spurious signals in a transmit chain of the RF power amplifier circuit.

69. 68. The RF power amplifier circuit of claim 67, wherein the level-down circuit is configured to control on / off of the at least one switch circuit.

70. 68. The RF power amplifier circuit of claim 67, wherein the RF power amplifier circuit is configured to generate a single voltage, and the level-down circuit is configured to be implemented using the single voltage.

71. 50. The RF power amplifier circuit of claim 49, further comprising an input impedance matching network and a reference potential port.

72. providing an input port; providing an RF output port; Providing an RF amplifier device; Providing an output impedance control section; wherein the output impedance control section comprises an impedance circuit and at least one switch circuit.

73. 73. The process for implementing an RF power amplifier circuit of claim 72, wherein the RF power amplifier circuit is configured to be implemented in a system in which the RF power amplifier circuit is configured to operate in an on mode and is also configured in an off mode.

74. 73. The process for implementing an RF power amplifier circuit of claim 72, wherein the output impedance control section is configured to correspond to an off mode S22 parameter.

75. 73. The process for implementing an RF power amplifier circuit of claim 72, wherein the RF power amplifier circuit is configured with the output impedance control section without a circulator.

76. 73. The process for implementing an RF power amplifier circuit of claim 72, wherein the output impedance control section is configured to control an S22 parameter in an off mode to be between 40 ohms and 60 ohms.

77. 73. The process for implementing an RF power amplifier circuit of claim 72, wherein the at least one switch circuit is configured to be active when the RF power amplifier circuit is inactive, and the at least one switch circuit is configured to be inactive when the RF power amplifier circuit is active.

78. 73. The process for implementing an RF power amplifier circuit of claim 72, wherein the at least one switch circuit comprises a control input.

79. 80. The process for implementing an RF power amplifier circuit of claim 78, wherein the control input is configured to control the at least one switch circuit to be inactive when the RF power amplifier circuit is active, and the control input is configured to control the at least one switch circuit to be active when the RF power amplifier circuit is inactive.

80. 80. The process for implementing an RF power amplifier circuit of claim 78, wherein the control input is generated by a controller associated with the RF power amplifier circuit.

81. 73. The process for implementing an RF power amplifier circuit of claim 72, wherein the output impedance control section is configured to perform impedance compensation.

82. 73. The process for implementing an RF power amplifier circuit of claim 72, wherein the at least one switch circuit is implemented by a plurality of switching devices in series.

83. 73. The process for implementing an RF power amplifier circuit of claim 72, wherein the at least one switch circuit is implemented with at least one FET switch, at least one CMOS switch, at least one GaAs FET switch, and / or at least one GaN FET switch.

84. 73. The process for implementing an RF power amplifier circuit of claim 72, wherein the output impedance control section is configured to provide impedance compensation for the RF power amplifier circuit by closing the at least one switch circuit and providing impedance compensation provided by the impedance circuit.

85. 73. The process for implementing an RF power amplifier circuit of claim 72, wherein the output impedance control section further comprises a rotation circuit.

86. 73. The process for implementing an RF power amplifier circuit of claim 72, wherein the output impedance control section is configured to implement two or more separate embodiments of the at least one switch circuit and two or more separate embodiments of the impedance circuit.

87. 73. The process for implementing an RF power amplifier circuit of claim 72, wherein the impedance circuit comprises one of the following: one or more capacitors, one or more capacitors in parallel with one or more resistors, one or more inductors, and / or one or more inductors in parallel with one or more resistors.

88. 73. The process for implementing an RF power amplifier circuit of claim 72, wherein the output impedance control section is configured to receive a control input from a controller.

89. 90. The process for implementing an RF power amplifier circuit of claim 88, wherein the output impedance control section further comprises a gate driver configured to be responsive to the controller.

90. 90. The process for implementing an RF power amplifier circuit of claim 88, wherein the output impedance control section further comprises a level-down circuit configured to be responsive to the controller.

91. 91. The process for implementing an RF power amplifier circuit of claim 90, wherein the level-down circuit is configured to limit the generation of spurious signals in a transmit chain of the RF power amplifier circuit.

92. 91. The process for implementing an RF power amplifier circuit of claim 90, wherein the level-down circuit is configured to control the on / off of the at least one switch circuit.

93. 91. The process of implementing an RF power amplifier circuit of claim 90, wherein the RF power amplifier circuit is configured to generate a single voltage and the level-down circuit is configured to be implemented using the single voltage.

94. providing an input impedance matching network; Providing a reference potential port; 73. A process for implementing the RF power amplifier circuit of claim 72, further comprising:

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