Method and system for manufacturing infrared transparent window wafer with integrated anti-reflection grating structure

Abstract

A method of fabricating an IR-transmitting window wafer with an integrated AR grating structure includes providing a handle wafer having a first surface and a second surface opposite the first surface; providing a device wafer including a monocrystalline silicon layer disposed on an oxide layer, the monocrystalline silicon layer having a planar side and the oxide layer having a bonding side opposite the planar side; forming the AR grating structure in a first portion of the first surface of the handle wafer; bonding the bonding side of the oxide layer to the first surface of the handle wafer; and etching a recess in the planar side of the monocrystalline silicon layer, wherein the buried oxide layer is removed, forming a plurality of recess walls, and exposing the AR grating structure in the first portion of the first surface of the handle wafer.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 430,957, filed December 7, 2022, entitled "Method and System for Manufacturing Infrared-Transparent Window Wafer with Integrated Anti-Reflection Grating Structure," the disclosure of which is incorporated herein by reference in its entirety for all purposes. [Background technology]

[0002]

[0002] As photodetector technology advances, new designs are able to achieve significantly improved resolution compared to past technologies. The resolution of a photodetector is determined, at least in part, by the number of pixels in the detector array. Typically, the more pixels in a detector array, the greater the level of detail that can be provided during image processing operations. Improvements in technology have made it possible to incorporate more pixels to improve resolution, while still producing pixels of much smaller size in the manufacturing process to maintain the overall form factor of the detector array.

[0003] Despite advances in detector arrays, there remains a need in the art for improved methods and systems related to detector arrays. Summary of the Invention

[0004]

[0004] In accordance with various aspects of the present disclosure, embodiments of the present disclosure relate to methods and systems for manufacturing infrared-transparent window wafers with integrated anti-reflection grating structures.

[0005] According to one embodiment of the present invention, a method for fabricating a focal plane array (FPA) structure is provided. The method includes providing a handle wafer having a first surface and a second surface opposite the first surface, providing a device wafer including a monocrystalline silicon layer disposed on an oxide layer, the monocrystalline silicon layer having a planar side and the oxide layer having a bonding side opposite the planar side, and forming an anti-reflection (AR) grating structure in a first portion of the first surface of the handle wafer. The method also includes bonding the bonding side of the oxide layer to the first surface of the handle wafer, etching a recess in the planar side of the monocrystalline silicon layer to remove the oxide layer, and forming a plurality of recess walls to expose the AR grating structure in the first portion of the first surface of the handle wafer.

[0006] In some embodiments, the method further includes forming an AR coating on the second surface of the handle wafer; depositing a getter material on a second portion of the first surface of the handle wafer, on the plurality of recess walls, or on a third portion of the second surface of the handle wafer; and bonding the FPA wafer to the planar side of the monocrystalline silicon layer. In various embodiments, the FPA wafer comprises an infrared detector pixel array and an infrared reference pixel. In some embodiments, the deposition of the getter material is performed using a shadow mask. In various embodiments, the method further includes etching a scribe alignment mark on the second surface of the handle wafer. In some embodiments, etching the recess on the planar side of the monocrystalline silicon layer is performed by dry etching followed by wet etching. In various embodiments, the first portion of the first surface of the handle wafer is disposed inside the plurality of recess walls.

[0007] According to another embodiment of the present invention, a method for fabricating an FPA structure is provided. The method includes providing a handle wafer having a first surface and a second surface opposite the first surface; providing a device wafer including a monocrystalline silicon layer disposed on an oxide layer, the monocrystalline silicon layer having a planar side and the oxide layer having a bonding side opposite the planar side; and forming an anti-reflective (AR) grating structure on a first portion of the first surface and a second portion of the second surface of the handle wafer. The method also includes bonding the bonding side of the oxide layer to the first surface of the handle wafer; etching a recess in the planar side of the monocrystalline silicon layer to remove the oxide layer; and forming a plurality of recess walls to expose the AR lattice structure on the first portion of the first surface of the handle wafer. In some embodiments, the method further includes depositing a getter material on a third portion of the first surface of the handle wafer, on the plurality of recess walls, or on a fourth portion of the second surface of the handle wafer; and bonding the FPA wafer to the planar side of the monocrystalline silicon layer.

[0008] According to certain embodiments of the present invention, a method for fabricating an FPA structure is provided. The method includes providing a handle wafer having a first surface and a second surface opposite the first surface, providing a device wafer including a monocrystalline silicon layer disposed on an oxide layer, the monocrystalline silicon layer having a planar side and the oxide layer having a bonding side opposite the planar side, and forming a first anti-reflection (AR) grating structure on a first portion of the first surface of the handle wafer. The method also includes bonding the bonding side of the oxide layer to the first surface of the handle wafer, forming a second AR grating structure on a second portion of the second surface of the handle wafer, etching a recess in the planar side of the monocrystalline silicon layer to remove the oxide layer, and forming a plurality of recess walls to expose the first AR grating structure on the first portion of the first surface of the handle wafer.

[0009] The present invention provides numerous advantages over conventional techniques. For example, embodiments of the present disclosure provide methods and systems for fabricating infrared-transparent window wafers incorporating antireflection grating structures. The embodiments enable etching a high-spatial-frequency antireflection (AR) grating structure into a first surface of an IR-transparent silicon handle wafer prior to bonding the handle wafer to a silicon device wafer to form a silicon-on-insulator (SOI) structure. The bonded SOI structure can be used to fabricate IR-transparent window wafers used in wafer-level vacuum packaging of uncooled bolometers. The disclosed methods enable fabrication of fine AR grating structures using submicron lithography and etching. Current approaches may form the AR grating structure after forming a cavity in an SOI structure that includes the handle wafer, which can present technical challenges due to non-planarity of the associated surfaces after cavity formation, making submicron lithography and etching unusable. To circumvent this technical challenge, embodiments disclose a fabrication method in which the AR grating structure is etched into the handle wafer prior to the bonding step that attaches the silicon device wafer to the handle wafer to form the SOI structure. These and other embodiments of the present disclosure, along with its many advantages and features, are described in further detail in conjunction with the following text and accompanying figures. [Brief explanation of the drawings]

[0010] Aspects of the present disclosure are described in more detail below with reference to the accompanying drawings, which are intended to be read in conjunction with both this summary, the detailed description, and the preferred and / or specific embodiments specifically discussed or disclosed. However, various aspects may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided for illustrative purposes only so that this disclosure will be thorough and complete, and will fully convey its full scope to those skilled in the art. [Figure 1A]1 illustrates a wafer-level vacuum packaging process for an uncooled bolometer-based focal plane array according to an embodiment of the present disclosure. [Figure 1B] 1 illustrates a wafer-level vacuum packaging process for an uncooled bolometer-based focal plane array according to an embodiment of the present disclosure. [Figure 1C] 1 illustrates a wafer-level vacuum packaging process for an uncooled bolometer-based focal plane array according to an embodiment of the present disclosure. [Figure 2] FIG. 1 is a cross-sectional view of a focal plane array assembly according to an embodiment of the present disclosure. [Figure 3] FIG. 1 illustrates an isometric view of a window die with an anti-reflection (AR) grating structure according to one embodiment of the present invention. [Figure 4A] 1 illustrates a cross-sectional view of a window die with AR grating structures on both sides according to an embodiment of the present disclosure. [Figure 4B] 4B is a graph illustrating the transmittance and reflectance of long wave infrared (LWIR) radiation through the window die of FIG. 4A in accordance with one embodiment of the present invention. [Figure 5] FIG. 2 is a cross-sectional view of a focal plane array assembly comprising an AR grating structure on a first surface of a handle die and an AR coating on a second surface of the handle die, according to one embodiment of the present invention. [Figure 6] FIG. 1B is a cross-sectional view of a focal plane array assembly with AR grating structures on both the first and second surfaces of the handle die according to one embodiment of the present invention. [Figure 7A] 1 illustrates a method of manufacturing a focal plane array assembly with an AR grating structure on a first surface of a handle die according to one embodiment of the present invention. [Figure 7B] 1 illustrates a method of manufacturing a focal plane array assembly with an AR grating structure on a first surface of a handle die according to one embodiment of the present invention. [Figure 7C] 1 illustrates a method of manufacturing a focal plane array assembly with an AR grating structure on a first surface of a handle die according to one embodiment of the present invention. [Figure 8]1 shows a simplified flowchart illustrating a method of manufacturing a focal plane array assembly with AR grating structures, according to one embodiment of the present invention. [Figure 9] FIG. 1B is a cross-sectional view of a window die with AR grating structures on both sides of the handle wafer according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0011]

[0021] The described embodiments relate generally to focal plane array (FPA) devices. More specifically, embodiments of the present disclosure provide methods and systems for fabricating infrared-transparent window wafers with integrated anti-reflection gratings.

[0012]

[0022] 1A-1C illustrate a wafer-level vacuum packaging (WLVP) process for uncooled bolometer-based focal plane arrays (FPAs) according to an embodiment of the present disclosure. In the illustrated embodiment, a solder ring is placed around each die on the FPA wafer, and a corresponding seal ring is placed on the corresponding window wafer. The FPA wafer and window wafer can be aligned and bonded in a vacuum environment. After wafer bonding, slots are cut in the window wafer to provide access to the probe pads on the FPA wafer, allowing for radiometric testing of the vacuum-packaged FPA at the wafer scale after bonding. Wafer-level vacuum packaging can provide a relatively small, lightweight, and low-cooling solution for packaging uncooled FPAs.

[0013]

[0023] Modern bolometer-based uncooled infrared (IR) imaging FPAs can thermally isolate bolometer pixels from the environment to maximize the temperature change of the bolometer pixels caused by the infrared scene flux incident on the pixel. Temperature-dependent resistive transducers can detect temperature changes caused by the scene through changes in resistance. Temperature-dependent resistive transducers can be made from, but are not limited to, vanadium oxide (VOx) or amorphous silicon (a-Si). An array of bolometer pixels addressed by a readout integrated circuit (ROIC) chip enables bolometer-based uncooled infrared imaging FPAs to image the scene. Thermal isolation of the bolometer pixels can be achieved by using relatively long, low-thermal-conductivity legs that electrically connect the bolometer transducer to the underlying ROIC. To achieve relatively high sensitivity, arrays of bolometer pixels can be vacuum-packaged to reduce or eliminate heat conduction by gas molecules within the package. A vacuum of less than 10 mTorr is maintained in the package to reduce or eliminate the effects of gas thermal conduction within the package.

[0014]

[0024] To maximize the transmission of scene radiation through an IR-transmitting silicon window in the spectral band of interest, such as the long-wave infrared (LWIR) spectral band (typically 7.5 μm to 13.5 μm), the window can be coated with an anti-reflection (AR) coating on both sides.

[0015]

[0025] FIG. 2 is a cross-sectional view of a focal plane array (FPA) assembly according to an embodiment of the present disclosure. FIG. 2 shows a cross-sectional view of an FPA assembly 200 in which a window die has an AR coating on both sides. The FPA assembly 200 includes a window die 220 and a device die 208. The window die 220 can be bonded to the device die 208 by solder joints 215. The device die 208 can include an infrared detector pixel array 218 disposed on a first surface 207 of the device die 208 and an optically blind infrared pixel array 216 disposed on the first surface 207. The device die 208 can further include solder ring metallization 214. The solder joints 215 can be formed on the solder ring metallization 214. The device die 208 can include bond pads 206 disposed on the first surface 207 of the device die 208. The bond pads 206 can be used to form connections to a semiconductor package. The bond pads 206 can be used to electrically connect to the ROIC, to address and bias the ROIC, to operate the ROIC, and to read the electrical signals output by the infrared detector pixel array 218.

[0016]

[0026] The window die 220 can include a handle die 224 and a device die 226. In some embodiments, the handle die 224 can be, for example, 600 μm thick, and the device die 226 can be, for example, 200 μm thick. The device die 226 can include a monocrystalline silicon layer 225 disposed on a buried oxide layer 222. In some embodiments, the buried oxide layer 222 can be, for example, 1-2 μm thick. The buried oxide layer 222 can be bonded to the bonding side of the handle die 224. The window die 220 can include a recess 202. The recess 202 can be formed by etching the device die 226, which also removes the buried oxide layer 222. The device die 226 can include a solder ring metallization 212. A solder joint 215 can be connected to the solder ring metallization 212.

[0017]

[0027] The cavity 209 may be formed adjacent to the recess 202 and may be located between the device die 208 and the window die 220. The cavity 209 and recess 202 may be in a vacuum environment. The getter material may be formed on the mating side of the handle die 224 in region 210a, on the die wall surface in region 210b, and on a second side of the device die 226 in region 210c. In this manner, the surface of the die wall is used to form the getter material, thereby increasing or maximizing the surface area of ​​the getter material within the cavity 209 and recess 202. The recess 202 may be made deeper or shallower by adjusting the thickness of the device die 226. If the optical aperture allows, the recess depth may be increased, thereby increasing the available getter area on the die wall surface in region 210b. In some embodiments, the perimeter of the recess 202, and therefore the size of the recess 202, may be reduced to allow getter to be formed on all sides of the recess 202. In this manner, the volume of recess 202 is reduced while allowing additional getter material to be disposed within the volume defined by recess 202. Accordingly, embodiments of the present invention not only utilize getter material to form a light blocking structure over infrared pixel array 216, but also increase the amount of getter material and thus the amount of getter area in a vacuum environment by depositing getter material on both the die wall surfaces in region 210b and / or the mating side of handle die 224 in region 210a. It should be noted that while embodiments of the present invention reduce the perimeter of recess 202, thereby reducing the volume corresponding to recess 202, this volume reduction reduces the volume-to-getter surface area ratio, which is typically undesirable. However, because getter material is formed on the die wall surfaces in region 210b, the volume-to-getter surface area ratio can be maintained or increased despite the reduced volume. As will be apparent to those skilled in the art, the amount of getter material that can be formed on the mating side of handle die 224 in region 210a is limited by the optical aperture required to receive infrared light passing through handle die 224 and reaching infrared detector pixel array 218. Obviously, many variations, modifications, and alternatives will be apparent to those of ordinary skill in the art.

[0018]

[0028] As shown in FIG. 2 , the height of cavity 209, measured along the Z direction, can be much smaller than the height of recess 202, also measured along the Z direction. As discussed above, the height of recess 202 is related to the thickness of device die 226 (e.g., 200 μm), while the height of cavity 209 is related to the thickness of solder ring 212, solder joint 215, and solder ring metallization layer 214 (on the order of 10 μm). Therefore, blocking light from reaching infrared pixel array 216 is facilitated by embodiments of the present invention because disposing getter material in region 210 c closer to infrared pixel array 216 provides more effective light blocking performance. At the same time, the height of recess 202 is independent of the height of cavity 209, allowing for a larger volume for a given surface area, which is desirable for achieving low-pressure (e.g., 10 mTorr) environments.

[0019]

[0029] A first anti-reflection (AR) coating 204 may be formed on the planar side of the handle die 224. A second AR coating 211 may be formed on the mating side of the handle die 224. The handle die 224 may be transparent to infrared light so that infrared light can pass through the handle die 224 and impinge on the infrared detector pixel array 218. The AR coating may be formed on both the planar side and the mating side of the handle die 224 in areas open to the collection aperture of the scene flux incident on the infrared detector pixel array 218. In some embodiments, the anti-reflection layer may be a deposited AR coating, such as a multilayer dielectric stack. In various embodiments, the AR layer may be formed from a high spatial frequency anti-reflection grating etched into the surface of the handle die.

[0020]

[0030] The height of the recess 202 is on the order of 200 μm, which allows the second AR coating 211 to be close enough to the infrared detector pixel array 218 to be within the depth of field of the imaging optics, such that any imperfections in the second AR coating 211 can adversely affect the imaging performance of the FPA assembly and result in image artifacts.

[0021]

[0031] 3 shows an isometric view of a window die with an anti-reflection (AR) grating structure according to one embodiment of the present invention. In the illustrated embodiment, a silicon handle wafer 302 is shown with a two-dimensional binary grating structure including a plurality of square pillars 310 having a width 308 (w), a periodically spaced pitch 304 (p), and a depth distance 306 (d). The square pillars are formed of silicon, and the depth distance is defined by etching into the silicon. The illustrated two-dimensional binary grating has a pitch p<λ edge / n Si λ is a high spatial frequency diffraction grating. edge is the shortest wavelength in the 7.5 μm to 13.5 μm WIIR spectral band of interest, i.e., λ edge = 7.5 μm, n Si Approximately 3.42 is the refractive index of silicon in the LWIR spectral band. edge / n Si In high spatial frequency gratings, the only propagation modes of the grating within the LWIR spectral band are the zeroth-order transmission mode T0 and the zeroth-order reflection mode R0. In some embodiments, the energy of the zeroth-order reflection mode R0 is reduced or minimized, thereby increasing or maximizing the transmission of the zeroth-order transmission mode T0. In imaging systems, the system's collection optics direct a radiation cone incident on a silicon window. In this case, the zeroth-order transmission mode T0 and the zeroth-order reflection mode R0 can remain the only propagation modes for all angles of incidence limited by the radiation cone.

[0022]

[0032] Examples of AR grating structures with two different pitches are shown in Table 1. [Table 1]

[0023]

[0033] The AR grating structure with a pitch p = 1.85 μm can suppress high-order diffraction modes from normal incidence up to an incident angle of approximately 39°. The AR grating structure with a pitch p = 1.75 μm can suppress high-order diffraction modes from normal incidence up to an incident angle of approximately 60°. These two grating structures can be used as anti-reflection structures because they suppress high-order diffraction over a wide range of incident angles.

[0024]

[0034] Refractive index n air To maximize the transmission of IR radiation through an air-to-silicon or equivalently silicon-to-air interface with θ = 1, the effective refractive index of the AR grating, n eff becomes:

number

number

[0025]

[0035] The example AR grating structures in both Figure 3 and Table 1 (pitch p = 1.85 μm and Si pillar w ~ 1.33 μm, or pitch p = 1.75 μm and Si pillar w ~ 1.26 μm) show n in the etched grating area. eff The pitch p of the AR grating can be approximately 1.84. As explained above, the exemplary AR grating structure with a pitch p=1.85 μm can suppress higher-order diffraction modes and function as an AR grating in the LWIR spectral band from normal incidence to an angle of incidence of 39°. The exemplary AR grating structure with a pitch p=1.75 μm can suppress higher-order diffraction modes and function as an AR grating in the LWIR spectral band from normal incidence to an angle of incidence of approximately 60°.

[0026]

[0036] Furthermore, the depth distance 306(d) can be determined as follows: The depth distance 306(d) is the effective refractive index of the grating, n eff The selected wavelength λ can be determined by the quarter-wave thickness requirement that minimizes the reflected radiation from the surface. peak , the minimum quarter-wave reflectance d within the LWIR spectral band is: d=λ peak / (4n eff ) For example, if the peak transmittance is λ peak = 9 μm, the optimum AR grating depth distance d to be etched into the silicon window is given by: d~9 / (4*1.84)~1.2μm The depth distance d is approximately 1.2 μm for both example AR grating structures in Table 1. This depth distance is etched into the silicon and acts as an anti-reflection structure for both the air-to-Si and Si-to-air (or vacuum) interfaces.

[0027]

[0037] Although a square prism 310 is shown in Figure 3, embodiments of the present invention are not limited to this particular shape, and other shapes, including circular, oval, complementary silicon ridge structures with square grooves, etc., may be used and are within the scope of the present invention. Many variations, modifications, and alternatives will be apparent to those skilled in the art.

[0028]

[0038] 4A shows a cross-sectional view of a window die with AR grating structures on both sides, according to an embodiment of the present disclosure. The window die 407 is made of silicon and has n Si = 3.42. The window die 407 can have a first surface 402 and a second surface 404 opposite the first surface 402. The AR grating structure on the first surface can have an index of refraction of n eff = 1.84 μm and d = 1.2 μm, and the AR grating structure on the second surface can have n eff= 1.84 μm and d = 1.2 μm. Arrow 406 represents incident LWIR radiation (n = 1) into air, and arrow 414 represents reflected LWIR radiation from first surface 402. Arrows 408 and 412 represent the zeroth order mode of LWIR radiation propagating within window die 407. Arrow 410 represents incident LWIR radiation exiting window die 407 into air or vacuum.

[0029]

[0039] 4B is a graph showing LWIR transmittance and reflectance through the window die of FIG. 4A in accordance with one embodiment of the present invention. FIG. 4B shows modeling of LWIR transmittance at normal incidence through a silicon window die with an optimally designed AR grating structure with an etch depth distance of 1.2 μm. Graph 420 shows the transmittance including dispersion and transmission losses through silicon, while graph 422 shows the transmittance without dispersion and transmission losses through silicon. As shown in FIG. 4B, λ peak The transmittance peak is observed at n = 9 μm. Si The transmission of a lossless silicon window (i.e., ignoring dispersion losses) of approximately 3.42 is λ peak = 9 μm, resulting in an average transmittance of approximately 94% across the 7.5-13.5 μm spectral band. In practice, IR-transmitting silicon used in infrared window applications may exhibit some degree of dispersion loss, which, when included, can reduce the average transmittance across the 7.5-13.5 μm spectral band to approximately 86% for a silicon window die thickness of 600 μm. By comparison, a bare silicon window without an anti-reflection structure on its surface has a significantly lower average transmittance across the 7.5-13.5 μm spectral band: 54% ignoring dispersion losses, and 49% including dispersion losses (see Table 2). [Table 2] Table 2

[0030]

[0040] 5 is a cross-sectional view of a focal plane array (FPA) assembly with an AR grating structure on a first surface of a handle die and an AR coating on a second surface of the handle die, according to one embodiment of the present invention. FIG. 5 shows a cross-sectional view of an FPA assembly 500 that is similar to FPA assembly 200, except that the first surface of handle die 224 includes an AR grating structure 511 and the second surface of handle die 224 includes a first AR coating 204. The inventors have determined that fabricating an AR grating structure 511 with submicron features in recess 202 presents numerous manufacturing challenges. Accordingly, embodiments of the present invention provide methods and systems for fabricating an AR grating structure 511 in recess 202 with desired optical properties.

[0031]

[0041] Figure 6 is a cross-sectional view of a focal plane array assembly including AR grating structures on both the first and second surfaces of the handle die, according to one embodiment of the present invention. The disclosure provided in connection with Figures 2 and 5 also applies to Figure 6, as appropriate. Figure 6 shows a cross-sectional view of an FPA assembly 600 that is similar to FPA assembly 200, except that AR grating structures 511 and 604 are included on both the first and second surfaces of handle die 224, respectively.

[0032]

[0042] 7A-7C illustrate a method for fabricating a focal plane array assembly with an AR grating structure on a first surface of a handle die according to one embodiment of the present invention. In the illustrated embodiment, the method includes etching a high-spatial frequency AR grating structure on a first surface of an IR-transparent silicon handle wafer before bonding the handle wafer to a silicon device wafer, thereby forming a silicon-on-insulator (SOI) structure including the high-spatial frequency AR grating structure. The bonded structure integrated with the high-spatial frequency AR grating structure can be used in the fabrication of IR-transparent window wafers used in wafer-level vacuum packaging processes for uncooled bolometers.

[0033]

[0043] The disclosed method enables the fabrication of submicron AR grating structures using lithography and etching processes. In contrast to approaches that form AR grating structures after forming cavities in an SOI structure, which may face technical challenges in that the non-planar surface prevents the use of submicron lithography and etching after cavity formation, embodiments of the present invention form the AR grating structure before forming the cavities in the SOI structure. Therefore, to circumvent this technical challenge, embodiments disclose a fabrication method, as shown in Figures 7A-7C, in which an AR grating structure is etched into a handle wafer prior to the bonding step that attaches a silicon-on-insulator wafer (i.e., a single-crystal silicon device layer and a buried oxide) to the handle wafer to form the SOI structure. As will be apparent to those skilled in the art, fabrication of SOI structures can utilize oxide growth on either the handle wafer and / or the single-crystal silicon wafer during the fabrication process of the SOI structure.

[0034]

[0044] As shown in FIG. 7A , a handle wafer 702 is provided having a first surface 707 and a second surface 709. AR grating structures 708 can be etched into the first surface 707 of the handle wafer 702. At this point in the fabrication process, the first surface 707 is planar, allowing for faithful sub-micron patterning and etching of the AR grating structures 708 into the first surface 707 of the handle wafer 702. The disclosed method further includes etching scribe alignment marks 710 into the second surface 709 of the handle wafer 702. The scribe alignment marks allow for alignment between the patterns on the first and second surfaces in subsequent fabrication steps. In some embodiments, the AR grating structures 708 are fabricated prior to fabrication of the scribe alignment marks 710.

[0035]

[0045] In some embodiments, a protective oxide layer 703 can be formed on the second surface 709. The thickness of the protective oxide layer 703 can be, for example, 1-2 μm. In various embodiments, the handle wafer 702 can have a thickness of, for example, 600 μm and can be made from silicon, which is IR transparent and has low scattering losses.

[0036]

[0046] As shown in FIG. 7B, a handle wafer 702, also referred to as a handle die, and a device wafer 704, also referred to as an SOI wafer, SOI die, or device die, can be bonded to form an SOI structure. The device wafer 704 can have a planar side 711 and a bonding side 715. The device wafer 704 can have a single crystal silicon device layer 717 disposed on a buried oxide layer 712. The bonding surface 715 of the device wafer 704 can be bonded to a first surface 707 of the handle wafer 702. In some embodiments, the buried oxide layer can have a thickness of, for example, 1-2 μm. In various embodiments, the device wafer 704 can have a thickness of, for example, 200 μm.

[0037]

[0047] In some embodiments, a buried oxide layer 712 is grown on the bond side 715 of the single crystal silicon device layer 717 before bonding the device wafer 704 and the handle wafer 702 because oxide growth consumes silicon during the oxide growth process. This process prevents altering the shape of the AR lattice structure 708 that was previously etched into the first surface 707 of the handle wafer 702. Thus, in these embodiments, the single crystal silicon device layer 717 and the buried oxide layer 712 are bonded to the handle wafer 702. Note that the recessed portions of the AR lattice structure 708 do not have to be bonded to the handle wafer 702. However, the inventors have determined that the protruding portions of the AR lattice structure 708 and other portions of the first surface 707 of the handle wafer 702 provide sufficient bonding area to form a bond suitable for SOI structures.

[0038]

[0048] In another embodiment, the AR grating structure 708 is fabricated on the first surface 707 of the handle wafer 702, after which a buried oxide is grown on the first surface 707 of the handle wafer 702. Because this oxide growth process consumes a portion of the AR grating structure 708, the AR grating structure is initially fabricated with larger dimensions than the final dimensions that will be obtained after growth and subsequent removal of the buried oxide, as described below in connection with FIG. 7C. Many variations, modifications, and alternatives will be apparent to those skilled in the art.

[0039]

[0049] As shown in FIG. 7C , recesses 706 can be etched in the planar side 711 of the single crystal silicon device layer 717 to remove the buried oxide layer 712, form recess walls 719, and expose the AR lattice structure 708. In some embodiments, the depth of the recesses 706 can be, for example, 200 μm. The recess etching can be performed by dry etching followed by wet etching, during which the buried oxide layer 712 is removed. In various embodiments, the fabrication method further includes depositing a getter material on a third portion of the first surface of the handle wafer, on the plurality of recess walls, or on a fourth portion of the second surface of the handle wafer, and bonding the FPA wafer to the planar side of the single crystal silicon layer.

[0040]

[0050] 8 is a simplified flowchart illustrating a method for fabricating an FPA structure with an AR grating structure according to an embodiment of the present disclosure. As shown in FIG. 8, the method for fabricating an FPA structure includes providing a handle wafer having a first surface and a second surface (840). The method also includes providing a device wafer having a planar side and a bonding side (842), the device wafer including a monocrystalline silicon layer and an oxide layer. The method further includes forming an AR grating structure on a first portion of the first surface of the handle wafer (844).

[0041]

[0051] The method also includes bonding the bonding surface of the device wafer to the first surface of the handle wafer (846). The method also includes etching a recess in the planar side of the device wafer to remove a portion of the oxide layer, form a plurality of recess walls, and expose an AR lattice structure on the first surface of the handle wafer (848). As shown in FIG. 7C , the recess 706 passes through a portion of the monocrystalline silicon device layer 717 and a portion of the oxide layer 712. Furthermore, the method also includes forming an anti-reflective (AR) coating on the second surface of the handle wafer (850). Additionally, the method also includes depositing a getter material on a second portion of the first surface, the plurality of recess walls, and / or a third portion of the second surface of the handle wafer (852). Additionally, the method also includes bonding an FPA wafer (e.g., an ROIC substrate) to the planar side of the monocrystalline silicon wafer (854).

[0042]

[0052] It should be understood that the specific steps illustrated in FIG. 8 provide a particular method for fabricating an FPA structure comprising an AR grating structure according to one embodiment of the present invention. Other sequences of steps may be performed according to alternative embodiments. For example, alternative embodiments of the present disclosure may perform the steps outlined above in a different order. Furthermore, the individual steps illustrated in FIG. 8 may include multiple sub-steps that may be performed in various sequences depending on the individual step. Furthermore, additional procedures may be added or removed depending on the particular application. Many variations, modifications, and alternatives will be apparent to those skilled in the art.

[0043]

[0053] In some embodiments, the AR grating structure can be formed on both sides of the handle wafer. Figure 9 shows a window wafer with an AR grating structure 708 fabricated on a first surface 707 of the handle wafer and an AR grating structure 902 fabricated on a second surface 709 of the handle wafer. The AR grating structures 708 and 902 can both be formed at the beginning of fabrication, similar to Figure 7A. In some embodiments, the AR grating structure 902 can be formed after the SOI wafer 704 is bonded to the handle wafer 702, because the second surface 709 of the handle wafer 702 remains relatively flat throughout the fabrication process. In various embodiments, the AR grating structure 902 can be formed after the recess 706 is formed.

[0044]

[0054] Various examples of the present disclosure are provided below. As used below, references to a series of examples shall be understood as referring to each example separately (e.g., "Examples 1-4" shall be understood as "Example 1, 2, 3, or 4").

[0045]

[0055] Example 1 is a method for fabricating a focal plane array (FPA) structure, the method including: providing a handle wafer having a first surface and a second surface opposite the first surface; providing a device wafer including a monocrystalline silicon layer disposed on an oxide layer, the monocrystalline silicon layer having a planar side and the oxide layer having a bonding side opposite the planar side; forming an anti-reflection (AR) grating structure on a first portion of the first surface of the handle wafer; bonding the bonding side of the oxide layer to the first surface of the handle wafer; and etching a recess in the planar side of the monocrystalline silicon layer to remove the oxide layer, form a plurality of recess walls, and expose the AR grating structure on the first portion of the first surface of the handle wafer.

[0046]

[0056] Example 2 is a method for fabricating the FPA structure of Example 1, further comprising the steps of forming an AR coating on the second surface of the handle wafer; depositing a getter material on a second portion of the first surface of the handle wafer, on the plurality of recess walls, or on a third portion of the second surface of the handle wafer; and bonding the FPA wafer to the planar side of the monocrystalline silicon layer.

[0047]

[0057] Example 3 is a method for manufacturing the FPA structure of Examples 1-2, in which the FPA wafer comprises an infrared detector pixel array and an infrared reference pixel.

[0048]

[0058] Example 4 is a method for manufacturing the FPA structure of Examples 1-2, in which deposition of the getter material is performed using a shadow mask.

[0049]

[0059] Example 5 is a method for manufacturing the FPA structure of Example 1, further comprising etching scribe alignment marks on the second surface of the handle wafer.

[0050]

[0060] Example 6 is a method for manufacturing the FPA structure of Example 1, in which the step of etching a recess in the flat side of the single crystal silicon layer is performed by dry etching and then wet etching.

[0051]

[0061] Example 7 is a method for manufacturing the FPA structure of Example 1, wherein the first portion of the first surface of the handle wafer is disposed inside the plurality of recess walls.

[0052]

[0062] Example 8 is a method of fabricating a focal plane array (FPA) structure, comprising: providing a handle wafer having a first surface and a second surface opposite the first surface; providing a device wafer including a monocrystalline silicon layer disposed on an oxide layer, the monocrystalline silicon layer having a planar side and the oxide layer having a bonding side opposite the planar side; forming an anti-reflection (AR) grating structure on a first portion of the first surface of the handle wafer and on a second portion of the second surface; bonding the bonding side of the oxide layer to the first surface of the handle wafer; and etching a recess in the planar side of the monocrystalline silicon layer to remove the oxide layer, form a plurality of recess walls, and expose the AR grating structure on the first portion of the first surface of the handle wafer.

[0053]

[0063] Example 9 is a method for fabricating the FPA structure of Example 8, further comprising depositing a getter material on a third portion of the first surface of the handle wafer, on the plurality of recess walls, or on a fourth portion of the second surface of the handle wafer, and bonding the FPA wafer to the planar side of the monocrystalline silicon layer.

[0054]

[0064] Example 10 is a method for manufacturing the FPA structure of Examples 8-9, in which the FPA wafer comprises an infrared detector pixel array and an infrared reference pixel.

[0055]

[0065] Example 11 is a method for manufacturing the FPA structure of Examples 8-9, in which deposition of the getter material is carried out using a shadow mask.

[0056]

[0066] Example 12 is a method for fabricating the FPA structure of Example 8, further comprising etching scribe alignment marks on the second surface of the handle wafer.

[0057]

[0067] Example 13 is a method for manufacturing the FPA structure of Example 8, in which the step of etching a recess in the flat side of the single-crystal silicon layer is performed by dry etching and then wet etching.

[0058]

[0068] Example 14 is a method of manufacturing the FPA structure of Example 8, wherein the first portion of the first surface of the handle wafer is disposed inside the plurality of recess walls.

[0059]

[0069] Example 15 is a method of fabricating a focal plane array (FPA) structure, the method comprising: providing a handle wafer having a first surface and a second surface opposite the first surface; providing a device wafer including a monocrystalline silicon layer disposed on an oxide layer, the monocrystalline silicon layer having a planar side and the oxide layer having a bonding side opposite the planar side; forming a first anti-reflection (AR) grating structure on a first portion of the first surface of the handle wafer; bonding the bonding side of the oxide layer to the first surface of the handle wafer; forming a second AR grating structure on a second portion of the second surface of the handle wafer; and etching a recess in the planar side of the monocrystalline silicon layer to remove the oxide layer, form a plurality of recess walls, and expose the AR grating structure on the first portion of the first surface of the handle wafer.

[0060]

[0070] Example 16 is a method for fabricating the FPA structure of Example 15, further comprising depositing a getter material on a third portion of the first surface of the handle wafer, on the plurality of recess walls, and on a fourth portion of the second surface of the handle wafer; and bonding the FPA wafer to the planar side of the monocrystalline silicon layer.

[0061]

[0071] Example 17 is a method for manufacturing the FPA structure of Examples 15-16, in which the FPA wafer comprises an infrared detector pixel array and an infrared reference pixel.

[0062]

[0072] Example 18 is a method for fabricating the FPA structure of Examples 15-16, in which deposition of the getter material is carried out using a shadow mask.

[0063]

[0073] Example 19 is the method of fabricating the FPA structure of Example 15, further comprising etching scribe alignment marks on the second surface of the handle wafer.

[0064]

[0074] Example 20 is a method for manufacturing the FPA structure of Example 15, in which the step of etching a recess in the flat side of the single-crystal silicon layer is performed by dry etching and then wet etching.

[0065]

[0075] The names of the various structures may be used interchangeably, for example, a device wafer may be called an FPA wafer, and a silicon-on-insulator wafer may be called a device wafer or an SOI structure.

[0066]

[0076] Those skilled in the art will appreciate that other modifications can be made to the apparatus and methods of the present invention to implement various applications of the method and system for manufacturing infrared-transmitting window wafers with integrated anti-reflection gratings without departing from the scope of the present invention.

[0067]

[0077] The examples and embodiments described herein are for illustrative purposes only. Various modifications and variations therein will be apparent to those skilled in the art. These are intended to be included within the spirit and scope of this application and the appended claims.

Claims

1. 1. A method for fabricating a focal plane array (FPA) structure, comprising: providing a handle wafer having a first surface and a second surface opposite the first surface; providing a device wafer including a monocrystalline silicon layer disposed on an oxide layer, the monocrystalline silicon layer having a planar side and the oxide layer having a bonding side opposite the planar side; forming an anti-reflective (AR) grating structure on a first portion of the first surface of the handle wafer; bonding the bonding side of the oxide layer to the first surface of the handle wafer; Etching a recess into the planar side of the monocrystalline silicon layer, removing the oxide layer; forming a plurality of recess walls; exposing the AR grating structure on the first portion of the first surface of the handle wafer; A method for manufacturing a focal plane array (FPA) structure, comprising:

2. forming an AR coating on the second surface of the handle wafer; depositing a getter material on a second portion of the first surface of the handle wafer, on the plurality of recess walls, or on a third portion of the second surface of the handle wafer; bonding an FPA wafer to the planar side of the single crystal silicon layer; The method of claim 1 further comprising:

3. The method of claim 2 , wherein the FPA wafer comprises an infrared detector pixel array and an infrared reference pixel.

4. The method of claim 2 , wherein the step of depositing the getter material is performed using a shadow mask.

5. The method of claim 1 , further comprising etching scribe alignment marks into the second surface of the handle wafer.

6. 2. The method of claim 1, wherein etching the recess into the planar side of the monocrystalline silicon layer is performed by dry etching followed by wet etching.

7. The method of claim 1 , wherein the first portion of the first surface of the handle wafer is disposed within the plurality of recess walls.

8. 1. A method for fabricating a focal plane array (FPA) structure, comprising: providing a handle wafer having a first surface and a second surface opposite the first surface; providing a device wafer including a monocrystalline silicon layer disposed on an oxide layer, the monocrystalline silicon layer having a planar side and the oxide layer having a bonding side opposite the planar side; forming an anti-reflection (AR) grating structure on a first portion of the first surface and a second portion of the second surface of the handle wafer; bonding the bonding side of the oxide layer to the first surface of the handle wafer; Etching a recess into the planar side of the monocrystalline silicon layer, removing the oxide layer; forming a plurality of recess walls; exposing the AR grating structure on the first portion of the first surface of the handle wafer.

9. depositing a getter material on a third portion of the first surface of the handle wafer, on the plurality of recess walls, or on a fourth portion of the second surface of the handle wafer; bonding an FPA wafer to the planar side of the single crystal silicon layer; The method of claim 8 further comprising:

10. The method of claim 9 , wherein the FPA wafer comprises an infrared detector pixel array and an infrared reference pixel.

11. The method of claim 9 , wherein the step of depositing the getter material is performed using a shadow mask.

12. 9. The method of claim 8, further comprising etching scribe alignment marks into the second surface of the handle wafer.

13. 9. The method of claim 8, wherein etching the recess into the planar side of the monocrystalline silicon layer is performed by dry etching followed by wet etching.

14. The method of claim 8 , wherein the first portion of the first surface of the handle wafer is disposed within the plurality of recess walls.

15. 1. A method for fabricating a focal plane array (FPA) structure, comprising: providing a handle wafer having a first surface and a second surface opposite the first surface; providing a device wafer including a monocrystalline silicon layer disposed on an oxide layer, the monocrystalline silicon layer having a planar side and the oxide layer having a bonding side opposite the planar side; forming a first anti-reflective (AR) grating structure on a first portion of the first surface of the handle wafer; bonding the bonding side of the oxide layer to the first surface of the handle wafer; Etching a recess into the planar side of the monocrystalline silicon layer, removing the oxide layer; forming a plurality of recess walls; exposing the AR grating structure on the first portion of the first surface of the handle wafer.

16. depositing a getter material onto a third portion of the first surface of the handle wafer, onto the plurality of recess walls, and onto a fourth portion of the second surface of the handle wafer; 16. The method of claim 15, further comprising bonding an FPA wafer to the planar side of the monocrystalline silicon layer.

17. The method of claim 16 , wherein the FPA wafer comprises an infrared detector pixel array and an infrared reference pixel.

18. 17. The method of claim 16, wherein the step of depositing the getter material is performed using a shadow mask.

19. 16. The method of claim 15, further comprising etching scribe alignment marks into the second surface of the handle wafer.

20. 16. The method of claim 15, wherein etching the recess into the planar side of the monocrystalline silicon layer is performed by dry etching followed by wet etching.

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