A reconfigurable computing platform for executing computations expressed as data flow graphs (DFGs) using a static data flow method

Abstract

A reconfigurable computing platform (100) is provided for static dataflow execution of a computation kernel represented as a data flow graph (DFG). The DFG is directly implemented on hardware. The computing platform (100) has multiple components arranged in a matrix, including processing elements (PEs) (102-1 to 102-n) and switching elements (SEs) (104-1 to 104-n). A computation process represented as a DFG is realized on the reconfigurable computing platform (100) by mapping multiple nodes of the DFG to the PEs (102-1 to 102-n) and routing edges between these nodes through a circuit-switched network formed by the SEs (104-1 to 104-n), thereby forming a virtual circuit. The reconfigurable computing platform (100) is configured to operate in a configuration and execution manner that allows multiple components to be configured prior to execution.

Description

[Technical Field]

[0001] The present invention relates to a hardware accelerator, which is essential for executing computational processes in a computing system. More specifically, the present invention relates to a reconfigurable computing platform for static dataflow execution of various computational processes expressed as a data flow graph (DFG), where the DFG is directly implemented on hardware. [Background technology]

[0002] In response to the increasing demand for faster computational performance, dedicated hardware accelerators have appeared in recent computing systems.

[0003] Hardware accelerators play a central role in enhancing the computational power of computing systems. These specialized units are designed to optimize the execution of specific computational tasks, significantly improving performance compared to traditional processors. The emergence of such hardware accelerators has been driven by the exponential growth of data-centric applications such as artificial intelligence, machine learning, signal processing, and scientific simulation.

[0004] Central processing units (CPUs) are valued for their versatility, featuring general-purpose processor pipelines capable of handling a wide variety of applications. However, non-computational operations in a general-purpose processor pipeline, such as instruction fetching and decoding, branch handling and speculative execution, scoreboarding, and interlocking, can consume significant amounts of power. These inefficiencies can degrade performance in specialized computational tasks.

[0005] Application-specific integrated circuits (ASICs) are custom designed and therefore highly efficient for specific applications. However, their inflexibility severely limits their effectiveness and performance for other computational tasks, resulting in performance degradation beyond the intended range of applications.

[0006] Field-programmable gate arrays (FPGAs) are reconfigurable, allowing dedicated accelerators to be synthesized as needed. However, the fine-grained nature of look-up tables (LUTs) can lead to long configuration times and slower operating frequencies, which impacts the overall computing performance of the FPGA.

[0007] Graphics Processing Units (GPUs) excel at accelerating parallel applications, but they also consume excessive power due to their complex control hardware, complex memory access patterns, and large register files. In particular, the complex warp scheduling hardware and the large and wide register banks consume significant power, limiting the overall processing efficiency of GPUs.

[0008] As mentioned above, existing hardware accelerators have drawbacks that limit their adaptability, power efficiency, and overall computing performance. Therefore, a hardware accelerator architecture that addresses these drawbacks by targeting a broader range of applications and improving power efficiency and performance is desirable. Summary of the Invention

[0009] This specification discloses a hardware accelerator (reconfigurable computing platform) configuration that represents a computational process as a data flow graph (DFG) and executes the DFG in a static data flow manner. The DFG is characterized by being directly implemented in hardware as shown in at least one of the drawings or described in relation to the drawings, and is more specifically defined in the claims. The reconfigurable computing platform includes multiple components arranged in a matrix. These components include processing elements (PEs) and switching elements (SEs). The reconfigurable computing platform is further configured to receive data via a fabric interface unit (FIF) connected to the periphery of the components arranged in the matrix.

[0010] This compute infrastructure is reconfigurable in terms of execution style and programming abstraction, allowing programmers to optimize the combination of computational processes and the compute infrastructure. Therefore, multiple components (PEs and SEs) can be reconfigured as vector SIMD datapaths, capable of pipelined multi-cycle operations (vector processing) and parallel independent operations on multiple data sets (SIMD parallelism). Furthermore, multiple components (PEs and SEs) can be reconfigured as MIMO dataflow datapaths, capable of processing multiple-input, multiple-output (MIMO) operations chained based on data dependencies. Furthermore, multiple components (PEs and SEs) can be reconfigured as subword SIMD datapaths, capable of performing mixed-precision operations on packed data.

[0011] Each PE has a multiplexer, a configuration register (CR), and a FIFO (First-In, First-Out Buffer). These are designed to store valid input operands before executing an operation, and also store operation results and transfer them sequentially to their corresponding destinations. The PE contains functional units such as an arithmetic logic unit (ALU) and a floating-point unit (FPU) to perform the actual operations. The CR is configured to link input operands and operation results to specific input sources and output destinations corresponding to the west, north, east, or south directions. The CR also allows the selection of various operations in these functional units.

[0012] The functional units in the PEs are configured to perform at least one of a plurality of operations, including, but not limited to, 32-bit pipelined multi-cycle arithmetic and logic operations, single-precision floating-point operations, sub-word SIMD arithmetic and logic operations in 8-bit and 16-bit data widths, reduction tree operations with arithmetic and logic operations after sub-word SIMD operations, compare and exchange operations, and conditional accumulate operations. The PEs can perform operations based on input operands received from the SEs and / or FIFs and generate operation results that are routed through the SEs and / or FIFs.

[0013] Each SE includes central control logic, input and output lanes, a CR, and a multiplexer in each output lane to control the routing of data.

[0014] This reconfigurable computing platform is configured to operate in a configuration mode and an execution mode. The CRs of the PEs and SEs are configured in the configuration mode, and the computation is executed in the execution mode. The configuration and execution are performed dynamically.

[0015] A computation is first represented in the form of a DFG. A DFG is a graph in which nodes represent operations and edges represent dependencies between operations. The DFG is assumed to contain computations that can be directly mapped onto the PEs of the infrastructure. Mapping this DFG onto the infrastructure involves assigning nodes to PEs and configuring SEs to configure suitable communication paths between PEs.

[0016] The contents of the CR define the operations to be performed by the PEs and the paths of intermediate data. In the execution mode of the reconfigurable computing platform, the PEs can execute the configured operations on the operands, and the SEs can form virtual circuits between PEs. Flow control in the reconfigurable computing platform is established by a ready-valid handshake mechanism.

[0017] By implementing the DFG in its original form, the reconfigurable computing platform uses local FIFOs and switching elements to communicate intermediate computation results, without going through the large register bank in a CPU or the high-bandwidth register bank in a GPU.

[0018] These and other features and advantages of the present invention can be understood by reference to the following detailed description of the invention and the accompanying drawings, in which like reference numerals refer to like elements throughout. [Brief explanation of the drawings]

[0019] [Figure 1] FIG. 1 is a diagram showing the configuration of a reconfigurable computing platform according to an embodiment of the present invention.

[0020] [Figure 2] FIG. 2 is a diagram illustrating an interface of a switching element (SE) according to one embodiment of the present invention.

[0021] [Figure 3]FIG. 3 is a diagram showing the configuration of an internal processing element (PE) and the configuration of an internal switching element (SE) according to one embodiment of the present invention.

[0022] [Figure 4] FIG. 4 is a diagram illustrating a corner processing element (PE) configuration and a periphery switching element (SE) configuration according to one embodiment of the present invention.

[0023] [Figure 5] FIG. 5 illustrates an example of an implementation of a data flow graph (DFG) on a reconfigurable computing platform in a portion of a PE and an SE according to an embodiment of the present invention.

[0024] [Figure 6] FIG. 6 illustrates a reconfigurable computing platform configured as a vector SIMD datapath according to one embodiment of the present invention.

[0025] [Figure 7] FIG. 7 illustrates a reconfigurable computing platform configured as a MIMO dataflow datapath according to one embodiment of the present invention.

[0026] [Figure 8] FIG. 8 illustrates a computational infrastructure configured as a sub-word SIMD datapath, according to one embodiment of the present invention.

[0027] Those skilled in the art will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of elements in the figures may be exaggerated to clearly show their relationship relative to other elements. DETAILED DESCRIPTION OF THE INVENTION

[0028] The embodiment described below relates to the configuration of a hardware accelerator (reconfigurable computing platform) for static dataflow execution of computational processes expressed as a data flow graph (DFG), where the DFG is directly implemented on the hardware.

[0029] FIG. 1 is a diagram illustrating the configuration of a reconfigurable computing board according to one embodiment of the present invention. FIG. 1 illustrates a reconfigurable computing board 100. The board 100 includes multiple components, namely, processing elements (PEs) 102-1 to 102-n, switching elements (SEs) 104-1 to 104-n, lanes 108-1 to 108-n, buffered lanes 110-1 to 110-n, and qPE lanes 112-1 to 112-n. As shown in FIG. 1, the reconfigurable computing board 100 is connected via a fabric interface unit (FIF) 106.

[0030] The plurality of components are arranged in a matrix. In one embodiment, the PEs 102-1 to 102-n and the SEs 104-1 to 104-n are arranged alternately in a two-dimensional array.

[0031] In one embodiment of the present invention, Figure 1 illustrates a reconfigurable computing board 100 configured in a 6 x 7 array. This embodiment of reconfigurable computing board 100 includes 21 PEs and 21 SEs. In one embodiment, for a reconfigurable computing board 100 having dimensions of M rows and N columns and having MN components, the number of PEs and SEs is defined by the following general formula: TIFF2025540451000002.tif1458

[0032] As shown in Figure 1, PEs 102-1 through 102-n and SEs 104-1 through 104-n are classified as interior elements, near-peripheral elements, peripheral elements, or corner elements based on their position in a two-dimensional array relative to FIF 106. SEs vary in the number of input and output lanes, and PEs vary in the sources to which input operands are multiplexed. These details are further explained using Figure 3, which visually illustrates the configuration of interior PEs, interior SEs, and the lanes connecting them, and Figure 4, which illustrates corner PEs, peripheral SEs, and their connections to FIFs.

[0033] In one embodiment, each of PEs 102-1 to 102-n is configured to receive up to three input operands, execute one of a plurality of operations corresponding to the reconfigurable computing board 106, and generate up to two operation results.

[0034] In various embodiments of the present invention, PEs 102-1 through 102-n are further configured to perform at least one of the following operations, including, but not limited to, 32-bit pipelined multi-cycle arithmetic and logic operations, single-precision floating-point operations, sub-word SIMD arithmetic and logic operations in 8-bit and 16-bit data widths, reduction tree operations including sub-word SIMD operations followed by arithmetic and logic operations, compare and exchange operations, and conditional accumulate operations.

[0035] PEs 102-1 to 102-n are configured to perform arithmetic processing on input operands received from FIF 106 and SEs 104-1 to 104-n to generate arithmetic results, and route the arithmetic results to other PEs or FIF 106 via SEs 104-1 to 104-n.

[0036] In one embodiment, constant values ​​as input operands may be provided to PEs 102-1 to 102-n at configuration time rather than at run time.

[0037] In another embodiment, the reconfigurable computing platform 100 can be configured with support for a third input operand and support for predicate functions. The third input operand serves multiple purposes. For example, to maximize throughput, it is necessary to adjust delays between edges in a DFG. To this end, the third input operand is used to perform pass-through operations through PEs that do not contribute to the operation, adjusting the pipeline depth of other nodes at the same level in the graph. This use case is described in connection with FIG. 8.

[0038] In one embodiment, the data of the third input operand can be extended by adding a predicate bit. Support for predicate functions in each PE enables the execution of local data-dependent control flow. For example, a PE configured to perform an addition operation can be reset or set by a predicate control signal sent along with the data. The result of the operation can be configured to be reused as a recursive input using the third input operand.

[0039] Each PE 102-1 to 102-n includes a configuration register that stores necessary configuration metadata related to the operation, the source of input operands, and the destination of the operation result. Depending on the position of a PE relative to the FIF 106 on the reconfigurable computing board 100, the input operands to that PE are multiplexed from different sources.

[0040] In one embodiment, input operands for each PE are buffered before operation, and similarly, operation results are buffered before being sent to adjacent SEs or FIFs 106. Furthermore, input operands are dequeued only if all input operands required for an operation are present and available, and there is space in all configured operation result buffers.

[0041] In one embodiment, the FIF 106 functions as a staging area where data is arranged in a specific pattern before it is input to the reconfigurable computing board 100. Similarly, the FIF 106 processes data output from the reconfigurable computing board 100 before writing it back to the source.

[0042] In another embodiment, the FIF 106 is an interface that allows a computing element (CE) or processor core to access the reconfigurable computing platform 100. The reconfigurable computing platform 100 functions as a coprocessor and conforms to an execution model based on the method described in our earlier Indian Patent No. 400171.

[0043] Figure 2 illustrates an interface diagram for a switching element (SE) according to one embodiment of the present invention. Referring to Figure 2, the SE 202 includes central control logic 204, input lanes 206, output lanes 208, configuration registers (CRs) 210, and multiplexers 212 located on all output lanes.

[0044] The central control logic 204 is configured to implement a flow control handshake mechanism for all output lanes of the SE. Each output lane has a CR 210 that provides enable and select signals to a multiplexer 212 to route input data to the appropriate output lane 208.

[0045] In one embodiment, the reconfigurable computing platform 100 is used in a configuration and execution manner similar to a field programmable gate array (FPGA), whereby the components of the computing platform 100 are configured before execution begins and do not change during execution.

[0046] In a circuit-switched network, a dedicated path is set up prior to communication. In the reconfigurable computing platform 100, a circuit-switched network is constructed by setting up the SEs 104-1 to 104-n, and data is routed to the internal PEs through the network for processing.

[0047] In one embodiment of the present invention, the corner SEs and periphery SEs located on the periphery (boundary) of the computational platform 100 and the interior SEs differ only in the number of input lanes and the number of output lanes, respectively. For example, an interior SE has eight input lanes and eight output lanes connected to PEs and SEs located in all directions around its periphery.

[0048] As shown in Fig. 2, a path connected to one or more adjacent SEs via a certain SE is provided with a FIFO (first-in, first-out buffer). On the other hand, a path connected to one or more adjacent PEs via a certain SE is composed entirely of combinational circuits, since the inputs and outputs of those PEs are already buffered by the FIFO.

[0049] The central control logic 204 ensures that data is transferred from the input lanes 206 only if all destination lanes are ready to receive data. In one embodiment, the output lanes 208 can be disabled, in which case data from the input lanes 206 is not transferred.

[0050] The CR 210 determines the routing between the input lanes 206 and output lanes 208, and the SE 202 prevents data from being sent back in the same direction it was received.

[0051] Figure 3 is a schematic diagram of an internal processing element (PE) and internal switching element (SE) according to one embodiment of the present invention. As shown in Figure 3, internal SE 302 has four adjacent SEs and four adjacent PEs. Connections to the SEs are via buffered lanes 306-1 through 306-n, and connections to the PEs are via lanes 308-1 through 308-n. Internal PE 304 has four adjacent SEs, which are connected via lanes 308-1 through 308-n.

[0052] FIG. 4 illustrates corner processing elements and periphery switching elements (SEs) according to one embodiment of the present invention. Referring to FIG. 4, peripheral SE 402 is connected to two adjacent SEs via buffered lanes 406-1 through 406-n. Additionally, peripheral SE 402 is provided with three input and two output FIF input / outputs (FIF IOs) 408-1 through 408-n for connection to FIF 106. Connections from peripheral SE 402 to corner PEs 404 and peripheral PEs (not shown in FIG. 4) are made via lanes 410-1 through 410-n.

[0053] In one embodiment, the inputs and outputs of FIF 106 are directly accessible only from peripheral and near-peripheral PEs (qPEs) without any additional buffers along the way. The near-peripheral PEs are configured with two qPE lanes, consisting of an additional input lane and an additional output lane, which are connected to the additional output lane and additional input lane of the peripheral SEs adjacent to OS8 and IS8, and OS9 and IS9, respectively, in FIG. 4. These lanes are then directly connected to the FIF inputs and outputs of IS1 and OS1, IS2 and OS2, and IS3.

[0054] In one embodiment, corner SE is not connected to FIF 106 because it is limited to handling connections between only three adjacent components.

[0055] The reconfigurable computing platform 100 disclosed in this invention is configured to operate in either a configuration mode or an execution mode.

[0056] In one embodiment of the present invention, to operate computational infrastructure 100 in configuration mode, it is necessary to change the data in each CR in PEs 102-1 to 102-n and SEs 104-1 to 104-n.

[0057] On the other hand, in the execution mode, PEs 102-1 to 102-n execute the set arithmetic operations on the operands, and SEs 104-1 to 104-n form virtual circuits between PEs 102-1 to 102-n. The arithmetic operations executed by PEs 102-1 to 102-n and the paths of intermediate data are defined by the contents of each CR.

[0058] Flow control in the reconfigurable computing platform 100 is established by a ready-valid handshake mechanism, which in one embodiment is implemented using a FIFO that ensures that data is not overwritten until it is consumed.

[0059] The handshake mechanism provides the flexibility to implement DFGs with uneven interior edges on the reconfigurable computing platform 100, albeit at the expense of reduced throughput. This flexibility further enhances the dataflow execution model of the computing platform 100.

[0060] In one embodiment of the present invention, the lanes of the reconfigurable computing platform 100 are configured to carry configuration metadata during the configuration phase and computational data during the execution phase. Because there are no dedicated configuration lanes, tag bits are used to distinguish between configuration metadata and execution data. Each component maintains a unique ID (coordinate-based address) that is fixed during the configuration phase. The configuration metadata also includes ID bits (coordinate-based addresses) to identify individual SEs and individual PEs. When an SE and / or PE receives a configuration word, the SE and / or PE may write the configuration word to its own CR or forward it to adjacent components on its south port. During the configuration phase, the configuration metadata with the ID bits is provided from the FIF to the top-level PEs and SEs. During each cycle, each component registers the received data in its configuration register if it is addressed to itself, or forwards the data to lower-level components if it is not addressed to itself. As a result, after several cycles, all components are configured.

[0061] Furthermore, the lanes of the reconfigurable computing platform 100 are configured with a width equal to the word length plus a width that includes bits used for tag bits and other configuration metadata, or multiple additional bits used as predicate bits by the PEs 102-1 to 102-n.

[0062] FIG. 5 is a diagram showing an example of implementing a DFG on a reconfigurable computing platform using a part of the PE and SE according to one embodiment of the present invention.

[0063] In one embodiment of the present invention, a computational function is first converted into a data flow graph (DFG). A DFG is a graph in which nodes represent computational operations and edges indicate dependencies between the operations. This DFG is expected to include computational operations that can be directly mapped to some or all of the PEs 102-1 through 102-n of the reconfigurable computing platform 100.

[0064] The process of mapping the DFG onto the reconfigurable computing platform 100 includes the process of placing nodes on all or some of the PEs 102-1 to 102-n and the process of configuring all or some of the SEs 104-1 to 104-n so that appropriate communication paths are configured between the PEs. The arithmetic operations performed by the PEs 102-1 to 102-n and the transmission paths of intermediate data are defined by the contents of each CR. In the execution mode of the reconfigurable computing platform, the PEs execute the set arithmetic operations on the operands, and the SEs can form virtual circuits between the PEs. In addition, flow control within the reconfigurable computing platform is established by a ready-valid handshake mechanism.

[0065] In the configuration phase, configuration metadata with ID bits (or coordinate-based addresses) is provided from the FIF 106 to the top-level PE and SE. In each cycle, each component registers the received configuration metadata in its own CR if it is addressed to itself, and forwards it to lower-level components if it is not addressed to itself. As a result, after a few cycles, all components are configured.

[0066] The CR of a PE stores information about an input source for receiving each input operand, an arithmetic operation to be executed, and an output destination to which each arithmetic operation result is transferred.

[0067] Referring to FIG. 5, the sample DFG 502 shown on the right is mapped onto the reconfigurable computing platform 100. PEs 506-2 and 506-3 are configured to receive input operands from their respective north and west FIF input / output units 510-(1,3) and 510-(2,4), perform an addition operation, and send the result to the south output lane 512-(1,2). PE 506-6 is configured to receive input operands from the west and east input lanes 512-3 and 512-4 of the adjacent SE 508-(5,6), perform a multiplication operation, and send the result to the north output lane 512-5. The result is ultimately sent as an output signal to the FIF via SE 508-2 and FIF input / output unit 510-5.

[0068] The CR of the SE stores information specifying which input source data is to be transferred to each output lane. The east output lane of SE508-5 and the west output lane of SE508-6 correspond to the input source of their respective north input lanes. Therefore, the intermediate calculation results from PE502-2 and PE502-3 are routed to the west and east input lanes of PE502-6.

[0069] Any unused PEs and unused paths within the SE are kept in a disabled state. When a PE is unused, it is in a disabled state, meaning that no operations are performed and all buffers remain disabled. When an output lane in an SE is disabled, no valid data is output from that lane.

[0070] During the execution phase, data is transmitted through the PEs and SEs using a ready-valid handshake mechanism. Enabled PEs sequentially accept and store valid input operands from their configured input sources, and execute the configured operation only when all required input operands are present in the buffer and there is free space in the output queue for the operation result. The output lanes of enabled SEs forward valid data received from their configured input sources. Data is dequeued from the internal buffer only when the receiving component is ready to accept it or when there is free space in the internal buffer.

[0071] 6 is a diagram illustrating the configuration of a reconfigurable computing board 600 configured as a vector SIMD data path according to an embodiment of the present invention. Referring to FIG. 6, it can be seen that a general DFG 602 including pipelined arithmetic processing used in neural networks is suitable for mapping onto the reconfigurable computing board 600 with a vector SIMD configuration. As shown in the figure, seven DFG 602 instances shown on the right side are mapped onto the reconfigurable computing board 600 in a 6-by-7 array. The inputs (a, b) and output (c) of the DFG 602 are each assigned a corresponding instance ID.

[0072] 7 is a diagram illustrating a configuration of a reconfigurable computing board 700 configured as a MIMO dataflow datapath according to an embodiment of the present invention. Referring to FIG. 7, a radix-2 FFT butterfly DFG 702 having levels L1, L2, and L3 shown on the right is configured as a MIMO operation sequence chained based on data dependency, and the DFG 702 is mapped onto a reconfigurable computing board 700 configured as a MIMO dataflow datapath. The reconfigurable computing board 700 shown in FIG. 7 has a 6x7 array configuration, where xo, yo, xi, and yi represent inputs to the radix-2 butterfly DFG 702, uo, wo, ui, and wi represent twiddle coefficients, and ao, bo, ai, and bi represent outputs.

[0073] The multiplication nodes of level L1 are mapped to PEs 704-(2, 3, 8, 11, 15, 18, 19, 20). The addition nodes of level L2 are mapped to PEs 704-(14 and 16), and the subtraction nodes are mapped to PEs 704-(6 and 12). The addition nodes of level L3 are mapped to PEs 704-(9 and 17), and the subtraction nodes are mapped to PEs 704-(13 and 5).

[0074] The inputs and twiddle coefficients are provided to the PEs 704 of level L1 via FIF input / output. The outputs from the PEs of level L1 are routed as follows: -SE706-(16 and 19) to PE704-16 -SE706-(10 and 7) to PE704-14 -SE706-(8 and 15) to PE704-12 -SE706-(2 and 6) to PE704-6 The outputs from the PEs at level L2 are routed as follows: -SE706-(12 and 13) to PE704-13 -SE706-(16 and 17) to PE704-17 -SE706-(5 and 8) to PE704-5 -SE706-(9 and 12) to PE704-9 The final outputs are routed to the FIF inputs and outputs via the following paths: -ao goes from PE704-5 to SE706-(8 and 4) in order -bo goes from PE704-17 to SE706-(17 and 20) in order. -ai goes from PE704-9 to SE706-(5 and 1) in order -bi goes from PE704-13 to SE706-(16 and 19) in order

[0075] 8 is a diagram showing the configuration of a reconfigurable computing platform 800 configured as subword-SIMD according to one embodiment of the present invention. The reconfigurable computing platform 800 disclosed in this specification is capable of performing SIMD execution on subwords of various data types, without being limited to int8 or int6 (both of which are signed integers with different bit widths).

[0076] Referring to Figure 8, three instances of DFG 802, which correspond to the depthwise convolution operations of a 3x3 array of the mobile net, are mapped onto a 6x7 array of reconfigurable computing board 800. DFG 802 consists of levels L1, L2, L3, and L4. At level L1, input is in 8-bit packed SIMD format and output is 16-bit wide. At levels L2 and L3, the input and output of each node remain 16-bit wide. At level L4, the output is quantized to 8-bit wide.

[0077] According to an embodiment of the present invention, the subword data type operation further includes an arithmetic / logical reduction stage. In this example, the nodes at level L1 of the three instances of DFG802 are mapped to PE804-(19, 20, 15), PE804-(1, 2, 8), and PE804-(18, 21, 4), respectively, and are configured to perform int8 multiplication of four 4x4 arrays, followed by a 4-to-1 reduction operation. The output data type of the reduction stage is quantized to a 16-bit width. The addition nodes at level L2 of the three instances of DFG802 are mapped to PE804-16, PE804-5, and PE804-14, respectively. The addition nodes at level L3 are mapped to PE804-13, PE804-6, and PE804-10, respectively. Finally, the ReLU (rectified linear unit) nodes at level L4 are mapped to PE804-17, PE804-3, and PE804-11, respectively.

[0078] The 8-bit wide packed SIMD input data for the three instances of DFG802 is supplied to the PEs of level L1 via the FIF input / output unit. The outputs from the level L1 nodes of the three instances of DFG802 are routed as follows: -SE806-(15 and 19) to PE804-16 -SE806-(4 and 5) to PE804-5 -SE806-(14 and 17) to PE804-14 The outputs from the summing nodes at level L2 of the three instances of DFG802 are routed as follows: - via SE806-16 to PE804-13 - via SE806-5 to PE804-6 - via SE806-13 to PE804-10 The outputs from the summing nodes at level L3 of the three instances of DFG802 are routed as follows: - Via SE806-13 to PE804-17 - via SE806-6 to PE804-3 - via SE806-10 to PE804-11

[0079] To adjust delays between edges in the DFG, these edges can be (i) routed through additional SEs or (ii) routed as pass-through operands through PEs. In this embodiment, PEs 804-(12, 9, 7) corresponding to the three instances of DFG 802 are each configured as pass-throughs and are used to adjust delays of edges from L1 nodes to L3 nodes. Edges from L1 to L2 pass-through nodes corresponding to the three instances of DFG 802 are routed along the following paths: - via SE806-15 to PE804-12 - via SE806-8 to PE804-9 - via SE806-7 to PE804-7 Edges from L2 pass-through nodes to L3 are routed as follows: - via SE806-12 to PE804-13 - via SE806-9 to PE804-6 - via SE806-6 to PE804-10

[0080] The present invention advantageously provides a reconfigurable computing platform for executing computations represented by a data flow graph (DFG) in a static data flow manner.

[0081] The reconfigurable computing platform of the present invention can be reconfigured at a coarse-grained level, thereby reducing inefficiencies caused by non-arithmetic operations in the pipeline of a general-purpose processor, such as instruction fetching and decoding, branching, speculative execution, scoreboarding, and interlocking, and thereby reducing power consumption.

[0082] The computing platform disclosed in this invention allows datapath reconfiguration according to the requirements of the computing kernel. In addition, the general-purpose ALU functional unit of the PE in this computing platform can be repurposed as a domain-specific accelerator (DSA) under certain constraints. This allows the computing platform of this invention to achieve significant energy savings.

[0083] The computational platform described here is designed as a coarse-grained, reconfigurable, polymorphic accelerator, overcoming the reconfiguration overhead of existing accelerators. Furthermore, it is designed to operate at high operating frequencies, achieving performance approaching that of dedicated accelerators.

[0084] The computational infrastructure described here is more energy efficient than existing hardware accelerators. It maximizes hardware utilization by leveraging polymorphic capabilities rather than complex warp scheduling as in GPUs. Furthermore, the computational infrastructure optimizes memory usage by utilizing local FIFOs and switching elements for intermediate result transmission rather than large, high-bandwidth register banks as in GPUs.

[0085] Those skilled in the art will appreciate that the above advantages and other advantages described herein are merely examples and are not intended to be exhaustive of all advantages of each embodiment of the present invention.

[0086] The present invention can be implemented in hardware alone or as a combination of hardware and software. The present invention can be implemented in a centralized manner in at least one computer system, or in a distributed manner in which components are distributed across multiple interconnected computer systems. The present invention can be suitably implemented as a computer system or other device configured to execute the methods described herein. A combination of hardware and software can include a general-purpose computer system loaded with and running a computer program. In this configuration, the program controls the computer system to implement the methods described herein. The present invention can also be implemented as hardware configured as part of an integrated circuit that performs other functions, or as firmware configured as part of a media rendering device.

[0087] While the present invention has been described with reference to particular embodiments, those skilled in the art will recognize that various modifications and equivalent substitutions may be made without departing from the scope of the invention. In addition, many modifications may be made to adapt the teachings of the invention to a particular situation or material. Therefore, it is not intended that the invention be limited to the particular embodiments disclosed, but rather that the invention will include all embodiments falling within the scope of the appended claims.

Claims

1. A reconfigurable computing platform (100) functions as a hardware accelerator and includes a plurality of components arranged in a matrix, the components including processing elements (PEs) (102-1 to 102-n) and switching elements (SEs) (104-1 to 104-n) connected to each other by bidirectional lanes, The reconfigurable computing platform (100) enables static dataflow execution by directly implementing various arithmetic processes expressed as a data flow graph (DFG) in all or part of the PEs (102-1 to 102-n) and the SEs (104-1 to 104-n), Furthermore, the reconfigurable computing platform (100) is dynamically reconfigurable through a configuration process and an execution process.

2. 2. The reconfigurable computing platform according to claim 1, wherein the PEs (102-1 to 102-n) and the SEs (104-1 to 104-n) are configured as a two-dimensional array in which they are alternately arranged.

3. 10. The reconfigurable computing platform (100) of claim 1, which is capable of reconfiguring at least one of the following: a vector SIMD data path that realizes pipelined multi-cycle operation processing (vector processing) and parallel independent operations on multiple data (SIMD parallelism); a MIMO data path that processes MIMO operation sequences chained based on data dependency; and a sub-word SIMD data path that can perform mixed-precision operations on packed data.

4. 2. The reconfigurable computing platform of claim 1, wherein the PEs are configured to execute at least one of a plurality of operations, the plurality of operations including 32-bit pipelined multi-cycle arithmetic and logic operations, single-precision floating-point operations, sub-word SIMD arithmetic and logic operations with 8-bit and 16-bit data widths, reduction tree operations with arithmetic and logic operations after sub-word SIMD operations, compare and exchange operations, and conditional accumulate operations.

5. The reconfigurable computing platform (100) of claim 1, wherein the PEs (102-1 to 102-n) have available a third input operand that is used for multiple purposes, including delay adjustment and transmission of data and its predicate control signal.

6. Each SE is a central control logic (204); an input lane (206) and an output lane (208); A configuration register (CR) (210); The reconfigurable computing platform (100) of claim 1, further comprising: a multiplexer (212) for controlling data routing in the output lanes.

7. The reconfigurable computing platform (100) of claim 6, configured to operate in either a configuration mode or an execution mode, wherein the CR (210) is configured in the configuration mode, computation is performed in the execution mode, and the configuration of the CR (210) is dynamically performed.

8. The reconfigurable computing platform (100) according to claim 7, wherein a plurality of nodes of the DFG are mapped to the PEs (102-1 to 102-n), and edges (inputs and outputs) between these nodes are routed via the SEs (104-1 to 104-n) to form a virtual circuit, thereby directly realizing the computational processing expressed as the DFG in all or part of the PEs (102-1 to 102-n) and the SEs (104-1 to 104-n).

9. 9. The reconfigurable computing board (100) according to claim 8, wherein the execution mode of the reconfigurable computing board (100) is such that the PEs (102-1 to 102-n) execute their set arithmetic operations on operands, the SEs (104-1 to 104-n) enable the PEs to form virtual circuits, the arithmetic operations and intermediate data paths executed by the PEs (102-1 to 102-n) are defined based on the contents of the CR (210), and flow control of the reconfigurable computing board (100) is established by a ready-valid handshake mechanism.

10. 10. The reconfigurable computing platform of claim 1, wherein the bidirectional lanes are used to transmit either configuration data or operational data at a given time.

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