Quantum algorithms using the lattice Boltzmann method

Abstract

A method for configuring a quantum circuit (300, 400) using the Lattice Boltzmann Method is disclosed. An initialization step (302, 402) is performed by configuring a quantum circuit, a first quantum register (f1), a second quantum register (f2), and at least a first ancillary register (a, a1). The quantum circuit is applied to the first quantum register (f1), the second quantum register (f2), and the first ancillary register (a, a1). The quantum circuit has, in order, (i) a collision step (304, 404) constructed using a first set of quantum gates, (ii) a propagation step (306, 406) constructed using a second set of quantum gates, and (iii) a macroscopic variable calculation step (308, 408) constructed using a third set of quantum gates.

Description

[Technical Field]

[0001] The present disclosure (hereinafter referred to as the "Disclosure") relates to a method for configuring a quantum circuit using the Lattice Boltzmann Method (LBM). The Disclosure also relates to a quantum computer or quantum simulator configured to perform the method. The Disclosure further relates to a non-volatile computer-readable medium having stored thereon computer program instructions executable by at least one processor of a classical computer to control the quantum computer or quantum simulator to perform the method.

[0002] Currently available quantum algorithms for solving multiphysics problems are designed to be applied to fault-tolerant quantum devices (perfect devices capable of error correction and with very little noise). This is mainly due to the complexity of quantum circuits, which is too large to be applied to currently available NISQ devices (noisy intermediate-scale quantum devices). In this sense, further redesign and optimization of quantum algorithms is necessary.

[0003] The present disclosure seeks to provide an improved method for configuring quantum circuits using the Lattice Boltzmann Method, a quantum computer or quantum simulator configured to perform the method, and a non-volatile computer-readable medium having stored thereon computer program instructions executable by at least one processor of a classical computer to control the quantum computer or quantum simulator to perform the method.

[0004] According to a first aspect, an embodiment of the present disclosure provides a method for configuring a quantum circuit using the Lattice Boltzmann method, the method comprising: performing an initial step by setting a first quantum register (f1), a second quantum register (f2), and at least a first ancillary register (a, a1) for the quantum circuit, wherein the first quantum register (f1) has four quantum bits (f10, f11, f12, f13) and the second quantum register (f2) has N-4 quantum bits (f20,...f2 N-5 ), wherein the first ancillary register (a, a1) comprises an ancillary quantum bit, and the method further comprises: applying the quantum circuit to the first quantum register (f1), the second quantum register (f2), and the first ancillary register (a, a1), wherein the quantum circuit (i) A collision step constructed using the first set of quantum gates; (ii) a propagation step constructed using a second set of quantum gates; (iii) a macroscopic variable computation step constructed using a third set of quantum gates; are provided in this order.

[0005] According to a second aspect, an embodiment of the present disclosure provides a quantum computer or quantum simulator configured to perform the aforementioned method according to the first aspect.

[0006] According to a third aspect, certain embodiments of the present disclosure seek to provide a non-volatile computer-readable medium storing computer program instructions executable by at least one processor of a classical computer to control a quantum computer or quantum simulator to perform the aforementioned method according to the first aspect.

[0007] SUMMARY OF THE INVENTION Embodiments of the present disclosure substantially eliminate or at least partially address the aforementioned problems in the prior art, enabling efficient and error-resistant quantum circuits.

[0008] Further aspects, advantages, features and objects of the present disclosure will become apparent from the accompanying drawings and detailed description of illustrative embodiments, taken in conjunction with the appended claims.

[0009] It will also be appreciated that features of the present disclosure can be combined in various combinations without departing from the scope defined by the appended claims. [Brief explanation of the drawings]

[0010] The foregoing summary, as well as the following detailed description of exemplary embodiments, will be better understood when read in conjunction with the accompanying drawings. For the purpose of illustrating the disclosure, exemplary configurations of the disclosure are shown in the drawings. However, the disclosure is not limited to the particular methods and apparatus disclosed therein. Also, the drawings are not to scale. Similar elements are designated by the same numerals wherever possible. Embodiments of the present disclosure will now be described, by way of example, with reference to the following drawings: [Figure 1A] FIG. 1 is a schematic diagram of a quantum computer. [Figure 1B] FIG. 1 is a schematic diagram of a quantum circuit of a quantum computer. [Figure 2] 1 is a schematic diagram of a quantum circuit that utilizes the Lattice Boltzmann Method (LBM), but is not optimized. [Figure 3] FIG. 1 is a schematic diagram of an optimized quantum circuit utilizing an LBM, according to one embodiment of the present disclosure. [Figure 4A] FIG. 1 is a schematic diagram of a further optimized quantum circuit utilizing LBM, according to one embodiment of the present disclosure. [Figure 4B] FIG. 10 is another schematic diagram of a further optimized quantum circuit utilizing LBM, according to an embodiment of the present disclosure. [Figure 5] This is a graph showing a comparison of experimental results using the Quantinuum H-series device H1-1 emulator. [Figure 6]This is a graph showing a comparison of experimental results using the Quantinuum H-series device H1-2 emulator. Detailed Description of the Embodiments

[0011] The following detailed description illustrates embodiments of the present disclosure and how they may be practiced. Although several forms for carrying out the present disclosure have been disclosed, those skilled in the art will recognize that other forms for carrying out the present disclosure are also possible.

[0012] According to a first aspect, an embodiment of the present disclosure provides a method for configuring a quantum circuit using the Lattice Boltzmann method, the method comprising: performing an initial step by setting a first quantum register (f1), a second quantum register (f2), and at least a first ancillary register (a, a1) for the quantum circuit, wherein the first quantum register (f1) has four quantum bits (f10, f11, f12, f13) and the second quantum register (f2) has N-4 quantum bits (f20,...f2 N-5 ), wherein the first ancillary register (a, a1) comprises an ancillary quantum bit, and the method further comprises: applying the quantum circuit to the first quantum register (f1), the second quantum register (f2), and the first ancillary register (a, a1), wherein the quantum circuit (i) A collision step constructed using the first set of quantum gates; (ii) a propagation step constructed using a second set of quantum gates; (iii) a macroscopic variable computation step constructed using a third set of quantum gates; are provided in this order.

[0013] According to a second aspect, an embodiment of the present disclosure provides a quantum computer or quantum simulator configured to perform the aforementioned method according to the first aspect.

[0014] According to a third aspect, certain embodiments of the present disclosure seek to provide a non-volatile computer-readable medium storing computer program instructions executable by at least one processor of a classical computer to control a quantum computer or quantum simulator to perform the aforementioned method according to the first aspect.

[0015] One of the main advantages of using the Lattice Boltzmann Method (LBM) is its simple and efficient implementation of the equations governing various physical processes, as will become clear from the comparative examples below.

[0016] In some embodiments, the method further comprises simulating a physical process by performing the collision step, the propagation step and the macroscopic variable calculation step. The method is suitable for simulating physical processes in the domain of Lattice Boltzmann applications. The simulation of a physical process on a quantum computer requires a mapping between a classical system (represented using a classical computer) and a quantum system (represented using a quantum computer). To this end, in some embodiments, the method further comprises: generating a mathematical equation corresponding to the physical process; Numerically discretizing said equation using the Lattice Boltzmann Method; establishing the collision step, the propagation step, and the macroscopic variable calculation step based on the numerically discretized equations; Includes:

[0017] The physical process is described by a corresponding mathematical equation, which is a partial differential equation. In some embodiments, the mathematical equation is a one-dimensional advection-diffusion equation. In this respect, the physical process is an advection-diffusion process, i.e., a process in which both advection and diffusion occur simultaneously, and both advection and diffusion are governed by the advection-diffusion equation. As an example, the mathematical equation (i.e., the advection-diffusion equation) is expressed as follows: TIFF2025540531000002.tif86140

[0018] The above equations are generally valid for advection-diffusion phenomena and are valid for both steady-state and unsteady-state conditions.

[0019] After generating the mathematical equations (corresponding to the physical processes), the equations are numerically discretized using the Lattice Boltzmann Method (LBM). Due to the close similarity between LBM and quantum systems, the LBM can be used as the basis for multiphysics quantum algorithms, in contrast to other standard numerical methods (e.g., finite volume or finite difference methods).

[0020] After discretization, a corresponding quantum circuit is constructed. A set of quantum gates and corresponding procedures are created to construct a mapping between classical and quantum systems. For this purpose, IBM's open-source SDK platform, Qiskit, can be used. It should be understood that the above method is not limited to a single platform and can use any of the various SDKs available for working with quantum computers. For purposes of this disclosure, simulation of the quantum circuit is preferably performed on a quantum computer with some degree of error correction capability.

[0021] The similarity between LBMs and quantum systems allows for a direct mapping of discretized mathematical expressions (corresponding to physical processes) into the framework of a quantum computer. This methodology is called "quantum native." This means that physical processes can be simulated on a quantum computer simply by applying the evolution of quantum states that encode various physical variables. In other words, there is no need to perform additional steps (e.g., switching between different types of information encoding and classical computation (hybrid)) during the various time steps of the quantum simulation.

[0022] In some embodiments, the method further includes obtaining initialization parameters. The initialization parameters are utilized during an initialization step. During the initialization step, the initialization parameters (corresponding to a physical process) and one or more input vectors having initial states in the LBM framework are configured. In this regard, in some embodiments, the initialization of any vector to a corresponding quantum state is achieved by using a reverse iterative procedure. The reverse iterative procedure is part of the Qiskit framework. The reverse iterative procedure is described, for example, in "Synthesis of Quantum-Logic Circuits" by V. V. Shende et al., IEEE Trans. on Computer-Aided Design, vol. 25, no. 6, June 2006, pp. 1000-1010, the contents of which are incorporated herein by reference.

[0023] LBM can be divided into three main steps. (i) Collision step (this is constructed using the first set of quantum gates). (ii) The propagation step (which is constructed using a second set of quantum gates). (iii) The macroscopic variables computation step (which is constructed using a third set of quantum gates).

[0024] Combining these three steps together results in the formation of a quantum circuit, which is suitable for one-off simulations: after a particular cycle of one time step of the simulation, measurement and re-initialization of the quantum state for the input of the next time step must be performed, or another method of connecting two time steps must be utilized.

[0025] A quantum circuit has N qubits (total), and an ancillary register (or registers) is introduced solely for computation. When new qubits are introduced into the quantum circuit, they are added to the second quantum register (f2). The first quantum register (f1) is fixed and consists of four qubits.

[0026] In some embodiments, in the above method, a first set of quantum gates (which corresponds to the collision step) sequentially: The last working qubit of the second quantum register f2 (f2 N-5 ) and the ancillary qubit in the first ancillary register (a, a1); It has the Y axis as the rotation axis, and uses the ancillary qubit of the first ancillary register (a, a1) as the control corresponding to the state of |0>, and the last working qubit (f2) of the second quantum register (f2) as the target. N-5 ) the first rotation operator (Ry) gate; It has the Y axis as the rotation axis, and uses the ancillary qubit of the first ancillary register (a, a1) as the control corresponding to the state of |1>, and the last working qubit (f2) of the second quantum register (f2) as the target. N-5 ), a second rotation operator (Ry) gate; Use the ancillary qubit in the first ancillary register (a, a1) as the control corresponding to the state |1>, and the last working qubit in the second quantum register (f2) as the target. N-5 ) using the first CX gate; The last working qubit (f2) of the second quantum register (f2 N-5 ) and the ancillary qubit in the first ancillary register (a, a1); It has.

[0027] The first set of quantum gates is illustrated in connection with Figures 3 and 4A-4B. The first and second rotation angles (used for the first and second rotation operator gates, respectively) depend on parameters provided during an initialization step. Such parameters may be part of the physical process being simulated. The first and second rotation angles may be provided in radians, for example, as defined in Qiskit.

[0028] Throughout this disclosure, the term "swap gate" refers to an operator for swapping quantum states between two qubits. Throughout this specification, phrases such as "using a qubit as a control" and "using a qubit as a target" mean that the value of the qubit "used as a control" is considered to determine whether a change is required in the value of the qubit "used as a target." The term "use" in phrases such as "using a qubit" should be understood to refer to using the qubit for a particular purpose, i.e., as a control or as a target.

[0029] In some embodiments, in the above method, the propagation step implements a computational basis state shift. In other words, a second set of gates (corresponding to the propagation step) implements a computational basis state shift. The propagation step is performed in two possible directions. The computational basis state shift can be implemented in various ways. Some examples of the second set of gates are shown using Figures 3 and 4A-4B.

[0030] In some embodiments, in the above method, the third set of quantum gates (which corresponds to the macroscopic variable calculation step) sequentially: The last working qubit (f2) of the second quantum register (f2 N-5 ) and the ancillary qubit in the first ancillary register (a, a1); A Hadamard gate applied to the ancilla qubit in the first ancilla register (a, a1); It has.

[0031] In the macroscopic variable calculation step, SWAP gates are used for state preparation, and Hadamard gates are used to implement the pointwise addition procedure. The third set of gates is shown in relation to Figures 2, 3, and 4A-4B.

[0032] Referring to the drawings, FIG. 1A is a schematic diagram of a quantum computer 100. The quantum computer 100 includes N qubits, depicted as a first qubit 110a, a second qubit 110b, and an Nth qubit 110c, respectively. The quantum computer 100 also includes a first ancilla qubit 110d. Each of the qubits 110a, 110b, and 110c is in a superposition of a ground state |0> and an excited state |1>. The quantum computer 100 further includes a state preparation means 102 employed to initialize the quantum computer 100. The quantum computer 100 also optionally includes an implementation means 104 employed to configure gates for implementing a quantum algorithm. Each gate uses one or more of the N qubits. The quantum computer 100 further includes a measurement means 106 employed to measure the states of one or more of the N qubits after execution of the quantum algorithm.

[0033] 1B is a schematic diagram of a quantum circuit 100B. Quantum circuit 100B can be illustrated using a first quantum register 112, a second quantum register 114, and a first ancillary register 116. Also illustrated is a classical register 160. The number of bits in classical register 160 is equal to the number of qubits in all other registers, i.e., the number of qubits in first quantum register 112, second quantum register 114, and first ancillary register 116. The term "classical register" refers to a line that provides an interface between a quantum computer and a classical computer.

[0034] The mapping of quantum registers onto quantum computer 100 of FIG. 1A is as follows: f10 corresponds to the first quantum bit 110a. f11 corresponds to the second qubit 110b, and so on. f2 N-5 corresponds to the Nth qubit 110c.

[0035] These N quantum bits are called working qubits. The above register naming is arbitrary. In this disclosure, the first quantum register 112 has four working qubits, and the second quantum register 114 has N-4 working qubits, where N is greater than 4. As an example, for N=6, the first quantum register 112 is composed of working qubits f10, f11, f12, and f13, and the second quantum register 114 is composed of working qubits f20 and f21.

[0036] Referring to FIG. 1B, quantum circuit 100B has an initialization phase 170 in which one or more qubits are set to an initial state, an implementation phase 172 in which the gates that make up the corresponding phase are set sequentially (i.e., set in a time-varying quantum system), and a measurement phase 174 that follows implementation phase 172.

[0037] For comparison, an unoptimized quantum circuit (which represents the prior art) and two quantum circuits optimized according to the present disclosure will be described using the case where the number of qubits is five (N=5). Figure 2 represents the unoptimized quantum circuit, and Figures 3 and 4A-B represent the optimized quantum circuits according to the present disclosure.

[0038] FIG. 2 is a schematic diagram of an unoptimized five-qubit quantum circuit 200 utilizing the Lattice Boltzmann Method (LBM). FIG. 2 represents the prior art. This five-qubit unoptimized quantum circuit 200 is configured using a first quantum register f1 and a second quantum register f2. In this diagram, the total number of working qubits, N, is five. The number of bits in the classical register c corresponds to the total number of qubits (including both working qubits and ancilla qubits). The five-qubit unoptimized quantum circuit 200 includes an unoptimized collision step 204, an unoptimized propagation step 206, and a macroscopic variable calculation step 208. Both the unoptimized collision step 204 and the unoptimized propagation step 206 include multiple multi-control gates. These gates are implemented sequentially, i.e., from left to right, as shown in FIG. 2A (and in all figures herein illustrating various quantum circuits). In Figure 2, the part of the quantum circuit drawn on the second level is actually a continuation of the part of the quantum circuit drawn on the first level. Similarly, the part of the quantum circuit drawn on the third level is a continuation of the part on the second level.

[0039] The unoptimized quantum circuit 200 uses LBM to simulate the one-dimensional physical process of concentration transport along a channel. An example of how such a quantum circuit can be configured is described in "Quantum algorithm for the advection-diffusion equation simulated with the lattice Boltzmann method" (author: Ljubomir Budinski), published in Volume 20, Article No. 57, Quantum Information Processing (2021). In the unoptimized quantum circuit 200, a similar one-dimensional advection-diffusion (ADE) model including 16 computational lattice sites was considered. This example was adopted to highlight in detail the technical advantages of the optimized quantum circuit of the present disclosure (shown in FIGS. 3 and 4A-4B). It should be understood that the aforementioned example of a one-dimensional physical problem with 16 computational lattice sites (i.e., a one-dimensional ADE model) is considered for convenience only, and the optimization principles provided in this disclosure are general and not limited to the aforementioned example.

[0040] The unoptimized quantum circuit 200 must be optimized to run correctly and efficiently on a NISQ device. Except for the initialization step 202, three steps (i.e., the unoptimized collision step 204, the unoptimized propagation step 206, and the macroscopic variable calculation step 208) are separated by gray barriers to indicate their beginning and end.

[0041] The problem areas of unoptimized quantum circuit 200 are collision step 204 and propagation step 206, due to the (conditionally speaking) large number of multi-control gates. Before being applied to a practical quantum computer, each of these multi-control gates is required to be decomposed from a given basis set into a sequence of two-qubit CX gates and other one-qubit gates. Each multi-control gate (having more than two controls) is decomposed using a decomposition algorithm. Such decomposition algorithms are well known in the art.

[0042] Decomposition depends on a device-specific set of basis gates and the device's qubit connectivity. As an example, unoptimized quantum circuit 200 can be decomposed using the IBM set of basis gates (I, SX, X, RZ, CX) using the IBM Qiskit transpiler. Transpiling converts the general form of unoptimized quantum circuit 200 (as shown in Figure 2) into a device-specific set of operations that can be executed on quantum hardware.

[0043] For the unoptimized quantum circuit 200, decomposition using the IBM basis gate set (as shown in Figure 2) yields the following gate counts: RZ = 312, CX = 244, SX = 77, and X = 9. These results indicate that the resulting circuit (the circuit obtained after decomposition) is too deep for practical device applications, even assuming full qubit connectivity. That is, the circuit contains too many one-qubit gates (i.e., RZ, SX, and X) and two-qubit gates (CX). In particular, the number of two-qubit CX gates is unacceptably high. In this configuration, even with some error correction and mitigation, it is not feasible to run the unoptimized quantum circuit 200 on a practical device. Therefore, further optimization is required.

[0044] This disclosure provides two optimized quantum circuits, which are illustrated in Figures 3 and 4A-4B.

[0045] FIG. 3 is a schematic diagram of an optimized quantum circuit setup 300 utilizing LBM according to one embodiment of the present disclosure. For comparison, the total number of working qubits N is also five in this diagram. The optimized quantum circuit 300 is configured with a first quantum register f1, a second quantum register f2, and a first ancillary register a, where the first quantum register f1 has four working qubits (f10, f11, f12, f13) and the second quantum register f2 has N-4 working qubits (f20, ... f2 N-5 ) The number of qubits in the first ancillary register a is fixed and equal to 1. The number of bits in the classical register c corresponds to the total number of qubits (including both working and ancillary qubits).

[0046] First listed is an initialization step 302. The optimized quantum circuit 300 has an optimized collision step 304, an unoptimized propagation step 306 (similar to FIG. 2), and a macroscopic variable calculation step 308. In other words, in the optimized quantum circuit 300, compared to the unoptimized collision step 204 of FIG. 2, only the collision step 304 has been optimized by reducing the number of quantum gates therein. The number of quantum gates in the collision step has been reduced from 16 multi-control gates to two SWAP gates (xx), two rotation operator (Ry) gates, and one CX gate (see FIG. 3).

[0047] Referring to FIG. 3, the first set of quantum gates (which corresponds to collision step 304) in order: The last working qubit of the second quantum register f2 (f2 N-5 ) and the ancillary qubit in the first ancillary register a; It has the Y axis as the rotation axis, and uses the ancillary qubit of the first ancillary register a as the control corresponding to the state of |0>, and the last working qubit of the second quantum register f2 (f2 N-5 ) the first rotation operator (Ry) gate; It has the Y axis as the rotation axis, and uses the ancillary qubit of the first ancillary register a as the control corresponding to the state of |1>, and the last working qubit of the second quantum register f2 (f2 N-5 ), a second rotation operator (Ry) gate; Use the ancillary qubit in the first ancillary register a as the control corresponding to the state |1>, and the last working qubit in the second quantum register f2 (f2 N-5 ) using the first CX gate; The last working qubit of the second quantum register f2 (f2 N-5 ) and the ancillary qubit of the first ancillary register a; It has.

[0048] For the optimized quantum circuit 300 (shown in Figure 3), the decomposition using the IBM basis gate set results in the following gate counts: RZ = 189, CX = 145, SX = 68, and X = 4. It can be seen that optimizing the collision step alone achieves a significant reduction in the number of quantum gates. In particular, the number of CX gates (the most problematic part of a quantum circuit for practical device implementation) is reduced by 41%.

[0049] 4A and 4B are schematic diagrams of a further optimized quantum circuit setup using LBM 400 according to one embodiment of the present disclosure. For comparison, in FIG. 4A the total number of working qubits N is also 5. In FIG. 4B, the total number of working qubits N is 7 to illustrate an optional modular section of the propagation step of further optimized quantum circuit 400.

[0050] A further optimized quantum circuit 400 is configured with a first quantum register f1, a second quantum register f2, and two ancillary registers a1 and a2, where the first quantum register f1 has four working qubits (f10, f11, f12, f13) and the second quantum register f2 has N-4 working qubits (f20,...f2 N-5 The number of qubits in the ancillary registers a1 and a2 is fixed and equal to 1. The number of bits in the classical register c corresponds to the total number of qubits (including both working qubits and ancillary qubits).

[0051] First listed is an initialization step 402. The further optimized quantum circuit 400 has an optimized collision step 404 (similar to that of FIG. 3), an optimized propagation step 406, and a macroscopic variable calculation step 408. In other words, in the further optimized quantum circuit 400, both the collision step 404 and the propagation step 406 have been optimized by having fewer quantum gates therein compared to the unoptimized collision step 204 and the unoptimized propagation step 206 of FIG.

[0052] Referring to FIGS. 4A and 4B, the first set of quantum gates (corresponding to collision step 404) are, in order: The last working qubit of the second quantum register f2 (f2 N-5 ) and the ancillary qubit in the first ancillary register a1; It has the Y axis as the rotation axis, and uses the ancillary qubit of the first ancillary register a1 as the control corresponding to the state of |0>, and the last working qubit of the second quantum register f2 (f2 N-5 ) the first rotation operator (Ry) gate; It has the Y axis as the rotation axis, and uses the ancillary qubit of the first ancillary register a1 as the control corresponding to the state of |1>, and the last working qubit of the second quantum register f2 (f2 N-5), a second rotation operator (Ry) gate; Use the ancillary qubit in the first ancillary register a1 as the control corresponding to the state |1>, and the last working qubit in the second quantum register f2 (f2 N-5 ) using the first CX gate; The last working qubit of the second quantum register f2 (f2 N-5 ) and the ancillary qubit of the first ancillary register a1; It has.

[0053] The propagation step 206 in FIG. 2 (representing the spatial evolution of the distribution function in the left-right direction) is replaced by the evolution of one general vector of states encoding the distribution function. This leads to an additional reduction in the depth of the circuit. In this regard, in some embodiments, the second set of quantum gates (corresponding to the propagation step 406) is (i) a first step 420 including four CX gates and a first X gate; (Ii) a first segment 424 containing seven multi-control gates; (Iii) if N>5, a second segment 426 including a first set 4262 of CX gates, a second set 4264 of CX gates, and an array 4266 of gates disposed between the first set 4262 and the second set 4264; (iv) a third segment 428 including two CX gates and a second X gate; in this order.

[0054] Referring to Figure 4A, N = 5, and therefore the further optimized quantum circuit 400 of Figure 4A does not include the second segment of the propagation step 426. In other words, if N is not greater than 5, the second segment 426 is omitted entirely. Referring to Figure 4B, N = 7, and therefore the further optimized quantum circuit 400 of Figure 4B does include the second segment of the propagation step 426.

[0055] In some embodiments, the four CX gates in the first step 420 are sequentially activated in the following order: a first CX gate in a first step 420 using the ancillary qubit in the first ancillary register a1 as the control corresponding to the state of |1> and the ancillary qubit in the second ancillary register a2 as the target; · A second CX gate in the first step 420 using the first working qubit (f10) in the first quantum register f1 as the control corresponding to the state |1> and the ancillary qubit in the first ancillary register a1 as the target; The last working qubit (f2 N-5 ) and the third CX gate in the first step 420 using the ancillary qubit in the first ancillary register a1 as the target; A fourth CX gate in the first step 420 using the ancillary qubit in the first ancillary register a1 as the control corresponding to state |1> and the second working qubit (f11) in the first quantum register f1 as the target.

[0056] The first X gate in the first step 420 is applied to the first working qubit (f10) in the first quantum register f1.

[0057] In some embodiments, the seven multi-control gates of the first segment 424 are used in the following order: first multi-control gate, second multi-control gate, third multi-control gate, fourth multi-control gate, fifth multi-control gate, sixth multi-control gate, and seventh multi-control gate, where: The first and fifth multi-control gates are the first control gates corresponding to the |0> state, and the last working qubit (f2 N-5), using the ancillary qubit in the first ancillary register a1 as the second control corresponding to the state |1>, and the second working qubit (f11) in the first quantum register f1 as the target; The second and fourth multi-control gates are used to control the last working qubit (f2 N-5 ) and the ancillary qubit in the first ancillary register a1, and use the third working qubit (f12) in the first quantum register f1 as the target; The third multi-control gate uses the second working qubit (f11) of the first quantum register f1, the third working qubit (f12) of the first quantum register f1, and the ancillary qubit of the first ancillary register a1 as controls corresponding to the state |1>, and uses the fourth working qubit (f13) of the first quantum register f1 as a target; The sixth multi-control gate controls the second working qubit (f11) of the first quantum register f1 and the last working qubit (f2 N-5 ) and use the ancillary qubit in the first ancillary register a1 as the control corresponding to the state of |1>, and use the third working qubit (f12) in the first quantum register f1 as the target; The seventh multi-control gate controls the second working qubit (f11) of the first quantum register f1 and the last working qubit (f2 N-5 ) and the ancillary qubit in the first ancillary register a1, and uses the third working qubit (f12) in the first quantum register f1 as the target.

[0058] Additionally, in some embodiments, the two CX gates and the second X gate of the third segment 428 are used sequentially in the following order: The last working qubit (f2 N-5 ) and the first CX gate of the third segment 428 using the ancillary qubit in the first ancillary register a1 as the target; a second CX gate in the third segment 428 using the first working qubit (f10) in the first quantum register f1 as the control corresponding to the state |1> and the ancillary qubit in the first ancillary register a1 as the target; Here, the second X gate of the third segment 428 is used for the ancillary qubit of the first ancillary register a1.

[0059] The optimization of the propagation step described above provides further technical advantages. One technical advantage is that when the number of working qubits increases, only the second segment 426 of the propagation step needs to be modified—that is, by adding additional gates to the second set of CX gates 4264 and the array of gates 4266. When additional qubits are introduced into the quantum circuit, the first step 420, the first segment 424, and the third segment 428 remain unchanged. In particular, the number of controls of the seven multi-control gates in the first segment 424 remains unchanged. As a result, the further optimized quantum circuit 400 can be easily scaled up. Furthermore, scaling up the further optimized quantum circuit 400 is much cheaper than scaling up the unoptimized quantum circuit 200.

[0060] For the further optimized quantum circuit 400, the decomposition using the IBM basis gate set (as shown in Figure 4A) yields the following gate counts: RZ = 129, CNOT = 86, SX = 50, and X = 12. It can be seen that by optimizing both the collision and propagation steps, a significant reduction in the number of quantum gates is achieved. For the CX gate, a further 41% reduction is achieved compared to the unoptimized quantum circuit 200 of Figure 2, for a total reduction of 65%. For the Z-axis rotation gate RZ, this total reduction is 59%. These results demonstrate that significant optimization of the unoptimized quantum circuit 200 (of Figure 2) has been achieved. This optimization makes the further optimized quantum circuit 400 fully applicable for implementation on a real quantum device. In other words, by achieving this significant reduction in the number of multi-control gates, the further optimized quantum circuit 400 is shorter, more efficient, and therefore more error-resistant.

[0061] A comparison of the number of gates is shown in the table below. Note that the exact number of gates is always device dependent. Here, the IBM basis gate set {RZ, SX, X, CX} is used, assuming full qubit connectivity. TIFF2025540531000003.tif76170

[0062] 4B , in some embodiments, first CX gate set 4262 of second segment 426 has four CX gates that use the first working qubit (f10), the second working qubit (f11), the third working qubit (f12), and the fourth working qubit (f13) of first quantum register f1 as their respective targets, in that order. Each of the four CX gates of first CX gate set 4262 uses the last working qubit (f2) of second quantum register f2 as a control corresponding to the |0> state. N-5 ) to use.

[0063] Further, in some embodiments, second CX gate set 4264 of second segment 426 has N-2 CX gates that use the first working qubit (f10), the second working qubit (f11), the third working qubit (f12), and so on up to the (N-2)th working qubit as their respective targets, in that order. Each of the N-2 CX gates in second CX gate set 4264 uses the last working qubit (f2) of second quantum register f2 as a control corresponding to the state |0>. N-5 ) is used. Here, the (N-2)th working qubit can be the working qubit in the first quantum register (f1) or the second quantum register (f2), depending on the value of N. As an example, when N=6, the second CX gate set 4264 may have four CX gates. Also, the (N-2)th working qubit is the fourth working qubit in the quantum circuit, which is the fourth working qubit (f13) in the first quantum register (f1). This working qubit (f13) is used as the target of the last of the four CX gates, as shown in FIG. 3A. When N>6, the (N-2)th working qubit is the working qubit (f2N-7) in the second quantum register f2. Referring to FIG. 4B, when N=7, the second set CX gates 4264 has five CX gates, and the (N-2)th working qubit is the first working qubit (f20) in the second quantum register f2. This working qubit (f20) is used as the target for the last of the five CX gates.

[0064] Additionally, in some embodiments, the array of gates 4266 is positioned after the first set of CX gates 4262 and before the second set of CX gates 4264. The number of gates in the array is a function of the total number of working qubits (N). It will be appreciated that the second set of CX gates 4264 and the array of gates 4266 depend on the value of N, further facilitating scaling up of the optimized quantum circuit.

[0065] In some embodiments, the array of gates 4266 comprises: N-5 multi-control gates, indexed 1 through N-5, arranged as an array of gates. The multi-control gate indexed "M" in this array uses all of the work qubits in the first quantum register f1 and the first M-1 work qubits in the second quantum register f2 as controls corresponding to the |1> state, and uses the Mth work qubit in the second quantum register f2 as a target. N-6 CX gates if N is greater than 6.

[0066] Here, the N-5 multi-control gates and the N-6 CX gates are interleaved. The gate arrangement 4266 starts from the first multi-control gate among the N-5 multi-control gates. Each CX gate controls the last working qubit (f2 N-5 ), and the Lth CX gate uses as a target the same working qubit that is used as a target by the Lth multi-control gate.

[0067] It will be appreciated that the second segment 426 in the propagation step is a modular segment. The addition of each new qubit to the quantum circuit introduces one multi-control gate and two CX gates, where the multi-control gate has N-2 controls starting from the first working qubit (f10), and the two CX gates have N-2 controls starting from the last working qubit (f2) as controls. N-5 ) and has the third-to-last working qubit (fN-7) as the target. This relationship holds for each new qubit added to the quantum circuit.

[0068] [Experimental Results] Quantum circuit optimization using LBM (e.g., further optimized quantum circuit 400) opens the possibility of performing simulations of physical processes on actual quantum devices. This is exemplified for the Quantinuum H-series device H1-1, where a comparison of the results, in the form of lattice Boltzmann probability distribution functions for ideal and emulated values, is shown in Figure 5. In this regard, a one-dimensional advection-diffusion equation was solved on a Quantinuum H1-1 device and compared with the H1-1 emulation and the low-noise "ideal" simulation provided by Qiskit Aer. The desired solution to the physical problem can be obtained from the measurement distribution with a simple post-processing step. The physically relevant state is displayed in the left half of the distribution graph. The number of shots in all runs was set to 1024. Figure 6 shows the results of two different runs on the Quantinuum H-series device H1-2 emulator, again compared with the ideal value. Again, the one-dimensional advection-diffusion equation was solved with two different numbers of shots on the Quantinuum H1-2 emulator and compared with the low-noise "ideal" simulation provided by Qiskit Aer.

[0069] As is clear from these results, a high level of overlap is achieved both between measurements and emulated values, and between measurements and ideal values, confirming the high efficiency of the optimizations mentioned above. The Quantinuum emulator is able to reproduce real quantum devices with reasonable accuracy, providing a very good indication of how optimized quantum circuits will perform on real quantum devices.

[0070] The present disclosure also relates to a quantum computer or quantum simulator configured to perform the above-described method for configuring such a quantum circuit utilizing LBM. The present disclosure further relates to a non-volatile computer-readable medium storing computer program instructions executable by at least one processor of a classical computer to control the quantum computer or quantum simulator to perform the above-described method. The various embodiments and variations disclosed above with respect to the above-described method apply mutatis mutandis to the quantum computer or quantum simulator and the non-volatile computer-readable medium.

Claims

1. A method for configuring a quantum circuit using the Lattice Boltzmann method, comprising: The method includes performing an initial step by configuring the quantum circuit with a first quantum register, a second quantum register, and at least a first ancillary register, wherein the first quantum register has four qubits, the second quantum register has N-4 qubits, and the first ancillary register has an ancillary qubit; The method further includes applying the quantum circuit to the first quantum register, the second quantum register, and the first ancillary register, wherein the quantum circuit comprises: (i) a collision step constructed using a first set of quantum gates; (ii) a propagation step constructed using a second set of quantum gates; (iii) a macroscopic variable computation step constructed using a third set of quantum gates; and A method comprising the steps of:

2. The method of claim 1 , further comprising simulating a physical process by performing the collision step, the propagation step, and the macroscopic variable calculation step.

3. generating a mathematical equation corresponding to said physical process; Numerically discretizing the equation using the Lattice Boltzmann Method; establishing the collision step, the propagation step and the macroscopic variable calculation step based on the numerically discretized equations; 3. The method of claim 2, comprising:

4. The method of claim 3 , wherein the mathematical formula is a one-dimensional advection-diffusion equation.

5. The first set of quantum gates, in order: a first SWAP gate applied between the last working qubit of the second quantum register and the ancillary qubit of the first ancillary register; a first rotation operator gate having a Y-axis as a rotation axis, using the ancilla qubit in the first ancilla register as a control corresponding to a state of |0>, and using the last working qubit in the second quantum register as a target; a second rotation operator gate having the Y-axis as a rotation axis, using the ancilla qubit in the first ancilla register as a control corresponding to the state of |1>, and using the last working qubit in the second quantum register as a target; a first CX gate using the ancilla qubit in the first ancilla register as a control corresponding to the state of |1> and the last working qubit in the second quantum register as a target; a second SWAP gate applied between the last working qubit of the second quantum register and the ancillary qubit of the first ancillary register; 10. The method of any preceding claim, comprising:

6. 10. The method of any preceding claim, wherein the propagating step performs a computational ground state shift.

7. The third set of quantum gates, in order: a SWAP gate applied between the last working qubit of the second quantum register and the ancillary qubit of the first ancillary register; a Hadamard gate applied to the ancilla qubit in the first ancilla register; 10. The method of any preceding claim, comprising:

8. The second set of quantum gates, in turn, A first step containing four CX gates and the first X gate; - The first segment contains seven multi-control gates; a second segment including a first set of CX gates, a second set of CX gates, and an array of gates disposed between the first set and the second set; A third segment containing two CX gates and a second X gate; 10. The method of any preceding claim, comprising:

9. The four CX gates in the first step are in the following order: a first CX gate in the first step, using the ancillary qubit in the first ancillary register as a control corresponding to the state |1> and the ancillary qubit in the second ancillary register as a target; a second CX gate in the first step, using a first working qubit in the first quantum register as a control corresponding to the state of |1> and using the ancillary qubit in the first ancillary register as a target; a third CX gate in the first step, using the last working qubit in the second quantum register as a control corresponding to the state of |1> and the ancillary qubit in the first ancillary register as a target; a fourth CX gate in the first step, using the ancillary qubit in the first ancillary register as a control corresponding to the state of |1> and the second working qubit in the first quantum register as a target; a first X gate of the first step used for the first working qubit in the first quantum register; The method according to claim 8, wherein

10. the seven multi-control gates of the first segment are used in the following order: a first multi-control gate, a second multi-control gate, a third multi-control gate, a fourth multi-control gate, a fifth multi-control gate, a sixth multi-control gate, and a seventh multi-control gate; the first multi-control gate and the fifth multi-control gate use the last working qubit in the second quantum register as a first control corresponding to a state of |0>, the ancilla qubit in the first ancilla register as a second control corresponding to a state of |1>, and the second working qubit in the first quantum register as a target; the second multi-control gate and the fourth multi-control gate use the last working qubit of the second quantum register and the ancilla qubit of the first ancilla register as controls corresponding to a state of |1> and use the third working qubit of the first quantum register as a target; the third multi-control gate uses the second working qubit of the first quantum register, the third working qubit of the first quantum register, and the ancilla qubit of the first ancilla register as controls corresponding to the state of |1>, and uses the fourth working qubit of the first quantum register as a target; the sixth multi-control gate uses the second working qubit in the first quantum register and the last working qubit in the second quantum register as controls corresponding to a |0> state, the ancilla qubit in the first ancilla register as controls corresponding to a |1> state, and the third working qubit in the first quantum register as a target; the seventh multi-control gate uses the second working qubit in the first quantum register, the last working qubit in the second quantum register, and the ancilla qubit in the first ancilla register as controls corresponding to the state |1>, and uses the third working qubit in the first quantum register as a target; 10. The method according to claim 8 or 9.

11. the first CX gate set of the second segment has four CX gates that use the first working qubit, the second working qubit, the third working qubit, and the fourth working qubit of the first quantum register as respective targets, in that order; each of the four CX gates in the first CX gate set uses the last working qubit in the second quantum register as a control corresponding to a state of |0>; the second CX gate set of the second segment has N-2 CX gates that use the first working qubit, the second working qubit, the third working qubit, up to the N-2th working qubit, in that order, as their respective targets; each of the N-2 CX gates in the second CX gate set uses the last working qubit in the second quantum register as a control corresponding to a state of |0>; the array of gates is positioned after the first set of CX gates and before the second set of CX gates, the number of gates in the array of gates being a function of the total number of working qubits; 11. The method according to any one of claims 8 to 10.

12. The gate arrangement is N-5 multi-control gates indexed from 1 to N-5; N-6 CX gates if N is greater than 6; and the N-5 multi-control gates are arranged as an array of gates, and the multi-control gate indexed "M" in the array uses all of the working qubits in the first quantum register and the first M-1 working qubits in the second quantum register as controls corresponding to the state of |1>, and uses the Mth working qubit in the second quantum register as a target; the N-5 multi-control gates and the N-6 CX gates are interleaved, the arrangement of the gates starting from a first multi-control gate among the N-5 multi-control gates, each CX gate using the last working qubit of the second quantum register as a control corresponding to a state of |0>, and an L-th CX gate using as a target the same working qubit used as a target by the L-th multi-control gate; The method of claim 11

13. The two CX gates and the second X gate of the third segment are: a first CX gate in the third segment, using the last working qubit in the second quantum register as a control corresponding to the state of |1> and the ancillary qubit in the first ancillary register as a target; a second CX gate in the third segment, using a first working qubit in the first quantum register as a control corresponding to the state of |1> and an ancillary qubit in the first ancillary register as a target; 13. The method of claim 8, wherein the second X gate of the third segment is used for the ancillary qubit in the first ancillary register.

14. 10. A quantum computer or quantum simulator configured to carry out a method according to any preceding claim.

15. A non-volatile computer-readable medium storing computer program instructions executable by at least one processor of a classical computer to control a quantum computer or quantum simulator to perform the method of any of claims 1 to 13.

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