Method and circuit for performing in-memory multiply-accumulate operations

Abstract

The present invention relates to a method for performing in-memory multiply-accumulate operations, the method comprising: x -1) A vector X=[X1X2...X] with m elements represented in bits m ] and each is (n w -1) Determine the result of a matrix product O with a matrix (I) consisting of m by n elements represented in bits, each element of the matrix product being a sum of dot products (II), the operation resulting in the dot product by applying the values ​​of these vectors and the values ​​of the associated time masks PX and PW to logic gates to generate at least one control signal SC for at least one current source, the control signal SC activating at least one current source to accumulate capacitive charge in the storage line.

Description

[Technical Field]

[0001] The present invention relates to the field of in-memory computation, and more particularly to a method and associated circuitry for performing in-memory multiply-accumulate (MAC) operations, especially for neural networks where the basic operation for perceptrons is MAC. [Background technology]

[0002] The emergence of the Internet of Things is creating a growing demand for ultra-low-power computing solutions to deploy artificial intelligence in such devices. An additional cost hindering machine learning in embedded systems comes from data movement consumption.

[0003] In a traditional von Neumann architecture, stored data must be moved from memory to the processor for incremental computation. In an example provided by Boris Murmann in his publication "Mixed-Signal Processing Opportunities for AI," data must be read from memory four times to perform a MAC operation (one multiplication and one addition). If we consider only the cost of accessing the data and estimate this access at 50 fJ / byte, the overall consumption is 200 fJ / MAC, limiting efficiency to 10 TOPS / W. One way to alleviate this constraint, known as the memory wall or von Neumann bottleneck, is to bring processing elements inside the memory to avoid power loss when accessing data.

[0004] In-memory computing is a technique that involves performing computer calculations entirely within the computer's memory. In-memory processing is a way to overcome the drawbacks of moving data between the processor and memory, particularly in terms of performance and energy costs.

[0005] Figure 1 shows the principle of in-memory computation of MAC operation in the prior art. m ] is relayed on several lines. The multiplication of this vector by the elements of the weight matrix W is performed inside the memory where the weight matrix W is stored. Accumulation in the current or voltage domain is performed for each column of the capacitive line, also called accumulation line AL. This mixed signal method produces the result of the MAC operation in analog, and an analog-to-digital converter A / D at the end of each accumulation line converts the result into a vector [O1,...,O n ]. Each accumulation line AL corresponds to a perceptron without an activation function.

[0006] There are various prior art approaches to performing such in-memory computations. In the resistive approach, shown in Figure 2 and discussed in the paper "A Fully Integrated Analog ReRAM Based 78.4 TOPS / W Compute-In-Memory Chip with Fully Parallel MAC Computing" by Q. Liu et al., memristors are used to perform multiplication. A vector X is transmitted in the form of an analog voltage on all lines. The weight W is stored as the conductance value of the memristor and modulates the current through each storage line AL. However, this approach requires a digital-to-analog converter with a high-intensity output current and a current comparator. According to the paper, this approach can perform multi-bit operations using up to 16 conductance states. However, process variations prevent achieving a higher bit count. Furthermore, in terms of energy consumption, writing requires a large current peak (approximately 6 μA in the publication "Memristor-based Reconfigurable Circuits: Challenges in Implementation" by Nguyen Cong Dao et al.). It should be noted that there is a trade-off between energy consumption and variability.

[0007] In the capacitive approach shown in Figure 3 and discussed in the publication "An 8-bit, 16-input, 3.2 pJ / op switched-capacitor dot product circuit in 28-nm FDSOI CMOS" by D. Bankman et al., multiplication is based on sharing charge or current on capacitive lines, typically using XNOR gates for binary multiplication. A unit capacitor is charged following each binary multiplication, and the charge is redistributed to all capacitors on the storage line AL, thereby providing the voltage to be converted by the analog-to-digital converter. To perform multibit operations with switched capacitors, Boris Murmann's paper "Mixed-Signal Computing for Deep Neural Network Inference" presents a topology similar to a digital multiplier that uses a storage line for each bit. However, this method requires additional circuitry to combine all the results of the lines, which is sufficient for small numbers of lines (<5) but increases power consumption for larger numbers of bits. Summary of the Invention [Means for solving the problem]

[0008] Therefore, there is a need to improve in-memory multiply-accumulate (MAC) techniques, especially in terms of energy consumption.

[0009] Method for performing in-memory multiply-accumulate (MAC) operations The aim of the present invention is to meet this objective and, according to one aspect thereof, provides a method for performing in-memory multiply-accumulate (MAC) operations, in particular for neural networks, each of which has (n x -1) a vector X = [X1X2...X m ] and each is (n W -1) a matrix of m × n elements represented in bits

[0010]

number

[0011] The result of matrix multiplication O is

[0012]

number

[0013] Each element of the matrix product O is determined as the sum of scalar products.

[0014]

number

[0015] and

[0016]

number

[0017] , i∈{1,...,n}, j∈{1,...,m}, and the bit vector X j =[X j [0],...,X j [n x -2]] and the weight bit vector W j,i =[W j,i [0],...,W j,i [n W -2]], and a multiply-accumulate operation is performed to apply a vector X to a set of logic gates to generate at least one control signal SC for controlling at least one current source. j and W j,i and the associated time mask value to obtain the scalar product R j,i , and the time mask PX=[PX(0),...,PX(n x -2)] is the vector X j is associated with the bits of the elements of the time mask PW=[PW(0),...,PW(n W-2)] is the vector W j,i associated with the bits of the elements of R, in particular the scalar product R j,i A control signal SC activates the at least one current source to store capacitive charge in a storage line in a manner proportional to .

[0018] The expression "performs an in-memory multiply-accumulate (MAC) operation" means that the operand X j and W j,i This means that these operations are performed in the memory of an electronic chip on which the

[0019] The expression "activating a current source" means enabling said current source to draw a current flowing in the storage line.

[0020] The present invention provides a new method for in-memory computation of MAC operations by reducing power consumption.

[0021] Preferably, at least one of the two vectors is signed, and X j [sign] is vector X j is the sign bit of and / or W j,i [sign] is the weight bit vector W j,i is the sign bit of the storage line, and a set of logic gates determines the polarity signal SP=X j [sign]×W j,i Generate [sign].

[0022] The time mask is preferably generated in the form of a pulse.

[0023] The time masks PX and PW are outside the memory, i.e., the operand X j and W j,i can be generated by a time mask generation unit located outside the memory of the electronic chip on which it is stored.

[0024] In one embodiment, the temporal mask PW(d) is substantially

[0025]

number

[0026] A period T equal to d is generated so that it is continuously activated during j is a unit of time corresponding to the duration of activation of the time mask associated with the least significant bit of c+d *For a period equal to T, each T d , which are generated so as to be continuously activated for

[0027] This scenario is

[0028]

number

[0029] corresponds to the presence of a single control signal that controls a single absolute current intensity value by charging or discharging the storage line, such that i∈{1,...,n} and j∈{1,...,m}.

[0030] Here, there is a weighting by the activation time of the current sources. In this scenario, the voltage across the terminals of the storage line for the multiply-accumulate operation

[0031]

number

[0032] teeth,

[0033]

number

[0034] where C is the value of the capacitance of the storage line and I is the current intensity of the current source. Note that the capacitance of the storage line can be parasitic and / or distributed capacitance.

[0035] If there are at least two current sources, each controlled by a respective control signal SC, the time mask PW(d) is substantially

[0036]

number

[0037] A period T equal to d can be generated so that it is continuously activated for d∈{0,...,max(b l -a l )} and PW's (n w -1) k bits in the interval [a l ,b l ], where k is the number of current sources or control signals, l∈{0,...,k-1}, and b l ≧a l and {a l ,b l}∈[0,(n w -2)], and a l and b l is in the interval [a l ,b l ] is in the interval [0,n W -2], and the longest interval is chosen to represent a partition of [0,max(b l -a l )] and T is the vector X j is a unit of time corresponding to the duration of activation of the time mask associated with the least significant bit of c+d *T.

[0038] This scenario is

[0039]

number

[0040] A plurality of control signals SC controlling k current sources, k≧2, by charging or discharging the storage line, such that l,j,i corresponds to the existence of i∈{0,...,k-1}.

[0041] Here, there is current weighting by having a number of current sources weighted by powers of two and controlled by control signals representing the value of the bit associated with this weighting. This advantageously improves the speed of calculation by reducing the duration of the control signals. In this case, the voltage across the terminals of the accumulation line for the multiplication and accumulation operation

[0042]

number

[0043] teeth,

[0044]

number

[0045] where C is the capacitance value of the storage line and I is the bottom current source (i.e., a l =0).

[0046] For example, (n W -1)=4 and k=2, the 4 bits can be divided evenly between the two sources.

[0047]

number

[0048]

number

[0049] Alternatively, the bits can be divided unevenly.

[0050]

number

[0051]

number

[0052] A circuit for performing in-memory multiply-accumulate (MAC) operations. According to another aspect of the present invention, there is also provided a circuit for performing in-memory multiply-accumulate operations, particularly for neural networks, the circuit comprising: X -1) a vector X = [X1X2...X m ] and each is (n W -1) a matrix of m × n elements represented in bits

[0053]

number

[0054] The result of matrix multiplication O with

[0055]

number

[0056] Each element of the matrix product O is the sum of the scalar products

[0057]

number

[0058] and

[0059]

number

[0060] , i∈{1,...,n}, j∈{1,...,m}, and the bit vector X j =[X j [0],...,X j [n x -2]] and the weight bit vector W j,i =[W j,i [0],...,W j,i [n W -2]], and this circuit is Vector X j and W j,i and the value of an associated time mask, PX=[PX(0),...,PX(n x -2)] is the vector X j is associated with the bits of the elements of the time mask PW=[PW(0),...,PW(n W -2)] is the vector W j,i a logic unit associated with a bit of the element of, the logic unit being configured to generate at its output at least one control signal SC for activating at least one current source; the at least one current source configured to be activated by a control signal SC to store capacitive charge in a storage line; Equipped with.

[0061] Preferably, at least one of the two vectors is signed, and X j [sign] is vector X j is the sign bit of and / or W j,i [sign] is the weight bit vector W j,i and the storage line is connected to the polarity signal SP=X j [sign]×W j,i [sign], and this signal SP is configured to be charged or discharged according to the sign bit X j [sign] and the sign bit W j,iIt is obtained at the output of an XOR or XNOR logic gate that receives [sign] and [sign] at its input.

[0062] In one embodiment, the logic units comprise NAND and / or NOR logic gates.

[0063] The logical unit is bit X j a first logic subunit for time masking the weight bit W j,i and a second logic subunit for time masking the first subunit, the two subunits being cascaded such that the output of the first subunit is the input of the second subunit.

[0064] The first subunit receives at its input the time masks PX and PW and the bit X j [0:n X -2] and receives two logic gate stages, i.e., a first stage comprising a plurality of logic gate levels, the levels being cascaded such that a signal at the output of one level becomes a signal at the input of the next level until finally a single signal is obtained at the output, said first stage including: j [0:n X -2] and the associated time mask PX are inputs to the first level logic gates, in particular NAND or NOR gates; a second stage comprising at least one logic gate level, in which the signals at the output of the first stage and each time mask PW become inputs to logic gates of said level, in particular NAND or NOR gates; It can be equipped with:

[0065] The second subunit receives at its input the signal at the output of the first subunit and the weight bit W j,i [0:n W-2] and may comprise a plurality of logic gate levels, which are cascaded such that the signal at the output of one level is the signal at the input of the next level, until finally a single signal corresponding to the control signal SC is obtained at the output, and each first level logic gate receives at its input the signal at the output of the first sub-unit and the corresponding weight bit W j,i [0:n W -2] and receive.

[0066] The second subunit is the bit vector X j The sign bit of X j [sign] and bit vector W j,i The sign bit W of j,i An XOR or XNOR gate can be provided that receives [sign] and [sign] at its inputs. If a positive sign is interpreted as a binary "0" and a negative sign is interpreted as a binary "1", an XOR gate can be used for the sign bit. If a positive sign is interpreted as a binary "1" and a negative sign is interpreted as a binary "0", an XNOR gate can be used for the sign bit.

[0067] In one embodiment, the at least one current source is created by a current mirror using CMOS transistors.

[0068] The current mirror preferably comprises a PMOS transistor for charging the storage line and an NMOS transistor for discharging said line.

[0069] Preferably, the current mirror has a cascode architecture, which increases the output impedance of the current mirror and provides a more stable current value despite fluctuations in the voltage on the storage line.

[0070] In one embodiment, the circuit comprises at least one electronic switch, in particular a pass gate, controlled by a control signal SC to activate said at least one current source.

[0071] The circuit may comprise at least one capacitor at the output of said at least one electronic switch to increase the capacitance of the storage line.

[0072] The circuit preferably comprises a secondary storage line connected to the storage line via a follower amplifier, such secondary storage line being for controlling the current.

[0073] Preferably, the circuit includes a follower amplifier connected between the storage line and the secondary storage line, which has the advantage of allowing each of the two storage lines to remain at the same voltage level in order to counteract charge sharing effects when the switches open and close.

[0074] In one embodiment, the circuit comprises an analog-to-digital converter connected directly to the storage line without a secondary storage line, or in particular connected to the secondary storage line via a follower amplifier.

[0075] The analog-to-digital converter is two analog comparators, one of which compares the value of the charge on the storage line to which the analog-to-digital converter is connected with +LSB, and the other of which compares the value of the charge on the storage line to which the analog-to-digital converter is connected with -LSB; a counter configured to increment or decrement according to the result of the comparison of the comparator, the output of which is the output of the converter; a charge injection unit configured to restore the charge on a storage line connected to the converter to its initial value if the counter indicates that this line has been discharged; a discharge unit configured to discharge a storage line connected to the converter and return this line to its initial value if the counter indicates that this line has been charged; It can be equipped with:

[0076] The analog-to-digital converter may comprise a look-up table (LUT) configured to receive the output of the counter at its input and to output a replacement value corresponding to the replacement value and / or activation function selected during calibration.

[0077] In particular, when the values ​​of the table LUT are selected during calibration, the output of the LUT acts via a feedback loop on the values ​​of the reference inputs +LSB and −LSB of the analog comparator, and / or unit time, and / or unit current.

[0078] The lookup table can be used to correct for non-linearities in the circuit or to cater for any other type of response.

[0079] If there is a single control signal that controls the current source, it is possible to act on it per unit time.

[0080] It is possible to affect a unit current if there are multiple control signals controlling multiple current sources that generate multiples of this current.

[0081] In any of the above cases, it is possible to affect the values ​​of the reference input +LSB and -LSB. This calibration can be performed at least once to measure the circuit's nonlinearity, calibrate the circuit, and reduce output errors.

[0082] By choosing appropriate values ​​for the LUT, it is also possible to mimic activation functions in artificial intelligence by adjusting the values ​​of the parameters of the control signal generation.

[0083] Activation functions are used to nonlinearly modify the data. They can be sigmoid, Tanh, ReLU, or other activation functions. In particular, activation functions represent a predefined nonlinear response that is desired to be obtained.

[0084] Alternatively, the analog to digital converter may be two analog comparators each configured to compare the voltage of the storage line to which the analog-to-digital converter is connected with a predefined threshold, i.e., to compare said voltage with a high voltage threshold V H , especially compared to +LSB, the voltage on the storage line is V H a first comparator configured to be activated when the voltage on the storage line is higher than a low voltage threshold V L , especially compared to -LSB, when the voltage on the storage line is V L a second comparator configured to be activated when the first comparator is lower than a digital unit configured to convert the result of the comparison into two separate output signals, a first signal indicative of activation of one of the two comparators, and a second signal specifying which of the two comparators has been activated; a counter configured to be incremented or decremented in accordance with the signal at the output of the digital unit, the output of which is the output of the converter; a charge injection unit connected to the output of the digital unit and configured to restore the charge on a storage line connected to the converter to an initial value when the digital unit indicates that this line has been discharged; a discharge unit connected to the output of the digital unit and configured to discharge a storage line connected to the converter and return this line to its initial value if the digital unit indicates that this line has been charged; Equipped with.

[0085] In one embodiment, the analog-to-digital converter comprises a delay circuit connected to the output of the digital unit and configured to generate pulses of duration T required to charge or discharge the line; Each of the injection unit and the discharge unit comprises at least one current source and an associated switch controlled by a delay circuit to close the switch associated with the injection unit and open the switch associated with the discharge unit for a time T in order to charge the storage line back to its initial value when the low threshold comparator is activated, indicating that the line has been discharged, resulting in a voltage drop corresponding to −1 LSB, or to close the switch associated with the discharge unit and open the switch associated with the injection unit for a time T in order to discharge the storage line back to its initial value when the high threshold comparator is activated, indicating that the line has been charged, resulting in a voltage increase corresponding to +LSB.

[0086] In another embodiment, the analog to digital converter comprises: a capacitor network comprising a main capacitor connected directly to the storage line and to ground, a peripheral capacitor, and a switch, wherein the capacitance of each peripheral capacitor is determined by a coefficient α, preferably α=α, corresponding to the charge required to compensate ±1 LSB;

[0087]

number

[0088] The capacitance of the main capacitor is proportional to the capacitance of the peripheral capacitor and the switch form two branches, the ends of which are connected to a reference voltage, i.e., V DD and a capacitor network connected to ground, each of the switches being disposed between each peripheral capacitor and the main capacitor or between each peripheral capacitor and one of the reference voltages, each pair of switches directly connected to the same peripheral capacitor being controlled by two complementary signals; an asynchronous finite state machine connected to the output of the digital unit and configured to control the switch according to a result of the comparison; Non-Overlapping Clock Generation Units NOC (Non-Overlapping Clock) at the output of the state machine, each configured to generate a pair of complementary control signals for controlling a switch, ensuring that the switch does not create a short circuit between one of the reference voltages and the storage line; Equipped with.

[0089] According to another aspect of the invention, there is also provided a method for injecting and collecting charge on a storage line of a circuit according to the invention, the method comprising: connecting only one of the peripheral capacitors, called the first peripheral capacitor, to the main capacitor, where the first peripheral capacitor has previously been connected to V DD connected to the step, The voltage on the storage line reaches the high voltage threshold V H disconnecting the first peripheral capacitor from the main capacitor and connecting the second peripheral capacitor that was previously connected to ground when The voltage on the storage line reaches the low voltage threshold V L When V is reached, the second peripheral capacitor is disconnected from the main capacitor and pre-charged to V DD connecting a third peripheral capacitor that was previously connected to Includes.

[0090] According to another aspect of the invention, the storage line of the circuit according to the invention is connected to a voltage V DD Also provided is a method for initializing to / 2, where the switches are alternately opened and closed so that only peripheral capacitors in the same branch are connected to the main capacitor (310).

[0091] In one embodiment, the circuitry comprises a time mask generation unit located external to the memory.

[0092] In one embodiment, the generating unit is configured to generate a temporal mask PW(d)

[0093]

number

[0094] A period T substantially equal to d , and the time mask PX(c) is activated continuously for each T d About 2 c+d *T, wherein T is a function of the vector X j is a unit of time corresponding to the duration of activation of the time mask associated with the least significant bit of

[0095] In this scenario, the circuit according to the invention preferably comprises a single absolute value of current strength, controlled by a single control signal SC.

[0096] In another embodiment, the circuit according to the invention comprises at least two current sources, each controlled by a respective control signal SC, and the generating unit determines whether the time mask PW(d) is

[0097]

number

[0098] A period T substantially equal to d , where d∈{0,...,max(b l -a l )} and PW's (n W -1) k bits in the interval [a l ,b l ], where k is the number of current sources or control signals, l∈{0,...,k-1}, and b l ≧a l and {a l ,b l}∈[0,(n W -2)], and a l and b l is in the interval [a l ,b l ] is in the interval [0,n W-2], and the longest interval is chosen to represent a partition of [0,max(b l -a l )] and T is the vector X j is the unit time corresponding to the duration of activation of the time mask associated with the least significant bit of d About 2 c+d *Continuously activated for a period of time substantially equal to T.

[0099] In another aspect of the present invention, there is also provided a set of circuits for performing in-memory multiply-accumulate MAC operations, particularly for neural networks, the set of circuits including: m ] and the weight matrix

[0100]

number

[0101] and a plurality of circuits according to the present invention configured to determine the result of a matrix multiplication with the time mask generation unit, the circuits being parallel to each other and sharing a single time mask generation unit located outside the memory.

[0102] The invention will be better understood by reading the following detailed description of non-limiting examples of its implementations and by examining the accompanying drawings, in which: [Brief explanation of the drawings]

[0103] [Figure 1] FIG. 1 is a diagram illustrating the principle of in-memory calculation of a MAC operation in the prior art. [Figure 2] FIG. 1 is a diagram illustrating an example of in-memory computation of a MAC operation using a resistive technique in the prior art. [Figure 3] FIG. 1 is a diagram illustrating an example of in-memory computation of a MAC operation using a capacitive approach in the prior art. [Figure 4] 1 is a circuit diagram that schematically illustrates the principle of in-memory computation of a MAC operation according to the present invention; [Figure 5]This is a diagram that reproduces the formula for the scalar product of two vectors of 4 bits each. [Figure 6] FIG. 6 is a diagram showing the time course of the scalar product terms of FIG. 5. [Figure 7] FIG. 10 shows the curve of the voltage of the storage line over time during a 100 MAC calculation. [Figure 8] FIG. 10 is a diagram showing a first example of a timing diagram of a time mask. [Figure 9] FIG. 10 shows a second example of a timing diagram of a time mask. [Figure 10] FIG. 10 is a diagram illustrating an example of a first logical subunit for time masking a 4-bit binary vector Xj. [Figure 11] FIG. 10 schematically illustrates an example of a second logical subunit for temporally masking a 4-bit binary vector Wj,i. [Figure 12] 9 is similar to FIG. 8 but shows some details of the scalar product of the vectors Xj and Wj,i based on a time mask. [Figure 13] FIG. 13 is a timing diagram of the control signals resulting from a simulation of the scalar product of vectors X and W given as an example in FIGS. 10 to 12. [Figure 14] 1 shows a schematic diagram of the architecture of a circuit according to the invention; [Figure 15] FIG. 15 shows a schematic diagram of a first embodiment of a current source that can be used in the circuit of FIG. 14; [Figure 16] FIG. 15 shows a schematic diagram of a second embodiment of a current source that can be used in the circuit of FIG. 14; [Figure 17] FIG. 15 is a schematic diagram illustrating an example of a switch that can be used in the circuit of FIG. 14. [Figure 18] FIG. 15 shows a schematic diagram of a storage line that can be used in the circuit of FIG. 14. [Figure 19] FIG. 15 shows a schematic diagram of a storage line and a secondary storage line that can be used in the circuit of FIG. 14. [Figure 20]FIG. 20 is similar to FIG. 19, but additionally shows a switch connected to the storage line. [Figure 21] FIG. 15 shows a schematic diagram of a first embodiment of an analog-to-digital converter that can be used in the circuit of FIG. 14; [Figure 22] FIG. 15 shows a schematic diagram of a second embodiment of an analog-to-digital converter that can be used in the circuit of FIG. 14; [Figure 23] FIG. 15 shows a schematic diagram of a third embodiment of an analog-to-digital converter that can be used in the circuit of FIG. 14; [Figure 24] 1 shows a schematic example of the architecture of a set of circuits according to the invention using a time weighting approach; [Figure 25] FIG. 1 shows a schematic diagram of an example of a circuit according to the present invention operating according to a current weighting technique; [Figure 26] FIG. 26 shows a first example of a timing diagram for a time mask that can be used in the circuit of FIG. 25. [Figure 27] 1 shows a schematic diagram of a first example of an architecture for a set of circuits according to the invention using a current weighting technique; [Figure 28] FIG. 26 shows a second example of a timing diagram for a time mask that can be used in the circuit of FIG. 25. [Figure 29] FIG. 2 shows a schematic diagram of a second example of an architecture for a set of circuits according to the invention using a current weighting technique; [Figure 30] FIG. 15 shows a schematic diagram of a fourth embodiment of an analog-to-digital converter that can be used in the circuit of FIG. 14; [Figure 31] FIG. 31 illustrates a first example of an implementation of the converter shown in FIG. 30. [Figure 32] FIG. 31 illustrates a second example of an implementation of the converter shown in FIG. 30. [Figure 33] FIG. 33 is a timing diagram of voltages associated with the second example of FIG. 32. [Figure 34]FIG. 33 is a diagram illustrating a schematic representation of a capacitor network with switches that can be used in the second example of FIG. 32. [Figure 35] 35 is a view similar to FIG. 34 after the switch has been toggled. [Figure 36] FIG. 35 shows two instances of the capacitor network of FIG. 34 during the initialization phase, to illustrate the alternating opening and closing of the switches forming the pairs of said network. DETAILED DESCRIPTION OF THE INVENTION

[0104] 1 to 3 show examples from the prior art and are described above.

[0105] FIG. 4 shows a schematic circuit illustrating the principle of in-memory computation of a MAC operation according to the present invention. This principle is based on charge accumulation on a capacitive line AL by a current source CS. The illustrated example concerns a ternary multiplication of a bit X by a weight bit W, taking into account the associated respective sign bit. Such a ternary multiplication is implemented in a logic unit LG, the output of which is a control signal that activates a switch SW, which allows the current source CS to charge or discharge the capacitive line AL, depending on the sign of the ternary multiplication result. The result is then digitized by an analog-to-digital converter ADC.

[0106] This principle of charge accumulation in a storage line is extrapolated to multi-bit multiplication.

[0107] FIG. 5 reproduces the formula for the scalar product of two vectors, a vector X and a vector W of weights, each of 4 bits.

[0108]

number

[0109] and n X = 4 and n W=4 and the vector does not have a sign bit in this example.

[0110] A control signal representing this scalar product is used to control the current source.

[0111] For this purpose, the current source is activated for a reference unit time T weighted by the weight of the scalar product term in FIG.

[0112] FIG. 6 shows such a signal corresponding to the time evolution of the scalar product term in FIG.

[0113] Depending on the sign of the scalar product, the storage line is either charged or discharged using a current source.

[0114] The method according to the invention takes advantage of the time required to charge a storage line with a low current for a long time, thanks to the recent advanced CMOS technology. With a reference unit time T of 20 nanoseconds, the total time for a 5-bit MAC operation is 5 microseconds. For a storage line capable of receiving 100 MAC results, the throughput is 50 GOPS (Giga Operations Per Second). This throughput is sufficiently high for many applications, such as audio applications, especially keyword spotting (KWS), where new data is input every 10 milliseconds.

[0115] Figure 7 shows the curve of the voltage change over time of the storage line during a 100 MAC calculation. This line is initialized to 0.5 V (half the dynamic range of the circuit powered at 1 V) to allow negative values ​​to be represented.

[0116] multi-bit vector X j and W j,i A logic unit LG is implemented which receives at its input these vectors and the associated time masks PX and PW in order to obtain control signals representing the scalar products of .

[0117] FIG. 8 shows a first example of a timing diagram of a time mask, where the generation of these signals starts with the lowest weighting.

[0118] For each bit of the elements of the vector X and the weight matrix W, a time mask PX and PW is generated.

[0119] For a 4-bit multiplication, four time masks are required, so there are a total of eight time masks, PX = [PX(0),...,PX(3)] associated with the bits of the elements of vector X and PW = [PW(0),...,PW(3)] associated with the bits of the elements of weight matrix W.

[0120] The temporal mask PW(d) is preferably

[0121]

number

[0122] A period T substantially equal to d T is generated so that it is continuously active for the least significant bit X j is the reference unit time corresponding to the duration of activation of the time mask associated with each T d About 2 c+d *T, where {c, d}∈{0,...,3}.

[0123] The generation of signals PX and PW can start with the highest weighting as shown in the example of FIG. 9, or can start in any order as long as the time masks PX and PW are synchronized.

[0124] The logic unit LG, which receives at its input the vectors X and W and the associated time masks PX and PW, preferably comprises a first logic subunit for time masking the bit X and a second logic subunit for time masking the weight bit W, these two subunits being cascaded such that the output of the first subunit is the input of the second subunit.

[0125] Figure 10 shows the 4-bit binary vector X j 10 shows a schematic example of a first logical subunit LGX for time masking the

[0126] The first logic subunit LGX comprises two logic gate stages, a first stage 10 and a second stage 11 .

[0127] In this example, the first stage 10 comprises four logic gate levels, the levels being cascaded such that the signal at the output of one level is the signal at the input of the next level, until finally a single signal 101 is obtained at the output. j [0], ..., X j [3] and the associated time masks PX(0),...,PX(3) are at the inputs of the first level logic gates, in this case the two-input NAND gates.

[0128] The signal 101 at the output of the first stage therefore has the following value:

[0129]

number

[0130] Represents.

[0131] The second stage 11 in this example comprises two logic gate levels: a two-input NAND gate level and a NOT gate level. The signal 101 at the output of the first stage and each time mask PW(0), ..., PW(3) are at the inputs of the logic gates of the NAND gate level.

[0132] The NOT gate level outputs four signals, denoted XW(0), ..., XW(3), which are injected into the inputs of the second logic subunit.

[0133] Figure 11 shows the 4-bit weight vector W j,i 10 shows a schematic example of a second logical subunit LGW for time masking the

[0134] The second subunit LGW receives at its input the signals XW(0), ..., XW(3) at the output of the first subunit and the weight bits W j,i [0], ..., W j,i [3] and comprises several logic gate levels, in this case four levels, which are cascaded such that the signal at the output of one level becomes the signal at the input of the next level, until finally a single signal corresponding to the control signal SC is obtained at the output. Each first level logic gate (in this example a two-input NAND) receives at its input the signals XW(0), ..., XW(3) at the output of the first sub-unit LGX and the corresponding weight bit W j,i [0], ..., W j,i [3]. Thus, the signal SC receives the following values:

[0135]

number

[0136] Represents.

[0137] The second subunit LGW receives at its input the vector X j (X j [4]) sign bit X j [sign] and vector W j,i (W j,i [4]) sign bit W j,i It also has an XNOR gate that receives [sign] and the polarity signal SP=X. j[sign]*W j,i [sign] is provided. Vector X j and W j,i Based on its value (+ or -), which represents the sign of the scalar product of , SP activates one of the switches SW to charge or discharge the storage line AL.

[0138] FIG. 12 shows the vector X based on the associated time mask. j and W j,i Reconsider the timing diagram of FIG. 8 by showing some details of the scalar product of

[0139] FIG. 13 shows the vector X given as an example in FIGS. 10 to 12. j and W j,i 1 shows a timing diagram of the resulting control signal SC from a simulation of the scalar product of vector X j and W j,i is the following, X j =

[11010] and W j,i

[10110] , where the sign bit is the rightmost bit.

[0140] The small peaks seen in signal SC in FIG. 13 simply indicate a transition to the same state, which does not actually occur.

[0141] 14 shows a schematic diagram of the architecture of a circuit 1 according to the invention, which comprises a generator PG for generating time masks PX, PW, logic subunits LGX, LGW, a current source CS, a switch SW, a storage line AL and an analog-to-digital converter ADC.

[0142] The generator PG is preferably located outside the memory and generates vectors X1, ..., X a Generate time masks PX, PW for all logical subunits LGX associated with

[0143] The output XW of the logic subunit LGX is a set of multiple lines of the weight matrix W, W 1,1 ,...Wm,1 , W 1,2 , ..., W m,2 , (...), W 1,n , ..., W m,n where the index of the second position, ranging from 1 to n, corresponds to the column of the matrix.

[0144] The values ​​of the vector X and the matrix W are preferably stored close to the logic unit to reduce the cost of accessing the data by using flip-flop registers or any other memory that can store values ​​without consuming too much power, such as SRAM memory, etc. Each bit is preferably stored separately to be used at the input of the logic unit.

[0145] In this example, each column of the matrix W has an associated storage line AL and an analog-to-digital converter ADC.

[0146] For each row of the weight matrix, the output XW is fed back to the input of the corresponding logic subunit LGW to obtain a control signal and a bias signal (not shown in Figure 14). As explained above, the bias signal is used to control a switch SW which activates a current source CS coupled to it to charge or discharge the storage line AL according to the change in the control signal over time.

[0147] A first embodiment of a current source CS that can be used in the circuit of FIG. 14 is shown in FIG.

[0148] The current source CS is created using a current mirror. One current mirror made up of PMOS transistor 14 charges the storage line AL, and another mirror made up of NMOS transistor 15 discharges the storage line AL. Figure 15 shows the storage line AL with the output of the current mirror connected to the storage line AL through a switch SW. The transistors used can be standard transistors, but if the number of transistors in the current mirror is increased, thick oxide transistors can be used to reduce gate leakage.

[0149] Since the voltage on the storage line AL can vary, it is possible to increase the output impedance of the current mirror by using a cascaded architecture, as shown in Figure 16. Such an architecture increases the dynamic range [V dd -0] realizes more stable current value throughout the entire V dd is the supply voltage of the circuit.

[0150] Since the current source must be activated and deactivated at multiple voltage levels on the storage line, an electronic switch SW of the pass-gate type (pass-gate switch) is preferably used.

[0151] Figure 17 shows a schematic example of such an electronic switch SW, which comprises two transistors, one NMOS 17 and one PMOS 16, whose drains are connected to each other as are their sources. A signal applied to the gate of one of the transistors is the binary complement of the signal applied to the gate of the other transistor.

[0152] This switch provides good performance over the entire dynamic range.

[0153] The storage line AL comprises a metal line, the capacitance of which is the capacitance of the metal line and of all parasitic capacitances 18 of the electronic switches SW connected to the storage line, as shown diagrammatically in FIG.

[0154] The line values ​​are easily estimated in simulations and the current source values ​​can be adjusted to match the capacitance of the storage line.

[0155] The capacitance of the storage line can be increased by adding an additional capacitor to the output of the switch.

[0156] In the embodiment shown in Figure 19, a secondary storage line DAL is added to control the current. A follower operational amplifier 19 can be connected between the two storage lines, AL and DAL, so that each remains at the same voltage level in order to counteract charge sharing effects when switch SW opens and closes. Figure 20 is similar to Figure 19 and additionally shows a switch connected to the storage line.

[0157] To reduce charge sharing, the secondary storage line DAL can be fabricated with a lower capacitance than the storage line AL so that charge is shared in proportion to the ratio between the capacitances of the two lines.

[0158] The analog-to-digital converter ADC is either directly connected to the storage line AL if there is no secondary storage line DAL, or is connected to the secondary storage line DAL via a follower operational amplifier 20, as shown in FIG.

[0159] FIG. 21 shows a schematic diagram of a first embodiment of an analog-to-digital converter ADC that can be used in the circuit of FIG.

[0160] In this example, the analog-to-digital converter ADC comprises two analog comparators 22 and 23, one of which compares the value of the charge on the storage line 21 to which the analog-to-digital converter ADC is connected with +LSB, and the other of which compares the value of the charge on the storage line 21 to which the analog-to-digital converter ADC is connected with -LSB. The analog-to-digital converter also comprises a counter 24 configured to increment or decrement according to the result of the comparison between the analog comparators 22 and 23, and the output 30 of the counter 24 is the output of the converter. The analog-to-digital converter ADC also comprises a charge injection unit 25 configured to restore the charge on the storage line 21 connected to the converter to its initial value if the counter indicates that this line has been discharged, and a discharge unit 26 configured to discharge the storage line 21 connected to the converter and restore it to its initial value if the counter indicates that this line has been charged.

[0161] 22 and 23 show schematically two variants of the converter of FIG. 21 in which the converter is provided with a feedback loop 32 for calibration purposes.

[0162] In fact, the feedback loop 32 can be introduced either to modify the value of the LSB according to the value at the output of the counter 24 (scenario shown in Figure 22) or to modify the unit time T in the time mask generator PG (scenario shown in Figure 23). In the case of Figure 23, the feedback loop 32 can be used to modify the unit current I of the basic current source instead of the unit time T, as will be explained later with reference to Figures 25 to 27.

[0163] 22 and 23, the analog-to-digital converter ADC comprises a look-up table LUT configured to receive at its input the output 30 of the counter 24 and to output a replacement value corresponding to the activation function or a correction value for calibration purposes. A feedback loop 32 is used to apply the output of the LUT to the reference inputs +LSB and −LSB values ​​of the analog comparators 22 and 23 and / or to adjust the unit time and / or unit current.

[0164] In the example shown in FIG. 22, feedback loop 32 applies the output of look-up table LUT to reference inputs +LSB and −LSB of comparators 22 and 23 .

[0165] In the example shown in FIG. 23, the loop 32 applies the output of the look-up table LUT to a time mask generator PG to modify the unit time T, or to a reference current source to modify the reference current I.

[0166] Thus, the lookup table can be used to calibrate a circuit by correcting for nonlinearities or to obtain a predefined nonlinear response that can correspond to an artificial intelligence activation function.

[0167] FIG. 30 shows a schematic diagram of a fourth embodiment of an analog-to-digital converter that can be used in the circuit of FIG.

[0168] This converter is called a level-crossing converter, and its voltage V m is connected to a storage line representing the result of the multiply-accumulate operation.

[0169] In the example of FIG. 30, the converter ADC: Two analog comparators 222, 233, each configured to compare the voltage on the storage line 21 to which the analog-to-digital converter is connected with a predefined threshold, i.e. to compare said voltage with a high voltage threshold V H , especially compared to +LSB, the voltage on the storage line 21 is V H a first comparator 222 configured to be activated when the voltage on the storage line 21 is higher than a low voltage threshold V L , especially compared to -LSB, the voltage on the storage line 21 is V L a second comparator 233 configured to be activated when a digital unit 243 configured to convert the result of the comparison into two separate output signals: a first signal indicative of activation of one of the two comparators, and a second signal specifying which of the two comparators has been activated; a counter 244 configured to be incremented or decremented according to the signal at the output of the digital unit, the output 30 of which is the output of the converter; a charge injection unit 25 connected to the output of the digital unit and configured to restore the charge on the storage line 21 connected to the converter to its initial value if the digital unit 243 indicates that this line 21 has been discharged; a discharge unit 26 connected to the output of the digital unit 243 and configured to discharge the storage line 21 connected to the converter and return it to its initial value if the digital unit 243 indicates that this line 21 has been charged; Equipped with.

[0170] The injection unit 25 and the discharge unit 26 can be implemented in different ways, two of which are described below: the first involves using a current source to charge / discharge the storage line, and the second involves using a capacitor network.

[0171] FIG. 31 shows an example of an implementation of the converter shown in FIG. 30 according to the first method using a current source.

[0172] In this example, the analog-to-digital converter ADC is connected to the output of the digital unit 243 and comprises a delay circuit 270 configured to generate pulses of duration T required to charge or discharge the line. Each of the injection unit 25 and the discharge unit 26 comprises at least one current source 250, 260 and an associated switch 251, 261 controlled by the delay circuit 270 to close a switch associated with the injection unit and open a switch associated with the discharge unit for time T in order to charge the storage line back to its initial value when the low threshold comparator is activated, indicating that the line has been discharged, resulting in a voltage drop corresponding to -1 LSB, or to close a switch associated with the discharge unit and open a switch associated with the injection unit for time T in order to discharge the storage line back to its initial value when the high threshold comparator is activated, indicating that the line has been charged, resulting in a voltage increase corresponding to +LSB.

[0173] FIG. 32 shows an example of an implementation of the converter shown in FIG. 30 according to a second method using a capacitor network.

[0174] In this example, the analog-to-digital converter ADC comprises a capacitor network 300, a finite state machine 280 and a non-overlapping clock generation unit (NOC, Non-Overlapping Clock).

[0175] The capacitor network 300 comprises a main capacitor 310 connected directly to the storage line 21 and ground, a peripheral capacitor 320, and a switch 330. The capacitance C α is proportional to the capacitance C of the main capacitor 310 by a coefficient α corresponding to the charge required to compensate for ±LSB, i.e., C α = αC. The peripheral capacitor 320 and switch 330 form two branches, the ends of which are connected to a reference voltage, i.e., V DD and ground. The switches 330 are each placed between each peripheral capacitor 320 and the main capacitor 310, or between each peripheral capacitor 320 and one of the reference voltages. Each pair of switches directly connected to the same peripheral capacitor provides two complementary signals, e.g.,

[0176]

number

[0177] and

[0178]

number

[0179] is controlled by

[0180] An asynchronous finite state machine 280 connected to the output of the digital unit 243 is configured to control the switch 330 according to the result of the comparison.

[0181] The non-overlapping clock generation units NOC are at the output of the state machine 280. Each unit NOC provides a pair of complementary control signals for controlling the switch 330, e.g.

[0182]

number

[0183] and

[0184]

number

[0185] , ensuring that the switches do not create a short circuit between one of the reference voltages and the storage line.

[0186] Figure 33 is a timing diagram of the voltages associated with the second example of Figure 32. This timing diagram shows the sequence of operations for resetting the storage line 21. First, the capacitance C located in the first branch connected to C α (all surrounding capacitances have the same value). In this example, the first connected capacitance is

[0187]

number

[0188] is the capacitance associated with the switch controlled by the current I charge charges the capacitive line 21. The voltage V m V H If V reaches V, then the opposite capacitance (located on the second branch and initially connected to ground) is connected to C, pulling the line to V m where the control signal for controlling the associated switch is

[0189]

number

[0190] becomes 1. Then the signal

[0191]

number

[0192] goes to zero and the calculation continues until one of the two comparators is next triggered. In fact, line 21 discharges again and line V m The voltage at V L , then the opposite capacitance (located on the first branch, initially V DD ) is connected to C, and the line is connected to V m where the control signal for controlling the associated switch is

[0193]

number

[0194] becomes 1. Then the signal

[0195]

number

[0196] becomes zero.

[0197] The diagram in FIG. 34 shows an example of a capacitor network 300 that can be used in the second example of FIG. 32, where the capacitor network 300 includes a main capacitor 310 with capacitance C corresponding to the capacitance of the storage line 21, and all capacitors C α = α.C has the same value as h1 , C h2 , C l1 , and C l2 and a peripheral capacitor 320 having a capacitance of

[0198] The principle of operation of the circuit of Figure 34 is as follows: The voltage V on line 21 m but

[0199]

number

[0200] As the line charges, the voltage Vm is V H increases until it reaches

[0201] The charge is: Q h1 =C h1 V H , Q C =CV H and Q l1 =0 After the switch is toggled, as shown in Figure 35, which is similar to Figure 34,

[0202]

number

[0203] The switch controlled by

[0204]

number

[0205] The switch controlled by opens.

[0206] Here, the charge is Q C =CV m and Q l1 =C l1 V m is.

[0207] therefore, CV H =V m (C+C l1 )

[0208]

number

[0209] This becomes:

[0210] where V m Perform the same calculation using V H instead of VL When you reach

[0211]

number

[0212] The switch controlled by

[0213]

number

[0214] The switch controlled by opens. The charge before switching is Q h2 =C h2 V DD , Q C =CV L , and Q h1 =C h1 V L After switching, the charge is Q h2 =C h2 V m , and Q C =CV m is.

[0215] therefore, C h2 V DD +CV L =V m (C h2 +C)

[0216]

number

[0217] This becomes:

[0218] where C l1 =C l2 =C h1 =C h2 =C α Assuming that ≠ C, V m The value of must be the same in the two configurations mentioned above.

[0219]

number

[0220]

number

[0221] This becomes:

[0222] where C α The value of C and the supply voltage V DD , and V H and V L The possible voltage steps are therefore given by

[0223]

number

[0224] is.

[0225] Thus, by switching the capacitance, it is possible to inject / remove charge into / from line 21, the resulting voltage jump being:

[0226]

number

[0227] is equal to.

[0228] Line 21, voltage

[0229]

number

[0230] To initialize to

[0231]

number

[0232] and

[0233]

number

[0234] And, a pair

[0235]

number

[0236] and

[0237]

number

[0238] It is possible to alternately connect and disconnect with the

[0239] Figure 36 shows schematically two instances of the capacitor network 300 of Figure 34 to illustrate the alternating opening and closing of the switches 330 that form part of the network. In practice, the opening and closing of the switches is alternating so that only peripheral capacitors 320 of the same branch are connected to the main capacitor 310.

[0240] The initial voltage

[0241]

number

[0242] First, the charge is

[0243]

number

[0244] , Q h1 =C α V DD , and Q l1 =0. Then,

[0245]

number

[0246] and

[0247]

number

[0248] The switch controlled by is closed. In this case, the charge is

[0249]

number

[0250] ,

[0251]

number

[0252] , and

[0253]

number

[0254] The law of conservation of charge is

[0255]

number

[0256] means.

[0257] C α Considering that = αC,

[0258]

number

[0259] is obtained.

[0260]

number

[0261] and

[0262]

number

[0263] When the switch controlled by is switched, and the law of conservation of charge is applied,

[0264]

number

[0265] is obtained.

[0266]

number

[0267] but

[0268]

number

[0269] When replaced with

[0270]

number

[0271] is obtained.

[0272] Therefore, by performing k switching operations, the error is

[0273]

number

[0274] where ε0 is the initial error and ε k tends to approach 0, and V m but

[0275]

number

[0276] This means that it converges to

[0277] FIG. 24 shows a schematic architecture of a set of circuits for performing in-memory multiply-accumulate MAC operations, particularly for neural networks, where the set of circuits computes the vector [X1,...,X m ] and the weight matrix ([W l,1 ,...,W m,1 ],...,[W 1,n ,...,W m,n ]), which are in parallel with each other and share a single time mask generation unit PG located outside the memory, and which operate at, for example, 50 MHz.

[0278] FIG. 25 shows a schematic diagram of a circuit according to the invention, which operates according to a current weighting technique.

[0279] Referring to the previous figure, it can be seen that it is possible to use a current source CS by weighting the charge / discharge times on the storage line AL. The voltage across the terminals of the storage line AL for a multiply-accumulate (MAC) operation is given by:

[0280]

number

[0281] where C is the capacitance value of the storage line and I is the current strength of the current source CS.

[0282] By weighting the current and reducing the charge / discharge time, it is possible to obtain the same scalar product result R.

[0283] According to the current weighting approach, there are multiple current sources (k is the number of current sources) that are weighted by a power of two and controlled by a control signal SC that represents the value of the bit associated with this weighting.

[0284] This advantageously increases the speed of calculation by reducing the duration of the control signal.

[0285] In the example shown in FIG. 25, the intensities I and 2 l *Two control signals SC that activate the current source I 0,j,i and SC 1,j,i where I is the reference elementary current associated with the least significant bit of index 0 to (k-1). In this example, k=2 since there are only two control signals.

[0286] The generation of the temporal mask PX is the same as for the temporal weighting seen above, but the generation of the temporal mask PW is different.

[0287] Indeed, taking the example of a 4-bit multiplication (without a sign bit), the time masks PX and PW are shown in FIG.

[0288] The calculation is half as long as with time weighting, and the signals PW(0) and PW(2) are identical to PW(1) and PW(3). In fact, the same signals are used, but in different current sources.

[0289] In the example timing diagram shown in FIG. 26, the four bits indicate that the control signal is:

[0290]

number

[0291]

number

[0292] is distributed equally between the two sources so that

[0293] FIG. 27 shows a set of circuits according to the invention, similar to FIG. 24, using the current weighting variant for a 4-bit multiplication with equal distribution of the bits between the two current sources.

[0294] The reference current for charging is I ref_P and the reference current for discharge is I ref_N is represented by I ref_P =I ref_N The corresponding current source transistor is dimensioned to provide such a current strength. The ratio W / L is related to the transconductance gm, which is defined as the ratio between the variation of the drain current and the variation of the gate-source voltage. Thus, for a given gate-source voltage, a higher W / L ratio leads to a higher current, where W is the width of the conductive channel and L is its length. A current source transistor with a higher weighting has a ratio of 4W / L.

[0295] Figure 28 shows a second example of a timing diagram for a time mask that can be used in the circuit of Figure 25. In this example, four bits are used to indicate that the control signal is:

[0296]

number

[0297]

number

[0298] is distributed unequally between the two sources so that

[0299] FIG. 29 shows a set of circuits according to the invention, similar to FIG. 27, using the current weighting variant for the case of a 4-bit multiplication with unequal distribution of bits between the two current sources.

[0300] The transistor of the current source with the higher weighting has a ratio of 8W / L. In fact, the second current source is the bit W j,i [3] only, and PW(3) is equivalent to PW(0), so the current is weighted 2 3 Therefore, the transistor sizes must be scaled by the same factor.

[0301] Applications of the present invention include optimizing computations in preprocessors, perceptrons, and classifiers.

[0302] The present invention is not limited to the exemplary embodiments described above. For example, the logic unit can be implemented using different logic gates, typically NOR gates, instead of NAND gates. The frequency of the time mask generation unit can be changed to suit the needs of the target application. [Explanation of symbols]

[0303] 1 circuit 10 First Section 11 Second Stage 14 PMOS transistors 15 NMOS transistors 16 PMOS 17 NMOS 18 Parasitic capacitance 19 Follower operational amplifier 21 Storage line, capacitive line, line 22 Analog Comparator 23 Analog Comparator 24 Counter 25 Charge Injection Unit 26 Discharge unit 30 Output 32 Feedback Loop, Loop 101 Signal 222 Analog Comparator, First Comparator 233 Analog Comparator, Second Comparator 243 Digital Unit 244 counter 250 current source 251 Switch 260 current source 261 Switch 270 Delay Circuit 280 Finite State Machines, Asynchronous Finite State Machines, State Machines 300 Capacitor Network 310 Main capacitor 320 Peripheral Capacitor 330 Switch

Claims

1. A method for performing in-memory multiply-accumulate (MAC) operations, particularly for neural networks, each of which has (n x -1) a vector X=[X 1 X 2 ...X m ] and each is (n W -1) a matrix of m × n elements represented in bits [Equation 1] The result of matrix multiplication O is [Equation 2] and each element of the matrix product O is determined as a sum of scalar products [Equation 3] and [Equation 4] , i∈{1,...,n}, j∈{1,...,m}, and the bit vector X j =[X j [0],...,X j [n x -2 ]] and the weight bit vector W j,i =[W j,i [0],...,W j,i [n W -2 ]], wherein the multiply-accumulate operation applies the vector X to a set of logic gates to generate at least one control signal SC for controlling at least one current source. j and W j,i and the associated time mask value to obtain the scalar product R j,i , and the time mask PX=[PX(0),...,PX(n x -2)] is the vector X j is associated with the bits of the elements of the time mask PW=[PW(0),...,PW(n W -2)] is the vector W j,i and in particular the scalar product R j,i wherein the control signal SC activates the at least one current source to store capacitive charge in a storage line in a manner proportional to

2. At least one of the two vectors is signed, and X j [sign] is the vector X j is the sign bit of and / or W j,i [sign] is the weight bit vector W j,i and the set of logic gates generates a polarity signal SP=X to charge or discharge the storage line (AL). j [sign]×W j,i The method of claim 1, wherein [sign] is generated.

3. 3. The method according to claim 1, wherein the time masks PX and PW are generated in the form of pulses.

4. 4. The method according to claim 1, wherein the time masks PX and PW are generated by a time mask generation unit located outside a memory.

5. The time mask PW(d) is effectively [Equation 5] A period T equal to d and T is generated so as to be continuously activated during the vector X j the unit time corresponding to the duration of activation of the time mask associated with the least significant bit of c+d *For a period equal to T, each T d The method of any one of claims 1 to 4, wherein the β-glucan is produced so as to be continuously activated for β-glucan.

6. The control signal SC is [Equation 6] 6. The method of claim 5, wherein a single absolute current intensity value is controlled by charging or discharging the storage line such that: i∈{1,...,n} and j∈{1,...,m}.

7. There are at least two current sources (CS), each controlled by a respective control signal SC, and said time mask PW(d) is substantially [Equation 7] A period T equal to d are generated so that they are continuously activated for d∈{0,...,max(b l -a l )} and PW's (n w -1) k bits in the interval [a l ,b l ], where k is the number of current sources or control signals, l∈{0,...,k-1}, and b l ≧a l and {a l ,b l }∈[0,(n w -2)], and a l and b l is in the interval [a l ,b l ] is in the interval [0,n W -2], and the longest interval is chosen to represent a partition of [0,max(b l -a l )], and T is the vector X j the unit time corresponding to the duration of activation of the time mask associated with the least significant bit of c+d *For a period equal to T, each T d The method of any one of claims 1 to 4, wherein the β-glucan is produced so as to be continuously activated for β-glucan.

8. The control signal is [Equation 8] 8. The method of claim 7, wherein l∈{0,...,k-1}.

9. the voltage across the terminals of said accumulation line (AL) for multiplication-accumulation operations [Equation 9] but, [Equation 10] where C is the capacitance value of the storage line (AL), and I is the capacitance of the bottom current source (CS) (i.e., a l 9. The method according to claim 1, wherein the current intensity is 0.

10. A circuit (1) for performing in-memory multiply-accumulate (MAC) operations, particularly for neural networks, said circuit comprising: X -1) a vector X=[X 1 X 2 ...X m ] and each is (n W -1) a matrix of a × n elements represented in bits [0011] The result of matrix multiplication O with [0012] and each element of the matrix product O is a sum of scalar products [0013] and [0014] , i∈{1,...,n}, j∈{1,...,m}, and the bit vector X j =[X j [0],...,X j [n x -2 ]] and the weight bit vector W j,i =[W j,i [0],...,W j,i [n W -2 ]], and the circuit is The vector X j and W j,i a logic unit (LG) including logic gates to which the values ​​of the time mask PX=[PX(0),...,PX(n x -2)] is the vector X j is associated with the bits of the elements of the time mask PW=[PW(0),...,PW(n W -2)] is the vector W j,i a logic unit (LG) associated with a bit of the element of said logic unit, said logic unit being configured to generate at its output at least one control signal SC for activating at least one current source (CS); said at least one current source (CS) configured to be activated by said control signal SC to store capacitive charges in a storage line (AL); A circuit (1).

11. At least one of the two vectors is signed, and X j [sign] is the vector X j is the sign bit of and / or W j,i [sign] is the weight bit vector W j,i and the storage line (AL) is the sign bit of the polarity signal SP=X j [sign]×W j,i [sign], and this signal SP is configured to be charged or discharged according to the sign bit X j [sign] and the sign bit W j,i 11. The circuit of claim 10, wherein the signal is obtained at the output of an XOR or XNOR logic gate receiving at its inputs [sign] and [sign].

12. 12. The circuit according to claim 10 or 11, wherein the logic unit (LG) comprises NAND and / or NOR logic gates.

13. The logic unit (LG) has a bit X j a first logic subunit (LGX) for time masking the weight bits W j,i and a second logic subunit (LGW) for time masking the first subunit, wherein the two subunits are cascaded such that the output of the first subunit is the input of the second subunit.

14. The first sub-unit (LGX) receives at its input the time masks PX and PW and the bit X j [0:n X -2] and receives two logic gate stages, i.e., A first stage (10) comprising a plurality of logic gate levels, said levels being cascaded such that the signal at the output of one level becomes the signal at the input of the next level until finally a single signal is obtained at the output, said first stage being arranged such that for each bit X j [0:n X -2] and said associated time mask PX are inputs of a first level logic gate (10), in particular a NAND or NOR gate; a second stage (11) comprising at least one logic gate level, in which the signal at the output of the first stage and each time mask PW become inputs to a logic gate of said level, in particular a NAND or NOR gate; Equipped with 14. The circuit of claim 13.

15. The second sub-unit (LGW) receives at its input the signal at the output of the first sub-unit (10) and the weight bit W j,i [0:n W -2] and comprises a plurality of logic gate levels (12), said levels being cascaded such that the signal at the output of one level becomes the signal at the input of the next level, until finally a single signal corresponding to the control signal SC is obtained at the output, and each first level logic gate receives at its input the signal at the output of the first sub-unit (LGX) and the corresponding weight bit W j,i [0:n W 15. The circuit of claim 14, wherein the signal is received by the signal receiving circuit.

16. The bit vector X j The sign bit X of j [sign] and the bit vector W j,i The sign bit W of j,i 16. The circuit of claim 15 when dependent on claim 11, comprising an XOR or XNOR gate receiving at its inputs [sign] and

17. 17. The circuit of any one of claims 10 to 16, wherein the at least one current source (CS) is created by a current mirror using CMOS transistors (14, 15).

18. 18. A circuit according to claim 17, wherein the current mirror comprises a PMOS transistor (14) for charging the storage line (AL) and an NMOS transistor (15) for discharging the line.

19. 19. The circuit of claim 17 or 18, wherein the current mirror has a cascode architecture.

20. 20. The circuit of any one of claims 10 to 19, comprising at least one electronic switch (SW), in particular a pass gate, controlled by said control signal SC to activate said at least one current source (CS).

21. 21. The circuit according to any one of claims 10 to 20, comprising at least one capacitor at the output of said at least one electronic switch (SW) to increase the capacitance of said storage line (AL).

22. 22. A circuit according to any one of claims 10 to 21, comprising a secondary storage line (DAL) connected to the storage line (AL) via a follower amplifier (19).

23. 23. The circuit of claim 22, comprising a follower amplifier (19) connected between the storage line (AL) and the secondary storage line (DAL).

24. 24. The circuit according to claim 22 or 23, comprising an analog-to-digital converter (ADC) connected either directly to the secondary storage line (DAL) if there is no such line, or in particular connected to the secondary storage line via a follower amplifier (20).

25. The analog-to-digital converter (ADC) two analog comparators (22, 23), one of which compares the value of the charge on the storage line (21) to which the analog-to-digital converter is connected with +LSB, and the other of which compares the value of the charge on the storage line (21) to which the analog-to-digital converter is connected with -LSB; a counter (24) configured to increment or decrement according to the result of the comparison of the comparator, the output (30) of which is the output of the converter; a charge injection unit (25) configured to restore the charge on the storage line (21) connected to the converter to its initial value when the counter indicates that this line has been discharged; a discharge unit (26) configured to discharge the storage line (21) connected to the converter (20) and return it to its initial value when the counter (24) indicates that the storage line (21) is charged; 25. The circuit of claim 24, comprising:

26. 26. The circuit of claim 25, wherein the analog-to-digital converter (ADC) comprises a look-up table (LUT) configured to receive at its input the output (30) of the counter (24) and to output a replacement value corresponding to a replacement value and / or activation function selected during calibration.

27. 27. The circuit of claim 26, wherein when the look-up table (LUT) values ​​are selected during calibration, the output of the look-up table acts via a feedback loop (32) on the values ​​of +LSB and −LSB of the reference inputs of the analog comparators (22, 23), and / or on unit time (T), and / or on unit current (I).

28. 28. The circuit of any one of claims 10 to 27, comprising a temporal mask generation unit (PG) located external to the memory.

29. The generating unit (PG) determines whether the temporal mask PW(d) is [Equation 15] A period T substantially equal to d , and the time mask PX(c) is activated continuously for each T d About 2 c+d *T, wherein T is a function of the vector X j 29. The circuit of claim 28, wherein the time period corresponds to a period of activation of the time mask associated with the least significant bit of

30. The generating unit (PG) comprises at least two current sources (CS) each controlled by a respective control signal SC, and the generating unit (PG) determines whether the time mask PW(d) is [0016] A period T substantially equal to d and configured to generate the temporal mask so that it is continuously activated for d∈{0,...,max(b l -a l )}, and the (n W -1) k bits in the interval [a l ,b l ], where k is the number of current sources or control signals, l∈{0,...,k-1}, and b l ≧a l and {a l ,b l }∈[0,(n W -2)], and a l and b l is in the interval [a l ,b l ] is in the interval [0,n W -2], and the longest interval is chosen to represent a partition of [0,max(b l -a l )], and T is the vector X j is a unit time corresponding to the duration of the activation of the time mask associated with the least significant bit of d About 2 c+d 29. The circuit of claim 28, wherein the circuit is continuously activated for a period substantially equal to *T.

31. A set of circuits for performing in-memory multiply-accumulate (MAC) operations, particularly for neural networks, for vectors X=[X 1 X 2 ...X m ] and the weight matrix [Equation 17] 31. A set of circuits comprising a plurality of circuits (1) according to any one of claims 10 to 30 configured to determine a result of a matrix multiplication with a , the circuits (1) being parallel to each other and sharing a single temporal mask generation unit (PG) located outside the memory.

32. The analog-to-digital converter (ADC) two analog comparators (222, 233) each configured to compare the voltage of the storage line (21) to which the analog-to-digital converter is connected with a predefined threshold, i.e., to compare said voltage with a high voltage threshold V H , especially compared to +LSB, the voltage on the storage line (21) is V H a first comparator (222) configured to be activated when the voltage on the storage line (21) is higher than a low voltage threshold V L , in particular compared to -LSB, the voltage on the storage line (21) is V L a second comparator (233) configured to be activated when a digital unit (243) configured to convert the result of said comparison into two separate output signals: a first signal indicative of activation of one of said two comparators, and a second signal specifying which of said two comparators has been activated; a counter (244) configured to be incremented or decremented according to the signal at the output of the digital unit, the output (30) of which is the output of the converter; a charge injection unit (25) connected to the output of the digital unit and configured to restore the charge on the storage line (21) connected to the converter to an initial value when the digital unit (243) indicates that this line has been discharged; a discharge unit (26) connected to the output of the digital unit and configured to discharge the storage line (21) connected to the converter back to its initial value if the digital unit (243) indicates that this line has been charged; 25. The circuit of claim 24, comprising:

33. the analog-to-digital converter (ADC) comprises a delay circuit (270) connected to the output of the digital unit (243) and configured to generate pulses of duration T required to charge or discharge the line; Each of the injection unit (25) and the discharge unit (26) comprises at least one current source (250, 260) and an associated switch (251, 261) controlled by the delay circuit (270) to close the switch associated with the injection unit and open the switch associated with the discharge unit for a time T in order to charge the storage line back to its initial value when a low threshold comparator is activated, indicating that the line has been discharged, resulting in a voltage drop corresponding to -1 LSB, or to close the switch associated with the discharge unit and open the switch associated with the injection unit for a time T in order to discharge the storage line back to its initial value when a high threshold comparator is activated, indicating that the line has been charged, resulting in a voltage increase corresponding to +LSB, 33. The circuit of claim 32.

34. The analog-to-digital converter (ADC) a capacitor network (300) comprising a main capacitor (310) connected directly to the storage line (21) and to ground, a peripheral capacitor (320), and a switch (330), wherein the capacitance of each peripheral capacitor (320) is multiplied by a coefficient α, preferably α=α, corresponding to the charge required to compensate ±LSB for the capacitance of the main capacitor (310); [Equation 18] and the peripheral capacitor (320) and the switch (330) form two branches, the ends of which are connected to a reference voltage, i.e., V DD and ground, each of said switches (330) being disposed between a respective peripheral capacitor (320) and said main capacitor (310) or between a respective peripheral capacitor (320) and one of said reference voltages, each pair of switches directly connected to the same peripheral capacitor being controlled by two complementary signals; an asynchronous finite state machine (280) connected to the output of the digital unit (243) and configured to control the switch (330) according to the comparison result; non-overlapping clock generation units (NOCs) at the output of the state machine (280), each configured to generate a pair of complementary control signals for controlling the switches (330) to ensure that the switches do not create a short circuit between one of the reference voltages and the storage line (21); Equipped with 33. The circuit of claim 32.

35. A method for injecting and collecting charges in a storage line (21) of a circuit according to claim 34, comprising: connecting only one of the peripheral capacitors, called the first peripheral capacitor, to the main capacitor, where the first peripheral capacitor has previously been connected to V DD connected to the step, The voltage of the storage line (21) is a high voltage threshold V H disconnecting the first peripheral capacitor from the main capacitor and connecting a second peripheral capacitor that was previously connected to ground when The voltage on the storage line is at a low voltage threshold V L When V reaches V, the second peripheral capacitor is disconnected from the main capacitor. DD connecting a third peripheral capacitor that was previously connected to A method comprising:

36. The storage line (21) of the circuit according to claim 34 is connected to a voltage V DD / 2, wherein the switches are alternately opened and closed so that only peripheral capacitors (320) of the same branch are connected to the main capacitor (310).

Images