Analog Adders for Multi-bit MAC Arrays in Reconfigurable Analog-Based Neural Networks

Abstract

Various embodiments include devices and methods for a multi-bit multiply-accumulate (MAC). Some embodiments may include an analog adder having a first adder capacitor. The first adder capacitor may add the multiple single-bit MAC outputs by receiving multiple single-bit MAC outputs from multiple single-bit MACs and storing the multiple single-bit MAC outputs. In some embodiments, the analog adder may output a multi-bit MAC output based on the addition of the multiple stored single-bit MAC outputs.

Description

[Background technology]

[0001] Neural networks are increasingly being used in a variety of computing devices. Power efficiency of these neural networks is an important aspect of their implementation in computing devices. Digital computations in neural network implementations have proven inefficient for many applications. Analog neural networks are implemented as a more power-efficient alternative. However, while they have demonstrated performance improvements over analog binary neural networks, analog multi-bit neural networks suffer from computational performance bottlenecks when performing analog computations and are inflexible for computations using variable bit-width inputs. Summary of the Invention [Means for solving the problem]

[0002] Various disclosed embodiments may include apparatus and methods for multi-bit multiply and accumulate. The embodiments include a multi-bit multiply-accumulate (MAC) having an analog adder having a first adder capacitor configured to receive a plurality of single-bit MAC outputs from a plurality of single-bit MACs and add the plurality of single-bit MAC outputs by storing the plurality of single-bit MAC outputs, and the analog adder configured to output a multi-bit MAC output based on the addition of the stored plurality of single-bit MAC outputs.

[0003] In some embodiments, the plurality of single-bit MACs are each configured to sequentially multiply an individual bit of a first multi-bit value and a different single bit of a second multi-bit value, the first multi-bit value and the second multi-bit value being represented by digital voltages, and accumulating results of the multiplications to generate the plurality of single-bit MAC outputs, the plurality of single-bit MAC outputs being analog voltages.

[0004] Some embodiments may further include a plurality of single-bit MAC switches, wherein a first single-bit MAC switch of the plurality of single-bit MAC switches is configured to selectively electrically connect a first single-bit MAC of the plurality of single-bit MACs to the first adder capacitor as controlled by the control device. In some embodiments, the first adder capacitor is configured to receive the plurality of single-bit MAC outputs from the plurality of single-bit MACs, comprising receiving a first single-bit MAC output of the plurality of single-bit MAC outputs from the first single-bit MAC in response to the first single-bit MAC switch selectively electrically connecting the first single-bit MAC to the first adder capacitor; the analog adder comprises an operational amplifier having an input and an output, the first adder capacitor being electrically connected between the input and the output, the operational amplifier configured to receive the plurality of single-bit MAC outputs at the input, sum the plurality of single-bit MAC outputs to produce a weighted average of the plurality of single-bit MAC outputs, and output the weighted average of the plurality of single-bit MAC outputs as an analog voltage to the analog-to-digital converter. In some embodiments, the analog summer is configured such that adding the plurality of single-bit MAC outputs comprises adding the plurality of single-bit MAC outputs to produce a weighted average of the plurality of single-bit MAC outputs, and storing the plurality of single-bit MAC outputs comprises storing the weighted average of the plurality of single-bit MAC outputs. In some embodiments, the analog summer is configured such that outputting a multi-bit MAC output comprises outputting a weighted average of the plurality of single-bit MAC outputs.

[0005] In some embodiments, the analog summer comprises a plurality of designated capacitors, a first designated capacitor of the plurality of designated capacitors electrically connected between the first single-bit MAC switch and the first summer capacitor, the first designated capacitor being 2 rwhere r is a position in a weight value of a bit to be multiplied with a bit of an activation value used in producing the first single-bit MAC output, and the first designated capacitor is configured to receive the first single-bit MAC output, weight the first single-bit MAC output, and output a weighted first single-bit MAC output. In some embodiments, the operational amplifier is configured such that receiving the multiple single-bit MAC outputs comprises receiving weighted first single-bit MAC outputs, and such that adding the multiple single-bit MAC outputs comprises adding the weighted first single-bit MAC outputs.

[0006] Some implementations may further include a plurality of single-bit MAC switches, wherein a first single-bit MAC switch of the plurality of single-bit MAC switches is configured to selectively electrically connect the first adder capacitor with a first single-bit MAC of the plurality of single-bit MACs as controlled by the control device. In some embodiments, the first adder capacitor is configured such that receiving the plurality of single-bit MAC outputs from the plurality of single-bit MACs comprises receiving a first single-bit MAC output of the plurality of single-bit MAC outputs from the first single-bit MAC in response to the first single-bit MAC switch selectively electrically connecting the first single-bit MAC with the first adder capacitor, and the analog adder further comprises a plurality of adder capacitors including a first adder capacitor associated with the first single-bit MAC, wherein the first adder capacitor is 2 rwhere r is the position in the weight value of the bit that is multiplied with the bit of the activation value used in producing the first single-bit MAC output by the first single-bit MAC. In some embodiments, the first adder capacitor is configured to weight the first single-bit MAC output, wherein the analog adder is configured such that storing the plurality of single-bit MAC outputs comprises storing the weighted first single-bit MAC output, and outputting the weighted first single-bit MAC output. In some embodiments, the analog summer comprises a plurality of summer switches including a first summer switch associated with the first capacitor, the first summer switch configured to selectively electrically connect the first summer capacitor to the first single-bit MAC via the first single-bit MAC switch as controlled by the control device, and a second summer switch of the plurality of summer switches selectively electrically connecting a second summer capacitor of the plurality of summer capacitors to the electrically conductive bus as controlled by the control device selectively electrically connects the first summer capacitor to the electrically conductive bus simultaneously with outputting the weighted first single-bit MAC output from the first summer capacitor to produce a weighted average of the plurality of weighted single-bit MAC outputs including the weighted first single-bit MAC output. In some embodiments, the analog summer is configured such that outputting the multi-bit MAC output comprises outputting a weighted average of the plurality of weighted single-bit MAC outputs.

[0007] Some embodiments further comprise a buffer electrically coupled between the plurality of single-bit MAC switches and the plurality of adder switches.

[0008] Some embodiments may further include a plurality of single-bit MAC switches, wherein a first single-bit MAC switch of the plurality of single-bit MAC switches is configured to selectively electrically connect the first adder capacitor with a first single-bit MAC of the plurality of single-bit MACs as controlled by the control device. In some embodiments, the first adder capacitor is configured such that receiving the plurality of single-bit MAC outputs from the plurality of single-bit MACs comprises receiving a first single-bit MAC output of the plurality of single-bit MAC outputs from the first single-bit MAC in response to the first single-bit MAC switch selectively electrically connecting the first single-bit MAC with the first adder capacitor, and the analog adder comprises a plurality of adder switches including a first adder switch of the plurality of adder switches associated with the first adder capacitor, and a second adder capacitor, the second adder capacitor associated with a second adder switch of the plurality of adder switches, and the first adder capacitor and the second adder capacitor have the same rated capacitance. In some embodiments, the first adder switch is configured to selectively and electrically connect the first adder capacitor to the multiple single-bit MACs via the multiple single-bit MAC switches as controlled by the control device, and to selectively and electrically connect the first adder capacitor to an electrically conductive bus as controlled by the control device. In some embodiments, the second adder switch is configured to selectively and electrically connect the second adder capacitor to the electrically conductive bus and selectively electrically connect the second adder capacitor that outputs the shared multiple single-bit MAC outputs to the analog-to-digital converter, simultaneously with the first adder capacitor sharing the multiple single-bit MAC outputs between the first adder capacitor and the second adder capacitor as controlled by the control device. In some embodiments, the analog adder is configured such that outputting a multi-bit MAC output comprises outputting the shared multiple single-bit MAC outputs.

[0009] In some embodiments, the analog adder comprises a buffer electrically connected between the plurality of single-bit MAC switches and the plurality of adder switches.

[0010] Some embodiments may further include a plurality of single-bit MAC switches, wherein a first single-bit MAC switch of the plurality of single-bit MAC switches is configured to selectively electrically connect the first single-bit MAC of the plurality of single-bit MACs and the first adder capacitor as controlled by the control device. In some embodiments, the first adder capacitor is configured to receive a first single-bit MAC output of the plurality of single-bit MAC outputs from the first single-bit MAC in response to the first single-bit MAC switch selectively and electrically connecting the first single-bit MAC and the first adder capacitor, the analog adder comprises a second adder capacitor, the first adder capacitor and the second adder capacitor having the same rated capacitance, and an adder switch configured to selectively and electrically connect the first adder capacitor and the second adder capacitor as controlled by the control device to share the plurality of single-bit MAC outputs between the first adder capacitor and the second adder capacitor, the second adder capacitor being configured to output the shared plurality of single-bit MAC outputs to the analog-to-digital converter. In some embodiments, the analog adder is configured to output a multi-bit MAC output comprises outputting the shared plurality of single-bit MAC outputs.

[0011] Some embodiments include a multi-bit MAC comprising an analog adder having a plurality of adder capacitors including a first adder capacitor and a plurality of single-bit MAC switches including a first single-bit MAC switch configured to selectively and electrically connect a first single-bit MAC of the plurality of single-bit MACs to the first adder capacitor as controlled by a control device, wherein the first adder capacitor is configured to add the first plurality of single-bit MAC outputs by receiving the first plurality of single-bit MAC outputs from the first single-bit MAC and by storing the first plurality of single-bit MAC outputs in response to the first single-bit MAC switch selectively and electrically connecting the first single-bit MAC to the first adder capacitor, and the analog adder is configured to output a multi-bit MAC output based on the addition of the stored first plurality of single-bit MAC outputs.

[0012] In some embodiments, the plurality of adder capacitors comprises a second adder capacitor and a third adder capacitor, wherein a combined rated capacitance of the pair of the second adder capacitor and the third adder capacitor is the same as a rated capacitance of the first adder capacitor, and the analog adder further comprises: a first adder switch configured to selectively and electrically connect the first adder capacitor and the second adder capacitor as controlled by the control device, sharing the first plurality of single-bit MAC outputs between the first adder capacitor and the second adder capacitor; and a second adder switch configured to selectively and electrically connect the second adder capacitor and the third adder capacitor as controlled by the control device, sharing the first plurality of single-bit MAC outputs shared between the second adder capacitor and the third adder capacitor. and a third adder switch configured to selectively electrically connect the third adder capacitor that outputs the weighted shared first plurality of single-bit MAC outputs to the analog-to-digital converter via the electrically conductive bus as controlled by the control device, at the same time that another third adder capacitor of the plurality of adder capacitors that outputs the weighted shared second plurality of single-bit MAC outputs to the analog-to-digital converter via the electrically conductive bus combines the weighted shared first plurality of single-bit MAC outputs and the weighted shared second plurality of single-bit MAC outputs into a weighted average of the shared plurality of single-bit MAC outputs. In some embodiments, the analog adder is configured such that outputting a multi-bit MAC output includes outputting a weighted average of the shared plurality of single-bit MAC outputs.

[0013] In some embodiments, the plurality of adder capacitors further comprises a second adder capacitor, and the analog adder further comprises a plurality of adder switches, including a first adder switch configured to selectively and electrically connect the first adder capacitor and the second adder capacitor as controlled by a control device, sharing the first plurality of single-bit MAC outputs between the first adder capacitor and the second adder capacitor, and a second adder switch configured to selectively and electrically connect the second adder capacitor to another second adder capacitor as controlled by the control device via an electrically conductive bus.

[0014] In some embodiments, the first adder switch is configured to share the first plurality of single-bit MAC outputs between the first adder capacitor and the second adder capacitor, selectively and electrically connecting the first adder capacitor and the second adder capacitor as controlled by the control device comprises dividing the first plurality of single-bit MAC outputs in half for each of the first adder capacitor and the second adder capacitor, the analog adder is configured to clear the first adder capacitor of half of the first plurality of single-bit MAC outputs, and the first adder switch is configured to share the first half of the first plurality of single-bit MAC outputs between the first adder capacitor and the second adder capacitor, selectively and electrically connecting the first adder capacitor and the second adder capacitor as controlled by the control device, dividing the first half of the first plurality of single-bit MAC outputs in half for each of the first adder capacitor and the second adder capacitor, producing a plurality of quarters of the first plurality of single-bit MAC outputs.

[0015] In some embodiments, the plurality of adder switches comprises another first adder switch configured to selectively and electrically connect the another first adder capacitor and the another second adder capacitor as controlled by the control device, while the second adder switch selectively and electrically connects the second adder capacitor and the another second adder capacitor.

[0016] In some embodiments, the plurality of adder switches comprises another first adder switch configured to selectively electrically disconnect the another first adder capacitor and the another second adder capacitor as controlled by the control device, while the second adder switch selectively electrically connects the second adder capacitor and the another second adder capacitor.

[0017] Further embodiments include methods for performing the operations of the device functions summarized above. Further aspects include a multi-bit MAC having means for performing the functions of any of the device functions summarized above.

[0018] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary aspects of various embodiments and, together with the general description given above and the detailed description given below, serve to explain the features of the claims. [Brief explanation of the drawings]

[0019] [Figure 1] FIG. 1 is a component block diagram illustrating an exemplary computing device suitable for implementing various embodiments. [Figure 2] FIG. 1 is a component block diagram illustrating an exemplary memory device configured to implement a multi-bit multiply-accumulate unit ("MAC") using a compute-in-memory (CIM) and / or near-memory-compute (NMC) array suitable for implementing various embodiments. [Figure 3]FIG. 1 is a circuit diagram illustrating an example multi-bit MAC using active integrator-based thermal weights suitable for implementing various embodiments. [Figure 4] FIG. 1 is a circuit block diagram illustrating an example multi-bit MAC using active integrator-based hardwired binary weights suitable for implementing various embodiments. [Figure 5] FIG. 1 is a circuit block diagram illustrating an example multi-bit MAC using a binary capacitive digital-to-analog converter (DAC) as a load, suitable for implementing various embodiments. [Figure 6] FIG. 1 is a circuit diagram illustrating an exemplary multi-bit MAC using a sequential binary accumulator as a load, suitable for implementing various embodiments. [Figure 7] FIG. 1 is a circuit diagram illustrating an exemplary multi-bit MAC using a sequential binary accumulator as a load, suitable for implementing various embodiments. [Figure 8] FIG. 1 is a timing diagram illustrating signal flow for an exemplary multi-bit MAC using a sequential binary accumulator as a load, suitable for implementing various embodiments. [Figure 9] FIG. 1 is a circuit diagram illustrating an exemplary single-bit MAC output adder for multi-bit activation values ​​and multi-bit weight values ​​suitable for implementing various embodiments. [Figure 10] FIG. 1 is a circuit diagram illustrating an exemplary single-bit MAC output adder for multi-bit activation values ​​and multi-bit weight values ​​suitable for implementing various embodiments. [Figure 11] FIG. 1 is a process flow diagram illustrating a method for control of a multi-bit MAC according to an embodiment. [Figure 12] FIG. 1 is a component block diagram illustrating an exemplary mobile computing device suitable for use with various aspects. [Figure 13]FIG. 1 is a component block diagram illustrating an exemplary mobile computing device suitable for use with various aspects. [Figure 14] FIG. 1 is a component block diagram illustrating an example server suitable for use with various aspects. DETAILED DESCRIPTION OF THE INVENTION

[0020] Various aspects will be described in detail with reference to the accompanying drawings. Whenever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. References made to specific examples and implementations are for illustrative purposes only and do not limit the scope of the claims.

[0021] Various aspects may include devices for implementing analog adders for multiply-accumulator ("MAC") arrays in reconfigurable analog-based neural networks, and methods for operating such devices. Some embodiments may include switched capacitive accumulation of analog signals for analog MAC arrays. Some embodiments may include sequential accumulation of weighted activation bits of analog signals for analog MAC arrays. Some embodiments may include flexible analog adders for variable bit-width accumulation for analog MAC arrays. Some embodiments may include different combinations of analog adders using capacitive charge sharing to achieve multi-bit MAC operations from inputs of single-bit MAC operation results.

[0022] The terms "multiply-accumulator" and "MAC" are used interchangeably herein to refer to a component of a computing device configured to implement or mimic the functionality of multiplication and accumulation of any number of bits and combinations of bits. For example, a single-bit MAC may implement or mimic the functionality of single-bit multiplication and accumulation. As another example, a multi-bit MAC may implement or mimic the functionality of multi-bit multiplication and accumulation. As used herein, a MAC may implement or mimic the functionality of multiplication and accumulation, at least in part, in the analog voltage domain.

[0023] The terms "storing," "charging," and "charging" are used interchangeably herein to refer to a voltage being received and held by a capacitor, as an analog value may be "stored" by connecting the capacitor to an input voltage, thereby charging the capacitor. The terms "outputting," "sharing," and "discharging" are used interchangeably herein with respect to the voltage provided by a capacitor through discharging the capacitor by connecting it to an output line. The terms "accumulating," "adding," and "summing" are used interchangeably herein with respect to voltages stored in a capacitor or capacitor array.

[0024] The terms “processor,” “processor core,” “controller,” and “control device,” unless otherwise stated, are used interchangeably herein to refer to any one or all of: a software-configured processor, a hardware-configured processor, a general-purpose processor, a special-purpose processor, a single-core processor, a homogeneous multi-core processor, a heterogeneous multi-core processor, a core of a multi-core processor, a microprocessor, a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), etc., a controller, a microcontroller, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), other programmable logic device, discrete gate logic, transistor logic, etc. A processor may be an integrated circuit, which may be configured such that parts of the integrated circuit reside on a single semiconductor material such as silicon.

[0025] The terms "computing device" and "mobile computing device" are used interchangeably herein to refer to any one or all of mobile phones, smartphones, personal or mobile multimedia players, personal digital assistants (PDAs), laptop computers, tablet computers, convertible laptop / tablets (2-in-1 computers), smartbooks, ultrabooks, netbooks, palmtop computers, wireless email receivers, multimedia Internet-enabled mobile phones, mobile game consoles, wireless game controllers, and similar personal electronic devices that include memory and a programmable processor. The term "computing device" may also refer to stationary computing devices, including personal computers, desktop computers, all-in-one computers, workstations, supercomputers, mainframe computers, embedded computers, servers, home theater computers, and game consoles.

[0026] Compute-in-memory (CIM) and near-memory compute (NMC) systems are deployed in computing devices for fast processing of data for neural networks. CIM or NMC systems use memory devices, such as static random access memory (SRAM), modified to perform certain operations, such as matrix multiplication. The matrices may be activation and weight matrices for neural networks. Some CIM and NMC systems may include memory cells, each of which may store a single-bit value and be configured to multiply the stored single-bit value by an input single-bit value. Some CIM and NMC systems may include memory cells, each of which may store a multi-bit value and be configured to multiply the stored multi-bit value by an input single-bit value. CIM and NMC multiplication of matrices can save energy and time compared to processor-based multiplication by avoiding the operation of loading values ​​into memory for each operation. The results of the multiplication may be output to an analog-to-digital converter and accumulated thereby. The combination of a CIM or NMC system and an analog-to-digital converter may function as an analog MAC.

[0027] Analog MACs have shown promising performance in binary neural networks that use single-bit-wide activation and weight values. However, analog MACs have proven inefficient for multi-bit-wide activation and / or weight values ​​due to computational performance bottlenecks when performing analog computations and a lack of flexibility for computations using variable bit-width inputs. Implementing switched-capacity accumulation for analog MAC arrays can bring greater flexibility and efficiency to deep neural networks.

[0028] The embodiments described herein solve the above problems of analog adders using an analog adder that can be implemented using switched-capacitance accumulation using switched capacitors. In some embodiments, the analog adder can use any number of configurations or combinations of configurations of switched capacitors. Various configurations of switched capacitors can include switched capacitors as integrator capacitors using thermal code-based weights, integrator capacitors using hardwired binary weights, binary digital-to-analog converters (DACs), and sequential binary accumulators. The analog adder can be configured for switched-capacitance accumulation of a voltage representation of the output of an analog MAC array.

[0029] An analog MAC array may be implemented by electrically connecting the outputs of "m" single-bit MACs to "p" capacitors. Each of the single-bit MACs may multiply "n" activation value bits by one of "m" weight value bits, accumulate the results of the multiplication, and output the result of the multiplication and accumulation as a voltage. In some embodiments, at least one of the activation values ​​and weight values ​​may be a multi-bit wide value. The multiplication may be performed such that each bit of the activation value is multiplied by a bit of the weight value. The activation values ​​may be input to the single-bit MACs bit-by-bit sequentially, from least significant bit to most significant bit, and each single-bit MAC may multiply each input bit by a weight value bit. The single-bit MAC may accumulate the results of the multiplications. Each single-bit MAC may output the result of each multiplication and accumulation, referred to herein as a single-bit MAC output. Various embodiments and examples herein are described with respect to single-bit MAC outputs resulting from each single-bit MAC multiplying multiple bits of a multi-bit activation value by a bit of a multi-bit weight value. However, various embodiments and examples may also be implemented using single-bit MAC outputs, where each single-bit MAC results from multiplying a bit of a multi-bit activation value with multiple bits of a multi-bit weight value.

[0030] A multi-bit MAC may be implemented by electrically connecting an analog MAC array of single-bit MACs to any number of analog adders and any combination of analog adders. The single-bit MACs may be selectively electrically connected to capacitors via switches, and the capacitors may function as analog adders by summing the voltage outputs of the single-bit MACs. The switches may include any type of electrically controlled switch, such as a relay and / or a transistor. The switches may control when the single-bit MAC outputs may be electrically connected to the capacitors. For example, the switches may electrically connect various single-bit MACs to the capacitors sequentially. Some switches, when closed, may electrically connect specific combinations of single-bit MACs and capacitors. Some switches, when closed, may output the analog adder result, referred to herein as the multi-bit MAC output, to the ADC. Some switches, when closed, may reset the capacitor. A controller may control the various switches to perform multiplication, addition, and output.

[0031] In some embodiments, the analog summer may be implemented using switched capacitors as integrator capacitors using thermal-based weights. Each single-bit MAC may be electrically connected via a single-bit MAC switch to an analog summer having an operational amplifier and a capacitor electrically connected to a feedback path of the operational amplifier. The single-bit MAC switches may be controlled so that the single-bit MAC outputs may be sequentially output to and received by the operational amplifier and the capacitor. For multi-bit activation values, the single-bit MAC switches may be controlled so that each single-bit MAC output may be sequentially output to and received by the operational amplifier. q The single-bit MAC switch may be controlled so that each of the single-bit MAC outputs can be output twice and received by the operational amplifier, where "q" may be the position of the activation value bit from the least significant bit where q=0 to the most significant bit where q=n-1. Similarly, for multi-bit weight values, the single-bit MAC switch may be controlled so that each of the single-bit MAC outputs can be output twice to the operational amplifier. rThe MAC may be controlled to output and receive multiple times, where "r" may be the position of the weight value bit from the least significant bit where r=0 to the most significant bit where r=m-1. The capacitor may be charged and the gain and output voltage of the operational amplifier may increase. The voltage output of the operational amplifier may be the integral over time of the voltage input to the operational amplifier weighted by the impedance of the capacitor, which may act as a summing operation for the single-bit MAC output.

[0032] In some embodiments, the analog summer may be implemented using switched capacitors as integrator capacitors with hardwired binary weights. In addition to the circuitry described above for the integrator capacitors with thermal-based weights, the integrator capacitors with hardwired binary weights may include a capacitor electrically connected between a single-bit MAC and an operational amplifier with a capacitor electrically connected in the feedback path. The single-bit MAC may be paired with designated capacitors with different rated capacitances to weight the single-bit MAC output.

[0033] In some embodiments, the analog summer may be implemented using switched capacitors as a binary DAC. A single-bit MAC may be electrically connected to "m" capacitors via single-bit MAC switches to the analog summer. The analog summer may include optional buffers and accumulator switches that may electrically connect the capacitors to receive the single-bit MAC outputs. The single-bit MAC switches and accumulator switches may be controlled so that the outputs of the single-bit MACs may be output to and received by designated capacitors. Each capacitor may have a different rated capacitance for weighting the single-bit MAC outputs to generate an average output of all of the capacitors.

[0034] In some embodiments, the analog adder may be configured using switched capacitors to function as a sequential binary accumulator. A single-bit MAC may be electrically connected in parallel to a pair of capacitors via a single-bit MAC switch configured to connect one single-bit MAC to the pair of capacitors. Optionally, a buffer may be electrically connected between the single-bit MAC switch and the pair of capacitors. The pair of capacitors may include a sampler capacitor and an accumulator capacitor with the same rated capacitance. The sampler reset switch may be closed to electrically connect the sampler capacitor to ground to discharge or reset the sampler capacitor. The single-bit MAC switch may be closed to electrically connect the single-bit MAC to the sampler capacitor, charging or charging the sampler capacitor with the single-bit MAC output. The accumulator switch may be closed to charge or charge the accumulator capacitor by sharing the charge or charge of the sampler capacitor. This switch control process may be repeated until all of the multiplications and accumulations of activation value bits and weight value bits are sequentially output to the analog adder.

[0035] In some embodiments, the accumulator capacitor may include multiple capacitors with the same composite nominal capacitance as the sampler capacitor. Each single-bit MAC may be electrically connected to a pair of sampler capacitors and accumulator capacitors. The number of MAC array switches for each of the accumulator capacitors may be configured to electrically connect the accumulator capacitors in parallel to the MAC output. The MAC array switches for each of the accumulator capacitors may be controlled to discharge or output the charge of the accumulator capacitors in parallel to the MAC output. The composite output of the accumulator capacitors in this configuration may be the average of the MAC array outputs with appropriate weighting.

[0036] 1 illustrates a system including a computing device 100 suitable for use with various embodiments. Computing device 100 may include an SoC 102 with a processor 104, memory 106, a communications interface 108, a memory interface 110, a peripheral device interface 120, and a MAC controller 124. Computing device 100 may further include a communications component 112, such as a wired or wireless modem, memory 114, and an antenna 116 for establishing a wireless communications link, and / or peripheral devices 122. Processor 104 may include any of a variety of processing devices, e.g., several processor cores.

[0037] The term "system on a chip" or "SoC" is used herein to generally refer to a set of interconnected electronic circuits, including, but not limited to, a processing device, memory, and a communication interface. The processor 104 may include a variety of different types of processors and / or processor cores, such as a general-purpose processor, a central processing unit (CPU), a digital signal processor (DSP), a graphics processing unit (GPU), an accelerated processing unit (APU), a secure processing unit (SPU), an intellectual property unit (IPU), a subsystem processor of a particular component of a computing device, such as an image processor for a camera subsystem or a display processor for a display, an auxiliary processor, a peripheral device processor, a single-core processor, a multi-core processor, a controller, and / or a microcontroller. The processing device may further embody other hardware and combinations of hardware, such as a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), other programmable logic devices, discrete gate logic, transistor logic, performance monitoring hardware, watchdog hardware, and / or a time reference. An integrated circuit may be configured such that the components of the integrated circuit reside on a single semiconductor material, such as silicon.

[0038] The SoC 102 may include one or more processors 104. The computing device 100 may include two or more SoCs 102, thereby increasing the number of processors 104 and processor cores. The computing device 100 may also include processors 104 that are not associated with the SoC 102. Individual processors 104 may be multi-core processors. The processors 104 may each be configured for a specific purpose, which may be the same or different from the other processors 104 of the computing device 100. One or more of the processors 104 and processor cores of the same or different configurations may be grouped together. A group of processors 104 or processor cores may be referred to as a multi-processor cluster.

[0039] The memory 106 of the SoC 102 may be volatile or nonvolatile memory configured to store data and processor-executable code for access by the processor 104 or other components of the SoC 102. The computing device 100 and / or the SoC 102 may include one or more memories 106, 114 configured for various purposes. The one or more memories 106 may include volatile memory, such as random access memory (RAM) or main memory, or cache memory. These memories 106 may be configured to temporarily hold limited amounts of data received from data sensors or subsystems, data and / or processor-executable code instructions requested from nonvolatile memory and loaded into the memory 106 from nonvolatile memory in anticipation of future access based on various factors, and / or intermediate processing data and / or processor-executable code instructions generated by the processor 104 that are not stored in nonvolatile memory but are temporarily stored for quick future access. In some embodiments, any number of the memories 106 and combinations of the memories 106 may include one-time programmable memory or read-only memory.

[0040] Memory 106 may be configured to at least temporarily store data and processor-executable code that is loaded into memory 106 from another memory device, such as another memory 106 or memory 114, for access by processor 104 or one or more of the other components of SoC 102. The data or processor-executable code loaded into memory 106 may be loaded in response to the execution of a function by processor 104 or other components of SoC 102. Loading data or processor-executable code into memory 106 in response to the execution of a function may result from a memory access request to memory 106 that is unsuccessful or a “miss” due to the requested data or processor-executable code not being present in memory 106. In response to the miss, a memory access request may be made to another memory 106 or memory 114 to load the requested data or processor-executable code into memory 106 from the other memory 106 or memory 114. The loading of data or processor-executable code into memory 106 in response to the execution of a function may result from a memory access request to another memory 106 or memory 114, and the data or processor-executable code may be loaded into memory 106 for later access.

[0041] The memory interface 110 and the memory 114 may cooperate to enable the computing device 100 to store and retrieve data and processor-executable code to and from volatile and / or non-volatile storage media. The memory 114 may be configured much like embodiments of the memory 106, such that the memory 114 may store data or processor-executable code for access by the processor 104 or one or more of the other components of the SoC 102. In some embodiments, the memory 114, being non-volatile, may retain information even after the computing device 100 is powered down. When power is restored and the computing device 100 reboots, the information stored in the memory 114 may be available to the computing device 100. In some embodiments, the memory 114, being volatile, may not retain information after the computing device 100 is powered down. The memory interface 110 may control access to the memory 114 and allow the processor 104 or other components of the SoC 12 to read data from and write data to the memory 114 .

[0042] The MAC controller 124 may be configured to control any number of single-bit MACs 126 and analog summer 128 and combinations thereof, which may be configured as multi-bit MACs 130, and may combine the outputs of the single-bit MACs 126 as described further herein. In some embodiments, the MAC controller 124 may be configured to control any number of switches and combinations of switches to selectively and electrically connect the single-bit MACs 126 to any number of components and combinations of components of the analog summer 128 via control of any number of switches and combinations of switches of the analog summer 128, as described further herein. In some embodiments, the MAC controller 124 may be the processor 104 and / or may be an integral component of the processor 104. In some embodiments, the single-bit MACs 126 and / or analog summer 128 may be integral components of the memory 106.

[0043] Some or all of the components of computing device 100 and / or SoC 102 may be arranged and / or combined differently while still performing the functionality of the various embodiments. Computing device 100 may not be limited to each one of the components, and multiple instances of each component may be included in various configurations of computing device 100.

[0044] 2 illustrates an exemplary memory device (e.g., memory 106 of FIG. 1 ) configured to implement a multi-bit MAC using a compute-in-memory (CIM) and / or near-memory-compute (NMC) array suitable for implementing various embodiments. The multi-bit MAC 200 (e.g., multi-bit MAC 130 of FIG. 1 ) may include any number of single-bit MACs 206 (e.g., single-bit MAC 126 of FIG. 1 ), successive integrators 208 (e.g., analog summers 128 of FIG. 1 ), multi-bit weight processing units 210, and analog-to-digital converters (ADCs) 212. The single-bit MACs 206 may function to convert signals from the digital domain to the analog domain. The successive integrators 208 and multi-bit weight processing units 210 may function using and generating signals in the analog domain. The ADC 212 may function to convert signals from the analog domain to the digital domain. Thus, the multi-bit MAC 200 may function, at least in part, in the analog domain.

[0045] The multi-bit MAC 200 may be configured as a grid of CIM and / or NMC cells in a memory device having components for multiplying bits of the “n”-bit activation values ​​204a, 204b, 204c with bits of the “m”-bit weight values ​​in parallel. The “n”-bit activation values ​​204a, 204b, 204c and bits of the “m”-bit weight values ​​may be represented by digital voltage signals to the CIM and / or NMC cells. Each of the CIM and / or NMC cells may multiply bits of the “n”-bit activation values ​​204a, 204b, 204c with bits of the “m”-bit weight values. The multi-bit MAC 200 may receive an “m”-bit weight value, and each of the CIM and / or NMC cells may store an “m”-bit weight value. For example, each row of the grid of CIM and / or NMC cells may store multiple “m”-bit weight values, and each row may store the same multiple “m”-bit weight values. The multi-bit MAC 200 may receive sequential inputs 202 of “n”-bit activation values ​​204 a, 204 b, 204 c. For example, the activation values ​​204 a, 204 b, 204 c may be input to a row of a grid of CIM and / or NMC cells. Bits of the “n”-bit activation values ​​204 a, 204 b, 204 c may be input sequentially to each of the CIM and / or NMC cells. For example, the “n”-bit activation values ​​204 a, 204 b, 204 c may be input sequentially to each of the CIM and / or NMC cells of a row of a grid of CIM and / or NMC cells, from least significant bit to most significant bit. Every bit of the “n”-bit activation values ​​204 a, 204 b, 204 c input to a CIM and / or NMC cell may be input in parallel to each of the CIM and / or NMC cells. For example, the least significant bits of the "n"-bit activation values ​​204a, 204b, 204c may be input in parallel to the CIM and / or NMC cells of each row of a grid of CIM and / or NMC cells. In some embodiments, the "n"-bit activation values ​​204a, 204b, 204c may be streamed to the CIM and / or NMC cells from an input interface (not shown).In some embodiments, the “n”-bit activation values ​​204a, 204b, 204c and / or the “m”-bit weight values ​​may be provided to the CIM and / or NMC cells from a memory (not shown), such as a register, buffer, cache, random access memory (RAM), etc. The CIM and / or NMC cells may multiply each sequentially received bit of the “n”-bit activation values ​​204a, 204b, 204c by the stored “m”-bit weight value. The output of the multiplication by the cells of the CIM and / or NMC grid may be an analog voltage. Each cell of the CIM and / or NMC grid may be electrically connected to any number and combination of voltage accumulators, such as capacitors (not shown), configured to accumulate the output of the multiplication by the cells of the CIM and / or NMC grid.

[0046] The combination of the cells of the CIM and / or NMC grid and the voltage accumulators electrically connected thereto may be referred to herein as single-bit MAC 206. A single-bit MAC output resulting from the multiplication and accumulation performed by single-bit MAC 206 may be output by single-bit MAC 206 to successive integrator 208. The single-bit MAC output may be represented by an analog voltage signal to successive integrator 208.

[0047] The successive integrators 208 may receive the single-bit MAC outputs of the single-bit MACs 206 and may combine the single-bit MAC outputs through addition or accumulation. Various embodiments include analog adders that can be used to implement the successive integrators 208. In some embodiments, each successive integrator 208 may add the single-bit MAC outputs from a single single-bit MAC 206. The addition of the single-bit MAC outputs by the successive integrators 208 may be performed over time in various manners, as further described herein, for example, with respect to FIGS. 3-10 . The addition of the single-bit MAC outputs by the successive integrators 208 may convert the single-bit MAC outputs, representing the results of the bitwise multiplication and accumulation, into an accumulated single-bit MAC output as an analog voltage signal with an appropriate weight corresponding to the bit position of each bit. The accumulated single-bit MAC output resulting from the addition of the single-bit MAC outputs by the successive integrators 208 may be output by the successive integrators 208 to the multi-bit weight processing unit 210.

[0048] The multi-bit weight processing unit 210 may receive the accumulated single-bit MAC outputs from the successive integrators 208 and may perform a weighted summation of the accumulated single-bit MAC outputs to produce a binary weighted average voltage of the accumulated single-bit MAC outputs, also referred to herein as the multi-bit MAC output. The binary weighted average voltage may be a voltage representing the multiplication of the “n”-bit activation values ​​204a, 204b, 204c and the “m”-bit weight value. The binary weighted average voltage may also be an analog signal. The binary weighted average voltage may be output by the multi-bit weight processing unit 210 to the ADC 212, which may convert the binary weighted average voltage to a digital signal.

[0049] 3-7, 9, and 10 illustrate examples of multi-bit MACs suitable for implementing various embodiments. With reference to FIG. 3 and with respect to FIGS. 1 and 2, multi-bit MACs 300, 400, 500, 600, 700, 900, 1000 (e.g., multi-bit MAC 130 of FIG. 1, multi-bit MAC 200 of FIG. 2) may be an electrical circuit having any number of single-bit MACs 206a, 206b, 206c, 206d (e.g., single-bit MAC 126 of FIG. 1, single-bit MAC 206 of FIG. 2), single-bit MAC switches 304a, 304b, 304c, 304d, electrically conductive buses 306, 316, and / or ADCs 212 (e.g., ADC 212 of FIG. 2).

[0050] Each of the single-bit MACs 206a, 206b, 206c, 206d may store a bit of an 'm'-bit weight value (W1, W2, W3, ..., Wm). Each single-bit MAC 206a, 206b, 206c, 206d may receive a sequential input (e.g., sequential input 202 in FIG. 2) of an 'n'-bit activation value (A1, A2, ..., An) (e.g., the 'n'-bit activation values ​​204a, 204b, 204c in FIG. 2). Each bit of the 'n'-bit activation value may be sequentially input to each of the single-bit MACs 206a, 206b, 206c, 206d. For example, the 'n'-bit activation value may be sequentially input to each of the single-bit MACs 206a, 206b, 206c, 206d from the least significant bit to the most significant bit. Any bit of the 'n'-bit activation value may be input in parallel to each of the single-bit MACs 206a, 206b, 206c, 206d. The bits of the 'n'-bit activation value and the 'm'-bit weight value may be represented by digital voltage signals to the single-bit MACs 206a, 206b, 206c, 206d. In some embodiments, the 'n'-bit activation value may be streamed to the single-bit MACs 206a, 206b, 206c, 206d from an input interface (not shown). In some embodiments, the 'n'-bit activation value and / or the 'm'-bit weight value may be provided to the single-bit MACs 206a, 206b, 206c, 206d from a memory (not shown), such as a register, buffer, cache, RAM, etc. The single-bit MACs 206a, 206b, 206c, 206d may multiply each sequentially received bit of the “n”-bit activation value by a received and / or stored bit of the “m”-bit weight value (A1, A2, ..., An x W1; A1, A2, ..., An x W2; A1, A2, ..., An x W3; ...A1, A2, ..., An x Wm) and accumulate the results of the multiplications.The single-bit MAC outputs resulting from the multiplications and accumulations performed by the single-bit MACs 206a, 206b, 206c, 206d may be output by the single-bit MACs 206a, 206b, 206c, 206d to analog summers of the multi-bit MACs 300, 400, 500, 600, 700, 900, 1000 (e.g., analog summer 128, successive integrator 208, multi-bit weight processing unit 210 of FIGS. 1 and 2), as described further herein. The single-bit MAC outputs may be represented by analog voltage signals to the analog summers of the multi-bit MACs 300, 400, 500, 600, 700, 900, 1000.

[0051] The single-bit MACs 206a, 206b, 206c, 206d may be electrically connected to the analog summer via an electrically conductive bus 306. Any number of single-bit MAC switches 304a, 304b, 304c, 304d may be controlled by a MAC controller (e.g., processor 104, MAC controller 124 of FIG. 1 ) to selectively and electrically connect the single-bit MACs 206a, 206b, 206c, 206d to the analog summer via the electrically conductive bus 306. For example, each single-bit MAC 206a, 206b, 206c, 206d may be selectively and electrically connected to the analog summer via a designated single-bit MAC switch 304a, 304b, 304c, 304d. Selectively electrically connecting the single-bit MACs 206a, 206b, 206c, 206d to the analog summers may output the single-bit MAC outputs generated by the single-bit MACs 206a, 206b, 206c, 206d to the analog summers by controlling the single-bit MAC switches 304a, 304b, 304c, 304d that are designated to close electronic circuits that electrically connect the single-bit MACs 206a, 206b, 206c, 206d to the analog summers.

[0052] The single-bit MAC switches 304a, 304b, 304c, 304d may be controlled such that the single-bit MAC outputs may be sequentially output by the single-bit MACs 206a, 206b, 206c, 206d to and received by the analog summers. For example, the single-bit MAC switches 304a, 304b, 304c, 304d may be controlled to electrically connect the single-bit MACs 206a, 206b, 206c, 206d together after multiplying the least significant bit (A1) of the “n”-bit activation value by the bits (W1, W2, W3, ..., Wm) of the “m”-bit weight value and accumulating the multiplication results. The single-bit MAC switches 304a, 304b, 304c, 304d may further be controlled to electrically connect the single-bit MACs 206a, 206b, 206c, 206d sequentially after multiplication and accumulation of the next most significant bit (A2) of the “n”-bit activation value with the bits (W1, W2, W3, ..., Wm) of the “m”-bit weight value. Such sequential control of the single-bit MAC switches 304a, 304b, 304c, 304d may continue with successive multiplications and accumulations of next most significant bits of the “n”-bit activation value up to the most significant bit (An) of the “n”-bit activation value. The single-bit MAC switches 304a, 304b, 304c, 304d may be further configured to repeatedly electrically connect the single-bit MACs 206a, 206b, 206c, 206d following multiplication and accumulation of bits of the “n”-bit activation value and bits of the “m”-bit weight value before successive multiplication and accumulation of more significant bits of the “n”-bit activation value and bits of the “m”-bit weight value, as further described herein.

[0053] FIGS. 3-7 illustrate exemplary embodiments of multi-bit MACs 300, 400, 500, 600, and 700, each having a single analog adder. The single analog adder example is for ease of illustration and description and is not intended to be limiting. The claims are not limited to a single analog adder, and other embodiments of multi-bit MACs 300, 400, 500, 600, and 700 may each use multiple analog adders. In such embodiments, the outputs of the multiple analog adders of multi-bit MACs 300, 400, 500, 600, and 700 may be combined. Similarly, FIGS. 9 and 10 illustrate exemplary embodiments of multi-bit MACs 900 and 1000, each having a single analog adder. In some embodiments, the single analog adders of multi-bit MACs 900 and 1000 shown in the examples of FIGS. 9 and 10 may each include multiple analog adders.

[0054] FIG. 3 illustrates an exemplary multi-bit MAC using integrator-based thermal weighting suitable for implementing various embodiments. Referring to FIGS. 1-3, the multi-bit MAC 300 may include any number of analog summers. In some embodiments, the analog summers may include any number of operational amplifiers 312 and integrator capacitors 314 (also referred to as summer capacitors). In some embodiments, the analog summers may further include any number of clear switches 308 and / or electrical grounds 310, or combinations thereof. The integrator capacitors 314 of the analog summers may be electrically connected to the feedback paths of the operational amplifiers 312. The integrator capacitors 314 and the inputs of the operational amplifiers 312 may be selectively electrically connected to the single-bit MACs 206a, 206b, 206c, and 206d via an electrically conductive bus 306 and designated single-bit MAC switches 304a, 304b, 304c, and 304d. The input of the integrator capacitor 314 and the operational amplifier 312 may be selectively electrically connected to electrical ground 310 via a clear switch 308. The output of the integrator capacitor 314 and the operational amplifier 312 may be electrically connected to the ADC 212 via an electrically conductive bus 316.

[0055] The analog summer may receive the single-bit MAC outputs from the single-bit MACs 206a, 206b, 206c, 206d at the input of the operational amplifier 312 and at the integrator capacitor 314. The integrator capacitor 314 may store the single-bit MAC outputs and store the sum of the single-bit MAC outputs as additional single-bit MAC outputs are received. For a multi-bit "n" bit activation value, the single-bit MAC switches 304a, 304b, 304c, 304d transmit each of the single-bit MAC outputs to the operational amplifier 312 and the integrator capacitor 314 in two steps. q The single-bit MAC switches 304a, 304b, 304c, 304d may be controlled so that each of the single-bit MAC outputs can be output twice to the operational amplifier 312 and the integrator capacitor 314, where "q" may be the position of the activation value bit from the least significant bit where q=0 to the most significant bit where q=n-1. Similarly, for a multi-bit "m"-bit weight value, the single-bit MAC switches 304a, 304b, 304c, 304d may be controlled so that each of the single-bit MAC outputs can be output twice to the operational amplifier 312 and the integrator capacitor 314. r The MAC may be controlled to output and receive all of the single-bit MAC outputs 2 times, where "r" may be the position of the weight value bit from the least significant bit where r=0 to the most significant bit where r=m-1. In some embodiments, it may take 2 q x 2 r It may take several cycles. The integrator capacitor 314 may charge, and the gain and output voltage of the operational amplifier 312 may increase. The analog voltage output of the operational amplifier 312, also referred to herein as the multi-bit MAC output, may be the integral over time of the voltage input to the operational amplifier 312 weighted by the impedance of the integrator capacitor 314, which may function as a weighted summation operation for the single-bit MAC output. The analog voltage output by the operational amplifier 312 may be output to and received by the ADC 212 via the electrically conductive bus 316 and converted to a digital signal by the ADC 212.

[0056] After completing all multiplications and additions of the "n"-bit activation value and the "m"-bit weight value bits, the multi-bit MAC 300 may be reset or cleared. The clear switch 308 may be controlled by a MAC controller (e.g., the processor 104, the MAC controller 124 of FIG. 1 ) to selectively electrically connect the analog summer, including the input of the operational amplifier 312 and the integrator capacitor 314, to electrical ground 310. Electrically connecting the components of the multi-bit MAC 300 to electrical ground 310 may discharge any remaining voltage within the multi-bit MAC 300 so that the next multiplication and addition of different combinations of the "n"-bit activation value and / or the "m"-bit weight value can be performed by the multi-bit MAC 300.

[0057] The multi-bit MAC300 using integrator-based thermal weighting requires 2-bits to complete all multiplications and additions of the 'n'-bit activation value and the 'm'-bit weight value. n x 2 m It may take several cycles. The multi-bit MAC 300 may be suitable for scenarios where at least one of the 'n'-bit activation values ​​and the 'm'-bit weight values ​​has a low dynamic range. The multi-bit MAC 300 may be particularly useful for use with binary weight multi-bit activations.

[0058] FIG. 4 illustrates an exemplary multi-bit MAC using integrator-based hardwired binary weights suitable for implementing various embodiments. Referring to FIGS. 1 through 4, the multi-bit MAC 400 may include any number of analog summers. In some embodiments, the analog summers may include any number of operational amplifiers 312, integrator capacitors 314 (also referred to as summer capacitors), and designated capacitors 402a, 402b, 402c, 402d. In some embodiments, the analog summers may further include any number of clear switches 308 and / or electrical grounds 310, and combinations thereof. The designated capacitors 402a, 402b, 402c, 402d of the analog summers may be selectively electrically connected to the single-bit MACs 206a, 206b, 206c, 206d via associated single-bit MAC switches 304a, 304b, 304c, 304d. The integrator capacitors 314 of the analog summers may be electrically connected to the feedback paths of the operational amplifiers 312. The inputs of the integrator capacitor 314 and the operational amplifier 312 may be electrically connected to designated capacitors 402a, 402b, 402c, 402d via an electrically conductive bus 306. The designated capacitors 402a, 402b, 402c, 402d, the integrator capacitor 314, and the inputs of the operational amplifier 312 may be selectively electrically connected to electrical ground 310 via a clear switch 308. The outputs of the integrator capacitor 314 and the operational amplifier 312 may be electrically connected to the ADC 212 via an electrically conductive bus 316.

[0059] The analog summer may receive single-bit MAC outputs from the single-bit MACs 206a, 206b, 206c, 206d at designated capacitors 402a, 402b, 402c, 402d, each of which may be associated with and selectively electrically connected to a particular single-bit MAC 206a, 206b, 206c, 206d. A designated capacitor 402a, 402b, 402c, 402d may be associated with a particular single-bit MAC 206a, 206b, 206c, 206d based on a relationship between the rated capacitance (“C”) of the designated capacitor 402a, 402b, 402c, 402d and the bit position of the “n”-bit activation value and / or “m”-bit activation value in the range from least significant bit to most significant bit that is multiplied by the particular single-bit MAC 206a, 206b, 206c, 206d. For a multi-bit “n”-bit activation value, the designated capacitor 402a, 402b, 402c, 402d may be associated with a particular single-bit MAC 206a, 206b, 206c, 206d based on a relationship between the rated capacitance (“C”) of the designated capacitor 402a, 402b, 402c, 402d and the bit position of the “n”-bit activation value and / or the “m”-bit activation value in the range from least significant bit to most significant bit that is multiplied by the particular single-bit MAC 206a, 206b, 206c, 206d. q The capacitors 402a, 402b, 402c, 402d may have a nominal capacitance of C, where "q" may be the position of the activation value bit from the least significant bit where q=0 to the most significant bit where q=n-1. Similarly, for a multi-bit "m"-bit weight value, the designated capacitors 402a, 402b, 402c, 402d may have a nominal capacitance of 2 rEach designated capacitor 402a, 402b, 402c, 402d may have a rated capacitance of C, where "r" may be the position of the weight value bit from the least significant bit, where r=0, to the most significant bit, where r=m-1. In some embodiments, each designated capacitor 402a, 402b, 402c, 402d may be a single capacitor having an appropriate rated capacitance for the particular single-bit MAC 206a, 206b, 206c, 206d associated with it. In some embodiments, each designated capacitor 402a, 402b, 402c, 402d may be multiple capacitors electrically connected in series and / or parallel that collectively have an appropriate rated capacitance for the particular single-bit MAC 206a, 206b, 206c, 206d associated with it. The rated capacitance of a designated capacitor 402a, 402b, 402c, 402d may serve as a hardwired binary weight for the single-bit MAC output received by the designated capacitor 402a, 402b, 402c, 402d from the associated particular single-bit MAC 206a, 206b, 206c, 206d.

[0060] A designated capacitor 402a, 402b, 402c, 402d may receive and store a single-bit MAC output from an associated single-bit MAC 206a, 206b, 206c, 206d when selectively electrically connected to the associated single-bit MAC 206a, 206b, 206c, 206d via an associated single-bit MAC switch 304a, 304b, 304c, 304d. A designated capacitor 402a, 402b, 402c, 402d may charge by receiving the single-bit MAC output when selectively electrically connected to the associated single-bit MAC 206a, 206b, 206c, 206d. When a designated capacitor 402a, 402b, 402c, 402d is selectively electrically disconnected from its associated single-bit MAC 206a, 206b, 206c, 206d, it may output or discharge a single-bit MAC output that is weighted relative to the rated capacitance of the designated capacitor 402a, 402b, 402c, 402d.

[0061] The weighted single-bit MAC outputs may be received at the input of the operational amplifier 312 and at the integrator capacitor 314. The integrator capacitor 314 may store the single-bit MAC outputs, e.g., in the form of a weighted single-bit MAC output, and may store a sum of the single-bit MAC outputs as additional single-bit MAC outputs are received, e.g., in the form of a sum of weighted single-bit MAC outputs as additional weighted single-bit MAC outputs are received. The integrator capacitor 314 may charge, and the gain and output voltage of the operational amplifier 312 may increase. The analog voltage output of the operational amplifier 312, also referred to herein as the multi-bit MAC output, may be the integral over time of the voltage input to the operational amplifier 312 weighted by the impedance of the integrator capacitor 314, which may function as a weighted summation operation for the single-bit MAC outputs. The analog voltage output by the operational amplifier 312 may be output to and received by the ADC 212 via the electrically conductive bus 316 and converted to a digital signal by the ADC 212.

[0062] After completing all multiplications and additions of the “n”-bit activation values ​​and “m”-bit weight value bits, the multi-bit MAC 400 may be reset or cleared. The clear switches 308 may be controlled to selectively electrically connect the analog summer, including designated capacitors 402a, 402b, 402c, 402d, the inputs of the operational amplifier 312, and the integrator capacitor 314, to electrical ground 310. Electrically connecting the components of the multi-bit MAC 400 to electrical ground 310 may discharge any remaining voltage within the multi-bit MAC 400 so that the next multiplication and addition of different combinations of the “n”-bit activation values ​​and / or “m”-bit weight values ​​can be performed by the multi-bit MAC 400.

[0063] The multi-bit MAC 400 using integrator-based hardwired binary weights may be configured similarly as the multi-bit MAC using an integrator-based thermal weighting function (e.g., the multi-bit MAC 300 of FIG. 3 ), both including an adder with an operational amplifier 312 and an integrator capacitor 314 electrically connected to the feedback path of the operational amplifier 312. However, the multi-bit MAC using an integrator-based thermal weighting function relies on the operational amplifier 312 and the integrator capacitor 314 to weight the received single-bit MAC output. Alternatively, the multi-bit MAC 400 uses the rated capacitances of the designated hardwired capacitors 402 a, 402 b, 402 c, and 402 d to weight the single-bit MAC output before the operational amplifier 312 and the integrator capacitor 314 receive the weighted single-bit MAC output. Thus, the multi-bit MAC 400 may perform the accumulation of the single-bit MAC output more quickly than the multi-bit MAC using an integrator-based thermal weighting function. For example, rather than having to wait for the integrator capacitor 314 to charge from sequentially received single-bit MAC outputs, the multi-bit MAC 400 may charge designated capacitors 402a, 402b, 402c, 402d in parallel and output weighted single-bit MAC outputs to the operational amplifier 312 and the integrator capacitor 314.

[0064] FIG. 5 shows an exemplary multi-bit MAC using a binary DAC as a load, suitable for implementing various embodiments. Referring to FIGS. 1 through 5, the multi-bit MAC 500 may include any number of analog summers. In some embodiments, the analog summers may include any number of summer switches 504a, 504b, 504c and summer capacitors 506a, 506b, 506c. In some embodiments, the analog summers may further include any number of optional buffers 502. In some embodiments, the analog summers may further include any number of clear switches 308, electrical ground 310, and / or designated electrical grounds 508, and combinations thereof. The summer capacitors 506a, 506b, 506c of the analog summers may be selectively electrically connected to the single-bit MACs 206a, 206b, 206c, 206d via the associated single-bit MAC switches 304a, 304b, 304c, 304d, the associated summer switches 504a, 504b, 504c, and the electrically conductive bus 306. The summer capacitors 506a, 506b, 506c may be electrically connected between the associated summer switches 504a, 504b, 504c and electrical ground 508. The summer capacitors 506a, 506b, 506c may be selectively electrically connected to electrical ground 310 via the summer switches 504a, 504b, 504c and the clear switches 308. The summer capacitors 506a, 506b, 506c may be electrically connected to the ADC 212 via the electrically conductive bus 316. The summer switches 504a, 504b, 504c may be controlled by a MAC controller (e.g., the processor 104, the MAC controller 124 of FIG. 1) to selectively electrically connect the summer capacitors 506a, 506b, 506c to the electrically conductive buses 306, 316.

[0065] The analog summer may receive single-bit MAC outputs from single-bit MACs 206a, 206b, 206c, 206d at summer capacitors 506a, 506b, 506c. Each summer capacitor 506a, 506b, 506c may be selectively, sequentially, and electrically connected to a single-bit MAC 206a, 206b, 206c, 206d. The summer capacitors 506a, 506b, 506c may have different sequential nominal capacitances ("C") that may correspond to the number of bits in an "n"-bit activation value and / or an "m"-bit weight value. For a multi-bit "n"-bit activation value, the summer capacitors 506a, 506b, 506c may have different sequential nominal capacitances ("C") that may correspond to the number of bits in an "m"-bit weight value. q The summator capacitors 506a, 506b, and 506c may have a nominal capacitance of C, where "q" may be a value from 0 to n-1. Similarly, for a multi-bit "m"-bit weight value, the summator capacitors 506a, 506b, and 506c may have a nominal capacitance of 2 r The adder capacitors 506a, 506b, 506c may have a nominal capacitance of C, where “r” may be a value from 0 to m−1. In some embodiments, each adder capacitor 506a, 506b, 506c may be a single capacitor having a nominal capacitance appropriate for the adder capacitor's 506a, 506b, 506c's position in the nominal capacitance sequence. In some embodiments, each adder capacitor 506a, 506c, 506c may be multiple capacitors electrically connected in series and / or parallel that collectively have a nominal capacitance appropriate for the adder capacitor's 506a, 506b, 506c's position in the nominal capacitance sequence. The nominal capacitances of the adder capacitors 506a, 506b, 506c may function as hardwired binary weights for the single-bit MAC outputs received by the adder capacitors 506a, 506b, 506c from the single-bit MACs 206a, 206b, 206c, 206d.

[0066] The adder capacitors 506a, 506b, 506c may receive and store single-bit MAC outputs from the single-bit MACs 206a, 206b, 206c, 206d when selectively electrically connected to the single-bit MACs 206a, 206b, 206c, 206d via the associated single-bit MAC switches 304a, 304b, 304c, 304d and the associated adder switches 504a, 504b, 504c. The single-bit MAC switches 304a, 304b, 304c, 304d and the adder switches 504a, 504b, 504c may be controlled to output the single-bit MAC outputs from the single-bit MACs 206a, 206b, 206c, 206d such that each adder capacitor 506a, 506b, 506c receives the single-bit MAC output. For example, the single-bit MAC switches 304a, 304b, 304c, 304d may be controlled to close a circuit electrically connecting the single-bit MAC 206a, 206b, 206c, 206d to the analog summer to output the single-bit MAC output to the analog summer. The adder switches 504a, 504b, 504c associated with each adder capacitor 506a, 506b, 506c may be controlled to sequentially charge each of the adder capacitors 506a, 506b, 506c with the single-bit MAC output by closing a circuit electrically connecting the single-bit MAC 206a, 206b, 206c, 206d and the associated adder capacitor 506a, 506b, 506c. In other words, each adder capacitor 506 a, 506 b, 506 c may receive a single-bit MAC output from each of the single-bit MACs 206 a, 206 b, 206 c, 206 d. In some embodiments, the adder switches 504 a, 504 b, 504 c may be controlled in a manner such that the single-bit MAC outputs are charged to the adder capacitors 506 a, 506 b, 506 c in an order based on the rated capacitance of the adder capacitors 506 a, 506 b, 506 c. The adder capacitors 506 a, 506 b, 506 c may charge by receiving the single-bit MAC outputs when selectively electrically connected to the single-bit MACs 206 a, 206 b, 206 c, 206 d.

[0067] When the adder capacitors 506a, 506b, 506c are selectively and electrically disconnected from the single-bit MACs 206a, 206b, 206c, 206d by the single-bit MAC switches 304a, 304b, 304c, 304d, and when selectively and electrically connected to the ADC 212 by the adder switches 504a, 504b, 504c, the adder capacitors 506a, 506b, 506c can output or discharge a single-bit MAC output that is weighted with respect to the rated capacitance of the adder capacitors 506a, 506b, 506c. The adder capacitors 506a, 506b, 506c may output or discharge a weighted single-bit MAC output when selectively and electrically disconnected from all of the associated single-bit MACs 206a, 206b, 206c, 206d by the single-bit MAC switches 304a, 304b, 304c, 304d, and when selectively and electrically connected to the ADC 212 by all of the adder switches 504a, 504b, 504c.

[0068] The weighted single-bit MAC outputs may be output as analog voltages to the electrical conductive bus 316 and to the ADC 212. The weighted single-bit MAC outputs may be combined by summing the analog voltages on the electrical conductive bus 316, also referred to herein as a multi-bit MAC output, to provide a weighted average of the analog voltages that are converted to a digital signal by the ADC 212.

[0069] After completing all multiplications and additions of the “n”-bit activation value and the “m”-bit weight value bits, the multi-bit MAC 500 may be reset or cleared. The clear switches 308 may be controlled to selectively electrically connect the analog summer, including the summer capacitors 506 a, 506 b, and 506 c, to electrical ground 310. The summer switches 504 a, 504 b, and 504 c may also be controlled to electrically connect the summer capacitors 506 a, 506 b, and 506 c to electrical ground 310 via the clear switches 308. Electrically connecting the components of the multi-bit MAC 500 to electrical ground 310 may discharge any remaining voltage within the multi-bit MAC 500 so that the next multiplication and addition of different combinations of the “n”-bit activation value and / or the “m”-bit weight value can be performed by the multi-bit MAC 500.

[0070] In some embodiments, the buffer 502 may be electrically connected between the single-bit MACs 206a, 206b, 206c, 206d and the summer capacitors 506a, 506b, 506c. The buffer 502 may be an analog buffer configured to reduce charging effects of the voltage and / or current of the summer capacitors 506a, 506b, 506c on the single-bit MACs 206a, 206b, 206c, 206d. In some embodiments, the buffer 502 may reduce charging effects compared to the charging effects without the buffer 502. For example, the buffer 502 may reduce voltage drops caused by mismatched relative impedances of the summer capacitors 506a, 506b, 506c and the single-bit MACs 206a, 206b, 206c, 206d. The buffer 502 may also be configured to improve the linearity of the single-bit MAC output from the single-bit MAC 206 a, 206 b, 206 c, 206 d to the summer capacitors 506 a, 506 b, 506 c. In some embodiments, the buffer 502 may improve the linearity compared to the linearity without the buffer 502. For example, the buffer 502 may improve the linearity of the single-bit MAC output by linearly amplifying the single-bit MAC output when losses occur in the transmission of the single-bit MAC output between the single-bit MAC 206 a, 206 b, 206 c, 206 d and the summer capacitors 506 a, 506 b, 506 c.

[0071] FIG. 6 illustrates an exemplary multi-bit MAC using a sequential binary accumulator as a load, suitable for implementing various embodiments. Referring to FIGS. 1 through 6, the multi-bit MAC 600 may include any number of analog adders. In some embodiments, the analog adders may include any number of adder switches 604a, 604b and adder capacitors 606a, 606b. In some embodiments, the analog adders may further include any number of optional buffers 502. In some embodiments, the analog adders may further include any number of clear switches 308, electrical ground 310, and / or designated electrical ground 508, and combinations thereof. The adder capacitors 606a, 606b of the analog adders may be selectively electrically connected to the single-bit MACs 206a, 206b, 206c, 206d via the associated single-bit MAC switches 304a, 304b, 304c, 304d, the associated adder switches 604a, 604b, and the electrically conductive bus 306. The summer capacitors 606a, 606b may be selectively electrically connected to one another via the summer switches 604a, 604b and the electrically conductive bus 316. The summer capacitors 606a, 606b may be electrically connected between the associated summer switch 604a, 604b and electrical ground 508. The summer capacitors 606a, 606b may be selectively electrically connected to electrical ground 310 via the summer switches 604a, 604b and the clear switch 308. The summer capacitors 606a, 606b may be electrically connected to the ADC 212 via the electrically conductive bus 316. The summer switches 604a, 604b may be controlled by a MAC controller (e.g., the processor 104, the MAC controller 124 in FIG. 1 ) to selectively electrically connect the summer capacitors 606a, 606b to the electrically conductive buses 306, 316.

[0072] The analog summer may receive the single-bit MAC outputs from the single-bit MACs 206a, 206b, 206c, and 206d at summer capacitors 606a, 606b. The summer capacitors 606a, 606b may include a sampler capacitor 606a and an accumulator capacitor 606b. The sampler capacitor 606a may be selectively electrically connected to the single-bit MACs 206a, 206b, 206c, and 206d. The accumulator capacitor 606b may be selectively electrically connected to the sampler capacitor 606a. The summer capacitors 606a, 606b may have the same rated capacitance (“C”). In some embodiments, each summer capacitor 606a, 606b may be a single capacitor having that rated capacitance. In some embodiments, each summer capacitor 606a, 606b may be multiple capacitors electrically connected in series and / or parallel that collectively have that rated capacitance. The nominal capacitances of the adder capacitors 606a, 606b may act as hardwired binary weights for the single-bit MAC outputs received by the adder capacitors 606a, 606b from the single-bit MACs 206a, 206b, 206c, 206d.

[0073] The sampler capacitor 606a may receive and store the single-bit MAC outputs from the single-bit MACs 206a, 206b, 206c, 206d when selectively electrically connected to the single-bit MACs 206a, 206b, 206c, 206d via the associated single-bit MAC switches 304a, 304b, 304c, 304d and associated adder switches 604a, 604b, i.e., the sampler switch 604a. The single-bit MAC switches 304a, 304b, 304c, 304d and the sampler switch 604a may be controlled to output the single-bit MAC outputs from the single-bit MACs 206a, 206b, 206c, 206d such that the sampler capacitor 606a receives the single-bit MAC outputs in a particular order. In some embodiments, the order may be sequential, starting with the multiplication and accumulation of the least significant bit of the “n”-bit activation value and the “m”-bit weight value, and ending with the multiplication and accumulation of the most significant bit of the “n”-bit activation value and the “m”-bit weight value. For example, the single-bit MAC switches 304a, 304b, 304c, 304d may be controlled to sequentially close circuits electrically connecting the single-bit MACs 206a, 206b, 206c, 206d to the analog summers to output the single-bit MAC outputs to the analog summers. The sampler switch 604a associated with the sampler capacitor 606a may be controlled to sequentially charge the single-bit MAC output to the sampler capacitor 606a by closing the circuit electrically connecting the single-bit MACs 206a, 206b, 206c, 206d to the sampler capacitor 606a. In other words, the sampler capacitor 606a may receive a single-bit MAC output from each of the single-bit MACs 206a, 206b, 206c, 206d. In some embodiments, the sampler switch 604a may be controlled in a manner such that the single-bit MAC outputs are charged to the sampler capacitor 606a in an order based on the bit positions of the bits of the 'n'-bit activation value and the 'm'-bit weight value that are multiplied to produce the single-bit MAC output.When selectively and electrically connected to the single-bit MACs 206a, 206b, 206c, and 206d, the sampler capacitor 606a may charge by receiving the single-bit MAC outputs. The sampler capacitor 606a may store a sample of the single-bit MAC output, which may include a combination of the received single-bit MAC outputs modified by sharing the sample of the single-bit MAC output with the accumulator capacitor 606b. The sample of the single-bit MAC output is referred to herein as a single-bit MAC output sample. The sampler capacitor 606a may store and output a single-bit MAC output sample in response to receiving each single-bit MAC output.

[0074] The accumulator capacitor 606b may receive and store the single-bit MAC output sample from the sampler capacitor 606a when selectively electrically connected to the sampler capacitor 606a via the adder switches 604a, 604b, i.e., the sampler switch 604a and the accumulator switch 604b. The sampler capacitor 606a may share or output the single-bit MAC output sample to the accumulator capacitor 606b when the sampler capacitor 606a is selectively disconnected from the single-bit MACs 206a, 206b, 206c, 206d and selectively connected to the accumulator capacitor 606b by the adder switches 604a, 604b. The accumulator capacitor 606b may receive and store the single-bit MAC output sample. For example, the single-bit MAC switches 304a, 304b, 304c, 304d may be controlled to selectively disconnect the sampler capacitor 606a from the single-bit MACs 206a, 206b, 206c, 206d. The sampler switch 604a may be controlled to electrically connect the sampler capacitor 606a to the electrically conductive bus 316, and the accumulator switch 604b may be controlled to electrically connect the accumulator capacitor 606b to the electrically conductive bus 316. The sampler capacitor 606a may output a single-bit MAC output sample to the accumulator capacitor 606b. After receiving the single-bit MAC output, the single-bit MAC output sample may be shared by the sampler capacitor 606a and the accumulator capacitor 606b (as further described herein in connection with FIG. 8). The process of receiving each single-bit MAC output output by sampler capacitor 606a, outputting a single-bit MAC output sample by sampler capacitor 606a, and receiving a single-bit MAC output sample by accumulator capacitor 606b may continue for every single multiplication and addition of the bits of the 'n'-bit activation value and the 'm'-bit weight value.

[0075] After completing the multiplication and addition of the bits of the “n”-bit activation value and the “m”-bit weight value, the sampler capacitor 606a may be reset or cleared. The clear switch 308 may be controlled to selectively electrically connect the sampler capacitor 606a to electrical ground 310. The sampler switch 604a may be controlled to selectively electrically connect the sampler capacitor 606a to electrical ground 310. The accumulator switch 604b may be controlled to selectively electrically disconnect the accumulator capacitor 606b from electrical ground 310. Electrically connecting the components of the multi-bit MAC 600 to electrical ground 310 may discharge any remaining voltage within the components so that the next multiplication and addition of different combinations of the “n”-bit activation value and / or the “m”-bit weight value can be performed by the multi-bit MAC 600.

[0076] The accumulator capacitor 606b can output or discharge a single-bit MAC output sample when selectively and electrically disconnected from the single-bit MACs 206a, 206b, 206c, and 206d by the single-bit MAC switches 304a, 304b, 304c, and 304d, when selectively and electrically disconnected from the sampler capacitor 606a by the sampler switch 604a, and when selectively and electrically connected to the ADC 212 by the accumulator switch 604b. The output of the accumulator capacitor 606b is also referred to herein as a multi-bit MAC output. The single-bit MAC output sample can be output as an analog voltage to the electrically conductive bus 316 and the ADC 212. The analog voltage on the electrically conductive bus 316 can be converted to a digital signal by the ADC 212.

[0077] After completing all multiplications and additions of the “n”-bit activation value and the “m”-bit weight value bits, the multi-bit MAC 600 may be reset or cleared. The clear switch 308 may be controlled to selectively electrically connect the analog summer, including the summer capacitors 606 a, 606 b, to electrical ground 310. The summer switches 604 a, 604 b may also be controlled to electrically connect the summer capacitors 606 a, 606 b to electrical ground 310 via the clear switch 308. Electrically connecting the components of the multi-bit MAC 600 to electrical ground 310 may discharge any remaining voltage within the multi-bit MAC 600 so that the next multiplication and addition of different combinations of the “n”-bit activation value and / or the “m”-bit weight value can be performed by the multi-bit MAC 600.

[0078] In some embodiments, the buffer 502 may be electrically connected between the single-bit MACs 206a, 206b, 206c, 206d and the summer capacitors 606a, 606b. The buffer 502 may be an analog buffer configured to reduce charging effects of the voltage and / or current of the summer capacitors 606a, 606b on the single-bit MACs 206a, 206b, 206c, 206d. In some embodiments, the buffer 502 may reduce charging effects compared to the charging effects without the buffer 502. For example, the buffer 502 may reduce voltage drops caused by mismatched relative impedances of the summer capacitors 606a, 606b and the single-bit MACs 206a, 206b, 206c, 206d. The buffer 502 may also be configured to improve the linearity of the single-bit MAC output from the single-bit MACs 206a, 206b, 206c, 206d to the summer capacitors 606a, 606b. In some embodiments, the buffer 502 may improve linearity compared to the linearity without the buffer 502. For example, the buffer 502 may improve the linearity of the single-bit MAC output by linearly amplifying the single-bit MAC output when loss occurs in the transmission of the single-bit MAC output between the single-bit MAC 206a, 206b, 206c, 206d and the summer capacitor 606a, 606b. The buffer 502 may be omitted in implementations for large “n”-bit activation values ​​and / or “m”-bit weight values, in which the single-bit MAC outputs of the single-bit MAC 206a, 206b, 206c, 206d are large because sharing the single-bit MAC output may not cause large loss between the single-bit MAC 206a, 206b, 206c, 206d and the sampler capacitor 606a. The loss between the single-bit MAC 206a, 206b, 206c, 206d and the sampler capacitor 606a may be a linear loss and may not introduce non-linearity.

[0079] FIG. 7 illustrates an exemplary multi-bit MAC using a sequential binary accumulator as a load, suitable for implementing various embodiments. Referring to FIGS. 1 through 7, the multi-bit MAC 700 may include any number of analog adders. In some embodiments, the analog adder may include any number of adder switches 702 and adder capacitors 606 a, 606 b. In some embodiments, the analog adder may further include any number of clear switches 308 a, 308 b, electrical grounds 310 a, 310 b, and / or designated electrical grounds 508, and combinations thereof. The adder capacitors 606 a, 606 b of the analog adders may be selectively electrically connected to the single-bit MACs 206 a, 206 b, 206 c, 206 d via the associated single-bit MAC switches 304 a, 304 b, 304 c, 304 d, the associated adder switches 702, and the electrically conductive bus 306. The summer capacitors 606a, 606b may be selectively electrically connected to one another via a summer switch 702 and the electrically conductive bus 316. The summer capacitors 606a, 606b may be electrically connected between the electrically conductive bus 316 and electrical ground 508. The summer capacitors 606a, 606b may be selectively electrically connected to electrical grounds 310a, 310b via clear switches 308a, 308b. The summer capacitors 606a, 606b may be electrically connected to the ADC 212 via the electrically conductive bus 316. The summer switch 702 may be controlled by a MAC controller (e.g., processor 104, MAC controller 124 in FIG. 1 ) to selectively electrically connect the summer capacitors 606a, 606b to one another.

[0080] The analog summer may receive the single-bit MAC outputs from the single-bit MACs 206a, 206b, 206c, and 206d at summer capacitors 606a, 606b. The summer capacitors 606a, 606b may include a sampler capacitor 606a and an accumulator capacitor 606b. The sampler capacitor 606a may be selectively electrically connected to the single-bit MACs 206a, 206b, 206c, and 206d. The accumulator capacitor 606b may be selectively electrically connected to the sampler capacitor 606a. The summer capacitors 606a, 606b may have the same rated capacitance (“C”). In some embodiments, each summer capacitor 606a, 606b may be a single capacitor having that rated capacitance. In some embodiments, each summer capacitor 606a, 606b may be multiple capacitors electrically connected in series and / or parallel that collectively have that rated capacitance. The nominal capacitances of the adder capacitors 606a, 606b may act as hardwired binary weights for the single-bit MAC outputs received by the adder capacitors 606a, 606b from the single-bit MACs 206a, 206b, 206c, 206d.

[0081] The sampler capacitor 606a may receive and store single-bit MAC outputs from the single-bit MACs 206a, 206b, 206c, 206d when selectively electrically connected to the single-bit MACs 206a, 206b, 206c, 206d via the associated single-bit MAC switches 304a, 304b, 304c, 304d. The single-bit MAC switches 304a, 304b, 304c, 304d may be controlled to output the single-bit MAC outputs from the single-bit MACs 206a, 206b, 206c, 206d such that the sampler capacitor 606a receives the single-bit MAC outputs in a particular order. In some embodiments, the order may be sequential, starting with the multiplication and accumulation of the least significant bit of the 'n'-bit activation value and the 'm'-bit weight value to the multiplication and accumulation of the most significant bit of the 'n'-bit activation value and the 'm'-bit weight value. For example, the single-bit MAC switches 304a, 304b, 304c, and 304d may be controlled to sequentially close circuits electrically connecting the single-bit MACs 206a, 206b, 206c, and 206d to the analog summers to output the single-bit MAC outputs to the analog summers. The sampler capacitor 606a may be sequentially charged with the single-bit MAC outputs by closing circuits electrically connecting the single-bit MACs 206a, 206b, 206c, and 206d and the sampler capacitor 606a. In other words, the sampler capacitor 606a may receive the single-bit MAC outputs from each of the single-bit MACs 206a, 206b, 206c, and 206d. In some embodiments, the single-bit MAC switches 304a, 304b, 304c, 304d may be controlled in a manner such that the single-bit MAC outputs are charged to the sampler capacitor 606a in an order based on the bit positions of the bits of the 'n'-bit activation value and the 'm'-bit weight value that are multiplied and accumulated to produce the single-bit MAC output. The sampler capacitor 606a may charge by receiving the single-bit MAC outputs when selectively and electrically connected to the single-bit MACs 206a, 206b, 206c, 206d.Sampler capacitor 606a may store a single-bit MAC output sample, which may include a combination of the received single-bit MAC outputs modified by sharing the single-bit MAC output sample with accumulator capacitor 606b. The single-bit MAC output sample is referred to herein as a single-bit MAC output sample. Sampler capacitor 606a may store and output a single-bit MAC output sample in response to receiving each single-bit MAC output.

[0082] The accumulator capacitor 606b may receive and store the single-bit MAC output sample from the sampler capacitor 606a when selectively electrically connected to the sampler capacitor 606a via the adder switch 702. The sampler capacitor 606a may discharge or output the single-bit MAC output sample to the accumulator capacitor 606b when the sampler capacitor 606a is selectively disconnected from the single-bit MACs 206a, 206b, 206c, 206d and selectively connected to the accumulator capacitor 606b by the adder switch 702. The accumulator capacitor 606b may receive and store the single-bit MAC output sample. For example, the single-bit MAC switches 304a, 304b, 304c, 304d may be controlled to selectively disconnect the sampler capacitor 606a from the single-bit MACs 206a, 206b, 206c, 206d. The adder switch 702 may be controlled to electrically connect the sampler capacitor 606a to the accumulator capacitor 606b via the electrically conductive bus 316. The sampler capacitor 606a may output a single-bit MAC output sample to the accumulator capacitor 606b. After receiving the single-bit MAC output, the single-bit MAC output sample may be shared by the sampler capacitor 606a and the accumulator capacitor 606b, as described further herein in connection with FIG. 8. The process of receiving each single-bit MAC output output by the sampler capacitor 606a, outputting a single-bit MAC output sample by the sampler capacitor 606a, and receiving the single-bit MAC output sample by the accumulator capacitor 606b may continue for all respective multiplications and additions of the bits of the 'n'-bit activation value and the 'm'-bit weight value.

[0083] After completing the multiplication and addition of the bits of the “n”-bit activation value and the “m”-bit weight value, the sampler capacitor 606a may be reset or cleared. The clear switch 308a may be controlled to selectively electrically connect the sampler capacitor 606a to electrical ground 310a. The clear switch 308b and the adder switch 702 may be controlled to selectively electrically disconnect the accumulator capacitor 606b from electrical ground 310a, 310b. Electrically connecting the components of the multi-bit MAC 700 to electrical ground 310a may discharge any remaining voltage within the components so that the next multiplication and addition of different combinations of the “n”-bit activation value and / or the “m”-bit weight value can be performed by the multi-bit MAC 700.

[0084] The accumulator capacitor 606b may output or discharge a single-bit MAC output sample when selectively and electrically disconnected from the single-bit MACs 206a, 206b, 206c, 206d and the sampler capacitor 606a by the adder switch 702, and when selectively and electrically connected to the ADC 212 by the electrically conductive bus 316. The output of the accumulator capacitor 606b is also referred to herein as a multi-bit MAC output. The single-bit MAC output sample may be output as an analog voltage to the electrically conductive bus 316 and the ADC 212. The analog voltage on the electrically conductive bus 316 may be converted to a digital signal by the ADC 212.

[0085] After completing all multiplications and additions of the “n”-bit activation value and the “m”-bit weight value bits, the multi-bit MAC 700 may be reset or cleared. The clear switches 308a, 308b may be controlled to selectively electrically connect the analog summers, including the summer capacitors 606a, 606b, to electrical ground 310a, 310b. Electrically connecting the components of the multi-bit MAC 700 to electrical ground 310a, 310b may discharge any remaining voltage within the multi-bit MAC 700 so that the next multiplication and addition of different combinations of the “n”-bit activation value and / or the “m”-bit weight value can be performed by the multi-bit MAC 700.

[0086] 8 shows an example signal flow for an example multi-bit MAC using sequential binary accumulators, suitable for implementing various embodiments. Referring to FIGS. 1-8, a signal timing diagram 800 for a multi-bit MAC using sequential binary accumulators (e.g., multi-bit MAC 700 of FIG. 7) may include an accumulator clear switch control signal ("accumulator clear switch"), a sampler clear switch control signal ("sampler clear switch"), and an adder switch control signal ("adder switch"), multiple single-bit MAC output signals (e.g., "single-bit MAC1", "single-bit MAC2", ... "single-bit MACb"), as well as a sampler capacitor voltage measurement ("sampler capacitor voltage") and an accumulator capacitor voltage measurement ("accumulator capacitor voltage"). The accumulator clear switch control signal, the sampler clear switch control signal, and the adder switch control signal may be control signals issued by a control device (not shown) for controlling the accumulator clear switch (e.g., clear switch 308b in FIG. 7), the sampler clear switch (e.g., clear switch 308a in FIG. 7), and the adder switch (e.g., adder switch 702 in FIG. 7). The single-bit MAC output signal may be a single-bit MAC output output by a single-bit MAC (e.g., single-bit MAC 206a, 206b, 206c, 206d in FIG. 7). The sampler capacitor voltage measurement may be the voltage of a sampler capacitor (e.g., sampler capacitor 606a in FIG. 7), and the accumulator capacitor voltage measurement may be the voltage of an accumulator capacitor (e.g., accumulator capacitor 606b in FIG. 7). The example shown in FIG. 8 may relate to the multi-bit MAC 700 described herein with reference to FIG. 7. However, the example shown in FIG. 8 is not intended to limit the scope of the claims or the specification, as it is clear that similar control signals, single-bit MAC outputs, and capacitor voltage measurements can be implemented for the various multi-bit MACs 200, 300, 400, 500, 600 described herein with reference to FIGS. 2 through 6.

[0087] In signal timing diagram 800, at time T0, the accumulator clear switch control signal and the sampler clear switch control signal may be asserted by a control device. The accumulator clear switch control signal and the sampler clear switch control signal may be asserted to selectively electrically connect the sampler capacitor and the accumulator capacitor to electrical ground (e.g., electrical ground 310a, 310b in FIG. 7) via clear switches such as the sampler clear switch and the accumulator clear switch. Because the sampler capacitor and the accumulator capacitor may be electrically connected to electrical ground, the sampler capacitor voltage measurement and the accumulator capacitor voltage measurement may exhibit little or no voltage. As described herein, the single-bit MAC switch (e.g., single-bit MAC switch 304a, 304b, 304c, 304d in FIG. 7) may be controlled to selectively electrically disconnect the single-bit MAC from the sampler capacitor and the accumulator capacitor. Thus, at time T0, the single-bit MAC output signal may not have any value. The adder switch control signal may be deasserted by the control device at time T0.

[0088] At time T1, the accumulator clear switch control signal and the sampler clear switch control signal may be deasserted by the control device, and the control device may selectively electrically disconnect the sampler capacitor and the accumulator capacitor from electrical ground via the clear switches. The first single-bit MAC may multiply the “n”-bit activation value by the least significant bit of the “m”-bit weight value, accumulate the multiplication results, and output a first single-bit MAC output (e.g., single-bit MAC1). The first single-bit MAC may be electrically connected to the sampler capacitor via the first single-bit MAC switch and output the single-bit MAC output to the sampler capacitor. The sampler capacitor may receive the first single-bit MAC output and indicate a first sampler capacitor voltage measurement (Vmult1). The adder switch control signal may be deasserted by the control device at time T0, and voltage may not be shared between the sampler capacitor and the accumulator capacitor. Therefore, the accumulator capacitor voltage measurement may remain at its previous voltage after time T0.

[0089] At time T2, an adder switch control signal may be asserted by the control device. In response, the adder switch may selectively electrically connect the sampler capacitor and the accumulator capacitor. A first sampler capacitor voltage measurement may be shared between the sampler capacitor and the accumulator capacitor. Each time the sampler capacitor and the accumulator capacitor share a sampler capacitor voltage measurement, the voltage of the sampler capacitor voltage measurement may be divided in half at the sampler capacitor, and half of that voltage may be provided to the accumulator capacitor. Thus, the first sampler capacitor voltage measurement may be (Vmult1) / 2, and the first accumulator capacitor voltage measurement (e.g., the first single-bit MAC output sample) may be (Vmult1) / 2.

[0090] At time T3, the adder switch control signal may be deasserted, and the sampler clear switch control signal may be asserted by the control device. Deasserting the adder switch control signal may cause the adder switch to selectively electrically disconnect the sampler capacitor and the accumulator capacitor. Asserting the sampler clear switch control signal may cause the clear switch to selectively electrically connect the sampler capacitor to electrical ground, which may pull the first sampler capacitor voltage measurement to 0 volts or near 0 volts. The first accumulator capacitor voltage measurement may remain at (Vmult1) / 2.

[0091] At time T4, the sampler clear switch control signal may be deasserted by the control device, and the second single-bit MAC may multiply the 'n'-bit activation value by the next most significant bit of the 'm'-bit weight value, accumulate the results of the multiplication, and output a second single-bit MAC output (e.g., single-bit MAC2). Deasserting the sampler clear switch control signal may cause the clear switch to selectively electrically disconnect the sampler capacitor from electrical ground. The sampler capacitor may receive the second single-bit MAC output, indicating a second sampler capacitor voltage measurement (Vmult2).

[0092] At time T5, an adder switch control signal may be asserted by the control device. In response, the adder switch may selectively electrically connect the sampler capacitor and the accumulator capacitor. The second sampler capacitor voltage measurement and the first accumulator capacitor voltage measurement may be shared between the sampler capacitor and the accumulator capacitor. Each time the sampler capacitor and the accumulator capacitor share an accumulator capacitor voltage measurement, the voltage of the accumulator capacitor voltage measurement may be divided in half at the accumulator capacitor, and half of that voltage may be provided to the sampler capacitor. Thus, the second sampler capacitor voltage measurement may be (Vmult1) / 4+(Vmult2) / 2, and the second accumulator capacitor voltage measurement (e.g., a second single-bit MAC output sample) may be (Vmult1) / 4+(Vmult2) / 2.

[0093] At time T6, the adder switch control signal may be deasserted, and the sampler clear switch control signal may be asserted by the control device. Deasserting the adder switch control signal may cause the adder switch to selectively electrically disconnect the sampler capacitor and the accumulator capacitor. Asserting the sampler clear switch control signal may cause the clear switch to selectively electrically connect the sampler capacitor to electrical ground, which may pull the second sampler capacitor voltage measurement to 0 volts or near 0 volts. The second accumulator capacitor voltage measurement may remain at (Vmult1) / 4+(Vmult2) / 2.

[0094] Over various time periods, the adder switch control signal and the sampler clear switch control signal may repeat the patterns shown at times T1-T6, and various single-bit MACs may repeatedly multiply the 'n'-bit activation value by the next most significant bit of the 'm'-bit weight value, accumulate the results of the multiplications, and output additional single-bit MAC outputs. The sampler capacitor voltage measurements and accumulator capacitor voltage measurements may vary accordingly.

[0095] At time Ts-2, the adder switch control signal may be deasserted and the sampler clear switch control signal may be asserted by the control device. Deasserting the adder switch control signal may cause the adder switch to selectively electrically disconnect the sampler capacitor and the accumulator capacitor. Asserting the sampler clear switch control signal may cause the clear switch to selectively electrically connect the sampler capacitor to electrical ground, which may pull the (b-1)th sampler capacitor voltage measurement to 0 volts or near 0 volts. The second accumulator capacitor voltage measurement is (Vmult1) / 2 b-1 +(Vmult2) / 2 b-2 It can stay at +...+(Vmultb-1) / 2.

[0096] At time Ts-1, the sampler clear switch control signal may be deasserted by the control device, and the bth single-bit MAC may multiply the 'n'-bit activation value by the most significant bit of the 'm'-bit weight value, accumulate the multiplication results, and output the bth single-bit MAC output (e.g., single-bit MACb). Deasserting the sampler clear switch control signal may cause the clear switch to selectively electrically disconnect the sampler capacitor from electrical ground. The sampler capacitor may receive a second single-bit MAC output, indicating a second sampler capacitor voltage measurement (Vmultb).

[0097] At time Ts, a summer switch control signal may be asserted by the control device. In response, the summer switch may selectively electrically connect the sampler capacitor and the accumulator capacitor. The bth sampler capacitor voltage measurement and the (b-1)th accumulator capacitor voltage measurement may be shared between the sampler capacitor and the accumulator capacitor. The bth sampler capacitor voltage measurement may be (Vmult1) / 2 b +(Vmult2) / 2 b-1+...+(Vmultb-1) / 4+(Vmultb) / 2, and the bth accumulator capacitor voltage measurement (e.g., the second single-bit MAC output sample) may be (Vmult1) / 2 b +(Vmult2) / 2 b-1 It could also be +...+(Vmultb-1) / 4+(Vmultb) / 2.

[0098] FIG. 9 shows an example of a single-bit MAC output adder for multi-bit activation values ​​and multi-bit weights suitable for implementing various embodiments. Referring to FIGS. 1 through 9, the multi-bit MAC 900 may include any number of analog adders. In some embodiments, the analog adders may include any number of adder switches 908a, 908b, 908c, 908d, 910a, 910b, 910c, 910d, 912a, 912b, 912c, 912d, and adder capacitors 904a, 904b, 904c, 904d, 906a, 906b, 906c, 906d, 906e, 906f, 906g, and 906h. In some embodiments, the analog adders may further include any number of designated electrical grounds 508. The summer capacitors 904a, 904b, 904c, and 904d of the analog summers, referred to herein as sampler capacitors, may be selectively electrically connected to the single-bit MACs 206, 206a, 206b, 206c, and 206d via associated single-bit MAC switches 304a, 304b, 304c, and 304d. The summer capacitors 904a, 904b, 904c, 904d, 906a, 906b, 906c, 906d, 906e, 906f, 906g, and 906h may be selectively electrically connected to each other via summer switches 908a, 908b, 908c, 908d, 910a, 910b, 910c, and 910d. The summer capacitors 904a, 904b, 904c, 904d, 906a, 906b, 906c, 906d, 906e, 906f, 906g, and 906h may be electrically connected between the electrically conductive bus 316 and electrical ground 508. The summer capacitors 904a, 904b, 904c, 904d, 906a, 906b, 906c, 906d, 906e, 906f, 906g, and 906h may be electrically connected to the ADC 212 via the electrically conductive bus 316 and the summer switches 912a, 912b, 912c, and 912d.The summer switches 908a, 908b, 908c, 908d, 910a, 910b, 910c, 910d, 912a, 912b, 912c, 912d may be controlled by a MAC controller (e.g., processor 104, MAC controller 124 of FIG. 1 ) to selectively electrically connect the summer capacitors 904a, 904b, 904c, 904d, 906a, 906b, 906c, 906d, 906e, 906f, 906g, 906h to each other and to the ADC 212. Additionally, some embodiments of the multi-bit MAC 900 may include any number of clear switches and electrical grounds and combinations thereof, as shown and described with reference to FIG.

[0099] The analog summer may receive single-bit MAC outputs from the single-bit MACs 206, 206a, 206b, 206c, 206d at sampler capacitors 904a, 904b, 904c, 904d. The sampler capacitors 904a, 904b, 904c, 904d may be selectively electrically connected to the single-bit MACs 206, 206a, 206b, 206c, 206d. The summer capacitors 906a, 906c, 906e, 906g, referred to herein as first accumulator capacitors, may be selectively electrically connected to the sampler capacitors 904a, 904b, 904c, 904d. Adder capacitors 906b, 906d, 906f, 906h, referred to herein as second accumulator capacitors, may be selectively electrically connected to the first accumulator capacitors 906a, 906c, 906e, 906g. Sampler capacitors 904a, 904b, 904c, 904d and pairs of first and second accumulator capacitors 906a, 906b, 906c, 906d, 906e, 906f, 906g, 906h may collectively have the same rated capacitance (“C”). The rated capacitance of second accumulator capacitors 906b, 906d, 906f, 906h may be proportional to the bit position of the “n”-bit activation value with which the bit of the “m”-bit weight value is multiplied, or the “m”-bit weight value with which the bit of the “n”-bit activation value is multiplied. For example, the rated capacitance of the second accumulator capacitors 906b, 906d, 906f, and 906h may be lowest for the least significant bits and highest for the most significant bits. As another example, the rated capacitance of the first accumulator capacitors 906a, 906c, 906e, and 906g may be highest for the least significant bits and lowest for the most significant bits. The combined capacitance of the pair of the first accumulator capacitors 906a, 906c, 906e, and 906g and the second accumulator capacitors 906b, 906d, 906f, and 906h may be equal to the capacitance of the sampler capacitors 904a, 904b, 904c, and 904d. In some embodiments, each adder capacitor 904a, 904b, 904c, 904d, 906a, 906b, 906c, 906d, 906e, 906f, 906g, 906h may be a single capacitor.In some embodiments, each summer capacitor 904a, 904b, 904c, 904d, 906a, 906b, 906c, 906d, 906e, 906f, 906g, 906h may be multiple capacitors electrically connected in series and / or parallel. The rated capacitances of the summer capacitors 904a, 904b, 904c, 904d, 906a, 906b, 906c, 906d, 906e, 906f, 906g, 906h may function as hardwired binary weights for the single-bit MAC outputs received by the analog summers from the single-bit MACs 206, 206a, 206b, 206c, 206d.

[0100] The sampler capacitors 904a, 904b, 904c, 904d, when selectively electrically connected to the single-bit MACs 206, 206a, 206b, 206c, 206d via the associated single-bit MAC switches 304a, 304b, 304c, 304d, can receive and store the single-bit MAC outputs from the single-bit MACs 206, 206a, 206b, 206c, 206d. The single-bit MAC switches 304a, 304b, 304c, 304d can be controlled to output the single-bit MAC outputs from the single-bit MACs 206, 206a, 206b, 206c, 206d such that the sampler capacitors 904a, 904b, 904c, 904d receive the single-bit MAC outputs in a particular order. In some embodiments, the order may be sequential, starting with the multiplication of the least significant bit of the “n”-bit activation value and the “m”-bit weight value to the multiplication of the most significant bit of the “n”-bit activation value and the “m”-bit weight value. For example, the single-bit MAC switches 304a, 304b, 304c, 304d may be controlled to sequentially close circuits electrically connecting the single-bit MACs 206, 206a, 206b, 206c, 206d to the analog summers to output the single-bit MAC outputs to the analog summers. The sampler capacitors 904a, 904b, 904c, 904d may be sequentially charged with the single-bit MAC outputs by closing circuits electrically connecting the single-bit MACs 206, 206a, 206b, 206c, 206d to the sampler capacitors 904a, 904b, 904c, 904d. In other words, the sampler capacitors 904a, 904b, 904c, 904d may receive the single-bit MAC output for each multiplication and accumulation of the 'n'-bit activation value and the 'm'-bit weight value from the single-bit MACs 206, 206a, 206b, 206c, 206d.In some embodiments, the single-bit MAC switches 304a, 304b, 304c, 304d may be controlled in a manner such that the single-bit MAC outputs are charged to the sampler capacitors 904a, 904b, 904c, 904d in an order based on the bit positions of the bits of the 'n'-bit activation value and the 'm'-bit weight value that are multiplied to produce the single-bit MAC output. The sampler capacitors 904a, 904b, 904c, 904d may be charged by receiving the single-bit MAC outputs when selectively electrically connected to the single-bit MACs 206, 206a, 206b, 206c, 206d. Sampler capacitors 904a, 904b, 904c, and 904d may store samples of the single-bit MAC output, which may include combinations of the received single-bit MAC outputs modified by sharing the samples of the single-bit MAC output with accumulator capacitors 906a, 906b, 906c, 906d, 906e, 906f, 906g, and 906h. The samples of the single-bit MAC output are referred to herein as single-bit MAC output samples. Sampler capacitors 904a, 904b, 904c, and 904d may store and output single-bit MAC output samples in response to receiving each single-bit MAC output.

[0101] The accumulator capacitors 906a, 906b, 906c, 906d, 906e, 906f, 906g, and 906h may receive and store single-bit MAC output samples from the sampler capacitors 904a, 904b, 904c, and 904d when selectively electrically connected to the sampler capacitors 904a, 904b, 904c, and 904d via the adder switches 908a, 908b, 908c, and 908d and / or the adder switches 910a, 910b, 910c, and 910d. The sampler capacitors 904a, 904b, 904c, 904d may discharge or output single-bit MAC output samples to the accumulator capacitors 906a, 906b, 906c, 906d, 906e, 906f, 906g, 906h when the sampler capacitors 904a, 904b, 904c, 904d are selectively disconnected from the single-bit MACs 206, 206a, 206b, 206c, 206d and selectively connected to the accumulator capacitors 906a, 906b, 906c, 906d, 906e, 906f, 906g, 906h by the adder switches 908a, 908b, 908c, 908d and / or the adder switches 910a, 910b, 910c, 910d. The accumulator capacitors 906a, 906b, 906c, 906d, 906e, 906f, 906g, and 906h may receive and store the single-bit MAC output samples. For example, the single-bit MAC switches 304a, 304b, 304c, and 304d may be controlled to selectively disconnect the sampler capacitors 904a, 904b, 904c, and 904d from the single-bit MACs 206, 206a, 206b, 206c, and 206d. The adder switches 908a, 908b, 908c, and 908d may be controlled to electrically connect the sampler capacitors 904a, 904b, 904c, and 904d to the accumulator capacitors 906a, 906b, 906c, 906d, 906e, 906f, 906g, and 906h via the electrically conductive bus 316. The adder switches 910a, 910b, 910c, 910d may also be controlled to electrically connect the sampler capacitors 904a, 904b, 904c, 904d to the second accumulator capacitors 906b, 906d, 906f, 906h via the electrically conductive bus 316.Sampler capacitors 904a, 904b, 904c, and 904d may output single-bit MAC output samples to accumulator capacitors 906a, 906b, 906c, 906d, 906e, 906f, 906g, and 906h. After receiving the single-bit MAC output samples, the single-bit MAC output samples may be shared by sampler capacitors 904a, 904b, 904c, and 904d and accumulator capacitors 906a, 906b, 906c, 906d, 906e, 906f, 906g, and 906h, as described further herein with reference to FIG. 8, in which pairs of accumulator capacitors 906a and 906b, 906c and 906d, 906e and 906f, and 906g and 906h may be represented as single accumulator capacitors. The process of receiving each single-bit MAC output output by sampler capacitors 904a, 904b, 904c, 904d, outputting a single-bit MAC output sample by sampler capacitors 904a, 904b, 904c, 904d, and receiving a single-bit MAC output sample by accumulator capacitors 906a, 906b, 906c, 906d, 906e, 906f, 906g, 906h may continue for every multiplication and addition of the bits of the 'n'-bit activation value and the 'm'-bit weight value.

[0102] The second accumulator capacitors 906b, 906d, 906f, 906h can output or discharge single-bit MAC output samples when selectively and electrically disconnected from the single-bit MACs 206, 206a, 206b, 206c, 206d, sampler capacitors 904a, 904b, 904c, 904d, and first accumulator capacitors 906a, 906c, 906e, 906g by adder switches 910a, 910b, 910c, 910d, and selectively and electrically connected to the ADC 212 by adder switches 912a, 912b, 912c, 912d. The summer switches 910a, 910b, 910c, 910d may be controlled to selectively electrically disconnect the second accumulator capacitors 906b, 906d, 906f, 906h from the single-bit MACs 206, 206a, 206b, 206c, 206d, the sampler capacitors 904a, 904b, 904c, 904d, and the first accumulator capacitors 906a, 906c, 906e, 906g. The summer switches 912a, 912b, 912c, 912d may be controlled to selectively electrically connect the second accumulator capacitors 906b, 906d, 906f, 906h to the ADC 212 via the electrically conductive circuit 316. The single-bit MAC output samples may be output as weighted analog voltages to the electrically conductive bus 316 and the ADC 212. The weight of each of the analog voltages may be based on the rated capacitance of the second accumulator capacitors 906b, 906d, 906f, and 906h that output the analog voltage. The combination of the weighted analog voltages on the conductive bus 316, sometimes referred to herein as a multi-bit MAC output, may be a summation of the weighted analog voltages to result in a weighted average analog voltage of the weighted analog voltages. This combination may result in a weighted average analog voltage because the accumulator capacitors 906b, 906d, 906f, and 906h are electrically connected in parallel to the electrical conductive bus 316. The weighted average analog voltage on the electrical conductive bus 316 may be converted to a digital signal by the ADC 212.

[0103] FIG. 10 shows an example of a single-bit MAC output adder for multi-bit activation values ​​and multi-bit weights, suitable for implementing various embodiments. Referring to FIGS. 1 through 10, the multi-bit MAC 1000 may include any number of analog adders. In some embodiments, the analog adder may include any number of adder switches 1004a, 1004b, 1004c, 1004d, 1006a, 1006b, 1006c, 1006d and adder capacitors 904a, 904b, 904c, 904d, 1002a, 1002b, 1002c, 1002d. In some embodiments, the analog adder may further include an output switch 1008. In some embodiments, the analog adder may further include any number of designated electrical grounds 508. In some embodiments, the analog summer may further include any number of clear switches 1010a, 1010b, 1010c, 1010d, 1014a, 1014b, 1014c, 1014d, 1016a, 1016b, 1016c, 1016d and combinations thereof, and electrical ground 1012. The summer capacitors 904a, 904b, 904c, 904d of the analog summer, referred to herein as sampler capacitors, may be selectively electrically connected to the single-bit MACs 206, 206a, 206b, 206c, 206d via associated single-bit MAC switches 304a, 304b, 304c, 304d. The summer capacitors 904a, 904b, 904c, 904d, 1002a, 1002b, 1002c, and 1002d may be selectively electrically connected to one another via summer switches 1004a, 1004b, 1004c, 1004d, 1006a, 1006b, 1006c, and 1006d. The summer capacitors 904a, 904b, 904c, 904d, 1002a, 1002b, 1002c, and 1002d may be electrically connected between the electrically conductive bus 316 and electrical ground 508. The summer capacitors 904a, 904b, 904c, 904d, 1002a, 1002b, 1002c, 1002d can be selectively electrically connected to electrical ground 508 via clear switches 1014a, 1014b, 1014c, 1014d, 1016a, 1016b, 1016c, 1016d.For example, pairs of summer capacitors 904a, 904b, 904c, 904d, 1002a, 1002b, 1002c, 1002d and clear switches 1014a, 1014b, 1014c, 1014d, 1016a, 1016b, 1016c, 1016d may be electrically connected in parallel to electrical ground 508. Summer capacitors 904d, 1002d may be electrically connected to ADC 212 via electrically conductive bus 316 and output switch 1008. Single-bit MACs 206a, 206b, 206c, 206d may be selectively electrically connected to electrical ground 1012 via clear switches 1010a, 1010b, 1010c, 1010d. The summer switches 1004a, 1004b, 1004c, 1004d, 1006a, 1006b, 1006c, 1006d may be controlled to selectively electrically connect the summer capacitors 904a, 904b, 904c, 904d, 1002a, 1002b, 1002c, 1002d to one another, and the output switch 1008 may be controlled by a MAC controller (e.g., processor 104, MAC controller 124 in FIG. 1 ) to selectively electrically connect the summer capacitors 904a, 904b, 904c, 904d, 1002a, 1002b, 1002c, 1002d to the ADC 212. The clear switches 1010a, 1010b, 1010c, 1010d, 1014a, 1014b, 1014c, 1014d, 1016a, 1016b, 1016c, and 1016d may also be controlled by the MAC controller.

[0104] The analog summer may receive single-bit MAC outputs from the single-bit MACs 206, 206a, 206b, 206c, 206d at sampler capacitors 904a, 904b, 904c, 904d. The sampler capacitors 904a, 904b, 904c, 904d may be selectively electrically connected to the single-bit MACs 206, 206a, 206b, 206c, 206d. The summer capacitors 1002a, 1002b, 1002c, 1002d, referred to herein as accumulator capacitors, may be selectively electrically connected to the sampler capacitors 904a, 904b, 904c, 904d. The sampler capacitors 904a, 904b, 904c, 904d and the accumulator capacitors 1002a, 1002b, 1002c, 1002d may have the same rated capacitance (“C”). In some embodiments, each summer capacitor 904a, 904b, 904c, 904d, 1002a, 1002b, 1002c, 1002d may be a single capacitor. In some embodiments, each summer capacitor 904a, 904b, 904c, 904d, 1002a, 1002b, 1002c, 1002d may be multiple capacitors electrically connected in series and / or parallel. The nominal capacitances of the summer capacitors 904a, 904b, 904c, 904d, 1002a, 1002b, 1002c, 1002d may function as hardwired binary weights for the single-bit MAC outputs received by the analog summers from the single-bit MACs 206, 206a, 206b, 206c, 206d.

[0105] The sampler capacitors 904a, 904b, 904c, 904d, when selectively electrically connected to the single-bit MACs 206, 206a, 206b, 206c, 206d via the associated single-bit MAC switches 304a, 304b, 304c, 304d, can receive and store the single-bit MAC outputs from the single-bit MACs 206, 206a, 206b, 206c, 206d. The single-bit MAC switches 304a, 304b, 304c, 304d can be controlled to output the single-bit MAC outputs from the single-bit MACs 206, 206a, 206b, 206c, 206d such that the sampler capacitors 904a, 904b, 904c, 904d receive the single-bit MAC outputs in a particular order. In some embodiments, the order may be sequential, starting with the multiplication of the least significant bit of the “n”-bit activation value and the “m”-bit weight value to the multiplication of the most significant bit of the “n”-bit activation value and the “m”-bit weight value. For example, the single-bit MAC switches 304a, 304b, 304c, 304d may be controlled to sequentially close circuits electrically connecting the single-bit MACs 206, 206a, 206b, 206c, 206d to the analog summers to output the single-bit MAC outputs to the analog summers. The sampler capacitors 904a, 904b, 904c, 904d may be sequentially charged with the single-bit MAC outputs by closing circuits electrically connecting the single-bit MACs 206, 206a, 206b, 206c, 206d to the sampler capacitors 904a, 904b, 904c, 904d. In other words, the sampler capacitors 904a, 904b, 904c, 904d may receive the single-bit MAC output for each multiplication and accumulation of the 'n'-bit activation value and the 'm'-bit weight value from the single-bit MACs 206, 206a, 206b, 206c, 206d.In some embodiments, the single-bit MAC switches 304a, 304b, 304c, 304d may be controlled in a manner such that the single-bit MAC outputs are charged to the sampler capacitors 904a, 904b, 904c, 904d in an order based on the bit positions of the bits of the 'n'-bit activation value and the 'm'-bit weight value that are multiplied to produce the single-bit MAC output. The sampler capacitors 904a, 904b, 904c, 904d may be charged by receiving the single-bit MAC outputs when selectively electrically connected to the single-bit MACs 206, 206a, 206b, 206c, 206d. Sampler capacitors 904a, 904b, 904c, and 904d may store samples of the single-bit MAC output, which may include a combination of the received single-bit MAC outputs modified by sharing the samples of the single-bit MAC output with accumulator capacitors 1002a, 1002b, 1002c, and 1002d. The samples of the single-bit MAC output are referred to herein as single-bit MAC output samples. Sampler capacitors 904a, 904b, 904c, and 904d may store and output single-bit MAC output samples in response to receiving each single-bit MAC output.

[0106] The accumulator capacitors 1002a, 1002b, 1002c, and 1002d can receive and store single-bit MAC output samples from the sampler capacitors 904a, 904b, 904c, and 904d when selectively electrically connected to the sampler capacitors 904a, 904b, 904c, and 904d via the adder switches 1004a, 1004b, 1004c, and 1004d. The sampler capacitors 904a, 904b, 904c, 904d may discharge or output single-bit MAC output samples to the accumulator capacitors 1002a, 1002b, 1002c, 1002d when the sampler capacitors 904a, 904b, 904c, 904d are selectively disconnected from the single-bit MACs 206, 206a, 206b, 206c, 206d and selectively connected to the accumulator capacitors 1002a, 1002b, 1002c, 1002d by the adder switches 1004a, 1004b, 1004c, 1004d. The accumulator capacitors 1002a, 1002b, 1002c, 1002d may receive and store the single-bit MAC output samples. For example, the single-bit MAC switches 304a, 304b, 304c, 304d may be controlled to selectively disconnect the sampler capacitors 904a, 904b, 904c, 904d from the single-bit MACs 206, 206a, 206b, 206c, 206d. The adder switches 1004a, 1004b, 1004c, 1004d may be controlled to electrically connect the sampler capacitors 904a, 904b, 904c, 904d to the accumulator capacitors 1002a, 1002b, 1002c, 1002d via the electrically conductive bus 316. The sampler capacitors 904a, 904b, 904c, 904d may output single-bit MAC output samples to the accumulator capacitors 1002a, 1002b, 1002c, 1002d. After receiving the single-bit MAC output sample, the single-bit MAC output sample may be shared by sampler capacitors 904a, 904b, 904c, 904d and accumulator capacitors 1002a, 1002b, 1002c, 1002d, as further described herein with reference to FIG. 8.The process of receiving each single-bit MAC output by sampler capacitors 904a, 904b, 904c, 904d, outputting a single-bit MAC output sample by sampler capacitors 904a, 904b, 904c, 904d, and receiving a single-bit MAC output sample by accumulator capacitors 1002a, 1002b, 1002c, 1002d may continue for every multiplication and addition of the bits of the 'n'-bit activation value and the 'm'-bit weight value.

[0107] In some embodiments, the accumulator capacitors 1002a, 1002b, 1002c, 1002d may output or discharge single-bit MAC output samples when selectively and electrically disconnected from the single-bit MACs 206a, 206b, 206c, 206d and the sampler capacitors 904a, 904b, 904c, 904d by the adder switches 1004a, 1004b, 1004c, 1004d, when selectively and electrically connected to the accumulator capacitors 1002a, 1002b, 1002c, 1002d by the adder switches 1006a, 1006b, 1006c, 1006d, and when selectively and electrically connected to the ADC 212 by the output switch 1008. Accumulator capacitors 1002a, 1002b, 1002c, and 1002d may be charged with the single-bit MAC output sample, and adder switches 1004a, 1004b, 1004c, and 1004d may be controlled to selectively electrically disconnect accumulator capacitors 1002a, 1002b, 1002c, and 1002d from sampler capacitors 904a, 904b, 904c, and 904d. For the least significant bit of an “m”-bit weight value, such as the single-bit MAC output of single-bit MAC 206a, the analog adder may divide the charge of the single-bit MAC output sample on accumulator capacitor 1002a in half. For example, the analog adder may reset sampler capacitor 904a, while adder switch 1004a is controlled to selectively electrically disconnect accumulator capacitor 1002a from sampler capacitor 904a. The adder switch 1004a may be controlled to selectively electrically connect the accumulator capacitor 1002a and the reset sampler capacitor 904a, dividing the single-bit MAC output sample of the accumulator capacitor 1002a with the sampler capacitor 904a. The adder switch 1004a may be controlled to selectively electrically disconnect the accumulator capacitor 1002a from the sampler capacitor 904a.

[0108] The adder switches 1006a, 1006b, 1006c, and 1006d may be controlled to sequentially electrically connect the accumulator capacitors 1002a, 1002b, 1002c, and 1002d from the least significant bit to the most significant bit. For example, the adder switch 1006a may be controlled to selectively electrically connect the accumulator capacitors 1002a and 1002b, while the adder switch 1006b may be controlled to selectively electrically disconnect the accumulator capacitors 1002a and 1002b from the accumulator capacitors 1002c and 1002d. The accumulator capacitors 1002a and 1002b may share single-bit MAC output samples, which may include sharing half of the single-bit MAC output samples of each of the accumulator capacitors 1002a and 1002b. For example, accumulator capacitors 1002a, 1002b may share one-quarter of the original single-bit MAC output sample on accumulator capacitor 1002a and one-half of the original single-bit MAC output sample on accumulator capacitor 1002b, because the single-bit MAC output sample was previously halved when divided by sampler capacitor 904a. The shared single-bit MAC output sample may be the new single-bit MAC output sample on accumulator capacitor 1002b. Subsequently, adder switch 1006b may be controlled to selectively electrically connect accumulator capacitors 1002b, 1002c, while adder switches 1006a, 1006c may be controlled to selectively electrically disconnect accumulator capacitors 1002b, 1002c from accumulator capacitors 1002a, 1002d. Accumulator capacitors 1002b, 1002c may share their single-bit MAC output samples. For example, accumulator capacitors 1002b, 1002c may share half of the new single-bit MAC output sample of accumulator capacitor 1002b and half of the original single-bit MAC output sample of accumulator capacitor 1002c, which may be one-eighth of the original single-bit MAC output sample of accumulator capacitor 1002a and one-fourth of the original single-bit MAC output sample of accumulator capacitor 1002b.The adder switches 1006a, 1006b, 1006c, 1006d can similarly be sequentially controlled to selectively electrically connect and disconnect the accumulator capacitors 1002a, 1002b, 1002c, 1002d until all of the accumulator capacitors 1002a, 1002b, 1002c, 1002d share a single-bit MAC output sample.

[0109] The output switch 1008 can be controlled to selectively electrically connect the accumulator capacitor 1006d to the ADC 212 via the electrically conductive circuit 316. The single-bit MAC output sample on the accumulator capacitor 1006d can be a weighted analog voltage of the combination of all the shared single-bit MAC output samples of the accumulator capacitors 1002a, 1002b, 1002c, 1002d that can be output to the electrically conductive bus 316 and the ADC 212. The weighted average analog voltage on the electrically conductive bus 316 can be converted to a digital signal by the ADC 212.

[0110] In some embodiments, the sampler capacitors 904a, 904b, 904c, 904d and the accumulator capacitors 1002a, 1002b, 1002c, 1002d are selectively and electrically disconnected from the single-bit MACs 206, 206a, 206b, 206c, 206d by the single-bit MAC switches 304a, 304b, 304c, 304d. When selectively electrically connected to sampler capacitors 904a, 904b, 904c, 904d and accumulator capacitors 1002a, 1002b, 1002c, 1002d by output switches 1004a, 1004b, 1004c, 1004d, 1006a, 1006b, 1006c, 1006d, and to ADC 212 by output switches 1008, adder switches 1004a, 1004b, 1004c, 1004d can output or discharge single-bit MAC output samples. Adder switches 1004a, 1004b, 1004c, 1004d can be controlled to selectively electrically connect pairs of sampler capacitors 904a, 904b, 904c, 904d and accumulator capacitors 1002a, 1002b, 1002c, 1002d such that the pairs can be charged with single-bit MAC output samples. The single-bit MAC switches 304a, 304b, 304c, 304d may be controlled to selectively electrically disconnect the pair of sampler capacitors 904a, 904b, 904c, 904d and accumulator capacitors 1002a, 1002b, 1002c, 1002d from the single-bit MACs 206, 206a, 206b, 206c, 206d. For the least significant bit of an “m”-bit weight value, such as the single-bit MAC output of the single-bit MAC 206a, the analog summer may divide in half the charge of the single-bit MAC output sample on the pair of sampler capacitor 904a and accumulator capacitor 1002a. For example, the analog summer may reset the sampler capacitor 904a, while the summer switch 1004a is controlled to selectively electrically disconnect the accumulator capacitor 1002a from the sampler capacitor 904a.The adder switch 1004a may be controlled to selectively electrically connect the accumulator capacitor 1002a and the reset sampler capacitor 904a, dividing the single-bit MAC output sample of the accumulator capacitor 1002a with the sampler capacitor 904a. The adder switch 1004a may be controlled to maintain the selective electrical connection of the pair of sampler capacitor 904a and accumulator capacitor 1002a.

[0111] The adder switches 1006a, 1006b, 1006c, and 1006d may be controlled to sequentially electrically connect pairs of sampler capacitors 904a, 904b, 904c, and 904d to accumulator capacitors 1002a, 1002b, 1002c, and 1002d from the least significant bit to the most significant bit. For example, the adder switch 1006a may be controlled to selectively electrically connect the pair of sampler capacitor 904a and accumulator capacitor 1002a to the pair of sampler capacitor 904b and accumulator capacitor 1002b. The summer switch 1006a is controlled for selective electrical connection, while the summer switch 1006b can be controlled to selectively electrically disconnect the pair of sampler capacitors 904a, 904b and accumulator capacitors 1002a, 1002b from the pair of sampler capacitors 904c, 904d and accumulator capacitors 1002c, 1002d. The pair of sampler capacitors 904a, 904b and accumulator capacitors 1002a, 1002b may share their single-bit MAC output samples, which may include sharing half of the single-bit MAC output samples of each of the pair of sampler capacitors 904a, 904b and accumulator capacitors 1002a, 1002b. For example, the sampler capacitors 904a, 904b and accumulator capacitor 1002a, 1002b pair may share one-quarter of the original single-bit MAC output sample of the sampler capacitor 904a, accumulator capacitor 1002a pair and one-half of the original single-bit MAC output sample of the sampler capacitor 904b, accumulator capacitor 1002b pair, since the single-bit MAC output sample was previously halved when it was divided between the accumulator capacitor 1002a and the sampler capacitor 904a. The shared single-bit MAC output sample may be the new single-bit MAC output sample of the sampler capacitor 904b, accumulator capacitor 1002b pair. Subsequently, the adder switch 1006b may be controlled to selectively electrically connect the sampler capacitors 904b, 904c and the accumulator capacitors 1002b, 1002c pair.The summer switch 1006b is controlled to selectively electrically connect, while the summer switches 1006a, 1006c can be controlled to selectively electrically disconnect the pair of sampler capacitors 904b, 904c and accumulator capacitors 1002b, 1002c from the pair of sampler capacitors 904a, 904d and accumulator capacitors 1002a, 1002d. The pair of sampler capacitors 904b, 904c and accumulator capacitors 1002b, 1002c can share their single-bit MAC output samples. For example, the pair of sampler capacitors 904b, 904c and accumulator capacitors 1002b, 1002c may share half of the new single-bit MAC output sample of the pair of sampler capacitor 904b and accumulator capacitor 1002b and half of the original single-bit MAC output sample of the pair of sampler capacitor 904c and accumulator capacitor 1002c, which may be one-eighth of the original single-bit MAC output sample of the pair of sampler capacitor 904a and accumulator capacitor 1002a and one-fourth of the original single-bit MAC output sample of the pair of sampler capacitor 904b and accumulator capacitor 1002b. The adder switches 1006a, 1006b, 1006c, 1006d may similarly be sequentially controlled to selectively electrically connect and disconnect pairs of sampler capacitors 904a, 904b, 904c, 904d and accumulator capacitors 1002a, 1002b, 1002c, 1002d until all of the pairs of sampler capacitors 904a, 904b, 904c, 904d and accumulator capacitors 1002a, 1002b, 1002c, 1002d share a single-bit MAC output sample.

[0112] The output switch 1008 can be controlled to selectively electrically connect the sampler capacitor 904d and accumulator capacitor 1002d pair to the ADC 212 via the electrically conductive circuit 316. The single-bit MAC output sample on the sampler capacitor 904d and accumulator capacitor 1002d pair can be a weighted analog voltage of the combination of all shared single-bit MAC output samples of the sampler capacitors 904a, 904b, 904c, 904d and accumulator capacitors 1002a, 1002b, 1002c, 1002d pairs that can be output to the electrically conductive bus 316 and the ADC 212. The weighted average analog voltage on the electrically conductive bus 316 can be converted to a digital signal by the ADC 212.

[0113] After completing all multiplications and additions of the “n”-bit activation value and the “m”-bit weight value bits, the multi-bit MAC 1000 may be reset or cleared. Clear switches 1014a, 1014b, 1014c, 1014d, 1016a, 1016b, 1016c, and 1016d may be controlled by the MAC controller to selectively electrically connect the analog summers, including summer capacitors 904a, 904b, 904c, 904d, 1002a, 1002b, 1002c, and 1002d, to electrical ground 508. Clear switches 1010a, 1010b, 1010c, and 1010d may be controlled by the MAC controller to selectively electrically connect the single-bit MACs 206a, 206b, 206c, and 206d to electrical ground 1012. Electrically connecting the components of the multi-bit MAC 1000 to electrical ground 508, 1012 may discharge any remaining voltage within the multi-bit MAC 1000 so that subsequent multiplications and additions of different combinations of “n”-bit activation values ​​and / or “m”-bit weight values ​​may be performed by the multi-bit MAC 1000.

[0114] FIG. 11 illustrates a method 1100 for control of a multi-bit MAC according to one embodiment. Referring to FIGS. 1-11, method 1100 may be implemented in a computing device (e.g., mobile computing device 100 of FIG. 1), in software executing on a processor (e.g., processor 104, MAC controller 124 of FIG. 1), in general-purpose hardware, in dedicated hardware (e.g., multi-bit MACs 130, 200, 300, 400, 500, 600, 700, 900, 1000 of FIGS. 1-7, 9, and 10), or in a combination of a processor configured in software and dedicated hardware, such as a processor running software and various memory / cache controllers in a multi-bit MAC control system that includes other individual components (e.g., memories 106, 114 shown in FIG. 1). To encompass alternative configurations enabled by various embodiments, the hardware implementing method 1100 is referred to herein as a “MAC device.”

[0115] At block 1102, a MAC device may receive sequential input of bits of an activation value. The sequential input of bits of an activation value may include bit-by-bit input of the "n"-bit activation value from least significant bit to most significant bit.

[0116] At block 1104, the MAC device may perform a multiply-and-accumulate operation on each bit of the sequential input and bit of the weight value. The MAC device may multiply each bit of the 'n'-bit activation value with a bit of the 'm'-bit weight value. The MAC device may sequentially multiply each bit of the 'n'-bit activation value with a bit of the 'm'-bit weight value, in order from least significant bit to most significant bit of the 'n'-bit activation value. In some embodiments, the MAC device may sequentially multiply each bit of the 'n'-bit activation value with all of the bits of the 'm'-bit weight value. For example, the MAC device may multiply each bit of the 'n'-bit activation value with a bit of the 'm'-bit weight value, from least significant bit to most significant bit, and then multiply each bit of the 'n'-bit activation value with another bit of the 'm'-bit weight value, from least significant bit to most significant bit. In some embodiments, the MAC device may multiply each bit of the 'n'-bit activation value with all of the bits of the 'm'-bit weight value in parallel. For example, the MAC device may multiply each bit of the 'n'-bit activation value by a bit of the 'm'-bit weight value, from least significant bit to most significant bit, and simultaneously multiply each bit of the 'n'-bit activation value by another bit of the 'm'-bit weight value, from least significant bit to most significant bit. The MAC device may accumulate the results of each multiplication.

[0117] In block 1106, the MAC device may control the switches (e.g., single-bit MAC switches 304a, 304b, 304c, 304d in FIGS. 3-7, 9, and 10) to output the results of the multiplications and accumulations, referred to herein as single-bit MAC outputs. In some embodiments, the single-bit MAC outputs may include the results of individual multiplications and accumulations of each bit of the “n”-bit activation value with a bit of the “m”-bit weight value. In some embodiments, the single-bit MAC outputs may include the results of cumulative multiplications and accumulations of each bit of the “n”-bit activation value with a bit of the “m”-bit weight value. The single-bit MAC outputs may be in the form of an analog voltage signal. The MAC device may control the switches to output the single-bit MAC outputs in various patterns. For example, in some embodiments, the MAC device may control the switches to output each single-bit MAC output sequentially, such as in ascending order of bit position of the “n”-bit activation value and then the bits of the “m”-bit weight value used in the multiplication. For example, in some embodiments, the MAC device may control the switch to output each single-bit MAC output once. In another example, in some embodiments, the MAC device may control the switch to output each single-bit MAC output twice. q The switch may be controlled to output each single-bit MAC output twice, where "q" may be the position of the activation value bit from the least significant bit where q=0 to the most significant bit where q=n-1. Similarly, for a multi-bit "m"-bit weight value, the MAC device may control each single-bit MAC output twice. r The switches may be controlled to output multiple times, where "r" may be the position of the weight value bit from the least significant bit where r=0 to the most significant bit where r=m-1. In some embodiments, it may take 2 q x 2 r It may take several cycles.

[0118] At block 1108, the MAC device may weight, add, and / or store the single-bit MAC outputs. In some embodiments, the MAC device may weight, add, and / or store the single-bit MAC outputs in different orders. For example, in some embodiments, the MAC device may weight the single-bit MAC outputs before adding and storing them. In another example, in some embodiments, the MAC device may add and store the single-bit MAC outputs before weighting them. In another example, in some embodiments, the MAC device may weight, add, and store the single-bit MAC outputs simultaneously. In another example, in some embodiments, the MAC device may iteratively weight, add, and / or store the single-bit MAC outputs in various combinations and orders. In another example, in some embodiments, the MAC device may iteratively weight, add, and store the single-bit MAC outputs in any of different orders. In some embodiments, as described herein with reference to Figures 3-7, 9, and 10, an analog summer of the MAC device (e.g., summer 128 of Figure 1) may perform weighting, summing, and / or storing of the single-bit MAC output in block 1108. In some embodiments, the MAC device may control various switches (e.g., adder switches 504a, 504b, 504c of FIG. 5 , adder switches 604a, 604b of FIGS. 6 and 7 , adder switch 702 of FIG. 7 , adder switches 908a, 908b, 908c, 908d, 910a, 910b, 910c, 910d, 912a, 912b, 912c, 912d of FIG. 9 , adder switches 1004a, 1004b, 1004c, 1004d, 1006a, 1006b, 1006c, 1006d of FIG. 10 ) to perform weighting, summing, and / or storing of the single-bit MAC output in block 1108.In some embodiments, capacitors of the MAC device (e.g., integrator capacitor 314 of FIGS. 3 and 4 , designated capacitors 402a, 402b, 402c, 402d of FIG. 4 , adder capacitors 506a, 506b, 506c of FIG. 5 , adder capacitors 606a, 606b of FIGS. 6 and 7 , adder capacitors 904a, 904b, 904c, 904d, 906a, 906b, 906c, 906d, 906e, 906f, 906g, 906h of FIG. 9 , adder capacitors 904a, 904b, 904c, 904d, 1002a, 1002b, 1002c, 1002d of FIG. 10 ) may be used to implement weighting, summing, and / or storing of the single-bit MAC output in block 1108.

[0119] In block 1110, the MAC device may average the single-bit MAC outputs. In some embodiments, averaging the single-bit MAC outputs may be part of weighting and adding the single-bit MAC outputs in block 1108. In some embodiments, averaging the single-bit MAC outputs may include combining multiple single-bit MAC outputs in an output to an ADC (e.g., ADC 212 of FIGS. 2-7, 9, and 10). In some embodiments, an analog summer of the MAC device may average the single-bit MAC outputs in block 1110, as described herein with reference to FIGS. 3-7, 9, and 10. The MAC device may control various switches (e.g., adder switches 912a, 912b, 912c, 912d in FIG. 9, adder switches 1004a, 1004b, 1004c, 1004d, 1006a, 1006b, 1006c, 1006d in FIG. 10) to combine multiple single-bit MAC outputs in the output to the ADC.

[0120] In block 1112, the MAC device may output an averaged single-bit MAC output, also referred to herein as a multi-bit MAC output. The MAC device may output the averaged single-bit MAC output to the ADC. In some embodiments, as described herein with reference to FIGS. 3-7, 9, and 10, an analog summer of the MAC device may output the averaged single-bit MAC output in block 1112. In some embodiments, the MAC device may control various switches (e.g., summer switches 504a, 504b, 504c of FIG. 5, summer switches 604a, 604b of FIGS. 6 and 7, summer switch 702 of FIG. 7, summer switches 908a, 908b, 908c, 910a, 910b, 910c, 910d, 912a, 912b, 912c, 912d of FIG. 9, output switch 1008 of FIG. 10) to output the averaged single-bit MAC output to the ADC.

[0121] The MAC device may clear the storage of the MAC device at block 1114. In some embodiments, the analog summer of the MAC device may clear the storage of the MAC device at block 1114, as described herein with reference to Figures 3-7, 9, and 10. In some embodiments, the MAC device may electrically connect the storage of the MAC device (e.g., integrator capacitor 314 of FIGS. 3 and 4 , designated capacitors 402a, 402b, 402c, 402d of FIG. 4 , adder capacitors 506a, 506b, 506c of FIG. 5 , adder capacitors 606a, 606b of FIGS. 6 and 7 , adder capacitors 904a, 904b, 904c, 904d, 906a, 906b, 906c, 906d, 906e, 906f of FIG. 9 , adder capacitors 904a, 904b, 904c, 904d, 1002a, 1002b, 1002c, 1002d of FIG. 10 ) to electrical ground (e.g., FIG. 3 3-7, adder switches 504a, 504b, 504c of FIG. 5, adder switches 604a, 604b of FIGS. 6 and 7, adder switch 702 of FIG. 7, adder switches 908a, 908b, 908c, 908d, 910a, 910b, 910c, 910d, 912a, 912b, 912c, 912d of FIG. 9, adder switches 1004a, 1004b, 1004c, 1004d, 1006a, 1006b, 1006c, 1006d of FIG. 10) to electrically connect to the electrical ground 310, 310a, 310b of FIGS. Electrically connecting the storage of a MAC device to electrical ground may pull the voltage of the storage down to or near 0 volts.

[0122] Various embodiments (including, but not limited to, those described above with reference to FIGS. 1-11 ) may be implemented in a wide variety of computing systems, including mobile computing devices, an example of a mobile computing device suitable for use with various embodiments is shown in FIG. 12 . The mobile computing device 1200 may include a processor 1202 coupled to a touchscreen controller 1204 and internal memory 1206. The processor 1202 may be one or more multi-core integrated circuits designated for general-purpose or specific processing tasks. The internal memory 1206 may be volatile or non-volatile memory, and may be secure and / or encrypted or non-secure and / or non-encrypted memory, or any combination thereof. Examples of memory types that may be utilized include, but are not limited to, DDR, LPDDR, GDDR, WIDEIO, RAM, SRAM, DRAM, P-RAM, R-RAM, M-RAM, STT-RAM, and embedded DRAM. The touchscreen controller 1204 and the processor 1202 may also be coupled to a touchscreen panel 1212, such as a resistive-sensing touchscreen, a capacitive-sensing touchscreen, an infrared-sensing touchscreen, etc. Additionally, the display of the mobile computing device 1200 need not have touchscreen capabilities.

[0123] The mobile computing device 1200 may have one or more wireless signal transceivers 1208 (e.g., Peanut, Bluetooth, ZigBee, Wi-Fi, RF radio) for transmitting and receiving communications and an antenna 1210 coupled to each other and / or to the processor 1202. The transceiver 1208 and antenna 1210 may be used with the circuitry described above to implement various wireless transmission protocol stacks and interfaces. The mobile computing device 1200 may include a cellular network wireless modem chip 1216 that enables communication over a cellular network and is coupled to the processor.

[0124] Mobile computing device 1200 may include a peripheral device connection interface 1218 coupled to processor 1202. Peripheral device connection interface 1218 may be configured solely to accept one type of connection or may be configured to accept various types of common or proprietary physical and communication connections, such as Universal Serial Bus (USB), FireWire, Thunderbolt, or PCIe. Peripheral device connection interface 1218 may also be coupled to a similarly configured peripheral device connection port (not shown).

[0125] The mobile computing device 1200 may also include a speaker 1214 for providing audio output. The mobile computing device 1200 may also include a housing 1220 constructed of plastic, metal, or a combination of materials for enclosing all or some of the components described herein. The mobile computing device 1200 may include a power source 1222, such as a disposable or rechargeable battery, coupled to the processor 1202. The rechargeable battery may also be coupled to a peripheral device connection port to receive charging current from a power source external to the mobile computing device 1200. The mobile computing device 1200 may also include a physical button 1224 for receiving user input. The mobile computing device 1200 may also include a power button 1226 for turning the mobile computing device 1200 on and off.

[0126] Various embodiments (including, but not limited to, the embodiments described above with reference to FIGS. 1-11 ) may be implemented in a wide variety of computing systems, including a laptop computer 1300, an example of which is shown in FIG. 13 . Many laptop computers include a touchpad touch surface 1317 that acts as the computer's pointing device and, therefore, can receive drag, scroll, and flick gestures similar to those implemented on the computing devices described above equipped with touchscreen displays. The laptop computer 1300 typically includes a processor 1311 coupled to volatile memory 1312 and large-capacity nonvolatile memory, such as a flash memory disk drive 1313. Additionally, the computer 1300 may have one or more antennas 1308 for transmitting and receiving electromagnetic radiation, which may be connected to a wireless data link and / or a cellular telephone transceiver 1316 coupled to the processor 1311. The computer 1300 may also include a floppy disk drive 1314 and a compact disk (CD) drive 1315 coupled to the processor 1311. In a notebook configuration, the computer housing includes a touchpad 1317, a keyboard 1318, and a display 1319, all coupled to the processor 1311. Other configurations of computing devices may include a computer mouse or trackball coupled to the processor (e.g., via a USB input), as is well known, and may also be used with various embodiments.

[0127] Various embodiments (including, but not limited to, those described above with reference to FIGS. 1-11 ) may be implemented in a fixed computing system, such as any of a variety of commercially available servers. An exemplary server 1400 is shown in FIG. 14 . Such a server 1400 typically includes one or more multi-core processor assemblies 1401 coupled to volatile memory 1402 and large-capacity non-volatile memory, such as a disk drive 1404. As shown in FIG. 14 , multi-core processor assemblies 1401 may be added to the server 1400 by inserting them into a rack of assemblies. The server 1400 may also include a floppy disk drive, compact disk (CD), or digital versatile disk (DVD) disk drive 1406 coupled to the processor 1401. The server 1400 may also include a network access port 1403 coupled to the multi-core processor assembly 1401 for establishing a network interface connection with a network 1405, such as a local area network, the Internet, a public switched telephone network, and / or a cellular data network (e.g., CDMA, TDMA, GSM, PCS, 3G, 4G, LTE, or any other type of cellular data network) coupled to other broadcast system computers and servers.

[0128] In the following, further embodiments are described to facilitate understanding of the present invention.

[0129] Example 1: A multi-bit multiply-accumulate (MAC) comprising an analog adder having a first adder capacitor, the first adder capacitor configured to add the multiple single-bit MAC outputs by receiving multiple single-bit MAC outputs from multiple single-bit MACs and storing the multiple single-bit MAC outputs, and the analog adder configured to output a multi-bit MAC output based on adding the stored multiple single-bit MAC outputs.

[0130] Example 2: The multi-bit MAC of Example 1, wherein the plurality of single-bit MACs are each configured to sequentially multiply an individual bit of the first multi-bit value and a different single bit of the second multi-bit value, the first multi-bit value and the second multi-bit value being represented by digital voltages, and accumulating results of the multiplications to generate the plurality of single-bit MAC outputs, the plurality of single-bit MAC outputs being analog voltages.

[0131] Example 3: An analog adder further comprising a plurality of single-bit MAC switches, wherein a first single-bit MAC switch of the plurality of single-bit MAC switches is configured to selectively and electrically connect a first single-bit MAC of the plurality of single-bit MACs to a first adder capacitor as controlled by a control device, wherein the first adder capacitor receives the plurality of single-bit MAC outputs from the plurality of single-bit MACs, and wherein the first single-bit MAC switch receives the first single-bit MAC output of the plurality of single-bit MAC outputs from the first single-bit MAC in response to the first single-bit MAC switch selectively and electrically connecting the first single-bit MAC to the first adder capacitor; the analog adder further comprising an operational amplifier having an input end and an output end, wherein the first adder capacitor is electrically connected between the input end and the output end, and the operational amplifier is configured to input a first single-bit MAC output to the input end. and adding the plurality of single-bit MAC outputs to produce a weighted average of the plurality of single-bit MAC outputs, wherein the analog adder is configured such that adding the plurality of single-bit MAC outputs comprises adding the plurality of single-bit MAC outputs to produce a weighted average of the plurality of single-bit MAC outputs and storing the plurality of single-bit MAC outputs comprises storing the weighted average of the plurality of single-bit MAC outputs; and outputting the weighted average of the plurality of single-bit MAC outputs as an analog voltage to an analog-to-digital converter, wherein the analog adder is configured such that outputting the multi-bit MAC output comprises outputting the weighted average of the plurality of single-bit MAC outputs.

[0132] Example 4: The analog summer further comprises a plurality of designated capacitors, a first designated capacitor of the plurality of designated capacitors electrically connected between the first single-bit MAC switch and the first summer capacitor, and the first designated capacitor is r4. The multi-bit MAC of any of Examples 1, 2, or 3, having a capacitor rating of r where r is a position in a weight value of a bit to be multiplied with a bit of an activation value used in producing the first single-bit MAC output, the first designated capacitor being configured to receive the first single-bit MAC output, weight the first single-bit MAC output, and output the weighted first single-bit MAC output, wherein receiving the plurality of single-bit MAC outputs is configured to comprise receiving the weighted first single-bit MAC output, and summing the plurality of single-bit MAC outputs comprises summing the weighted first single-bit MAC output.

[0133] Example 5: A method for implementing an analog adder circuit, further comprising: a plurality of single-bit MAC switches; a first single-bit MAC switch of the plurality of single-bit MAC switches configured to selectively electrically connect a first single-bit MAC of the plurality of single-bit MACs to a first adder capacitor as controlled by a control device; and the analog adder further comprising a first adder capacitor associated with the first single-bit MAC, the first adder capacitor being 2 single-bit MACs. rwherein r is a position in a weight value of a bit to be multiplied with a bit of an activation value used in producing the first single-bit MAC output by the first single-bit MAC, and the first adder capacitor is configured such that receiving the plurality of single-bit MAC outputs from the plurality of single-bit MACs comprises receiving a first single-bit MAC output of the plurality of single-bit MAC outputs from the first single-bit MAC in response to the first single-bit MAC switch selectively and electrically connecting the first single-bit MAC and the first adder capacitor, and the first adder capacitor is further configured to weight the first single-bit MAC output, and the analog adder is configured such that storing the plurality of single-bit MAC outputs comprises storing the weighted first single-bit MAC output. and a plurality of adder switches configured to selectively and electrically connect the first adder capacitor to the first single-bit MAC via the first single-bit MAC switch as controlled by the control device, and a second adder switch of the plurality of adder switches configured to selectively and electrically connect a second adder capacitor of the plurality of adder capacitors to the electrically conductive bus as controlled by the control device, outputting the weighted first single-bit MAC output from the first adder capacitor and producing a weighted average of the plurality of weighted single-bit MAC outputs, including the weighted first single-bit MAC output; and the multi-bit MAC of either Example 1 or 2, wherein the analog adder is configured such that outputting the multi-bit MAC output comprises outputting the weighted average of the plurality of weighted single-bit MAC outputs.

[0134] Example 6: The multi-bit MAC of Example 5, further comprising a buffer electrically coupled between the plurality of single-bit MAC switches and the plurality of adder switches.

[0135] Example 7: An analog adder further comprising a plurality of single-bit MAC switches, wherein a first single-bit MAC switch of the plurality of single-bit MAC switches is configured to selectively and electrically connect a first single-bit MAC of the plurality of single-bit MACs to a first adder capacitor as controlled by a control device, wherein the first adder capacitor receives a plurality of single-bit MAC outputs from the plurality of single-bit MACs, and wherein the first single-bit MAC switch receives a first single-bit MAC output of the plurality of single-bit MAC outputs from the first single-bit MAC in response to the first single-bit MAC switch selectively and electrically connecting the first single-bit MAC to the first adder capacitor; the analog adder further comprising a first adder switch of the plurality of adder switches associated with the first adder capacitor, and a second adder capacitor, wherein the second adder capacitor is associated with a second adder switch of the plurality of adder switches, and 3. The multi-bit MAC of any of Examples 1 or 2, wherein the multi-bit MAC capacitors have the same capacitor rating; the first adder switch is configured to selectively and electrically connect the first adder capacitor to the plurality of single-bit MAC outputs via the plurality of single-bit MAC switches as controlled by the control device and to selectively and electrically connect the first adder capacitor to an electrically conductive bus as controlled by the control device; the second adder switch is configured to selectively and electrically connect the second adder capacitor to the electrically conductive bus and to selectively and electrically connect the second adder capacitor that outputs the shared plurality of single-bit MAC outputs to an analog-to-digital converter at the same time as the first adder capacitor shares the plurality of single-bit MAC outputs between the first adder capacitor and the second adder capacitor as controlled by the control device; and wherein outputting the multi-bit MAC output comprises outputting the shared plurality of single-bit MAC outputs.

[0136] Example 8: The multi-bit MAC of Example 7, wherein the analog adder further comprises a buffer electrically coupled between the plurality of single-bit MAC switches and the plurality of adder switches.

[0137] Example 9: An analog adder further comprising a plurality of single-bit MAC switches, wherein a first single-bit MAC switch of the plurality of single-bit MAC switches is configured to selectively and electrically connect a first single-bit MAC of the plurality of single-bit MACs to a first adder capacitor as controlled by a control device, wherein the first adder capacitor is configured to receive a plurality of single-bit MAC outputs from the plurality of single-bit MACs, and wherein the first single-bit MAC switch is configured to selectively and electrically connect the first single-bit MAC to the first adder capacitor, and wherein the first adder capacitor is configured to receive a first single-bit MAC output of the plurality of single-bit MAC outputs from the first single-bit MAC in response to the first single-bit MAC switch selectively and electrically connecting the first single-bit MAC to the first adder capacitor; 3. The multi-bit MAC of either Example 1 or 2, comprising: a second adder capacitor, wherein the first adder capacitor and the second adder capacitor have the same rated capacitance; and a adder switch configured to selectively electrically connect the first adder capacitor and the second adder capacitor as controlled by the control device, sharing the plurality of single-bit MAC outputs between the first adder capacitor and the second adder capacitor; wherein the second adder capacitor is configured to output the shared plurality of single-bit MAC outputs to the analog-to-digital converter; and wherein the analog adder is configured such that outputting the multi-bit MAC output comprises outputting the shared plurality of single-bit MAC outputs.

[0138] Further examples include methods of performing the operations of the device functions summarized in any of Examples 1, 2, 3, 4, 5, 6, 7, 8, or 9. Further examples include multi-bit MACs having means for performing any of the functions of the device functions summarized in any of Examples 1, 2, 3, 4, 5, 6, 7, 8, or 9.

[0139] Example 10: A multi-bit MAC comprising an analog adder having a plurality of adder capacitors including a first adder capacitor, and a plurality of single-bit MAC switches including a first single-bit MAC switch configured to selectively and electrically connect a first single-bit MAC of a plurality of single-bit multiply-accumulate units (MACs) to the first adder capacitor as controlled by a control device, wherein the first adder capacitor is configured to add the first plurality of single-bit MAC outputs by receiving the first plurality of single-bit MAC outputs from the first single-bit MAC in response to the first single-bit MAC switch selectively and electrically connecting the first single-bit MAC to the first adder capacitor and by storing the first plurality of single-bit MAC outputs, and the analog adder is configured to output a multi-bit MAC output based on the addition of the stored first plurality of single-bit MAC outputs.

[0140] Example 11: The plurality of adder capacitors further comprises a second adder capacitor and a third adder capacitor, wherein a combined rated capacitance of the pair of the second adder capacitor and the third adder capacitor is the same as the rated capacitance of the first adder capacitor, and the analog adder further comprises: a first adder switch configured to selectively and electrically connect the first adder capacitor and the second adder capacitor as controlled by a control device, which shares the first plurality of single-bit MAC outputs between the first adder capacitor and the second adder capacitor; and a second adder switch configured to selectively and electrically connect the second adder capacitor and the third adder capacitor as controlled by the control device, which shares the first plurality of single-bit MAC outputs shared between the second adder capacitor and the third adder capacitor, wherein the third adder capacitor is configured to weight the shared first plurality of single-bit MAC outputs. and a third adder switch configured to selectively electrically connect the third adder capacitor that outputs the weighted shared first plurality of single-bit MAC outputs to the analog-to-digital converter via the electrically conductive bus as controlled by the control device, at the same time that another third adder capacitor of the plurality of adder capacitors that outputs the weighted shared second plurality of single-bit MAC outputs to the analog-to-digital converter via the electrically conductive bus combines the weighted shared first plurality of single-bit MAC outputs and the weighted shared second plurality of single-bit MAC outputs into a weighted average of the shared plurality of single-bit MAC outputs, wherein the analog adder is configured such that outputting the multi-bit MAC output comprises outputting a weighted average of the shared plurality of single-bit MAC outputs.

[0141] Example 12: The multi-bit MAC of Example 10, wherein the plurality of adder capacitors further comprises a second adder capacitor, and wherein the analog adder further comprises a plurality of adder switches, including: a first adder switch configured to selectively and electrically connect the first adder capacitor and the second adder capacitor as controlled by the control device, sharing the first plurality of single-bit MAC outputs between the first adder capacitor and the second adder capacitor; and a second adder switch configured to selectively and electrically connect the second adder capacitor to another second adder capacitor as controlled by the control device via an electrically conductive bus.

[0142] Example 13: The multi-bit MAC of Example 12, wherein the first adder switch is configured to share the first plurality of single-bit MAC outputs between the first adder capacitor and the second adder capacitor, selectively and electrically connecting the first adder capacitor and the second adder capacitor as controlled by the control device comprises dividing the first plurality of single-bit MAC outputs in half for each of the first adder capacitor and the second adder capacitor, the analog adder is further configured to clear the first adder capacitor of half of the first plurality of single-bit MAC outputs, and the first adder switch is further configured to share the first half of the first plurality of single-bit MAC outputs between the first adder capacitor and the second adder capacitor, dividing the half of the first plurality of single-bit MAC outputs in half for each of the first adder capacitor and the second adder capacitor to produce a plurality of quarters of the first plurality of single-bit MAC outputs.

[0143] Example 14: The multi-bit MAC of either Example 12 or 13, wherein the plurality of adder switches further comprises another first adder switch, the another first adder switch configured to selectively and electrically connect the another first adder capacitor and the another second adder capacitor as controlled by the control device, while the second adder switch selectively and electrically connects the second adder capacitor and the another second adder capacitor.

[0144] Example 15: The multi-bit MAC of either Example 12 or 13, wherein the plurality of adder switches further comprises another first adder switch, the another first adder switch configured to selectively electrically disconnect the another first adder capacitor and the another second adder capacitor as controlled by the control device, while the second adder switch selectively electrically connects the second adder capacitor and the another second adder capacitor.

[0145] Further examples include methods of performing the operations of the device functions summarized in any of Examples 10, 11, 12, 13, 14, or 15. Further examples include multi-bit MACs having means for performing any of the functions of the device functions summarized in any of the Examples.

[0146] Computer program code or "program code" for execution on a programmable processor to perform operations of various embodiments may be written in a high-level programming language such as C, C++, C#, Smalltalk, Java, JavaScript, Visual Basic, Structured Query Language (e.g., Transact-SQL), Perl, or a variety of other programming languages. Program code or program stored on a computer-readable storage medium as used in this application may refer to machine code (such as object code) whose format is understandable by a processor.

[0147] The above method descriptions and process flow diagrams are provided merely as illustrative examples and do not require or imply that the operations of the various embodiments must be performed in the order presented. As will be understood by one of ordinary skill in the art, the order of operations in the above-described embodiments may be performed in any order. Words such as "then," "then," and "next" do not limit the order of operations; these words are merely used to guide the reader through the method descriptions. Furthermore, any reference to a claim element in the singular, for example, using the article "a," "an," or "the," should not be construed as limiting the element to the singular.

[0148] The various illustrative logical blocks, modules, circuits, and algorithmic operations described in connection with the various embodiments may be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability of hardware and software, the various illustrative components, blocks, modules, circuits, and operations have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the particular application and design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the claims.

[0149] The hardware used to implement the various exemplary logic, logic blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed using general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. Alternatively, some operations or methods may be performed by circuitry specific to a given function.

[0150] In one or more embodiments, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored as one or more instructions or code on a non-transitory computer-readable or processor-readable medium. The operations of a method or algorithm disclosed herein may be embodied in a processor-executable software module that may reside on a non-transitory computer-readable or processor-readable storage medium. A non-transitory computer-readable or processor-readable storage medium may be any storage medium that can be accessed by a computer or processor. By way of example and not limitation, such non-transitory computer-readable or processor-readable medium may include RAM, ROM, EEPROM, FLASH memory, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. As used herein, disk and disc include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically and discs reproduce data optically using lasers. Combinations of the above are also included within the scope of non-transitory computer-readable medium and non-transitory processor-readable medium. Additionally, the operations of a method or algorithm may reside as one or any combination or set of code and / or instructions on a non-transitory processor-readable medium and / or a non-transitory computer-readable medium, which may be incorporated into a computer program product.

[0151] The foregoing description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the claims. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and implementations without departing from the scope of the claims. Thus, the present disclosure is not intended to be limited to the embodiments and implementations described herein, but is to be accorded the widest scope consistent with the claims and the principles and novel features disclosed herein. [Explanation of symbols]

[0152] 100 computing devices 102 SoC 104 processors 106 memory 108 Communication Interface 110 Memory Interface 112 Communication Components 114 memory 116 Antenna 120 Peripheral Device Interface 122 Peripheral Devices 124 MAC Controller 126 Single-bit MAC 128 Analog Adder 130 Multi-bit MAC 200 Multi-bit MAC 202 Sequential Input 204 Activation Value 206 Single-bit MAC 208 Successive integrator 210 Multi-bit Weight Processing Unit 212 Analog-to-Digital Converter (ADC) 304 Single-bit MAC Switch 306 Electrical Conduction Bus 308 Clear Switch 310 Ground 312 Operational Amplifier 314 Integrator Capacitor 316 Electrical Conduction Bus 402 Capacitor 502 buffers 504 Adder Switch 506 Adder Capacitor 508 Ground 604 Adder Switch 606 Adder Capacitor 702 Adder Switch 904 Adder Capacitor 906 Adder Capacitor 908 Adder Switch 910 Adder Switch 912 Adder Switch 1002 Adder Capacitor 1004 Adder Switch 1006 Adder Switch 1008 Output Switch 1010 Clear Switch 1012 Ground 1014 Clear Switch 1016 Clear Switch 1200 Mobile Computing Devices 1202 processor 1204 Touchscreen Controller 1206 internal memory 1208 Radio Signal Transceiver 1210 Antenna 1212 Touch Screen Panel 1214 Speaker 1216 Cellular Network Wireless Modem Chip 1218 Peripheral device connection interface 1220 Housing 1222 Power supply 1224 Physical Buttons 1226 Power Button 1300 laptop computer 1308 Antenna 1311 processor 1312 Volatile Memory 1313 Disk Drive 1314 Floppy disk drive 1315 Compact Disc (CD) Drive 1316 Cellular Telephone Transceiver 1317 Touchpad touch surface, touchpad 1318 keyboard 1319 Display 1400 Server 1401 Multi-Core Processor Assembly 1402 Volatile Memory 1403 Network Access Port 1404 disk drive 1405 Network 1406 Digital Versatile Disc (DVD) Disc Drive

Claims

1. 1. A multi-bit multiply-accumulate (MAC) unit comprising an analog adder having a first adder capacitor and a plurality of single-bit MAC switches, the first adder capacitor: Receives multiple single-bit MAC outputs from multiple single-bit MACs, storing said plurality of single-bit MAC outputs; and configured to add the plurality of single-bit MAC outputs by the analog adder is configured to output a multi-bit MAC output based on adding the stored plurality of single-bit MAC outputs; a first single-bit MAC switch of the plurality of single-bit MAC switches configured to selectively electrically connect a first single-bit MAC of the plurality of single-bit MACs to the first adder capacitor as controlled by a control device; the first adder capacitor is configured to receive the plurality of single-bit MAC outputs from a plurality of single-bit MACs in response to the first single-bit MAC switch selectively electrically connecting the first single-bit MAC and the first adder capacitor, comprising receiving a first single-bit MAC output of the plurality of single-bit MAC outputs from the first single-bit MAC; The analog summer further comprises an operational amplifier having an input and an output, the first summer capacitor being electrically connected between the input and the output, the operational amplifier comprising: receiving the plurality of single-bit MAC outputs at the input; adding the plurality of single-bit MAC outputs to produce a weighted average of the plurality of single-bit MAC outputs; The analog adder adding a plurality of single-bit MAC outputs comprises adding the plurality of single-bit MAC outputs to produce the weighted average of the plurality of single-bit MAC outputs; Storing the plurality of single-bit MAC outputs comprises storing the weighted average of the plurality of single-bit MAC outputs. and adding, outputting the weighted average of the plurality of single-bit MAC outputs as an analog voltage to an analog-to-digital converter, wherein the analog summer is configured such that outputting a multi-bit MAC output comprises outputting the weighted average of the plurality of single-bit MAC outputs; configured to: Multi-bit MAC.

2. the analog adder further comprising: a plurality of designated capacitors, a first designated capacitor of the plurality of designated capacitors electrically connected between the first single-bit MAC switch and the first adder capacitor, the first designated capacitor being r where r is the position in the weight value of the bit that is multiplied with the bit of the activation value used in producing the first single-bit MAC output, and the first designated capacitor has a capacitor rating of receiving the first single-bit MAC output; weighting the first single-bit MAC output; outputting the weighted first single-bit MAC output, wherein the operational amplifier further comprises: receiving the plurality of single-bit MAC outputs comprises receiving the weighted first single-bit MAC output. It is configured to output configured to:

2. The multi-bit MAC of claim 1, wherein adding the plurality of single-bit MAC outputs comprises adding the weighted first single-bit MAC outputs.

3. A method of multi-bit multiplication and accumulation, comprising: Receives multiple single-bit multiply-accumulate (MAC) outputs from multiple single-bit MACs; storing said plurality of single-bit MAC outputs; adding the plurality of single-bit MAC outputs by a first adder capacitor of an analog adder by and outputting a multi-bit MAC output based on the summation of the stored single-bit MAC outputs by the analog adder; The method further comprises: selectively electrically connecting a first single-bit MAC of the plurality of single-bit MACs to the first adder capacitor by a first single-bit MAC switch; receiving the plurality of single-bit MAC outputs from a plurality of single-bit MACs comprises receiving a first single-bit MAC output of the plurality of single-bit MAC outputs from the first single-bit MAC in response to selectively electrically connecting the first single-bit MAC and the first adder capacitor; Steps and receiving the plurality of single-bit MAC outputs at an input of an operational amplifier of the analog summer; adding the plurality of single-bit MAC outputs to produce a weighted average of the plurality of single-bit MAC outputs; adding a plurality of single-bit MAC outputs comprises adding the plurality of single-bit MAC outputs to produce the weighted average of the plurality of single-bit MAC outputs; storing the plurality of single-bit MAC outputs comprises storing the weighted average of the plurality of single-bit MAC outputs. Steps and outputting the weighted average of the plurality of single-bit MAC outputs as an analog voltage to an analog-to-digital converter; outputting a multi-bit MAC output comprises outputting the weighted average of the plurality of single-bit MAC outputs. method.

4. 1. A multi-bit multiply-accumulate (MAC) unit comprising an analog adder, the analog adder comprising: a plurality of adder capacitors, including a first adder capacitor; a plurality of single-bit MAC switches, including a first single-bit MAC switch configured to selectively electrically connect a first single-bit MAC of the plurality of single-bit MACs to the first adder capacitor, as controlled by a control device; the first adder capacitor: receiving a first plurality of single-bit MAC outputs from the first single-bit MAC in response to the first single-bit MAC switch selectively electrically connecting the first single-bit MAC and the first adder capacitor; Storing the first plurality of single-bit MAC outputs configured to sum the first plurality of single-bit MAC outputs by The multi-bit MAC, wherein the analog adder is configured to output a multi-bit MAC output based on adding the stored first plurality of single-bit MAC outputs.

5. the plurality of adder capacitors further comprises a second adder capacitor and a third adder capacitor, and a combined rated capacitance of the pair of the second adder capacitor and the third adder capacitor is the same as a rated capacitance of the first adder capacitor; the analog adder further comprising: a first adder switch configured to selectively electrically connect the first adder capacitor and the second adder capacitor as controlled by the control device, the first adder switch sharing the first plurality of single-bit MAC outputs between the first adder capacitor and the second adder capacitor; a second adder switch configured to selectively electrically connect the second adder capacitor and the third adder capacitor that share the shared first plurality of single-bit MAC outputs between the second adder capacitor and the third adder capacitor as controlled by the control device, wherein the third adder capacitor is configured to weight the shared first plurality of single-bit MAC outputs; a third adder switch configured to selectively electrically connect the third adder capacitor that outputs the weighted shared first plurality of single-bit MAC outputs to the analog-to-digital converter via the electrically conductive bus as controlled by the control device, at the same time as another third adder capacitor of the plurality of adder capacitors that outputs the weighted shared second plurality of single-bit MAC outputs to the analog-to-digital converter combines the weighted shared first plurality of single-bit MAC outputs and the weighted shared second plurality of single-bit MAC outputs into a weighted average of the shared plurality of single-bit MAC outputs; and a plurality of adder switches, including 5. The multi-bit MAC of claim 4, wherein the analog adder is configured such that outputting a multi-bit MAC output comprises outputting the weighted average of the shared single-bit MAC outputs.

6. the plurality of adder capacitors further comprising a second adder capacitor; the analog adder further comprising: a first adder switch configured to selectively electrically connect the first adder capacitor and the second adder capacitor as controlled by the control device, the first adder switch sharing the first plurality of single-bit MAC outputs between the first adder capacitor and the second adder capacitor; a second adder switch configured to selectively electrically connect the second adder capacitor to another second adder capacitor as controlled by the control device via an electrically conductive bus; and 5. The multi-bit MAC of claim 4, comprising a plurality of adder switches, including:

7. the first adder switch is configured to share the first plurality of single-bit MAC outputs between the first adder capacitor and the second adder capacitor, and selectively electrically connecting the first adder capacitor and the second adder capacitor as controlled by the control device comprises dividing the first plurality of single-bit MAC outputs in half for each of the first adder capacitor and the second adder capacitor; the analog summer is further configured to clear the first summer capacitor of the half of the first plurality of single-bit MAC outputs; 7. The multi-bit MAC of claim 6, wherein the first adder switch is further configured to selectively electrically connect the first adder capacitor and the second adder capacitor as controlled by the control device to share the half of the first plurality of single-bit MAC outputs between the first adder capacitor and the second adder capacitor, and divide the half of the first plurality of single-bit MAC outputs in half for each of the first adder capacitor and the second adder capacitor, producing multiple quarters of the first plurality of single-bit MAC outputs.

8. 7. The multi-bit MAC of claim 6, wherein the plurality of adder switches further comprises another first adder switch configured to selectively electrically connect another first adder capacitor and the another second adder capacitor as controlled by the control device, while the second adder switch selectively electrically connects the second adder capacitor and the another second adder capacitor.

9. 7. The multi-bit MAC of claim 6, wherein the plurality of adder switches further comprises another first adder switch configured to selectively electrically disconnect another first adder capacitor from the another second adder capacitor as controlled by the control device, while the second adder switch selectively electrically connects the second adder capacitor to the another second adder capacitor.

10. 1. A method of multi-bit multiplication and accumulation, comprising: selectively electrically connecting, by a first single-bit multiply-accumulate (MAC) switch of the plurality of single-bit MAC switches, a first single-bit MAC of the plurality of single-bit MACs and a first adder capacitor of the plurality of adder capacitors; receiving a first plurality of single-bit MAC outputs from the first single-bit MAC in response to the first single-bit MAC switch selectively electrically connecting the first single-bit MAC and the first adder capacitor; storing the first plurality of single-bit MAC outputs; adding the first plurality of single-bit MAC outputs by and outputting a multi-bit MAC output based on summing the stored first plurality of single-bit MAC outputs.

11. selectively electrically connecting the first adder capacitor and the second adder capacitor of the plurality of adder capacitors by a first adder switch of a plurality of adder switches, the first adder capacitor and the second adder capacitor sharing the first plurality of single-bit MAC outputs between the first adder capacitor and the second adder capacitor; selectively and electrically connecting the second adder capacitor and the third adder capacitor of the plurality of adder capacitors, which share the shared first plurality of single-bit MAC outputs between the second adder capacitor and a third adder capacitor, by a second adder switch of the plurality of adder switches, wherein a combined rated capacitance of the pair of the second adder capacitor and the third adder capacitor is the same as a rated capacitance of the first adder capacitor; weighting the shared first plurality of single-bit MAC outputs by the third adder capacitor; a third adder capacitor of the plurality of adder capacitors that outputs the weighted shared second plurality of single-bit MAC outputs to an analog-to-digital converter via an electrically conductive bus combines the weighted shared first plurality of single-bit MAC outputs and the weighted shared second plurality of single-bit MAC outputs into a weighted average of the shared plurality of single-bit MAC outputs; and selectively electrically connecting the third adder capacitor that outputs the weighted shared first plurality of single-bit MAC outputs to the analog-to-digital converter via the electrically conductive bus with a third adder switch of the plurality of adder switches; 11. The method of claim 10, wherein outputting a multi-bit MAC output comprises outputting the weighted average of the shared single-bit MAC outputs.

12. selectively electrically connecting the first adder capacitor and the second adder capacitor of the plurality of adder capacitors by a first adder switch of a plurality of adder switches, the first adder capacitor and the second adder capacitor sharing the first plurality of single-bit MAC outputs between the first adder capacitor and the second adder capacitor; and selectively electrically connecting, by a second adder switch of the plurality of adder switches, the second adder capacitor to another second adder capacitor of the plurality of adder capacitors via an electrically conductive bus.

13. selectively electrically connecting the first adder capacitor and the second adder capacitor to share the first plurality of single-bit MAC outputs between the first adder capacitor and the second adder capacitor comprises dividing the first plurality of single-bit MAC outputs in half for each of the first adder capacitor and the second adder capacitor; The method further comprises: clearing the first adder capacitors of the half of the first plurality of single-bit MAC outputs; 13. The method of claim 12, comprising selectively electrically connecting the first adder capacitor and the second adder capacitor as controlled by the first adder switch to share the half of the first plurality of single-bit MAC outputs between the first adder capacitor and the second adder capacitor, and dividing the half of the first plurality of single-bit MAC outputs in half for each of the first adder capacitor and the second adder capacitor to produce multiple quarters of the first plurality of single-bit MAC outputs.

14. 13. The method of claim 12, further comprising: selectively and electrically connecting another first adder capacitor of the plurality of adder capacitors to the another second adder capacitor by another first adder switch of the plurality of adder switches while the second adder switch selectively and electrically connects the second adder capacitor to the another second adder capacitor.

15. 13. The method of claim 12, further comprising: selectively electrically disconnecting another first adder capacitor of the plurality of adder capacitors from the another second adder capacitor by another first adder switch of the plurality of adder switches while the second adder switch selectively electrically connects the second adder capacitor to the another second adder capacitor.

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