Backside power supply network

Abstract

The assembly may include a reconfiguration element having a front surface and a back surface, the reconfiguration element having a semiconductor die having a front side and a back side, the semiconductor die having circuit components located closer to the front side than the back side and vias extending from the back side of the semiconductor die to connect to the circuit components, the reconfiguration element having insulating material disposed along a side of the semiconductor die, power rails extending from the front surface to the back side of the reconfiguration element and also configured to supply power to the semiconductor die, and interconnect structures electrically connecting the power rails to the vias and configured to supply power to the semiconductor die from the back side of the semiconductor die.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE The present disclosure relates to semiconductor device structures. Some embodiments relate to backside power supplies.

[0002] [Incorporation by reference of prior application] Any and all applications for which a claimed invention, whether foreign or domestic, is claimed, is identified in an Application Data Sheet filed with this application, and the entire contents of such applications are incorporated herein by reference under 37 CFR 1.57.

[0003] This application is a pro rata application of U.S. Provisional Patent Application No. 63 / 385,754, filed December 1, 2022, which is incorporated by reference in its entirety. [Background technology]

[0004] The approaches described in this section are approaches that could be pursued, but not necessarily approaches that had previously been conceived or pursued. Thus, unless otherwise indicated, it should not be assumed that any of the approaches described in this section qualify as prior art merely by virtue of their incorporation into this section.

[0005] As features in semiconductor devices continue to shrink, power delivery issues become increasingly concerning because it becomes difficult to efficiently deliver power to semiconductor devices due to electrical isolation issues, feature size constraints, losses due to traversing multiple metal layers, etc. Backside power delivery schemes alleviate the problem by separating the power delivery from the signal routing. However, backside power delivery schemes present several challenges, and they can significantly complicate the manufacturing process. Summary of the Invention

[0006] The systems, methods, and devices described herein each have several aspects, no single one of which is solely responsible for its desirable attributes. Without limiting the scope of the disclosure, some non-limiting features will now be broadly described.

[0007] In some aspects, the technology described herein relates to an assembly including a reconfiguration element having a front surface and a back surface, the reconfiguration element having a semiconductor die having a front side and a back side, the semiconductor die having circuit components located closer to the front side than the back side and vias extending from the back side of the semiconductor die to connect to the circuit components, the reconfiguration element having insulating material disposed along a side of the semiconductor die, a power rail extending from the front surface to the back side of the reconfiguration element and also configured to supply power to the semiconductor die, and an interconnect structure electrically connecting the power rail to the via and configured to supply power to the semiconductor die from the back side of the semiconductor die.

[0008] In some aspects, the technology described herein relates to an assembly characterized in that the insulating material comprises an inorganic dielectric.

[0009] In some aspects, the technology described herein relates to an assembly characterized in that the insulating material comprises silicon oxide.

[0010] In some aspects, the technology described herein relates to an assembly characterized in that the insulating material comprises an organic dielectric.

[0011] In some aspects, the technology described herein relates to an assembly in which the interconnect structure comprises a redistribution layer disposed on a backside of the reconfigurable element.

[0012] In some aspects, the technology described herein relates to an assembly in which the interconnect structure comprises interconnect elements hybrid bonded to the backside of a semiconductor die.

[0013] In some aspects, the technology described herein relates to assemblies characterized in that the interconnect structure is comprised of one or more metallization layers.

[0014] In some aspects, the technology described herein relates to an assembly further including a power supply die, the power supply die being hybrid bonded to a backside of the reconfiguration element.

[0015] In some aspects, the technology described herein relates to an assembly in which the power supply die is characterized by a redistribution layer.

[0016] In some aspects, the technology described herein relates to an assembly characterized in that the reconfiguration element further comprises an integrated voltage regulator.

[0017] In some aspects, the technology described herein relates to an assembly further including a dummy die, the dummy die being directly bonded to a backside of the reconfiguration element.

[0018] In some aspects, the technology described herein relates to an assembly further including a second reconfigurable element, the second reconfigurable element having an integrated voltage regulator and an integrated power supply circuit component, and the second reconfigurable element being hybrid bonded to the reconfigurable element.

[0019] In some aspects, the technology described herein relates to an assembly further including a dummy die, the dummy die being directly bonded to the second reconfigurable element.

[0020] In some aspects, the technology described herein relates to an assembly further including a stack, the stack having a dummy die directly bonded to the second reconfigurable element.

[0021] In some aspects, the technology described herein relates to an assembly further comprising an integrated voltage regulator hybrid-bonded to the reconfigurable element.

[0022] In some aspects, the technology described herein relates to an assembly in which the reconfigurable element further comprises a dummy semiconductor element, and the power rail is provided within the dummy semiconductor element.

[0023] In some aspects, the technology described herein relates to an assembly, wherein the reconfiguration element further comprises an integrated voltage regulator, and the assembly further comprises a power supply die, the power supply die comprising one or more memory banks.

[0024] In some aspects, the technology described herein relates to an assembly further including an optical input / output system, the optical input / output system being bonded to a surface of the reconfigurable element.

[0025] In some aspects, the technology described herein relates to an assembly further including a second reconfigurable element hybrid-bonded to the reconfigurable element, the second reconfigurable element having integrated power supply circuitry, one or more memory banks, and one or more integrated voltage regulators.

[0026] In some aspects, the technology described herein relates to assemblies characterized in that the circuit components consist of one or more transistors.

[0027] In some aspects, the technology described herein relates to assemblies characterized in that the semiconductor die has a thickness of less than 5 μm.

[0028] In some aspects, the technology described herein relates to assemblies in which the semiconductor die is characterized by a thickness of less than 1 μm.

[0029] In some aspects, the technology described herein relates to an assembly characterized in that the semiconductor die is a logic die or a processor die.

[0030] In some aspects, the technology described herein relates to an assembly including an insulating material, including a power rail extending through the insulating material, and including an integrated device die at least partially embedded in the insulating material, the integrated device die having a front side and a back side, the integrated device die having power supply structures extending from the back side of the semiconductor die to connect to circuit components and circuit components located closer to the front side than the back side, the assembly including the insulating material, the power rail, and an interconnect structure deposited on the back side of the integrated device die, the interconnect structure providing power between the power rail and the power supply structure at the back side of the integrated device die.

[0031] In some aspects, the technology described herein relates to an assembly characterized in that the insulating material comprises an inorganic dielectric.

[0032] In some aspects, the technology described herein relates to an assembly further comprising a power supply die hybrid bonded to the interconnect structure.

[0033] In some aspects, the technology described herein relates to an assembly further including a dummy die, the dummy die being direct bonded to the interconnect structure.

[0034] In some aspects, the technology described herein relates to a method of forming a bonded structure with a backside power supply, the method including forming a bonding surface on a backside of a reconfiguration element, the reconfiguration element having a front side and a back side, the reconfiguration element having a semiconductor die having a front side and a back side, the semiconductor die having circuit components located closer to the front side than the back side and vias extending from the backside of the semiconductor die to connect to the circuit components, the reconfiguration element having insulating material along a side of the semiconductor die, power rails extending from the front side to the backside of the reconfiguration element and also configured to supply power to the semiconductor die, and interconnect structures electrically connecting the power rails to the vias and configured to supply power to the semiconductor die from the backside of the semiconductor die, the method further including direct-bonding a second element to the bonding surface of the reconfiguration element.

[0035] In some aspects, the technology described herein relates to a method wherein the second device comprises an integrated voltage regulator.

[0036] These and other features, aspects, and advantages of the present disclosure will be described with reference to the drawings of certain embodiments, which are intended to illustrate, but not limit, the present disclosure. It should be understood that the accompanying drawings, which are incorporated into and form a part of this specification, are for the purpose of illustrating the concepts disclosed herein and are not drawn to scale. [Brief explanation of the drawings]

[0037] [Figure 1A] FIG. 1 is a side view of an exemplary device according to some embodiments. [Figure 1B] FIG. 1 is a rear view of an exemplary device according to some embodiments. [Figure 1C] FIG. 1 is a side view of an exemplary device according to some embodiments. [Figure 2] FIG. 1 illustrates an exemplary device having a power supply according to some embodiments. [Figure 3] FIG. 1 illustrates an example device with a dummy die according to some embodiments. [Figure 4] FIG. 1 illustrates an example device having a reconfigurable power supply layer and a dummy die according to some embodiments. [Figure 5] FIG. 1 illustrates an example device having a power supply layer and a dummy die according to some embodiments. [Figure 6] FIG. 1 illustrates an example device having a memory bank layer according to some embodiments. [Figure 7] 1 illustrates a device with a reconfigurable power supply layer including a memory bank layer and a dummy die according to some embodiments. [Figure 8] 1 is a flow chart illustrating an example process for manufacturing an assembly including a backside power supply according to some embodiments. [Figure 9A] FIG. 1 is a diagram illustrating a direct bonding process according to some embodiments. [Figure 9B] FIG. 1 is a diagram illustrating a direct bonding process according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0038] Although several embodiments, examples, and illustrations are disclosed below, those skilled in the art will understand that the invention described herein extends beyond the specifically disclosed embodiments, examples, and illustrations and also includes other uses of the invention and obvious modifications and equivalents thereof. Examples of the invention are described with reference to the drawings of the invention, where like reference numerals refer to like elements throughout the specification. The terminology used in the description provided herein is not intended to be construed in any limited or restrictive manner, simply because it is used in connection with the detailed description of several specific embodiments of the invention. In addition, embodiments of the invention may have several novel features, and no single feature is responsible for desirable attributes or is essential to practicing the invention described herein.

[0039] In conventional semiconductor devices, both signal transmission and power delivery are achieved through the front side of the device. As device features continue to shrink, it becomes increasingly difficult to provide both power and signals through the front side of the device without adversely affecting device performance. For example, as semiconductor devices increase in density and complexity, the number of metal layers containing signal and power lines also tends to increase, effectively increasing the length of the wires and reducing the size (e.g., cross-sectional area) of the interconnects that deliver power to transistors. This can result in significant power losses due to the high resistance of the thin copper commonly used for front-side power delivery. For example, a typical device may be designed to tolerate a power delivery loss (e.g., voltage drop) of approximately 10%. However, large voltage drops can be seen at smaller manufacturing nodes and when many (e.g., approximately 10, 15, 20, or more) metal layers are present. In some processes, metal interconnects may be made of alternative materials, such as cobalt or tungsten, at lower back-end-of-line (BEOL) levels, which can reduce losses, but the benefits of using other conductive materials may be limited and a fundamentally different approach may be required. However, power lines occupy a significant amount of space on the front side of the chip and device, effectively increasing device cell size and chip size.

[0040] A backside power distribution scheme can alleviate some of the issues associated with scaling semiconductor devices to smaller process nodes, including reduced on-chip IR drop, scaling chip area, and reduced back-end-of-line (BEOL) complexity. For example, a backside power distribution scheme can reduce frontside congestion by eliminating or reducing the need to route power through the frontside. A backside power distribution scheme allows shorter, wider, and thicker lines (which can have lower resistance than longer, thinner lines) to be used for power distribution, thereby reducing power distribution losses. A backside power distribution scheme can also achieve significant space savings and facilitate increased density. Additionally, a backside power distribution scheme can improve signal integrity because the power distribution is relatively far from the signal transmission, thereby reducing the risk of the power distribution interfering with signal transmission.

[0041] While backside power delivery offers many potential benefits, significant challenges, such as extreme substrate thinning (e.g., less than 1 μm), backside-to-frontside alignment, and heat dissipation, may arise with the fabrication of backside-powered devices, due in part to the device silicon being sandwiched between dielectric layers to enable frontside signal routing and backside power routing. For example, backside power delivery implementations may use direct bonding, which may introduce distortion or warpage into the structure and complicate subsequent processing. Material choices for vias may be limited because backside power delivery components may be formed relatively early in the manufacturing process, potentially before front-end-of-line (FEOL) processing is complete. Thus, it may be impractical or impossible to use some materials, such as copper, and it may be important to select materials that can withstand the high processing temperatures used in pre-processing high-quality semiconductor devices in advanced manufacturing processes.

[0042] Some embodiments herein can provide front-side package-level access for power and ground (earth) rails and signal lines, while providing a backside power supply to the device die. In some embodiments, relatively large power and / or ground rails can be provided outside the die footprint, thereby enabling power delivery from the front of the package to the second backside without significant voltage drop. In some embodiments, the backside power lines may be accessible to allow efficient heat extraction of heat generated during operation. In some embodiments, power and / or ground rails can be provided outside the die area using a reconfiguration approach. In some embodiments, integrated voltage regulators, passives, etc. can have different dimensions than the device die, making reconfiguration wafers or elements particularly attractive. As used herein, the term "power" can be interpreted to include positive potential, negative potential, and / or zero potential (e.g., ground), unless the context clearly indicates otherwise.

[0043] As described herein and in the accompanying drawings, in some backside power supply embodiments, direct bonding and / or direct hybrid bonding can be used to form semiconductor device assemblies with backside power supplies and / or other features, as described in detail herein. While the examples herein show direct or direct hybrid bonds at specific locations within a device stack, it will be recognized that the specific locations of the direct or direct hybrid bonds may vary depending on the particular implementation.

[0044] In addition to reducing losses due to resistance in metal layers and interfaces and mitigating signal integrity concerns, a backside power delivery scheme enables more efficient cooling, as power lines, which can be a significant source of Joule heat, may be accessible for attaching cooling solutions, such as heat spreaders or liquid cooling. For example, the cooling solution may be attached to the second surface, which is relatively close to the power lines, compared to some other integrated circuit device designs. For example, packaged device dies typically have their front side facing downward (e.g., toward the printed circuit board or socket to which the device die is attached). If power delivery circuitry is provided on the backside of the die, the power delivery circuitry may be located near a heat spreader, heat sink, liquid cooling, fan, or other cooling means that may be attached to the exposed surface of the device. In various embodiments disclosed herein, the active circuitry (e.g., transistors) of a device (e.g., die) may be located closer to the front side of the device than to the backside of the device.

[0045] As briefly discussed above, in some embodiments, the power supply may originate at the front side of the die or package and be routed to the backside for backside power supply. In some embodiments, the die may include signal pads but not power rails. Alternatively, the power rails may be formed outside the die in a surrounding dielectric (e.g., an inorganic dielectric, such as silicon oxide) as part of a reconfigurable wafer or device. In some embodiments, the logic die may include signal wiring. In some embodiments, the logic die may include buried power rails, power vias, or backside contacts (BSCs) to source and / or drain (e.g., backside direct source contacts). In some embodiments, the logic die may include blind backside through-silicon vias (TSVs). In some embodiments, the logic die may be part of a reconfigurable device or wafer. For example, the logic die may be reconfigured onto a dummy or sacrificial carrier, and power and / or ground rails may be formed in the reconfigurable wafer around the periphery of the logic die. In some embodiments, a direct bonding interface may be formed on the backside of the reconfigurable element. In some embodiments, backside power delivery may be facilitated by direct bonding of power delivery circuitry to power delivery circuitry on the backside of the reconfigurable element and / or depositing power delivery circuitry on the backside of the reconfigurable element. In some embodiments, the direct-bonded power delivery circuitry may be comprised of silicon (e.g., a silicon wafer). In some embodiments, the direct-bonded power delivery circuitry may be comprised of the reconfigurable element and may include passive (e.g., resistors, inductors, capacitors, etc.) integrated voltage regulators, etc. A backside power delivery network may be configured to provide one or more voltages to the logic die.

[0046] 1A illustrates a side view of a reconfiguration element 100 including a backside power supply (power delivery) according to some embodiments. In FIG. 1A, power (including power supply and / or ground) can be routed from a front side 101 (also referred to herein as the surface 101 of the reconfiguration element 100) of the reconfiguration element 100 to a back side 103 (also referred to herein as the back side 103 of the reconfiguration element 100) of the reconfiguration element 100. The reconfiguration element may include an integrated device die (e.g., a processor or logic die 102) having a front side 104 (also referred to herein as the front side 104) and a back side 106 (also referred to herein as the back side 106). While only one die 102 is illustrated, it should be recognized that the reconfiguration element 100 may include multiple dies arranged next to each other and separated from each other by a dielectric 116. The die 102 may be a central processing unit (CPU), a graphics processing unit (GPU), a computer chip, a microprocessor, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a memory chip or stack (e.g., static random access memory (SRAM), dynamic random access memory (DRAM), NAND, etc.), or a combination thereof. The die 102 may have a backside portion 108 (e.g., formed of a semiconductor material, e.g., silicon) that includes a power delivery structure 110. The power delivery structure 110 may be, for example, a buried power rail, a through silicon via (TSV), a nanoTSV, a power via, or a source and The die 102 may include a front side portion 112 that may include active devices (e.g., transistors formed during front-end processing) and signaling structures (e.g., build-up layers including dielectric and metallization formed during back-end of line processing). The front side portion 112 may have routing lines connected to the active area 105, which may have active circuitry (e.g., one or more transistors, active devices, and device cells, device circuits, or electronic components for processing, storing, or transmitting signals) at or near the surface 104 of the die 102.Thus, the transistors in the active area 105 can be connected to routing circuitry and devices in the front side portion 112 and to power supply structures 110 (e.g., buried power rails, nanoTSVs, backside contacts to source and / or drain, etc.). As shown, the power supply structures 110 may extend from the back side 106 of the die 102 through the back side portion 108 to the active area 105 containing the transistors. In some embodiments, the power supply structures 110 may only partially penetrate the semiconductor material (e.g., silicon, gallium arsenide, indium phosphide, gallium nitride, silicon carbide, or any other suitable semiconductor material) of the back side portion 108 and terminate within the semiconductor material to connect to the transistors in the active area 105. In some embodiments, the power supply structures 110 provide power to the transistor or device cells by directly contacting the source / drain regions from the front side of the transistor or device (e.g., contacts to the drain and source from the front side via buried power rails), from the side of the transistor cell or device (e.g., electrical contacts to the source and drain regions using buried power rails, power vias, etc.), or from the back side (e.g., BSC). In other embodiments, the power supply structures 110 may pass power completely through the semiconductor material of the backside portion 108 to routing circuitry in the front side portion 112, which can pass power to the transistors in the active area 105.

[0047] In some embodiments, power can be delivered from the backside portion 108 to the active area 105 and the frontside portion 112 via power delivery structures 110 (e.g., power rails or nanoTSVs). The reconfiguration element can include an interconnect structure (e.g., a redistribution layer (RDL) or backside routing layer 118) including backside power delivery lines 120 embedded in the backside insulating material 107. In some embodiments, the reconfiguration element can include a frontside routing layer 122 including power delivery lines 124 embedded in the frontside insulating material 109. The backside routing layer 118 and the frontside routing layer 122 can include one or multiple dielectric and metallization layers in various embodiments. Power rails 114 disposed in the redistribution dielectric 116 can be configured to deliver power to the backside layer 118. Advantageously, the power rails 114 may be relatively thick, e.g., about 0.5 μm to about 5 μm in width (e.g., diameter if circular in cross section), to allow power transmission from the front side to the back side of the die 102 with minimal voltage loss (e.g., less than 10%). In some embodiments, the power rails may be about 0.1 μm to 1 μm in width, or 1 μm to 10 μm in width. The power rails 114 may be made of any suitable conductor, such as copper, aluminum, nickel, cobalt, etc. In some embodiments, the die 102 may be less than 20 μm, less than 10 μm, less than 1 μm, or less than 0.5 μm in thickness.

[0048] In some embodiments, the reconfigurable dielectric 116 may be comprised of an inorganic dielectric, such as a silicon-containing dielectric, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or the like. The reconfigurable dielectric 116 may include one or more layers of an insulator or dielectric. For example, in one embodiment, the reconfigurable dielectric 116 may include a single dielectric layer, such as a single silicon oxide layer. In other embodiments, the reconfigurable dielectric 116 may include multiple layers of an insulator or dielectric. For example, the reconfigurable dielectric 116 may include a first dielectric layer (e.g., silicon nitride) and a second dielectric layer (e.g., silicon oxide) deposited on the first dielectric layer. In some embodiments, the first dielectric layer may include a conformal layer that encapsulates the die 102, and the second dielectric layer may include a filler material deposited on the first layer and extending to the outer edge of the reconfigurable element 100. In some embodiments, two or more second dielectric layers are used as the filler material. In other embodiments, the reconstructed dielectric 116 may comprise an organic dielectric, such as molding compound, epoxy molding compound (EMC), resin, or the like.

[0049] In some embodiments, the reconfigurable element may be attached or affixed to another element 126. Element 126 may be, for example, a printed circuit board to which the reconfigurable element is attached via, for example, a flip chip, a ball grid array (BGA), or the like, as described in more detail below. In some embodiments, the reconfigurable element may be bonded (e.g., direct bonded or direct hybrid bonded) to element 126. For example, element 126 may comprise a dummy element configured to provide cooling, structural support, or the like. In some embodiments, element 126 may comprise a device die, wafer, or substrate including features such as active circuitry (e.g., transistors), input / output, memory, cache, etc. In some embodiments, element 126 may comprise an interposer die or wafer, which may be an active interposer or a passive interposer without any active devices. In other embodiments, element 126 may consist of another reconfigurable element (similar to reconfigurable element 100) with one or more dies embedded in a reconfigurable dielectric. Additional elements (e.g., active elements, power delivery elements, cooling elements, dummy elements, etc.) may be attached to backside routing layer 118, for example, by direct bonding, solder balls, etc.

[0050] FIG. 1B is a bottom view of the reconfiguration element 100 shown in FIG. 1A. As shown in FIG. 1B, the reconfiguration element 100 may further include an integrated voltage regulator (IVR) 128. The IVR 128 may comprise an electrical device configured to control or regulate the voltage supplied to the die 102. The IVR 128 may be attached (e.g., direct bonded, soldered, or wire bonded) to the element 126. In some embodiments, power may be supplied through the element 126 and may be routed from the front side 101 of the reconfiguration element 100 to the back side 103 of the reconfiguration element 100 via power rails 114 (e.g., through-dielectric vias) extending through the reconfiguration dielectric 116. A backside routing layer 118 may route power from the power rails 114 to a power delivery structure 110, which may route power into the backside portion 108 of the die 102. As mentioned above, in some embodiments, the vias of the power delivery structure 110 can pass at least partially through the backside portion 108 to deliver power to the transistors in the active area 105, rather than routing the power along routing circuitry in the front side portion 112. In other embodiments, the vias of the power delivery structure 110 can extend through the die to routing circuitry in the front side portion 112, which can route power to the transistors in the active area 105. In some embodiments, the power delivery lines 124 in the front side routing layer 122 can also provide some power from the front side 101 to the die 102.

[0051] Beneficially, by routing power from the backside 106 of the die 102 to the active area 105, the number of signal lines at the front side 104 of the die 102 can be increased because the space at the front side 104 that would otherwise be occupied by power lines can instead be used for signal lines and signals. In some embodiments, only signal pads are provided at the front side 104 of the die 102, such that only signals are transmitted from the front side 104 to the active area 105. In some embodiments, at least 90% of the pads at the front side 104 (e.g., at least 95% of the pads) are configured to conduct signals (as opposed to power) to the die 102. In some embodiments, at least 30% of the pads at the front side 104 (e.g., at least 50% of the pads) are configured to conduct signals (as opposed to power or dummy pads) to the die 102. In some embodiments, at least 70% of the active or non-dummy pads at the front side 104 are configured to conduct signals to the die 102. In some embodiments, more than 50% of the active or non-dummy pads at surface 104 are configured to conduct signals to die 102 .

[0052] To form the reconfiguration element 100, the die 102 may be attached (e.g., glued or direct bonded) to a temporary (false) carrier or handle. The die 102 may be embedded in a reconfiguration dielectric layer 116, and the power rails 114 may be disposed within the dielectric 116. The dielectric 116, power rails 114, and die 102 may be thinned from the backside, thereby forming a substantially flush backside of the reconfiguration element. The power delivery structures 110 may be exposed after backside thinning to contact the frontside transistors and devices, or may be formed (e.g., drilled and filled) after backside thinning. A backside routing layer 118 may be deposited and patterned so as to extend over the backside 106 of the die 102, the rear of the reconfiguration dielectric 116, and the rear ends of the power rails 114. The front-side routing layer 122 may be provided on the surface 104 of the die, the front of the reconstructed dielectric 116, and the front end of the power rail 114. One or both of the front-side and back-side routing layers 122, 118 may comprise a redistribution layer (RDL) for carrying signals laterally (e.g., laterally inward or laterally outward) along the device 100. As discussed above, one or both of the front-side and back-side routing layers 122, 118 may be prepared for direct bonding (e.g., hybrid bonding). As used herein, supplying power to the die 102 may pass electrical current to power devices on the die 102 and may also connect the devices to electrical ground.

[0053] FIG. 1C illustrates a reconfiguration element similar to that shown in FIG. 1A. However, in FIG. 1C, rather than being disposed within the reconfiguration dielectric 116, the power rails 114 may instead be surrounded on one or more sides by another material different from the element 130 (e.g., semiconductor element or dummy silicon, glass, ceramic, etc.) or the reconfiguration dielectric 116. In FIG. 1C, the power rails 114 may be comprised of through-substrate vias (TSVs) disposed through the element 130 or dummy semiconductor element 110. In some embodiments, the die 102 and element 130 may be embedded within the reconfiguration dielectric 116. In some embodiments, the element 130 may be comprised of a passive element (e.g., a capacitor, inductor, etc.) or other active element. Beneficially, the use of the element 130 can help reduce stress and provide structural support as well as a heat dissipation path for the reconfiguration element 100.

[0054] FIG. 2 illustrates an exemplary embodiment of a device having a power supply die 132 according to some embodiments. Unless otherwise specified, the structure illustrated in FIG. 2 is generally similar to the structures illustrated in FIGS. 1A-1C. The device of FIG. 2C includes an integrated voltage regulator 128 disposed within a reconfiguration dielectric 116. As shown, several IVRs 128 may be coupled to a redistribution layer 136 by vias or rails 114 extending from the IVRs to the backside of the reconfiguration device 100. While the IVRs 128 illustrated in FIG. 2 are connected to front-side routing 122, the IVRs 128 may further be connected from the top side of the IVRs to back-side routing 118 or a redistribution layer (RDL) 136 illustrated in FIG. 1C. In FIG. 2, the device 126 may be a printed circuit board, and the reconfiguration device may be attached to and electrically connected to the device 126 via BGA balls 134. In other embodiments, element 126 may comprise any other type of element, such as an integrated device die, another reconfigurable element, an interposer (e.g., organic, inorganic, or semiconductor, glass, etc.), a wafer, a substrate, a panel, etc. As noted above, element 126 may alternatively be directly bonded (e.g., hybrid bonded) to element 126. Power supply die 132 may be bonded (e.g., direct bonded) to reconfigurable element 100. Power supply die 132 may include a redistribution layer (RDL) 136. Power supply die 132 may have pads 138 that may be electrically connected to corresponding pads (not shown) on reconfigurable element 100. In some embodiments, as shown in FIG. 2 , power supply die 132 may be directly bonded (e.g., hybrid bonded) to reconfigurable element 100 at a direct bonding interface 140. Thus, in the illustrated embodiment, a backside routing layer may not be deposited on the backside 103 of the reconfiguration element 100. Alternatively, the RDL 136 may be deposited on the power supply die 132 and directly bonded to the reconfiguration element 100 (e.g., directly bonded to the reconfiguration dielectric 116, to the backside 106 of the die 102 (which may have a bonding layer applied to it), and to the power rail 114).2, the RDL 136 may comprise an interconnect device hybrid bonded to the reconfigurable device 100. In some embodiments, the power supply die 132 may be directly bonded (hybrid bonded) to a direct bonding layer formed on or over the reconfigurable device 100.

[0055] While FIG. 2 shows the power supply die 132 including the redistribution layer 136 and pads 138 and directly bonded (e.g., directly hybrid bonded) to the reconfiguration element 100, other configurations are possible. For example, in some embodiments, the redistribution layer 136 can be deposited on the backside 106 of the die 102 using semiconductor processing techniques, such as lithography, etching, deposition, and polishing. In some embodiments, rather than bonding the power supply die 132 to the reconfiguration element 100, the power supply function can be realized by depositing it directly on the backside of the reconfiguration element 100, and this power supply function can be part of the reconfiguration element 100. Beneficially, directly bonding the power die 132 to the reconfiguration element 100 can provide a more efficient process using multiple pins for power (including ground). As mentioned above, as used herein, supplying power to the die 102 may involve passing electrical current to power devices on the die 102, and may also involve connecting the devices to electrical ground.

[0056] 3 illustrates an example assembly including at least one of a dummy die 142, a structural support die, a carrier die, a passive die, or a heat dissipation element of the example assembly. The dummy die 142 may be bonded (e.g., direct bonded) to the reconfiguration element 100. In some embodiments, the dummy die 142 may be bonded (e.g., direct bonded) to the reconfiguration element 100. In some embodiments, the dummy die 142 may have electrically inactive elements, e.g., the dummy die 142 may have no active circuit components (e.g., no transistors). In some embodiments, the dummy die 142 may have passive circuitry (e.g., capacitors, resistors, inductors, transformers, etc.), while in other embodiments, the dummy die 142 may have no passive devices. In some embodiments, the dummy die 142 may include a structural support element (e.g., a semiconductor material, such as silicon) that provides mechanical support and / or reduces stresses imposed on the die 102. In some embodiments, the dummy die 142 may be used, for example, to aid in heat spreading and dissipate heat from the die 102. For example, in some embodiments, the dummy die 142 may comprise a heat spreader or heat sink. In some embodiments, the dummy die 142 may be used to provide cavity cooling. For example, one or more cooling cavities may be provided within the dummy die 142, and a cooling fluid may be provided in the cooling cavities to remove heat from the die 102. In the embodiment of FIG. 3, a bonding interface 136 may be provided between opposing bonding layers of the dummy die 142 and the reconfigurable device 100. 3, routing layer 111 may be provided on backside 130 of reconfiguration element 100, and routing layer 113 may be provided on the front of dummy die 142. The respective bonding surfaces of routing layers 111 and 113 may be directly bonded to each other along bonding interface 136.However, in other embodiments, bonding interface 136 may be provided between the routing layer of dummy die 142 and the backside 103 of the reconfiguration element (e.g., the backside of dielectric 116, die 102, and rails 114). In some embodiments, routing layer 111 may be provided between the backside 103 of the reconfiguration element 100 and dummy die 142, and dummy die 142 may be directly bonded to routing layer 111 without any separate routing layer 113 on the front of dummy die 142.

[0057] In some embodiments, multiple elements can be bonded together (e.g., direct bonded or direct hybrid bonded) to form an assembly. For example, a second element having power supply circuitry can be bonded (e.g., direct hybrid bonded) to the reconfigurable element 100, and a third element, such as a dummy die, a heat spreader, a passive element, or a liquid cooling element, can be attached to the second element, e.g., by direct bonding. In some embodiments, the second element and / or the third element can be a reconfigurable element.

[0058] 4 illustrates an exemplary embodiment in which a second reconfigurable element 144 is bonded (e.g., direct hybrid bonded) to the reconfigurable element 100 along bonding interface 136a, and a third element 146 (which may be substantially similar to element 142 of FIG. 3, e.g., a dummy die, heat spreader, liquid cooling, etc.) is bonded (e.g., direct bonded) to the second reconfigurable element 144 along bonding interface 136b, thereby forming a stack. The second reconfigurable element 144 may include an integrated voltage regulator (IVR) 128, a spacer 148, and any other suitable active, passive, or dummy devices. In some embodiments, the second reconfigurable element 144 may include a passive, integrated power supply, etc. 4, in some embodiments, the second reconfigurable element 144 may have a redistribution layer (RDL) 150; however, in other embodiments, the redistribution layer 150 may not be provided within the second reconfigurable element 144; instead, the redistribution layer may be formed (e.g., deposited) on the reconfigurable element 100. In some embodiments, the spacer 148 and the IVR 128 may be reconfigured within the dielectric 116a, and the redistribution layer 150 may be deposited on the dielectric 116a, the spacer 148, and the IVR 128. The bonding surface of the RDL 150 may be hybrid bonded to the reconfigurable element 100. Although not shown, through-dielectric vias (e.g., conductive vias similar to the power rails 114) may be provided in the dielectric 116a.

[0059] FIG. 5 illustrates an exemplary embodiment generally similar to the embodiment illustrated in FIG. 4 . However, instead of the second reconfigurable element 144, the second element 152 may not be reconfigured. For example, the second element 152 may be a wafer or a singulated portion thereof. The second element 152 may have the same or similar functionality as the second reconfigurable element 144. In some embodiments, for example, IVR and / or passive devices may be patterned or formed in the second element 152. The second element 152 may be directly bonded to the reconfigurable element 100 along bonding interface 136 a, and the third element 146 may be directly bonded to the second element 152 along bonding interface 136 b. It should be recognized that the bonding interfaces 136 a and 136 b may be located at other locations, such as along the backside 103 of the reconfigurable element 100, depending on the location of the respective bonding layers.

[0060] 4 and 5 show assemblies in which the second element is either formed from a single piece (e.g., formed from a silicon wafer) or is a reconfigurable element. However, other implementations are possible. For example, integrated voltage regulators, passives, integrated power supplies, spacers, etc. may be bonded (e.g., direct bonded or hybrid bonded) to the reconfigurable element 100. In some embodiments, a filler material (e.g., a dielectric) may be deposited after the individual components are bonded to the reconfigurable element 100.

[0061] 6 and 7 illustrate embodiments in which additional or alternative circuit components are provided in a second element 152, which is bonded (e.g., direct-bonded) to the reconfigurable element 100. In FIG. 6, the second element 152 comprises a semiconductor element (e.g., a single semiconductor component in some embodiments) in which a memory bank 154 is formed. In some embodiments, the second element 152 may comprise a memory device (e.g., NAND, DRAM, SRAM, etc.). As shown in FIG. 6, in some embodiments, a fourth element 156 may be bonded (e.g., direct-bonded) to a surface of the reconfigurable element 100. The fourth element 156 may comprise electrical signal input / output, optical signal input / output, cache, etc. As discussed above, the element 146 may comprise a dummy element that may provide structural support and / or heat transfer to the assembly.

[0062] 7, instead of a single element formed with a memory bank, the second element 152 is a reconfigurable element having integrated voltage regulators, spacers, memory banks (or memory devices), and / or other devices embedded within the dielectric 116a. Using the direct bonding techniques of Figures 6 and 7, high-speed connections between the memory banks 154 and the logic die 102 are possible with high pin counts due to the fine pitch achievable with the direct bonding process.

[0063] FIG. 8 is a flow diagram illustrating an example process 800 for fabricating an assembly including a backside power supply, according to some embodiments. In block 802, a reconstructed wafer may be formed. For example, in a die-to-wafer bonding process, a known good logic die may be bonded (e.g., direct bonded) to a carrier wafer. The front side of the logic die (e.g., the side closest to the logic circuitry) may be bonded to the carrier wafer. Integrated voltage regulators, passives, etc. may also be direct bonded to the carrier wafer, although in some embodiments these may be formed or attached by other means, such as by deposition or soldering, or such elements may not be present. Gaps between the dies may be filled with a dielectric (e.g., one or more layers of, e.g., silicon nitride, silicon oxide, etc., by a deposition process). One or more power and / or ground rails may be formed in the dielectric and may extend from the front surface of the dielectric to the back surface of the dielectric. The power and / or ground rails may be formed next to the dielectric, for example, by selectively etching some areas of the dielectric to provide gaps that can be filled by deposition, electroplating, etc. Alternatively, the power and / or ground rails may be formed before the dielectric, for example, by electroplating the power rails (e.g., copper pillars) followed by dielectric deposition. Each logic die and its associated dielectric, power / ground rails, and other associated circuit components may comprise a reconfigurable element. A reconfigurable wafer may have one reconfigurable element or two or more reconfigurable elements. In some embodiments, the reconfigurable element may comprise one or more dies, where the one or more dies comprise one or more logic and / or memory dies.

[0064] In block 804, the backside of the reconfigurable element may be thinned, for example, by chemical mechanical polishing (CMP), etching, or backgrinding, to expose power supply contacts. The power supply contacts may be, for example, buried power rails, nanoTSVs, power vias, or contact pads in electrical contact with or portions of backside contacts (BSCs) to source and / or drain (e.g., backside direct source contacts), etc. After thinning, in block 806, a hybrid bonding interface layer may optionally be formed on the exposed backside of the reconfigurable element to facilitate subsequent bonding of additional die, dummy silicon, etc.

[0065] A second element may be bonded to the backside of the reconfigurable element in block 808. As discussed above, the second element may be, for example, a power supply die, dummy silicon, a reconfigurable die, or the like.

[0066] In block 810, the carrier may be removed from the reconfigurable element, thereby exposing a surface of the reconfigurable element. The surface may then be further processed, for example, by polishing. In block 812, the surface of the reconfigurable element may be metallized.

[0067] Direct Bonding

[0068] Various embodiments disclosed herein relate to direct-bonded structures in which two or more elements can be directly bonded to one another without an intervening adhesive. Such processes and structures are referred to herein as "direct bonding" processes or "direct-bonded" structures. Direct bonding allows for the bonding of one material on one element to one material on another element without traditional adhesives (also referred to herein as a "homogeneous" direct bond), in which case the materials on the different elements do not need to be identical. Direct bonding also allows for the bonding of multiple materials on one element to multiple materials on another element (e.g., hybrid bonding).

[0069] In some embodiments (not shown), each bonding layer comprises a single material. In these uniform direct bonding processes, only one material on each component is directly bonded. Exemplary uniform direct bonding processes include ZIBOND® technology, commercially available from Adeia, Inc., San Jose, California. The materials of opposing bonding layers on different components can be the same or different, and these materials can be elemental or compound. For example, in some implementations, a non-conductive bonding layer can be a blanket deposited on a base substrate portion without patterning conductive features (e.g., pad-less). In other embodiments, bonding layers can be patterned on one or both components, and these bonding layers can be the same or different, but one material on each component is directly bonded across the entire surface of the component (or across the entire surface of the smaller component if the components are of different sizes) without adhesive. In another embodiment of uniform direct bonding, one or both of the non-conductive bonding layers may include one or more conductive features, but the conductive features are not included during bonding. For example, in some embodiments, opposing non-conductive bonding layers may be uniformly direct bonded to each other, and after bonding, through-substrate vias (TSVs) may then be formed through one of the devices, thereby enabling electrical communication to the other device.

[0070] In various embodiments, bonding layers 908a and / or 908b may be comprised of a non-conductive material, such as a dielectric or undoped semiconductor material, e.g., undoped silicon, including native oxides. Dielectric bonding surfaces or materials suitable for direct bonding include, but are not limited to, inorganic dielectrics, such as silicon oxide, silicon nitride, or silicon oxynitride, or materials containing carbon, such as silicon carbide, silicon oxycarbonitride, low-K dielectrics, SiCOH dielectrics, silicon carbonitride, or diamond-like carbon or diamond surfaces. Such carbon-containing ceramic materials may be considered inorganic despite the carbon content. In some embodiments, the dielectric at the bonding surface does not include a polymeric material, such as an epoxy (e.g., an epoxy adhesive, a cured epoxy, or an epoxy composite, e.g., FR-4), a resin, or a molding compound.

[0071] In other embodiments, the bonding layer may be made of an electrically conductive material, such as a vapor-deposited conductive oxide material, such as indium tin oxide (ITO), as disclosed in U.S. Provisional Patent Application No. 63 / 524,564, filed June 30, 2023, the entire contents of which are incorporated herein by reference for providing examples of conductive bonding layers without shorting contacts through the interface.

[0072] Direct bonding allows a first element and a second element to be directly bonded to each other without adhesive, which differs from a vapor deposition process and results in a structurally different interface compared to that achieved by vapor deposition. In one application, the width of the first element in the bonded structure is approximately the same as the width of the second element. In some other embodiments, the width of the first element in the bonded structure differs from the width of the second element. The width or area of ​​the larger element in the bonded structure may be at least 10% larger than the width or area of ​​the smaller element. Furthermore, the interface between directly bonded structures, unlike the interface beneath the vapor deposition layer, may contain defective regions where nanometer-scale voids (nanovoids) exist. Nanovoids may form due to activation of one or both of the bonding surfaces (e.g., exposure to plasma, as described below).

[0073] The bond interface between non-conductive bonding surfaces may contain a higher concentration of material from the activation and / or final chemical treatment process compared to the bulk of the bonding layer. For example, in embodiments utilizing nitrogen plasma for activation, a nitrogen peak may form at the bond interface. The nitrogen peak may be detectable using secondary ion mass spectrometry (SIMS). In various embodiments, for example, a nitrogen termination treatment (e.g., exposing the bonding layer to a nitrogen-containing plasma) can replace OH groups on a hydrolyzed (OH-terminated) surface with NH molecules, resulting in a nitrogen-terminated surface. In embodiments utilizing oxygen plasma for activation, an oxygen peak may form at the bond interface. In some embodiments, the bond interface may be comprised of silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. As described herein, the direct bond comprises a covalent bond, which is stronger than van der Waals bonds. The bonding layer may further have a polished surface that is planarized to a high degree of smoothness.

[0074] In direct bonding processes, such as uniform direct bonding and hybrid bonding, two components are bonded together without an intervening adhesive. In non-direct bonding processes that use adhesives, an intervening material is typically applied to one or both components to achieve a physical bond between the components. For example, in some adhesive-based processes, a flowable adhesive (e.g., an organic adhesive, such as an epoxy), which may contain a conductive filler material, may be applied to one or more components and cured to form a physical bond (rather than a chemical or covalent bond) between the components. Typical organic adhesives do not form strong chemical or covalent bonds with either component. In such processes, the bond between the components is weak and / or easily destroyed by, for example, reheating or defluxing.

[0075] In contrast, direct bonding processes join two elements together by forming strong chemical bonds (e.g., covalent bonds) between opposing non-conductive materials. For example, in direct bonding processes between non-conductive materials, one or both non-conductive surfaces of two elements are planarized and chemically pretreated (e.g., activated and / or terminated) so that when the elements are brought into contact with each other, strong chemical bonds (e.g., covalent bonds) are formed, which are stronger than van der Waals or hydrogen bonds. In some embodiments (e.g., between opposing dielectric surfaces, e.g., between opposing silicon oxide surfaces), chemical bonds may spontaneously form at room temperature upon contact. In some embodiments, the chemical bonds between the opposing non-conductive materials may be strengthened after the elements are annealed.

[0076] As mentioned above, hybrid bonding is a type of direct bonding in which both non-conductive features are directly bonded to non-conductive features and conductive features are directly bonded to conductive features of the components being bonded. The non-conductive bonding materials and interfaces can be as described above, while the conductive bond can be formed, for example, as a direct metal-to-metal bond. In a conventional metal bonding process, a fusible metal alloy (e.g., solder) can be placed between the conductors of two components, heated to melt the alloy, and cooled to form a bond between the two components. The resulting bond often has a sharp interface with the conductors from both components, which can be reversed by reheating. In contrast, direct metal bonding used in hybrid bonding does not require molten or semi-fusible metal alloys, and as a result, strong mechanical and electrical bonds can be obtained without the extremely high temperatures and pressures of thermocompression bonding, and interdiffusion of bonded conductive features is often observed, with grain growth occurring across the bonding interface between the elements.

[0077] 9A and 9B schematically illustrate cross-sectional side views of first and second elements 902, 904, respectively, before and after a process for forming a direct-bonded structure, particularly a hybrid-bonded structure, according to some embodiments. In FIG. 9B, the bonded structure 900 has the first and second elements 902, 904 directly bonded to one another at a bond interface 918 without an intervening adhesive. A conductive feature 906 a of the first element 902 may be electrically connected to a corresponding conductive feature 906 b of the second element 904. In the illustrated hybrid-bonded structure 900, the conductive feature 906 a is directly bonded to the corresponding conductive feature 906 b without an intervening solder or conductive adhesive.

[0078] In the illustrated embodiment, the conductive features 906a, 906b are embedded within the first bonding layer 908a of the first element 902 and the second bonding layer 908b of the second element 904, respectively, making the conductive features 906a, 906b part of the bonding layers 908a, 908b. Field regions of the bonding layers 908a, 908b extend between and partially or completely surround the conductive features 908a, 908b. The bonding layers 908a, 908b may comprise a layer of non-conductive material suitable for direct bonding, as described above, and the field regions are directly bonded to each other without adhesive. The non-conductive bonding layers 908a, 908b may be provided on the front surfaces 914a, 914b of the base substrate portions 910a, 910b, respectively.

[0079] The first and second elements 902, 904 may comprise microelectronic elements, e.g., semiconductor elements, including, for example, integrated device dies, wafers, passive devices, discrete active devices such as power switches, MEMS, etc. In some embodiments, the base substrate portion may include device portions, e.g., bulk semiconductor (e.g., silicon) portions of the elements 902, 904, and back-end-of-line (BEOL) interconnect layers over such semiconductor portions. The bonding layers 908a, 908b may be provided as part of such BEOL layers during device fabrication, as part of a redistribution layer (RDL), or as special bonding layers added to an existing device, with bond pads extending from underlying contacts. Active devices and / or circuit components may be patterned and / or otherwise provided in or on base substrate portions 910a, 910b, and may be in electrical communication with at least some of the conductive features 908a, 908b. The active devices and / or circuit components may be provided at or near the front surfaces 914a, 914b of base substrate portions 910a, 910b and / or at or near the opposite rear surfaces (backsides) 916a, 916b of base substrate portions 910a, 910b. In other embodiments, base substrate portions 910a, 910b may not include active circuit components, but may instead include a dummy substrate, a passive interposer, a passive optical element (e.g., a glass substrate, a grating, a lens), or the like. Although bonding layers 908a, 908b are shown as being provided on the front side of the device, similar bonding layers may additionally or alternatively be provided on the back side of the device.

[0080] In some embodiments, the base substrate portions 910a, 910b may have significantly different coefficients of thermal expansion (CTE), and bonding elements including such different base substrate portions may form a heterogeneous bonded structure. The difference in CTE between the base substrate portions 910a, 910b, particularly the bulk semiconductor (typically single-crystalline) portions of the base substrate portions 910a, 910b, may be greater than 5 ppm / °C or greater than 10 ppm / °C. For example, the difference in CTE between the base substrate portions 910a, 910b may be in the range of 5 ppm / °C to 100 ppm / °C, 5 ppm / °C to 40 ppm / °C, 10 ppm / °C to 100 ppm / °C, or 10 ppm / °C to 40 ppm / °C.

[0081] In some embodiments, one of the base substrate portions 910 a, 910 b may be made of an optoelectronic single crystal material useful for opto-piezoelectric or pyroelectric applications, while the other of the base substrate portions 910 a, 910 b is made of a more conventional substrate material, for example, one of the base substrate portions 910 a, 910 b may be made of lithium tantalate (LiTaO) or lithium niobate (LiNbO), and the other of the base substrate portions 910 a, 910 b may be made of silicon (Si), quartz, fused silica, sapphire, or glass. In other embodiments, one of the base substrate portions 910a, 910b may be comprised of a single III-V semiconductor material, such as gallium arsenide (GaAs) or gallium nitride (GaN), and the other of the base substrate portions 910a, 910b may be comprised of a non-III-V semiconductor material, such as silicon (Si), or another material with a similar CTE, such as quartz, fused silica, sapphire, or glass. In yet other embodiments, one of the base substrate portions 910a, 910b may be comprised of a semiconductor material, and the other of the base substrate portions 910a, 910b may be comprised of a packaging material, such as glass, an organic, or a ceramic substrate.

[0082] In some configurations, the first element 902 may comprise a singulated element, such as a singulated integrated device die. In other configurations, the first element 902 may comprise a carrier or substrate (e.g., a semiconductor wafer) containing multiple (e.g., tens, hundreds, or more) device regions that, when singulated, form multiple integrated device dies, although in other embodiments, such a carrier may comprise a packaging substrate or a passive or active interposer. Similarly, the second element 904 may comprise a singulated element, such as a singulated integrated device die. In other configurations, the second element 904 may comprise a carrier or substrate (e.g., a semiconductor wafer). Accordingly, embodiments disclosed herein are applicable to wafer-to-wafer (W2W), die-to-die (D2D), or die-to-wafer (D2W) bonding processes. In a W2W process, two or more wafers may be directly bonded together (e.g., direct hybrid bonding) and then singulated using an appropriate singulation process. After singulation, the side edges of the singulated structure (e.g., the side edges of the two bonded elements) may be substantially coplanar (substantially aligned x-y dimensions) with one another, and / or the edges of the bonding interfaces for both bonded and singulated elements may be coextensive, and these edges may include indicia indicative of the common singulation process for the bonded structure (e.g., saw marks if a saw singulation process is used).

[0083] Although only two elements 902, 904 are shown, any suitable number of elements can be stacked in the bonded structure 900. For example, a third element (not shown) can be stacked on the second element 904, a fourth element (not shown) can be stacked on the third element, and so on. In such an embodiment, through-substrate vias (TSVs) can be formed to enable vertical electrical communication between and / or among the vertically stacked elements. Additionally or alternatively, one or more additional elements (not shown) can be stacked laterally adjacent to each other along the first element 902. In some embodiments, the laterally stacked additional elements can be smaller than the second element. In some embodiments, the bonded structure can be encapsulated in an insulating material, such as an inorganic dielectric (e.g., silicon oxide, silicon nitride, silicon oxycarbonitride, etc.). One or more insulating layers can be provided on the bonded structure. For example, in some embodiments, a first insulating layer can be conformally deposited on the bonded structure, and a second insulating layer (which can comprise the same or a different material as the first insulating layer) can be provided on the first insulating layer.

[0084] To achieve direct bonding between the bonding layers 908a, 908b, the bonding layers 908a, 908b can be prepared for direct bonding. The non-conductive bonding 912a, 912b at the top or outer surfaces of the bonding layers 908a, 908b can be prepared for direct bonding by polishing, for example, chemical mechanical polishing (CMP). The roughness of the polished bonding surfaces 912a, 912b can be less than 15 Å rms. For example, the roughness of the bonding surfaces 912a, 912b can be in the range of approximately 0.1 Å rms to 15 Å rms, 0.5 Å rms to 10 Å rms, or 1 Å rms to 5 Å rms. Additionally, the polishing can be optimized to leave the conductive features 906a, 906b recessed relative to the field regions of the bonding layers 908a, 908b.

[0085] Pretreatment to enable direct bonding may further include cleaning one or both of the bonding surfaces 912a, 912b and exposing them to a plasma and / or an etchant to activate at least one of the surfaces 912a, 912b. In some embodiments, one or both of the surfaces 912a, 912b may be terminated with chemical species after or during activation (e.g., during a plasma and / or etch process). Without being bound by theory, in some embodiments, the activation process may be performed to break chemical bonds at the bonding surfaces 912a, 912b, and the termination process may provide additional chemical species at the bonding surfaces 912a, 912b that alter the chemical bonds and / or improve bonding energy during direct bonding. In some examples, activation and / or termination are performed in the same step, e.g., in a plasma, thereby activating and terminating the surfaces 912a, 912b. In other embodiments, one or both of the bonding surfaces 912a, 912b may be terminated in a separate process to provide additional chemical species for direct bonding. In various implementations, the terminating species may comprise nitrogen. For example, in some embodiments, the bonding surfaces 912a, 912b may be exposed to a nitrogen-containing plasma. Other terminating species may be suitable for improving bonding energy, depending on the material of the bonding surfaces 912a, 912b. Furthermore, in some embodiments, the bonding surfaces 912a, 912b may be exposed to fluorine. For example, one or more fluorine concentration peaks may be present at or near the bond interface 918 between the first element 902 and the second element 904. Typically, the fluorine concentration peaks occur at the interface between material layers.Additional examples of activation and / or termination treatments are described in U.S. Pat. No. 9,391,143 at column 5, line 55 to column 7, line 3; column 8, line 52 to column 9, line 45; column 10, lines 24 to 36; column 11, lines 24 to 32, lines 42 to 47, lines 52 to 55, and lines 60 to 64; column 12, lines 3 to 14, lines 31 to 33, and lines 55 to 67; and column 14, lines 38 to 40. and lines 44-50 of US Patent No. 10,434,749, and at column 4, lines 41-50, column 5, lines 7-22, lines 39, lines 55-61, column 8, lines 25-31, lines 35-40, lines 49-56, and column 12, lines 46-61, which U.S. patent applications are incorporated by reference and their teachings on activation and termination are incorporated herein by reference.

[0086] Thus, in the direct-bonded structure 900, the bond interface 918 between the two non-conductive materials (e.g., bonding layers 908a, 908b) may have a relatively high nitrogen (or other terminating species) content and / or a very smooth interface with a fluorine concentration peak at the bond interface 918. In some embodiments, the nitrogen and / or fluorine concentration peak can be detected using various types of inspection techniques, such as SIMS techniques. The polished bonding surfaces 912a, 912b may be slightly rough after the activation process (e.g., about 1 Å rms to 30 Å rms, 3 Å rms to 20 Å rms, or even rougher). In some embodiments, a slightly smoother surface can be achieved as a result of activation and / or terminating prior to bonding, for example, if a plasma treatment preferentially erodes high points on the bonding surface.

[0087] The non-conductive bonding layers 908a, 908b can be directly bonded to one another without adhesive. In some embodiments, the elements 902, 904 are brought together at room temperature, without the need for an applied voltage and without the need for external pressure or force beyond that used to prevent the two elements 902, 904 from contacting one another. Contact alone can result in direct bonding (e.g., covalent dielectric bonding) between the non-conductive layer surfaces of the bonding layers 908a, 908b. Subsequent annealing of the bonded structure 900 can directly bond the conductive features 906a, 906b to one another.

[0088] In some embodiments, prior to direct bonding, the conductive features 906a, 906b are recessed relative to the surrounding field region, resulting in a total gap between opposing contacts after dielectric bonding and before annealing of less than 15 nm, or even less than 10 nm. Because the recess depth of the conductive features 906a, 906b can vary across each element due to process variations, this gap may represent the maximum or average gap (before annealing) between corresponding conductive features 906a, 906b of two joining elements. Upon annealing, the conductive features 906a, 906b can expand and contact each other, thereby forming a direct metal-to-metal bond.

[0089] During annealing, the conductive features 906 a, 906 b (e.g., metallic material) can expand while the direct bonds between the surrounding non-conductive materials of the bonding layers 908 a, 908 b resist separation of the elements, resulting in thermal expansion increasing the internal contact pressure between the opposing conductive features. Annealing can also cause metal grain growth across the bonding interface, resulting in grains from one element migrating at least partially across the bonding interface into the other element, and vice versa. Thus, in some hybrid bonding embodiments, the opposing conductive materials are joined without heating above the melting temperature of the conductive materials, resulting in bonds that can occur at lower annealing temperatures compared to solder or thermocompression bonding.

[0090] In various embodiments, the conductive features 906 a, 906 b may comprise separate pads, contacts, electrodes, or traces at least partially embedded within non-conductive field regions of the bonding layers 908 a, 908 b. In some embodiments, the conductive features 906 a, 906 b may comprise exposed contact surfaces of TSVs (e.g., through silicon vias).

[0091] As mentioned above, in some embodiments, in the elements 902, 904 of FIG. 9A prior to direct bonding, a portion of each of the conductive features 906 a, 906 b may be recessed below the non-conductive bonding surface 911 a, 911 b, e.g., by less than 30 nm, less than 20 nm, 15 nm, or less than 10 nm, e.g., by a range of 2 nm to 20 nm, or a range of 4 nm to 10 nm. Due to process variations, both the dielectric thickness and the conductor recess depth may vary across an element. Thus, the recess depth ranges described above may apply to individual conductive features 906 a, 906 b, or may apply to the average recess depth for a local non-conductive field region. Even for individual conductive features 906a, 906b, the vertical recess depth may vary throughout the conductive feature, and therefore may be measured at or near the lateral midpoint or center of the cavity formed in a given conductive feature 906a, 906b, or may be measured at the side of the cavity.

[0092] Beneficially, the use of hybrid bonding technology (e.g., Direct Bond Interconnect, or DBI® technology, commercially available from Adair, Inc., San Jose, California) enables the realization of high densities (e.g., small or fine pitch for conventional arrays) of interconnections between conductive features 906a, 906b across the direct bond interface 918.

[0093] In some embodiments, the pitch p of the conductive features 906a, 906b, e.g., conductive traces embedded within the bonding surface of one of the bonded elements, may be less than 40 μm, less than 20 μm, less than 10 μm, less than 5 μm, less than 2 μm, or even less than 1 μm. For some applications, the ratio of the pitch of the conductive features 906a, 906b to one of the lateral dimensions of the bonding pad (e.g., the diameter) is less than 20, less than 10, less than 5, or less than 3, and in some cases, desirably, less than 2. In various embodiments, the conductive features 906a, 906b and / or traces may be comprised of copper or a copper alloy, although other metals, such as nickel, aluminum, or alloys thereof, may be suitable. The conductive features disclosed herein, e.g., conductive features 906a, 906b, may be comprised of metal particulates (e.g., copper particulates). Additionally, the larger lateral dimension (eg, pad diameter) may also be small, for example, in the range of 0.25 μm to 30 μm, in the range of about 0.25 μm to 5 μm, or in the range of about 0.5 μm to 5 μm.

[0094] For hybrid bonded elements 902, 904, the orientation of one or more conductive features 906a, 906b as viewed from the opposing element may be opposite, as shown. As is known in the art, conductive features generally have sidewalls at a near-perpendicular angle, particularly when the conductor sidewalls are formed directly by directional reactive ion etching (RIE) through the conductive material or indirectly by etching the surrounding insulator in a damascene process. However, some slight taper to the conductor sidewall may exist, with the conductor tapering away from the surface initially exposed to the etch. The taper may be even more pronounced when the conductive sidewalls are formed directly or indirectly with an isotropic wet or dry etch. In the illustrated embodiment, at least one conductive feature 906b (and / or at least one internal conductive feature, e.g., a back-end electronics feature) in the bonding layer 908b of the upper element 904 may taper or taper upward, away from the bonding surface 912b. In contrast, at least one conductive feature 906a (and / or at least one internal conductive feature, e.g., a BEOL feature) in the bonding layer 908a of the lower element 902 may taper or narrow downwardly, away from the bonding surface 910a. Similarly, any bonding layers (not shown) on the backsides 916a, 916b of the elements 902, 904 may taper or narrow downwardly, away from the backside, with an opposite taper orientation relative to the frontside conductive features 906a, 906b of the same element.

[0095] As described above, during the annealing phase of bonding, the conductive features 906a, 906b can expand and contact each other, thereby forming a direct metal-to-metal bond. In some embodiments, the materials of the conductive features 906a, 906b of the opposing elements 902, 904 can interdiffuse during the annealing process. In some embodiments, the metal grains grow and interdigitate across the bond interface 918. In some embodiments, the metal is or includes copper, which may have grains oriented along the 911 crystallographic plane to enhance copper diffusion across the bond interface 918. In some embodiments, the conductive features 906a, 906b may include a nanotwinned copper crystal structure, which can aid in the coalescence of the conductive features during high-temperature annealing. Substantially no gaps develop between the non-conductive bonding layers 908a, 908b at or near the bonded conductive features 906a, 906b. In some embodiments, a barrier layer may be provided below or laterally surrounding the conductive features 906a, 906b (which may comprise copper, for example), however, in other embodiments, there may not be a barrier layer below the conductive features 906a, 906b.

[0096] Additional Embodiments

[0097] In the foregoing specification, the systems and processes have been described with reference to these specific embodiments. It will be apparent, however, that various modifications and changes can be made to such embodiments without departing from the broad spirit and scope of the embodiments disclosed herein. The specification and drawings are, therefore, to be regarded in an illustrative rather than a restrictive sense.

[0098] While the systems and processes have been disclosed in connection with certain specific embodiments and examples, those skilled in the art will understand that various embodiments of the systems and processes extend beyond the specifically disclosed embodiments to other variations and / or systems and processes, as well as obvious modifications and equivalents thereof. Additionally, while several variations of the system and process embodiments have been shown and described in detail, other modifications within the scope of the present disclosure will be readily apparent to those skilled in the art based on this disclosure. Furthermore, various combinations or subcombinations of specific features of the embodiments and specific embodiments may be made and still fall within the scope of the present disclosure. It should be understood that various features of the disclosed embodiments and various embodiments may be combined with or substituted for one another to form various modes of implementing the disclosed systems and processes. Any methods disclosed herein need not be performed in the order described. Thus, the scope of the systems and processes disclosed herein should not be limited by the specific embodiments described above.

[0099] It will be recognized that each of the systems and methods of the present disclosure has several innovative embodiments, and no single one of these embodiments will be responsible for or required to achieve the desired attributes disclosed herein. The various features and processes described above can be used independently of one another or can be combined in various ways. All possible combinations and subcombinations are within the scope of the present disclosure.

[0100] Certain features described in this disclosure in the context of separate embodiments can also be embodied in combination in a single embodiment. Conversely, various features described in the context of a single embodiment can also be embodied in multiple embodiments separately or in any suitable subcombination. Furthermore, while features may be described above as operative in certain combinations and may initially be claimed as such, one or more features from a claimed combination may in some cases be excluded from the combination, and the claimed combination may relate to subcombinations or variations of the subcombination. No single feature or group of features is required or essential to each and every embodiment.

[0101] Additionally, as used herein, conditional terms, particularly "can," "could," "might," "may," "for example," and the like, unless otherwise specified and understood differently within the context in which they are used, are generally intended to mean that certain embodiments include certain features, elements, and / or steps, and that other embodiments do not include certain features, elements, and / or steps. Thus, such conditional terms are generally intended to mean that features, elements, and / or steps are required in any way by one or more embodiments, or that one or more embodiments necessarily include logic for determining, with or without author input or direction, whether those features, elements, and / or steps are included or performed in any suitable embodiment. In the original specification, terms such as "comprising," "including," "having," and the like are synonymous and are used inclusively in an open-ended manner, not excluding additional elements, features, acts, or operations. Additionally, the term "or" is used in its inclusive sense (not its exclusive sense), and thus, for example, when used to conjunctively connect a list of elements, the term "or" may refer to one, some, or all of the elements in the list. Additionally, the articles "a," "an," and "the" used in the original specification and the appended claims should be construed to mean "one or more" or "at least one or more" unless expressly specified otherwise. Similarly, while operations may be described in a particular order in the figures, it should be recognized that such operations need not be performed in the particular order or sequential order shown to achieve desirable results, and that not all illustrated operations need be performed. Additionally, the figures may generally depict one or more example processes in the form of a flow chart, although other operations not shown may be included in the generally depicted example methods and processes.For example, one or more additional operations may be performed before, after, concurrently with, or between any of the illustrated operations. In addition, operations may be rearranged or reordered in other embodiments. In addition, other embodiments are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve desirable results.

[0102] Furthermore, various modifications and variations can be made to the methods and devices described herein, specific examples of which are shown in the drawings and described in detail herein. However, it should be understood that these embodiments are not limited to the specific forms or methods disclosed; rather, the embodiments cover various described embodiments and all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as set forth in the appended claims. Furthermore, any particular feature, aspect, method, characteristic, feature, quality, attribute, element, etc., associated with an embodiment or embodiment, if disclosed herein, can be used in all embodiments or embodiments described herein. Methods disclosed herein need not be performed in the order described. Although methods disclosed herein may include certain actions performed by a practitioner, such methods may further include any third-party direction of those actions, either explicitly or by implication. Furthermore, ranges disclosed herein include any and all overlaps, subranges, and combinations thereof. For example, terms such as "up to," "at least," "more than," "less than," "between," etc., are inclusive of the recited numbers. For example, a number preceded by "about" or "approximately" is inclusive of the stated number and should be interpreted in accordance with the context (e.g., as precisely as reasonably possible under the circumstances, e.g., ±5%, ±10%, ±15%, etc.). For example, "about 3.5 mm" means "including 3.5 mm." Phrases preceded by the term "substantially" are inclusive of the stated number and should be interpreted in accordance with the context (e.g., as precisely as reasonably possible under the circumstances). For example, "substantially constant" includes "constant." Unless otherwise specified, all measurements are taken at standard conditions, including temperature and pressure.

[0103] As used herein, the phrase "at least one of" a list of items refers to any combination of such items, where such combination contains only one element. By way of example, "at least one of A, B, or C" includes A, B, C, A·B, A·C, B·C, and A·B·C. Conjunctions, such as "at least one of X, Y, and Z," are understood in their commonly used context to mean that an item, term, etc., can be at least one of X, Y, or Z, unless otherwise specified. Thus, such conjunctions do not imply that a particular embodiment must have at least one of X, at least one of Y, and at least one of Z. Headings provided herein, if any, are provided for convenience only and do not necessarily affect the scope or meaning of the devices and methods disclosed herein.

[0104] Thus, the claimed invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the inventions, principles, and novel features disclosed herein.

Claims

1. 1. An assembly comprising: a reconfigurable element having a front surface and a back surface, the reconfigurable element comprising: a semiconductor die having a front side and a back side, the semiconductor die having circuit components located closer to the front side than to the back side and vias extending from the back side of the semiconductor die to connect to the circuit components; an insulating material disposed along a side of the semiconductor die; a power rail extending from the front surface to the back surface of the reconfiguration element and also configured to supply power to the semiconductor die; an interconnect structure configured to electrically connect the power rail to the via and to provide power to the semiconductor die from the backside of the semiconductor die.

2. The assembly of claim 1 , wherein the insulating material comprises an inorganic dielectric.

3. The assembly of claim 2 , wherein the insulating material comprises silicon oxide.

4. The assembly of claim 1 , wherein the insulating material comprises an organic dielectric.

5. The assembly of claim 1 , wherein the interconnect structure comprises a redistribution layer disposed on the back surface of the reconfigurable element.

6. The assembly of claim 1 , wherein the interconnect structure comprises an interconnect element hybrid bonded to the backside of the semiconductor die.

7. The assembly of claim 1 , wherein the interconnect structure comprises one or more metallization layers.

8. further comprising a power supply die; The assembly of claim 1 , wherein the power supply die is hybrid bonded to the backside of the reconfiguration element.

9. The assembly of claim 8 , wherein the power supply die comprises a redistribution layer.

10. The assembly of claim 1 , wherein the reconfiguration element further comprises an integrated voltage regulator.

11. The assembly of claim 1 , further comprising a dummy die, the dummy die being directly bonded to the backside of the reconfiguration element.

12. Further comprising a second reconstructing element, the second reconstructing element comprising: an integrated voltage regulator; an integrated power supply circuit component; The assembly of claim 1 , wherein the second reconfigurable element is hybrid bonded to the reconfigurable element.

13. The assembly of claim 12 , further comprising a dummy die, the dummy die being directly bonded to the second reconfiguration element.

14. The assembly of claim 12 , further comprising a stack, the stack having a dummy die directly bonded to the second reconfiguration element.

15. The assembly of claim 1 , further comprising an integrated voltage regulator hybrid-bonded to the reconfigurable element.

16. The assembly of claim 1 , wherein the reconfigurable element further comprises a dummy semiconductor element, and the power rail is disposed within the dummy semiconductor element.

17. the reconfiguration element further comprises an integrated voltage regulator; The assembly of claim 1 , further comprising a power supply die, the power supply die having one or more memory banks.

18. The assembly of claim 17 , further comprising an optical input / output system, the optical input / output system being bonded to the surface of the reconfiguration element.

19. further comprising a second reconfigurable element hybrid-bonded to the reconfigurable element; The second reconfiguration element an integrated power supply circuit component; one or more memory banks; and one or more integrated voltage regulators.

20. The assembly of claim 1 , wherein the circuit component comprises one or more transistors.

21. The assembly of claim 1 , wherein the semiconductor die has a thickness of less than 5 μm.

22. The assembly of claim 1 , wherein the semiconductor die has a thickness of less than 1 μm.

23. The assembly of claim 1 , wherein the semiconductor die is a logic die or a processor die.

24. 1. An assembly comprising: Including insulating material, a power rail extending through the insulating material; an integrated device die at least partially embedded in the insulating material, the integrated device die having a front side and a back side, the integrated device die having circuit components located closer to the front side than to the back side and power delivery structures extending from the back side of the integrated device die to connect to the circuit components; an interconnect structure deposited on the insulating material, the power rail, and the backside of the integrated device die, the interconnect structure providing power between the power rail and the power supply structure at the backside of the integrated device die.

25. The assembly of claim 24 , wherein the insulating material comprises an inorganic dielectric.

26. The assembly of claim 24 further comprising a power supply die hybrid bonded to the interconnect structure.

27. 25. The assembly of claim 24, further comprising a dummy die, said dummy die being direct bonded to said interconnect structure.

28. 1. A method for forming a bonded structure having a backside power supply, the method comprising: forming a bonding surface on a back surface of a reconfigurable element, the reconfigurable element having a front surface and a back surface; The reconfiguration element a semiconductor die having a front side and a back side, the semiconductor die having circuit components located closer to the front side than to the back side and vias extending from the back side of the semiconductor die to connect to the circuit components; an insulating material disposed along a side of the semiconductor die; a power rail extending from the front surface to the back surface of the reconfiguration element and also configured to supply power to the semiconductor die; an interconnect structure configured to electrically connect the power rail to the via and to provide power to the semiconductor die from the backside of the semiconductor die; The method includes direct bonding a second element to the bonding surface of the reconfigurable element.

29. 30. The assembly of claim 28, wherein the second element comprises an integrated voltage regulator.

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