Processors that delay flushing of the instruction pipeline

Abstract

In a general aspect, a processor includes a plurality of control registers, an instruction processing pipeline operatively coupled to the plurality of control registers, and a pipeline flush control unit operatively coupled to the instruction processing pipeline. The pipeline flush control unit is configured to record an indication of a first instruction in response to completion of execution of the first instruction by the instruction processing pipeline. The first instruction is configured to write to a first control register of the control registers. The pipeline flush control unit is also configured to identify a second instruction in the instruction processing pipeline before completion of execution of the second instruction and determine whether the second instruction conflicts with the first instruction based on a predetermined set of criteria. If the second instruction is determined to conflict with the first instruction, the pipeline flush control unit initiates a flush of the instruction processing pipeline.

Description

[Technical Field]

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS] This application claims priority to U.S. patent application Ser. No. 63 / 476,858, filed December 22, 2022, entitled "PROCESSOR WITH DELAYED INSTRUCTION PIPELINE FLUSH," the disclosure of which is incorporated herein by reference in its entirety.

[0002] This specification relates to computer processing devices, such as microprocessors, processors, central processing units, and the like. More particularly, this disclosure relates to computer processing devices and associated systems and methods for improving processing performance by delaying flushing of an instruction processing pipeline. [Background technology]

[0003] A processor, such as one implemented in a computing system, may include an instruction execution pipeline (pipeline) for processing instructions (e.g., machine-readable instructions of a software program). For example, a processor such as a RISC-V® processor, an x86 processor, an ARM® processor, a Power® processor, etc. may include circuitry that implements one or more pipelines for processing instructions.

[0004] Such a pipeline can operate such that multiple instructions flow through the pipeline at different instruction processing stages, where the number of instruction processing stages in the pipeline depends on the particular implementation architecture. Certain instructions, such as instructions that modify the processor's control registers (CRs), can affect the operation of the pipeline through which instructions flow as they are processed. In some processor architectures, such CRs may be referred to as control and status registers (CSRs). For purposes of this disclosure, such registers are collectively referred to as control registers or CRs. Other types of instructions can also affect the operation of the pipeline. For example, a taken branch instruction that causes the processor to begin executing a different instruction sequence can affect the operation of the pipeline.

[0005] For purposes of this disclosure, instructions that affect the operation of the pipeline are generally referred to as control register instructions (i.e., CR instructions), although other instructions may also affect the operation of the pipeline (e.g., taken branches). Further, for purposes of this disclosure, instructions that do not modify the CR or change the behavior of the pipeline are generally referred to as non-CR instructions. For example, a CR instruction may modify the way the pipeline processes instructions by, for example, modifying floating-point operations, modifying virtual memory operations, modifying virtualization and hypervisor state, etc. That is, a CR instruction may modify the way the pipeline processes instructions by enabling certain modes of operation (e.g., floating-point operations), disabling certain modes of operation, changing control information (e.g., where in memory instructions are fetched), etc., to name a few.

[0006] Non-CR instructions that do not affect pipeline behavior may include arithmetic instructions, load instructions, store instructions, and not-taken branch instructions, to name a few. For properly ordered software program instructions to execute correctly, a change in pipeline behavior must be applied to instructions processed after the pipeline change and before any additional changes to the pipeline due to the execution of subsequently received instructions. To prevent improper execution of instructions in a pipeline when its behavior is modified (in which case such a change in pipeline behavior would not be properly applied), conventional processors flush (i.e., empty) the pipeline after execution of each CR instruction (or other instruction that modifies the pipeline behavior) and then resume program execution using the pipeline's modified behavior. Such pipeline flushes can adversely affect the processor's performance in executing programs because execution cycles used to process instructions flushed from the pipeline are wasted. This is because such instructions cannot complete processing in the pipeline, e.g., they are flushed from the pipeline when a flush occurs, regardless of their current stage in the pipeline. Summary of the Invention

[0007] In a general aspect, a processor includes a plurality of control registers and an instruction processing pipeline operatively coupled to the plurality of control registers. The instruction processing pipeline is configured to execute a plurality of machine-readable instructions based on respective information stored in the plurality of control registers. The processor also includes a pipeline flush control unit operatively coupled to the instruction processing pipeline. The pipeline flush control unit is configured to record an indication of a first instruction in response to completion of execution of the first instruction by the instruction processing pipeline. The first instruction is configured to write to a first control register of the plurality of control registers. The pipeline flush control unit is also configured to identify a second instruction in the instruction processing pipeline before completion of execution of the second instruction and determine whether the second instruction conflicts with the first instruction based on a predetermined set of criteria. If it is determined that the second instruction conflicts with the first instruction, the pipeline flush control unit initiates a flush of the instruction processing pipeline.

[0008] Implementations may include one or more of the following aspects, or any combination thereof: For example, if it is determined that the second instruction does not conflict with the first instruction, the instruction processing pipeline may be configured to complete execution of the second instruction.

[0009] The second instruction may be configured to write to a second control register of the plurality of control registers. The pipeline flush control unit may be further configured to record an indication of the second instruction, identify a third instruction in the instruction processing pipeline before completion of execution of the third instruction, and determine whether the third instruction conflicts with the first instruction or the second instruction based on a predetermined set of criteria. If it is determined that the third instruction conflicts with the first instruction or the second instruction, the pipeline flush control may initiate a flush of the instruction processing pipeline. If it is determined that the third instruction does not conflict with either the first instruction or the second instruction, the instruction processing pipeline may be further configured to complete execution of the third instruction.

[0010] The pipeline flush control unit may include an accumulator configured to store an indication of the first instruction and an indication of the second instruction, and the processor may be configured to clear the accumulator in response to initiating a flush of the instruction processing pipeline.

[0011] The instruction processing pipeline may include, in order, a fetch stage, a decode stage, an execution stage, a memory stage, and a write-back stage. The instruction processing pipeline may include a RISC-V style instruction processing pipeline.

[0012] In another general aspect, a processor includes a plurality of control registers (CRs) and an instruction processing pipeline operatively coupled to the plurality of CRs. The instruction processing pipeline is configured to execute a plurality of machine-readable instructions based on respective information stored in the plurality of CRs. The plurality of machine-readable instructions include a plurality of CR instructions and a plurality of non-CR instructions. The processor also includes a pipeline flush control unit operatively coupled to the instruction processing pipeline. The pipeline flush control unit is configured to record an indication of a first instruction in response to completion of execution of the first instruction by the instruction processing pipeline, where the first instruction is a first CR instruction of the plurality of CR instructions. The pipeline flush control unit is configured to identify a second instruction in the instruction processing pipeline before completion of execution of the second instruction and determine whether the second instruction conflicts with the first CR instruction based on a predetermined set of criteria. If it is determined that the second instruction conflicts with the first CR instruction, the pipeline flush control unit is configured to initiate a flush of the instruction processing pipeline.

[0013] Implementations may include one or more of the following aspects, or any combination thereof. For example, if it is determined that the second instruction does not conflict with the first instruction, the instruction processing pipeline may be configured to complete execution of the second instruction. The second instruction may be a non-CR instruction among a plurality of non-CR instructions.

[0014] The second instruction may be a second CR instruction of the plurality of CR instructions, and the pipeline flush control unit may be configured to record an indication of the second CR instruction and to identify a third instruction in the instruction processing pipeline before completion of execution of the third instruction. The pipeline flush control unit may be configured to determine whether the third instruction conflicts with the first CR instruction or the second CR instruction based on a predetermined set of criteria, and to initiate a flush of the instruction processing pipeline if it is determined that the third instruction conflicts with the first CR instruction or the second CR instruction.

[0015] If it is determined that the third instruction does not conflict with either the first CR instruction or the second instruction, the instruction processing pipeline may be configured to complete execution of the third instruction. The third instruction may be a non-CR instruction.

[0016] The pipeline flush control unit may include an accumulator configured to store an indication of the first CR instruction and an indication of the second CR instruction. The processor may be configured to clear the accumulator in response to initiating a flush of the instruction processing pipeline.

[0017] The instruction processing pipeline may include a RISC-V style instruction processing pipeline.

[0018] In another general aspect, a method for processing machine-readable instructions includes completing execution of a first instruction of the machine-readable instructions in an instruction processing pipeline of a processor, and determining that the processor can delay flushing of the instruction processing pipeline in response to completing execution of the first instruction. The method further includes recording an indication of the first instruction, examining the instruction processing pipeline to identify a second instruction of the machine-readable instructions in the instruction processing pipeline before completion of execution of the second instruction, and determining whether the second instruction conflicts with the first instruction based on a predetermined set of criteria. If it is determined that the second instruction conflicts with the first instruction, the method includes initiating a flush of the instruction processing pipeline.

[0019] Implementations may include one or more of the following aspects, or any combination thereof: For example, the first instruction may be a control register (CR) instruction and the second instruction may be a non-CR instruction.

[0020] If it is determined that the second instruction does not conflict with the first instruction, the method may further include completing execution of the second instruction.

[0021] The first instruction may be a first control register (CR) instruction and the second instruction may be a second CR instruction. The method may include recording an indication of the second CR instruction, identifying a third instruction from the machine-readable instructions in the instruction processing pipeline before completion of execution of the third instruction, and determining whether the third instruction conflicts with the first CR instruction or the second CR instruction based on a predetermined set of criteria. If the third instruction is determined to conflict with the first CR instruction or the second CR instruction, the method may include initiating a flush of the instruction processing pipeline.

[0022] The third instruction may be a non-CR instruction.

[0023] If it is determined that the third instruction does not conflict with either the first or second CR instruction, the method may include completing execution of the third instruction.

[0024] In another general aspect, a processor includes a plurality of control registers and an instruction processing pipeline operatively coupled to the plurality of control registers. The instruction processing pipeline is configured to execute a plurality of machine-readable instructions based on respective information stored in the plurality of control registers. The processor further includes a pipeline flush control unit operatively coupled to the instruction processing pipeline. The pipeline flush control unit and the instruction processing pipeline are configured to record an indication of the first instruction in response to completion of execution of the first instruction by the instruction processing pipeline. The first instruction is configured to write to a first control register of the plurality of control registers. The pipeline flush control unit and the instruction processing pipeline are further configured to identify a second instruction in the instruction processing pipeline before completion of execution of the second instruction, determine that the second instruction does not conflict with the first instruction based on a predetermined set of criteria, and complete execution of the second instruction. The pipeline flush control unit and the instruction processing pipeline are further configured to identify a third instruction in the instruction processing pipeline, determine that the third instruction conflicts with the first instruction based on a predetermined set of criteria, and, in response to determining that the third instruction conflicts with the first instruction, initiate a flush of the instruction processing pipeline before completion of execution of the third instruction. [Brief explanation of the drawings]

[0025] [Figure 1] FIG. 2 is a block diagram illustrating an example of a processor.

[0026] [Figure 2] FIG. 2 is a block diagram illustrating an example of an instruction processing pipeline that may be included in the processor of FIG. 1.

[0027] [Figure 3] FIG. 2 is a block diagram illustrating an example of a pipeline flush control unit that may be included in the processor of FIG. 1.

[0028] [Figure 4A] 1 is a table showing example instruction group classification conflicts and conflict criteria for control register (CR) instructions and non-CR instructions, respectively. [Figure 4B] 1 is a table showing example instruction group classification conflicts and conflict criteria for control register (CR) instructions and non-CR instructions, respectively.

[0029] [Figure 5A] FIG. 5 is a timing diagram illustrating an example flush of an instruction processing pipeline based on the example instruction classifications and conflict criteria of FIGS. 4A and 4B. [Figure 5B] FIG. 5 is a timing diagram illustrating an example flush of an instruction processing pipeline based on the example instruction classifications and conflict criteria of FIGS. 4A and 4B.

[0030] [Figure 6] 1 is a flow chart illustrating a method for delaying flushing of an instruction processing pipeline.

[0031] [Figure 7] FIG. 1 illustrates an example architecture of a computing device that may be used to implement aspects according to the present disclosure.

[0032] Like reference numbers in the various drawings indicate like and / or similar elements. DETAILED DESCRIPTION OF THE INVENTION

[0033] The present disclosure relates to computer processing devices, such as processors, microprocessors, central processing units, graphics processing units, tensor processing units, and accelerators (hereinafter "processors"), and related systems and methods that can improve processor execution performance by reducing the occurrence of flushes in the instruction processing pipeline. For example, techniques described herein include storing a set of conflict criteria, using the criteria to identify interfering instructions, flushing the instruction processing pipeline if an interfering instruction is identified, and allowing processing to continue without flushing the pipeline if no interfering instructions are present. In some implementations, the conflict criteria may be predetermined based on an analysis of a given processor's instruction set and its control registers (CRs). In some implementations, the conflict criteria may be determined by the designer or implementer of the instruction set used by the processor.

[0034] Unless an interfering instruction is identified in the instruction processing pipeline (e.g., from instructions concurrently existing in various stages of the instruction processing pipeline), instruction execution can continue until a conflict is identified, after which an instruction processing pipeline flush may be initiated. Thus, for example, when a given sequence of instructions is executed, the number of instruction processing pipeline flushes can be reduced, thereby improving execution performance, compared to a conventional approach in which a flush is initiated after each CR instruction has completed execution. For example, for a sequence of instructions including three non-interfering CR instructions and a subsequent instruction that is interfered with by one or more of the preceding non-interfering CR instructions, the number of instruction processing pipeline flushes can be reduced from three to one, compared to a conventional approach in which a flush is initiated after each CR instruction has completed execution.

[0035] In some implementations, various instructions may be categorized into multiple groups, and conflict criteria between instructions may be determined and assigned based on these groups. For example, CR instructions may be grouped based on the respective CRs to which they can be written. For example, CR instructions that write to CRs that affect virtual memory operations may be categorized into a first CR instruction group. CR instructions that write to CRs that affect the virtualization and hypervisor state of the processor may be categorized into a second CR instruction group. CR instructions that write to CRs that affect floating-point operations may be categorized into a third CR instruction group. In implementations described herein, CR instructions of a given category may be considered to be mutually non-interfering (i.e., do not interfere with each other). Non-CR instructions may also be categorized into non-CR instruction groups. For example, floating-point operation instructions may be categorized into a first non-CR instruction group, and integer arithmetic operations may be in a second non-CR instruction group. Other types of non-CR instructions may be categorized into other respective non-CR instruction groups.

[0036] These classification groupings are provided as examples and for illustrative purposes. Depending on the implementation, additional, fewer, and / or different groupings may be used. For example, CR instructions that require an immediate flush of the associated instruction processing pipeline may be classified into an additional CR instruction group. In some implementations, such CR instructions may include CR instructions that write to a CR that controls the flushing of the instruction processing pipeline, CR instructions that write to a CR used for debug operations, etc. Also, in some implementations, non-CR instructions that perform memory loads or memory stores may be classified into respective groups. Again, other instruction classification groupings are possible for both CR and non-CR instructions. In some implementations, each instruction in a given group may include an indication (e.g., a bit field) of the individual group. In other implementations, other approaches, such as a lookup table or an indexed list, may be used to determine the group of each instruction.

[0037] In some implementations, the conflict criteria may include, for each CR instruction group, an indication of interfering (other) CR instruction groups. For example, in the above example, the first CR instruction group (virtual memory) may be indicated as interfering with the second CR instruction group (virtualization and hypervisor) and with the third CR instruction group (floating point). Similarly, both the second CR instruction group and the third CR instruction group may be indicated as interfering with the first CR instruction group, although there is no conflict between the instructions in the second CR instruction group and the instructions in the third CR instruction group. In this example, the first CR instruction group may be considered to mutually interfere with the second CR instruction group and the third CR instruction group, and vice versa.

[0038] For non-CR instruction groups, the conflict criteria may include, for each non-CR instruction group, an indication of CR instruction groups that interfere with the instructions of this non-CR instruction group. For example, a non-CR instruction group for floating-point arithmetic instructions may be indicated as being interfered with by the second CR instruction group (floating-point CR instructions) described above. Similar to the instruction group classifications, the conflict criteria may each be included in each instruction (e.g., as a bit field) or may be listed in a lookup table or indexed list, to name a few.

[0039] 1 is a block diagram illustrating an example processor 100. Processor 100 can use techniques described herein to delay flushing of the instruction processing pipeline based on detection of instruction-to-instruction interference, thereby reducing the occurrence of such flushes. For example, processor 100 may be configured to delay flushing of the instruction processing pipeline based on the absence of instruction-to-instruction interference executed by processor 100. Accordingly, implementations of processor 100 can improve execution performance relative to conventional processor implementations that initiate flushing of the instruction processing pipeline after completion of each CR instruction. Processor 100 is shown as an example for illustrative purposes. In some implementations, the techniques described herein may be implemented in processors having other configurations.

[0040] 1 , processor 100 includes instruction processing pipeline 110, CR 120, memory 130, and pipeline flush control unit 140. CR 120, memory 130, and pipeline flush control unit 140 are operatively coupled (functionally coupled, operatively connected, etc.) with instruction processing pipeline 110. In some implementations, one or more elements of processor 100 may be integrated with one another. For example, memory 130 or a portion thereof may be included in instruction processing pipeline 110. In some implementations, pipeline flush control unit 140 may be integrated with instruction processing pipeline 110. That is, in such implementations, the functionality of pipeline flush control unit 140 may be implemented by instruction processing pipeline 110.

[0041] The instruction processing pipeline 110 may be a sequential, multi-stage instruction processing pipeline including multiple consecutive stages. An example of such an instruction processing pipeline is further described below with respect to FIG. 2. The instruction processing pipeline 110 may be configured to execute machine-readable instructions (e.g., instructions of a software program stored in memory 130). These instructions may include CR instructions and non-CR instructions. The execution of such instructions may be based in part on control and status information stored in CR 120, and information in the CR may be modified (e.g., written) by CR instructions.

[0042] In this example, using techniques described herein, pipeline flush control unit 140 may determine whether instructions being processed in instruction processing pipeline 110 may or will interfere with each other (e.g., whether a CR instruction may interfere with a subsequently executed CR instruction or a subsequently executed non-CR instruction). If pipeline flush control unit 140 determines that interference between instructions being processed in instruction processing pipeline 110 will occur, pipeline flush control unit 140 may initiate a flush of instruction processing pipeline 110 to remove all instructions currently being processed in instruction processing pipeline 110 to prevent such interference. If pipeline flush control unit 140 determines that instructions being processed in the pipeline will not interfere, instruction processing pipeline 110 may continue processing instructions until an interference with an instruction in progress (e.g., that has not yet completed execution) in instruction processing pipeline 110 is identified, or a specific request to flush instruction processing pipeline 110 is made, for example, by writing to a respective CR in CR 120, followed by initiating the flush.

[0043] FIG. 2 is a block diagram illustrating an example of an instruction processing pipeline 200 that may be included in the processor of FIG. 1. For example, instruction processing pipeline 200 may implement instruction processing pipeline 110 of processor 100. As shown in FIG. 2, instruction processing pipeline 200 includes five sequential stages for processing machine-readable instructions, e.g., CR instructions and non-CR instructions. These stages include a fetch stage 210, a decode stage 220, an execute stage 230, a memory stage 240, and a write-back stage 250. Thus, in this example, instruction processing pipeline 200 may have five instructions in various stages of execution by instruction processing pipeline 200. Fetch stage 210 may fetch instructions from a memory, such as an instruction cache memory. Decode stage 220 may decode the fetched instructions to generate one or more respective micro-operations, detect the instruction class of the fetched instructions, or identify source or destination registers for the fetched instructions. The execute stage 230 may perform operations encoded by the instruction or execute micro-operations generated by the decode stage 220. The memory stage 240 may perform memory loads and / or stores associated with each instruction. The writeback stage 250 may write the results of each instruction to a register file, which may include the processor's CR.

[0044] Execution of a given instruction in instruction processing pipeline 200 does not complete until the instruction has been processed by write-back stage 250. Thus, when write-back stage 250 completes processing a CR instruction, the execution of instructions in earlier stages of instruction processing pipeline 200 (i.e., instructions that complete execution at a later time than the CR instruction that was written back) may be affected, e.g., interfered with, by the CR instruction. For example, if there is interference between instructions in earlier stages of instruction processing pipeline 200 when the CR instruction completes, those earlier instructions may not execute properly.

[0045] For example, an interfering instruction may be defined as an instruction whose completion of execution modifies how that instruction or another instruction is processed by the pipeline. As an example, if a CR instruction completes a writeback and modifies a floating-point operation in the pipeline, any floating-point instructions in progress (i.e., partially processed) in the pipeline may not be processed in accordance with the modification throughout the pipeline, and may be processed improperly even if they are able to reach the writeback stage. That is, instructions in a software program are typically executed according to a sequential program flow, with all previous instructions in the sequential flow completing their processing before the next instruction completes its processing. However, due to parallel and sequential processing by the instruction processing pipeline 200 (e.g., instructions passing through successive stages of the pipeline, and different instructions being processed simultaneously in parallel in different stages), if the operation of the instruction processing pipeline is modified by the execution of the CR instruction, the modified operation of the pipeline may affect instructions following the CR instruction in the sequence of processing, as well as instructions still being processed in one or more earlier pipeline stages. Consequently, subsequent instructions may not be processed properly. To mitigate this problem and also promote efficient use of processing cycles, instruction processing pipeline 200 may be flushed in response to an interfering instruction being identified, or flushing of instruction processing pipeline 200 may be delayed if no interfering instructions are identified.

[0046] 1, instruction processing pipeline 200 may be operatively coupled with a pipeline flush control unit (e.g., pipeline flush control unit 140 of processor 100). In other implementations, elements of pipeline flush control unit 140 may be included in or integrated with instruction processing pipeline 200 rather than being implemented in a separate unit. For example, in some implementations, instruction processing pipeline 200 may be configured to implement the functionality of a pipeline flush control unit (e.g., pipeline flush control unit 140 of FIG. 1 and / or pipeline flush control unit 300 of FIG. 3).

[0047] In some implementations, instruction processing pipeline 200 may be the instruction processing pipeline of a RISC-V processor or another instruction processing pipeline 200 and may include fewer stages, different stages, or additional stages. For example, in some implementations, the instruction processing pipeline may include a fetch stage, an execute stage, and a writeback stage. In some implementations, the instruction processing pipeline may include an x86 instruction processing pipeline.

[0048] 3 is a block diagram illustrating an example of a pipeline flush control unit 300 that may be included in the processor of FIG. 1. For example, pipeline flush control unit 300 may implement pipeline flush control unit 140 of processor 100. In some implementations, pipeline flush control unit 300 may be operatively coupled to an instruction processing pipeline (e.g., instruction processing pipeline 110 of processor 100 or instruction processing pipeline 200 of FIG. 2). In other implementations, as described above, elements of pipeline flush control unit 300 may be included in or integrated with the instruction processing pipeline rather than being implemented in a separate unit. For example, in some implementations, the instruction processing pipeline may be configured to implement the functionality of pipeline flush control unit 300.

[0049] 3, the pipeline flush control unit 300 includes a conflict accumulator 310, a conflict comparison unit 320, and a conflict specification block 330. In this example, the conflict accumulator 310 may be configured to record (store) an indication of instructions (e.g., CR instructions) that have completed processing (e.g., processed in a writeback stage of an associated instruction processing pipeline) that can delay flushing of the associated instruction processing pipeline, e.g., instructions that do not require immediate pipeline flushing. That is, the conflict accumulator 310 may be used to record one or more CR instruction classification groups for CR instructions that have completed processing, and the conflict comparison unit 320 may compare the stored CR instruction indications with the instruction classifications of subsequent instructions. If the conflict comparison unit 320 identifies a match with one of the conflict criteria included in the conflict specification block 330, a pipeline flush is initiated.

[0050] 3 , conflict comparison unit 320 may be configured to identify instructions in progress within the instruction processing pipeline and determine whether such instructions in progress conflict with the CR instruction records included in conflict accumulator 310. For example, conflict comparison unit 320 may determine a grouping classification for the instructions in progress by examining the instructions in progress within the instruction processing pipeline, e.g., by reading respective instruction information from one or more stages of the pipeline. Conflict comparison unit 320 may then identify which instruction grouping classifications are designated as interfering with the grouping classification of the instructions in progress from conflict specification block 330. Conflict comparison unit 320 may then compare these interfering instruction classes from conflict specification block 330 with any instruction grouping classification indications recorded in conflict accumulator 310. That is, if the conflict accumulator 310 contains a recorded indication of a completed instruction having the instruction classification specified in the conflict specification block 330 for the in-flight instruction, the conflict comparison unit 320 may initiate a flush of the associated instruction processing pipeline to remove the in-flight instruction and any other in-flight instructions. The instruction processing pipeline may then fetch the next instruction according to the program flow and any control or state changes made in the corresponding CR.

[0051] In an implementation, initiating a flush of the instruction processing pipeline may result in any stored instruction group classification indications being cleared from conflict accumulator 310. Furthermore, in some implementations, when a CR instruction completes its writeback, if instructions in progress within the associated instruction processing pipeline have also completed their writeback processing, the indication of this CR instruction may be removed from conflict accumulator 310 without flushing the instruction processing pipeline. That is, the indication of the completed CR instruction recorded in accumulator 310 may be removed because it is no longer at risk of conflicting with instructions that later enter the instruction processing pipeline, e.g., instructions fetched after the writeback processing of the completed CR instruction, because those later instructions will be processed with the changes from this CR instruction.

[0052] In some implementations, as described above, the instruction group classification and conflict designation may each be included in the instruction (e.g., in corresponding fields of the instruction). For example, such fields may be defined as part of a corresponding instruction set architecture (ISA) or as an extension to the ISA corresponding to a given processor implementation. In such implementations, the conflict designation block 330 of the pipeline flush control unit 300 may be omitted, and the conflict comparison unit 320 may compare the instruction group classification and / or conflict designation included in such fields of the current instruction with the indication included in the conflict accumulator 310.

[0053] 4A and 4B are tables illustrating example instruction group classifications and conflict criteria for CR instructions (table 400 in FIG. 4A) and non-CR instructions (table 450 in FIG. 4B), respectively. In some implementations, different instruction group classifications and / or different conflict criteria may be used than those described in this example. In some implementations, the instruction classifications and conflict criteria shown in tables 400 and 450 may be stored in a pipeline flush control unit (e.g., in conflict specification block 330 of pipeline flush control unit 300) and used to determine instruction conflicts that will cause a flush of the associated instruction processing pipeline.

[0054] 4A , column 410 of table 400 includes different CR instruction classifications A, B, C, and D, and column 420 includes each CR instruction classification for a CR instruction that interferes with a CR instruction belonging to the classification in the corresponding row of column 410. That is, column 420 includes each conflict criterion for the CR instruction classification in column 410. As described herein, these CR instruction classifications and conflict criteria may be predetermined based on a particular processor implementation. Some implementations may use different and / or additional instruction group classifications and / or conflict criteria than those described herein.

[0055] Using the example CR instruction categories described above and with further reference to table 400, CR instruction category A may be associated with CR instructions that modify a CR associated with virtual memory operations. CR instruction category B may be associated with CR instructions that modify a CR associated with virtualization and hypervisor state. CR instruction category C may be associated with CR instructions that modify a CR associated with floating-point operations. CR instruction category D may be associated with CR instructions that modify a CR that causes an immediate flush of the associated instruction processing pipeline, such as a CR used to request a flush of the instruction pipeline, a CR associated with a debug operation, etc. As shown in column 420, the conflict criteria for CR instruction category A indicate that instructions included in that category interfere with CR instructions belonging to CR instruction categories B and C. Similarly, the respective conflict criteria for CR instruction categories B and C indicate that instructions included in these categories interfere with CR instructions belonging to CR instruction category A.

[0056] Referring to FIG. 4B , column 460 of table 450 includes non-CR instruction categories I_1, I_2, and I_3, and column 470 includes respective CR instruction categories for CR instructions that interfere with non-CR instructions included in each category in column 460. That is, column 470 includes respective conflict criteria for the non-CR instruction categories in column 460. As described herein, these non-CR instruction categories and conflict criteria may be predetermined based on a particular processor implementation. In this example, non-CR instructions in category I_1 are subject to (e.g., interfered with by) conflict criteria imposed by CR instructions in category A. That is, non-CR instructions in category I_1 may be interfered with (e.g., may not execute properly) due to modifications made to the CR by CR instructions in category A. For example, in this example, CR instructions related to virtual memory operations (category A in table 400) are shown as interfering with non-CR instructions in category I_1. Such non-CR instructions may include, for example, certain loads, stores, and instruction fetches.

[0057] 4B , in this example, a non-CR instruction in category I_2 is subject to conflict criteria indicating interference with (e.g., interfered with by) a CR instruction belonging to category B. That is, due to modifications made to the CR by a CR instruction in category B, a non-CR instruction belonging to category I_2 may be interfered with (e.g., may not execute properly). For example, in this example, CR instructions related to virtualization and hypervisor state (category B in table 400) are shown as interfering with non-CR instructions in category I_2. Such non-CR instructions may include, for example, instructions that attempt to read from guest memory or state.

[0058] 4B , in this example, a non-CR instruction in category I_3 is subject to conflict criteria indicating interference with (e.g., interfered with by) a CR instruction belonging to category C. That is, due to modifications made to the CR by a CR instruction in category C, the non-CR instruction belonging to category I_3 may be interfered with (e.g., may not execute properly). For example, in this example, a CR instruction related to floating-point operations (category C in table 400) is shown as interfering with a non-CR instruction in category I_3. Such non-CR instructions may include floating-point arithmetic instructions.

[0059] The instruction classifications and conflict criteria shown in Figures 4A and 4B are provided as examples and for illustrative purposes. In some implementations, other classifications and / or conflict criteria are possible. For example, CR instructions related to virtual memory operations may interfere with CR instructions and / or non-CR instructions other than those shown in Tables 400 and 450. Also, other classifications of instructions, fewer classifications of instructions, additional classifications of instructions, other conflict criteria, fewer conflict criteria, additional conflict criteria, etc. may be used in some implementations. Furthermore, in some implementations, the conflict criteria may be dynamic in that they may depend on the state of the processor. For example, if the processor is operating in a mode in which virtual memory is disabled, changes to virtual memory (other than enabling it) do not need to cause a flush, but if the processor is operating in a mode in which virtual memory is enabled, changes to virtual memory do need to cause a flush.

[0060] 5A and 5B are timing diagrams illustrating an example of delayed instruction processing pipeline flushing. As described herein, such delayed instruction processing pipeline flushing can improve processor performance by reducing the occurrence of instruction pipeline flushes compared to conventional approaches. In this example, when executed in, for example, instruction processing pipeline 200 of FIG. 2, instruction pipeline flushing may be performed based on the example instruction classifications and conflict criteria of FIGS. 4A and 4B. Thus, the example of FIGS. 5A and 5B shows an instruction passing through a fetch stage, a decode stage, an execution stage, a memory stage, and a write-back stage in order.

[0061] In the examples of Figures 5A and 5B, time progresses moving from top to bottom as shown in the respective timing diagrams. For purposes of illustration, each unit of instruction processing and the flushing of the instruction processing pipeline are shown as occurring in a single processor cycle. In some implementations, these units of instruction processing and / or the flushing of the instruction pipeline may include or may occur over multiple processor cycles. The sequence of events in the timing diagrams of Figures 5A and 5B assumes that the associated instruction processing pipeline has been cleared (e.g., has just been flushed) or is about to begin executing the first instruction in the software program.

[0062] 5A and with further reference to at least FIGS. 4A and 4B, a timing diagram 500 illustrates an example of processing a CR instruction (CR_B) of category B, a CR instruction (CR_C) of category C, and a non-CR instruction (I_2) belonging to the I_2 category. As shown in FIG. 5A, in cycle 1, CR_B is fetched. In cycle 2, CR_B advances to the decode stage, and CR_C is fetched. In cycle 3, CR_B advances to the execute stage, CR_C advances to the decode stage, and I_2 is fetched. In cycle 4, CR_B advances to the memory stage, CR_C advances to the execute stage, and I_2 advances to the decode stage. Although not shown in FIG. 5A, additional instructions may be fetched in cycle 4, as well as in cycles 5 and 6, and similarly pass through the associated instruction processing pipeline (e.g., instruction processing pipeline 200).

[0063] In cycle 5, CR_B advances to the write-back stage and completes execution. Because CR_B (like the category D CR instructions) does not require an immediate flush and because it is the first instruction in this sequence to reach the write-back stage, flushing of the instruction processing pipeline can be delayed. In cycle 5, an indication that CR_B has completed may be recorded, for example, in a conflict accumulator. Also in cycle 5, the instruction processing pipeline may be inspected to identify CR_C as the next instruction to advance to the write-back stage. Because CR_B and CR_C do not interfere (conflict) with each other, in cycle 6, CR_C advances to the write-back stage, completes execution, and an indication that CR_C has completed may also be recorded, for example, in a conflict accumulator. Similarly, in cycle 6, the instruction processing pipeline may be inspected to identify I_2 as the next instruction to advance to the write-back stage. Because CR_B conflicts with I_2, a flush of the instruction processing pipeline is initiated in cycle 6, for example, by the pipeline flush control unit, and the process proceeds to cycle 7, where the instruction processing pipeline is flushed. That is, in some implementations, the interference of CR_B with I_2 of I_2 may be determined by the pipeline flush control unit and an indication of CR_B in a conflict accumulator, for example, by the conflict accumulator 310, the conflict comparison unit 320, and the conflict designation block 330 of the pipeline flush control unit 300. In this example, initiating a flush of the instruction processing pipeline may result in previously recorded conflicts being cleared, for example, from the accumulator.

[0064] In cycle 8, the next instruction is fetched and progresses through the instruction processing pipeline. The next instruction fetched in cycle 8 may be based on the associated program flow and control or status information modified by CR_B and / or CR_C. In some implementations, the next instruction may be I_2, but may also be another instruction. Also, although not shown in FIG. 5A , additional instructions may be fetched and begin to progress through the associated instruction processing pipeline in cycles 9-12 of timing diagram 500.

[0065] 5B , and with further reference to at least FIGS. 4A and 4B , a timing diagram 550 illustrates an example of processing a CR instruction of category B (CR_B), a CR instruction of category C (CR_C), a non-CR instruction belonging to the I_1 category (I_1), and a CR instruction of category A (CR_A). As illustrated in FIG. 5B , in cycle 1, CR_B is fetched. In cycle 2, CR_B advances to the decode stage, and CR_C is fetched. In cycle 3, CR_B advances to the execute stage, CR_C advances to the decode stage, and I_1 is fetched. In cycle 4, CR_B advances to the memory stage, CR_C advances to the execute stage, I_1 advances to the decode stage, and CR_A is fetched. Although not illustrated in FIG. 5B , additional instructions may be fetched in cycle 5, as well as in cycles 6 and 7, and similarly pass through the instruction processing pipeline (e.g., instruction processing pipeline 200).

[0066] In cycle 5, CR_B advances to the write-back stage and completes execution. Because CR_B does not require an immediate flush and is the first instruction in this sequence to reach the write-back stage, flushing of the instruction processing pipeline can be delayed. In cycle 5, an indication that CR_B has completed may be recorded, for example, in a conflict accumulator. Also in cycle 5, the instruction processing pipeline may be examined to identify CR_C as the next instruction to advance to the write-back stage. Because CR_B and CR_C do not interfere (conflict) with each other, in cycle 6, CR_C advances to the write-back stage, completes execution, and an indication that CR_C has completed may also be recorded, for example, in a conflict accumulator. Similarly, in cycle 6, the instruction processing pipeline may be examined to identify I_1 as the next instruction to advance to the write-back stage.

[0067] Because CR_B and CR_C do not conflict with I_1, in cycle 7, I_1 proceeds to the write-back stage and completes execution. In this example, because I_1 is a non-CR instruction, no indication that the instruction has completed execution may be recorded because neither control nor status information may be modified by I_1. Similarly, in cycle 7, the instruction processing pipeline may be examined to identify CR_A as the next instruction to proceed to the write-back stage. Because CR_A conflicts with both CR_B and CR_C, in cycle 7, a flush of the instruction processing pipeline is initiated, for example, by a pipeline flush control unit, and the process proceeds to cycle 8, where the instruction processing pipeline is flushed. That is, in some implementations, the interaction of CR_A with CR_B and CR_C may be determined by the pipeline flush control unit and indications of CR_B and CR_C in the conflict accumulator, e.g., by conflict accumulator 310, conflict comparison unit 320, and conflict specification block 330 of pipeline flush control unit 300. In this example, similar to the example of FIG. 5A, initiating a flush of the instruction processing pipeline may result in previously recorded conflicts being cleared, e.g., from the accumulator.

[0068] In cycle 9, the next instruction is fetched and progresses through the instruction processing pipeline. The next instruction fetched in cycle 9 may be based on the associated program flow and control or status information modified by CR_B and / or CR_C. In some implementations, the next instruction may be CR_A, but may also be another instruction. Also, although not shown in FIG. 5B, additional instructions may be fetched and begin to progress through the associated instruction processing pipeline in cycles 10-13 of timing diagram 550.

[0069] FIG. 6 is a flowchart illustrating a method 600 for delaying the flushing of an instruction processing pipeline. In some implementations, the method 600 can be implemented using the apparatus and techniques described herein. As shown in FIG. 6, the method 600 begins at block 610. At block 610, the instruction pipeline on which the method 600 is implemented is empty (e.g., no instructions are currently being processed). The method 600 allows instructions to begin executing until a CR instruction occurs. At block 620, a determination may be made as to whether the flushing of the instruction processing pipeline can be delayed based on, for example, the associated instruction classification and conflict criteria. If the CR instruction does not allow the flushing of the instruction pipeline to be delayed, for example, if it is a category D CR instruction in FIG. 4A , the method proceeds to block 650, where the instruction processing pipeline is flushed. The method 600 then returns to the beginning of block 610.

[0070] If, at block 620, it is determined that the flush of the instruction processing pipeline can be delayed, e.g., if the CR instruction is in category A, B, or C of FIG. 4A , the method 600 proceeds to block 630, where an indication of the CR instruction is added (recorded) in a conflict accumulator (e.g., conflict accumulator 310 of pipeline flush control unit 300). The method then proceeds to block 640, where subsequent instructions are identified, and a determination of whether a conflict has occurred may be made, e.g., using pipeline flush control unit 300, based on the respective conflict criteria and the indication recorded in the conflict accumulator. If no conflict is identified, instruction processing may continue, and the method may return to block 630. At block 630, a further indication (for a non-interfering CR instruction) may be added to the conflict accumulator.

[0071] If a conflict is identified at block 640, the method 600 may proceed to block 650, where the instruction processing pipeline may be flushed and the accumulator may be cleared. After processing of block 650 is completed, the method 600 returns to the beginning of block 610 (with the instruction processing pipeline empty).

[0072] In some implementations, if a CR instruction did not modify the original value stored in the associated CR, a flush that would otherwise be initiated based on the corresponding conflict criteria can be delayed because writing an unchanged value to the CR would not cause interference. In such implementations, the original value of the CR can be retrieved (e.g., from the CR or a memory location) before writing to the CR. If the retrieved value matches the value to be written, the flush that would otherwise be initiated can be delayed. Furthermore, a CR instruction that writes the same value as one already stored in the corresponding CR may not be recorded in a conflict accumulator, for example, because writing that value to the corresponding CR would not cause interference.

[0073] 7 illustrates an example architecture of a computing device 750 that may be used to implement aspects of the present disclosure, including any of the computing devices described herein, such as a computing device including processor 100, or other computing devices that may be utilized in various possible embodiments. The computing device illustrated in FIG. 7 may be used to execute operating systems, application programs, and software modules as described herein.

[0074] Computing device 750, in some embodiments, includes at least one processing device 760 (e.g., a central processing unit (CPU)). Various processing devices are available from various manufacturers (e.g., Intel or Advanced Micro Devices). In this example, computing device 750 also includes a system memory 762 and a system bus 764 that couples various system components, including the system memory 762, to the processing device 760. The system bus 764 may be one of several types of bus structures, including a memory bus or memory controller; a peripheral bus; and a local bus using any of a variety of bus architectures.

[0075] Examples of computing devices suitable for computing device 750 include a server computer, an edge computer, a desktop computer, a laptop computer, a tablet computer, a mobile computing device (e.g., a smartphone, an iPod® or iPad® mobile digital device, or other mobile device), or other device configured to process digital instructions.

[0076] The system memory 762 includes a read-only memory 766 and a random access memory 768. A basic input / output system 770, which contains the basic routines that help transfer information within the computing device 750, such as during start-up, is typically stored in the read-only memory 766.

[0077] Computing device 750, in some embodiments, also includes a secondary storage device 772 (e.g., a hard disk drive) for storing digital data. The secondary storage device 772 is connected to system bus 764 by a secondary storage interface 774. The secondary storage device 772 and its associated computer-readable media may provide non-volatile storage of computer-readable instructions (including application programs and program modules), data structures, and other data for computing device 750.

[0078] Although the example environment described herein utilizes a hard disk drive as a secondary storage device, other embodiments use other types of computer-readable storage media. Examples of these other types of computer-readable storage media include magnetic cassettes, flash memory cards, digital video disks, Verneuil cartridges, compact disk read-only memories, digital versatile disk read-only memories, random access memories, or read-only memories. Some embodiments include non-transitory computer-readable media. Furthermore, such computer-readable storage media may include local storage or cloud-based storage.

[0079] The secondary storage device 772 or system memory 762 may store a number of program modules, including an operating system 776, one or more application programs 778, other program modules 780 (e.g., software engines described herein), and program data 782. The computing device 750 may utilize any suitable operating system, such as Microsoft Windows®, Google Chrome® OS or Android®, Apple® OS, Unix®, or Linux® and variants, and other operating systems suitable for a computing device. Other examples may include Microsoft, Google, or Apple operating systems, or other suitable operating systems used in tablet computing devices.

[0080] In some embodiments, a user provides input to the computing device 750 through one or more input devices 784. Examples of input devices 784 include a keyboard 786, a mouse 788, a microphone 790, and a touch sensor 792 (e.g., a touchpad or touch-sensitive display). Other embodiments include other input devices 784. The input devices are often connected to the processing device 760 via an input / output interface 794 coupled to the system bus 764. These input devices 784 may be connected by various input / output interfaces, such as a parallel port, a serial port, a game port, or a universal serial bus. Wireless communication between the input devices and the input / output interface 794 is also possible, which in some possible embodiments may include infrared, BLUETOOTH® wireless technology, 802.11a / b / g / n, cellular, ultra-wideband (UWB), ZigBee®, or other radio frequency communication systems.

[0081] In this example embodiment, a display device 796 (e.g., a monitor, LCD display device, projector, or touch-sensitive display device) is also connected to the system bus 764 via an interface, such as a video adapter 798. In addition to the display device 796, computing device 750 may also include various other peripheral devices (not shown), such as speakers or a printer.

[0082] When used in a local area networking environment or a wide area networking environment (e.g., the Internet), computing device 750 is typically connected to the network through network interface 1000 (e.g., an Ethernet interface or a WiFi interface). In other possible embodiments, other communication devices are used. For example, some embodiments of computing device 750 include a modem for communicating over the network.

[0083] Computing device 750 typically includes at least some form of computer-readable media. Computer-readable media includes any available media that can be accessed by computing device 750. By way of example, computer-readable media include computer-readable storage media and computer-readable communication media.

[0084] Computer-readable storage media include volatile and nonvolatile, removable and non-removable media implemented in any device configured to store information such as computer-readable instructions, data structures, program modules, or other data, including, but not limited to, random access memory, read-only memory, electrically erasable programmable read-only memory, flash memory or other memory technology, compact disc read-only memory, digital versatile disk or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and that can be accessed by computing device 750.

[0085] Computer-readable communication media typically embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal (e.g., carrier wave or other transport means) and includes any information delivery media. The term "modulated data signal" refers to a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal. By way of example, computer-readable communication media include wired media (e.g., a wired network or direct-wired connection) and wireless media (e.g., acoustic, radio frequency, infrared, and other wireless media). Combinations of any of the above are also included within the scope of computer-readable media.

[0086] 7 is also an example of a programmable electronic device, which may include one or more such computing devices, which may be coupled together using a suitable data communications network to jointly perform various functions, methods, or operations disclosed herein.

Claims

1. several control registers; an instruction processing pipeline operatively coupled to the plurality of control registers, the instruction processing pipeline configured to execute a plurality of machine-readable instructions based on respective information stored in the plurality of control registers; and a pipeline flush control unit operatively coupled to the instruction processing pipeline, the pipeline flush control unit comprising: recording an indication of a first instruction in response to completion of execution of the first instruction by the instruction processing pipeline, the first instruction being configured to write to a first control register of the plurality of control registers; identifying a second instruction in the instruction processing pipeline before completion of execution of the second instruction; determining whether the second instruction conflicts with the first instruction based on a predetermined set of criteria; and If the second instruction is determined to conflict with the first instruction, then initiating a flush of the instruction processing pipeline. It is configured as follows: A processor comprising:

2. 2. The processor of claim 1, wherein the instruction processing pipeline is configured to complete execution of the second instruction if it is determined that the second instruction does not conflict with the first instruction.

3. the second instruction is configured to write to a second control register of the plurality of control registers; the pipeline flush control unit further comprising: recording an indication of said second instruction; identifying a third instruction in the instruction processing pipeline before completion of execution of the third instruction; determining whether the third instruction conflicts with the first instruction or the second instruction based on the predetermined set of criteria; and If the third instruction is determined to conflict with the first instruction or the second instruction, then initiating a flush of the instruction processing pipeline.

3. A processor according to claim 1 or 2, configured to:

4. 4. The processor of claim 3, wherein the instruction processing pipeline is further configured to complete execution of the third instruction if it is determined that the third instruction does not conflict with either the first instruction or the second instruction.

5. The processor of claim 1 or 2, wherein the pipeline flush control unit includes an accumulator configured to store the indication of the first instruction and the indication of the second instruction.

6. 6. The processor of claim 5, wherein the processor is configured to clear the accumulator in response to initiating a flush of the instruction processing pipeline.

7. The instruction processing pipeline, in order: Fetch stage; Decode stage; Execution stage; a memory stage; and Light Backstage 3. The processor of claim 1, comprising:

8. 3. The processor of claim 1, wherein the instruction processing pipeline includes a RISC-V type instruction processing pipeline.

9. several control registers (CR); an instruction processing pipeline operatively coupled to the plurality of CRs, the instruction processing pipeline configured to execute a plurality of machine-readable instructions based on respective information stored in the plurality of CRs, the plurality of machine-readable instructions including a plurality of CR instructions and a plurality of non-CR instructions; and a pipeline flush control unit operatively coupled to the instruction processing pipeline, the pipeline flush control unit comprising: recording an indication of a first instruction in response to completion of execution of the first instruction by the instruction processing pipeline, the first instruction being a first CR instruction of the plurality of CR instructions; identifying a second instruction in the instruction processing pipeline before completion of execution of the second instruction; determining whether the second instruction conflicts with the first CR instruction based on a predetermined set of criteria; and If the second instruction is determined to conflict with the first CR instruction, then initiating a flush of the instruction processing pipeline. It is configured as follows: A processor comprising:

10. 10. The processor of claim 9, wherein the instruction processing pipeline is configured to complete execution of the second instruction if it is determined that the second instruction does not conflict with the first instruction.

11. 11. The processor of claim 9, wherein the second instruction is a non-CR instruction among the plurality of non-CR instructions.

12. the second instruction is a second CR instruction among the plurality of CR instructions, the pipeline flush control unit further comprising: recording an indication of said second CR instruction; identifying a third instruction in the instruction processing pipeline before completion of execution of the third instruction; determining whether the third command conflicts with the first CR command or the second CR command based on the predetermined set of criteria; and If it is determined that the third instruction conflicts with the first CR instruction or the second CR instruction, a flush of the instruction processing pipeline is initiated.

11. A processor according to claim 9 or 10, configured to:

13. 13. The processor of claim 12, wherein the instruction processing pipeline is further configured to complete execution of the third instruction if it is determined that the third instruction does not conflict with either the first CR instruction or the second instruction.

14. 13. The processor of claim 12, wherein the third instruction is a non-CR instruction.

15. 13. The processor of claim 12, wherein the pipeline flush control unit includes an accumulator configured to store the indication of the first CR instruction and the indication of the second CR instruction.

16. 16. The processor of claim 15, wherein the processor is configured to clear the accumulator in response to initiating a flush of the instruction processing pipeline.

17. 11. The processor of claim 9, wherein the instruction processing pipeline comprises a RISC-V style instruction processing pipeline.

18. 1. A method for processing machine-readable instructions, said method comprising: completing execution of a first one of the machine-readable instructions within an instruction processing pipeline of the processor; determining that the processor can delay flushing of the instruction processing pipeline in response to completing the execution of the first instruction; recording an indication of said first instruction; examining the instruction processing pipeline to identify a second one of the machine-readable instructions in the instruction processing pipeline before completion of execution of the second instruction; determining whether the second instruction conflicts with the first instruction based on a predetermined set of criteria; and initiating a flush of the instruction processing pipeline if the second instruction is determined to conflict with the first instruction. A method comprising:

19. the first instruction is a control register (CR) instruction; and 20. The method of claim 18, wherein the second instruction is a non-CR instruction.

20. 20. The method of claim 18 or 19, wherein if it is determined that the second instruction does not conflict with the first instruction, the method further comprises completing execution of the second instruction.

21. the first instruction is a first control register (CR) instruction; and the second instruction is a second CR instruction, The method further comprises: recording an indication of said second CR instruction; identifying a third one of the machine-readable instructions in the instruction processing pipeline before completion of execution of the third instruction; determining whether the third command conflicts with the first CR command or the second CR command based on the predetermined set of criteria; and initiating a flush of the instruction processing pipeline if the third instruction is determined to conflict with the first CR instruction or the second CR instruction.

20. The method of claim 18, comprising:

22. 22. The method of claim 21, wherein the third instruction is a non-CR instruction.

23. 23. The method of claim 21 or 22, wherein if it is determined that the third instruction does not conflict with either the first CR instruction or the second CR instruction, the method further comprises completing execution of the third instruction.

24. several control registers; an instruction processing pipeline operatively coupled to the plurality of control registers, the instruction processing pipeline configured to execute a plurality of machine-readable instructions based on respective information stored in the plurality of control registers; and a pipeline flush control unit operatively coupled to the instruction processing pipeline, the pipeline flush control unit and the instruction processing pipeline comprising: recording an indication of a first instruction in response to completion of execution of the first instruction by the instruction processing pipeline, the first instruction being configured to write to a first control register of the plurality of control registers; identifying a second instruction in the instruction processing pipeline before completion of execution of the second instruction; determining that the second instruction does not conflict with the first instruction based on a predetermined set of criteria; completing execution of said second instruction; identifying a third instruction in the instruction processing pipeline; determining that the third instruction conflicts with the first instruction based on the predetermined set of criteria; and In response to the determination that the third instruction conflicts with the first instruction, initiate a flush of the instruction processing pipeline before completing execution of the third instruction. It is configured as follows: A processor comprising:

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