Semiconductor device with bonding layer having functional and non-functional conductive pads

Abstract

A semiconductor device is disclosed having an interconnect bonding layer with functional and non-functional metal contact pads surrounded by a dielectric material. The functional metal contact pads are exposed to the bonding surface and connected to a buried metal layer. The non-functional metal contact pads are distributed in areas with no or few functional metal contact pads, are exposed to the bonding surface, and terminate at a partial depth of the functional metal contact pads. Each of the functional and non-functional metal contact pads is formed using a single damascene process with one etching step.

Description

[Technical Field]

[0001] This application claims the benefit under 35 U.S.C. §119(e)(1) of U.S. Provisional Application No. 63 / 477,551, filed December 28, 2022, the entire contents of which are incorporated herein by reference.

[0002] The field relates to microelectronics having functional and non-functional conductive (eg, metal) pads on bonding layers. [Background technology]

[0003] The semiconductor industry has experienced tremendous growth over the past few decades as engineers developed chips packed with increasingly smaller transistors, as correctly predicted by Moore's Law. However, the industry recognizes that efforts to reduce the size of transistors on silicon chips are approaching physical limits. Meanwhile, consumer electronics, including computers and smartphones, continue to become increasingly complex, requiring more efficient use of transistors. One approach to improving three-dimensional (3D) integration is to stack chips or wafers on top of each other to form 3D integrated structures. Direct hybrid bonding enables high-density interconnections between stacked devices. However, direct bonding between semiconductor devices can present challenges because it utilizes planarized bonding surfaces with tight flatness tolerances.

[0004] Specific embodiments will now be described with reference to the following figures, which are offered by way of example and not limitation: [Prior art documents] [Patent documents]

[0005] [Patent Document 1] U.S. Provisional Patent Application No. 63 / 524,564 [Patent Document 2] U.S. Patent No. 9,391,143 [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device having at least one functional metal pad and at least one dummy metal pad embedded in a bonding layer, the at least one functional metal pad being formed by a dual damascene process. [Figure 2] 1 is a schematic cross-sectional view of one embodiment showing a semiconductor device having at least one functional metal pad and at least one dummy metal pad embedded in a bonding layer, each of the at least one functional metal pad and the at least one dummy metal pad being formed by a single damascene process. [Figure 3] FIG. 1 is a schematic cross-sectional view of another embodiment of the present disclosure showing a semiconductor device having at least one functional metal pad and at least one dummy metal pad embedded in a bonding layer, each of the at least one functional metal pad and the at least one dummy metal pad being formed by a single damascene process. [Figure 4] 4A-4C are schematic cross-sectional views illustrating an exemplary process for fabricating functional metal pads and dummy metal pads embedded in the bonding layer shown in FIG. 3. [Figure 5] 4A-4C are schematic cross-sectional views illustrating an exemplary process for fabricating functional metal pads and dummy metal pads embedded in the bonding layer shown in FIG. 3. [Figure 6] 4A-4C are schematic cross-sectional views illustrating an exemplary process for fabricating functional metal pads and dummy metal pads embedded in the bonding layer shown in FIG. 3. [Figure 7] 4A-4C are schematic cross-sectional views illustrating an exemplary process for fabricating functional metal pads and dummy metal pads embedded in the bonding layer shown in FIG. 3. [Figure 8]4A-4C are schematic cross-sectional views illustrating an exemplary process for fabricating functional metal pads and dummy metal pads embedded in the bonding layer shown in FIG. 3. [Figure 9] 4A-4C are schematic cross-sectional views illustrating an exemplary process for fabricating functional metal pads and dummy metal pads embedded in the bonding layer shown in FIG. 3. [Figure 10] 4A-4C are schematic cross-sectional views illustrating an exemplary process for fabricating functional metal pads and dummy metal pads embedded in the bonding layer shown in FIG. 3. [Figure 11A] 1 is a schematic cross-sectional view illustrating an exemplary conductive pad fabricated by employing a dual damascene process. [Figure 11B] 1 is a schematic cross-sectional view illustrating an exemplary conductive pad fabricated by employing a dual damascene process. [Figure 11C] 1A-1C are schematic cross-sectional views illustrating exemplary conductive pads fabricated by employing a single damascene process according to various embodiments disclosed herein. [Figure 11D] 1A-1C are schematic cross-sectional views illustrating exemplary conductive pads fabricated by employing a single damascene process according to various embodiments disclosed herein. [Figure 12] 3A-3C are schematic cross-sectional views illustrating an exemplary process for fabricating functional metal pads and dummy metal pads embedded in the bonding layer shown in FIG. 2. [Figure 13] 3A-3C are schematic cross-sectional views illustrating an exemplary process for fabricating functional metal pads and dummy metal pads embedded in the bonding layer shown in FIG. 2. [Figure 14] 1 is a schematic cross-sectional view of two microelectronic elements configured to be bonded together. [Figure 15] 15 is a schematic cross-sectional view of a bonding structure comprising the two microelectronic elements of FIG. 14 bonded together. DETAILED DESCRIPTION OF THE INVENTION

[0007] When a bonding layer is formed on a semiconductor device, the conductive contact pads are embedded in a non-conductive (e.g., dielectric) layer. Chemical mechanical processing (CMP) is performed to remove excess material on the dielectric layer and planarize the surface. Semiconductors can be fabricated to be directly bonded to other semiconductor devices or devices without an intervening adhesive. Due to the thermal expansion mismatch between the metal and dielectric materials used, thin-film processes can create stress in the bonding layer, for example, tension in the metal traces and compression in the dielectric material. This stress can cause deformation and / or warpage in the semiconductor device, such as a device die or chip, wafer, or passive device. Therefore, there is a continuing need to reduce stress in the bonding layer and distortion in the semiconductor device.

[0008] To reduce stress and strain in the bonding layer due to the mismatch in thermal expansion between the metal and dielectric materials, in various embodiments, electrically non-functional (or dummy) metal pads can be embedded in the non-conductive dielectric material of the bonding layer in areas where there are no or few functional metal pads. This can be done to achieve a more uniform distribution of the metal pads in the dielectric material, including both functional and non-functional materials. The mismatch in thermal expansion between two combined materials results in one material being under tension and the other being under compression. The thermal expansion coefficient of a metal, such as copper, is typically greater than that of a dielectric material, such as silicon oxide. Therefore, during a deposition or annealing process (or other process using high temperatures) in which a semiconductor device cools from a high temperature, the metal material contracts more than the dielectric material. Because the two materials are positioned side by side, the metal material may be under tension and the dielectric material may be under compression. However, if the two materials are uniformly distributed relative to each other, the expansion of one material is absorbed or offset by the contraction of the other material. In this way, tensile and compressive stresses can be reduced or controlled. Thus, a uniform or near-uniform distribution of metal pads in the dielectric material helps to relieve stress and reduce distortion due to thermal expansion mismatch.

[0009] In various embodiments, electrically non-functional or dummy metal pads in an interconnect or bonding layer may be shallower than electrically functional or active pads. If the non-functional metal pads extended to a greater depth (e.g., to the same depth as the functional pads), the dummy pads could short out metal traces buried in the interconnect layer below the dummy pads.

[0010] Conventionally, functional metal pads in a dielectric layer can be formed by a dual damascene process. FIG. 1 shows a schematic cross-sectional view of a semiconductor device 100 having a device layer or device portion 102 and an interconnect structure 103 disposed on the device layer 102 (also referred to herein as the device portion). As described herein, in various embodiments, the interconnect structure 103 can include multiple non-conductive layers (e.g., dielectric layers 104 and 106 in FIG. 1 ) deposited on the device layer 102. The second dielectric or bonding layer 106, which forms at least a portion of the interconnect structure 103, can be fabricated to be bonded to another element or device (e.g., directly hybrid bonded) and can accordingly function as a non-conductive bonding layer. The first dielectric layer 104 and the second dielectric layer 106 can be formed of the same or different materials. While the interconnect structure 103 includes two or more dielectric layers 104, 106, other embodiments may include more or fewer dielectric layers. The metal layer 108 is embedded in the second dielectric layer 104 and connects to the circuitry 101 patterned or otherwise provided in the device layer 102 through vias 105 or other conductors (e.g., other traces and / or vias). A plurality of vias 110 connect to the metal layer 108 (e.g., traces) at one end and to functional metal pads 112 at the other end within the second dielectric layer 106. The vias 110 may be made of copper, tungsten, or polysilicon. The functional metal pads 112 may be exposed at a surface 116 of the dielectric material 106. Non-functional or dummy metal pads 114 are also exposed at the surface 116 of the dielectric material 106 and extend partially into the dielectric material 106, terminating before reaching the underlying interconnect metal layer 108. The non-functional metal pads 114 are distributed in areas where there are no or few functional metal pads 112.

[0011] A dual damascene process can be used to form functional metal pads 112 along with vias 110 in the dielectric layer 106 of FIG. 1 . The dual damascene process can be performed, for example, by a two-step etching method: a via-first process to form narrow holes 110a in the second dielectric layer 106, followed by a trench-forming process to form wider trenches 112a. In the via-first method, finer-pitch, high-aspect-ratio holes 110a extend through the second dielectric material 106, as shown in FIG. 1 for vias 110. This process is typically more difficult than the subsequent trench-forming process. Due to the expensive patterning masks, the dual damascene process is more complex than the single damascene process. On the other hand, the trench process, as shown in FIG. 1 , is used to form larger-sized metal contact pads, such as electrically functional or active pads 112 and electrically inactive or non-functional pads 114 (also referred to herein as dummy pads). Therefore, the trench formation process is typically simpler than the via formation process.Another drawback of utilizing narrow via structures 110 is that they typically come with high electrical resistance due to their small cross-sectional dimensions.

[0012] One feature of the dual damascene process shown in Figure 1 is that the functional contact pad 112 and via 110 have a two-stage, discontinuous sidewall structure due to the two-stage etching process. This is evidenced by the corners 118, 120 between the functional pad 112 portion and the via 110 portion, as shown in Figure 1. In reality, these corners may not be as sharp as shown schematically in Figure 1. However, the stepped or cornered connection between the via 110 and the functional pad 112 is a sidewall discontinuity that causes the sidewall to be jagged and / or non-unitary.

[0013] Thus, there is an incentive to replace the relatively complex dual damascene process, which uses expensive masks, with a simpler manufacturing process. Single damascene processes reduce processing costs and can be simplified to manufacture. FIG. 2 is a schematic cross-sectional view of an exemplary embodiment of the present disclosure. In FIG. 2, an interconnect structure or layer 203 is disposed on a microelectronic device layer or device portion 202. The interconnect structure 203 comprises a second non-conductive or dielectric layer 206 that forms or includes a bonding layer for the semiconductor device 200, and a first non-conductive or dielectric layer 204 having an embedded conductive layer or underlying interconnect 208. The conductive layer 208 can be an interconnect metal layer for further connection to an external device or device. The device layer 202 can comprise a semiconductor device portion patterned with devices (e.g., an active layer 201 shown schematically in FIG. 2). In other embodiments, the device layer 202 can comprise an interposer or portion of another electronic device, with or without active devices therein. The device layer 202 may include wafers, integrated device dies or chips, such as complementary metal oxide semiconductor (CMOS) chips, or passive devices.

[0014] A conductive (e.g., metal) layer 208 can be embedded or buried in the dielectric layer 204 adjacent to the device layer 202. In some embodiments, the interconnect metal layer 208 can be the outermost layer of the device layer 202; for example, the metal layer 208 can be formed in a dielectric layer disposed over the semiconductor portion of the device layer 202 during back-end-of-line (BEOL) processing. In some embodiments, the metal layer 208 can be a redistribution layer (RDL) disposed before the second dielectric layer 206 is deposited. In some embodiments, the metal layer 208 can be in electrical communication with one or more devices in the device layer 202, for example, electrically connected to the active circuitry 201 in the device layer 202 through vias 205. At least one functional or active metal pad 212 and at least one non-functional metal pad 214 can be partially embedded in the second dielectric layer 206. The functional or active metal pads 212 extend from the top surface 216 through at least a portion of the second dielectric layer 206 and connect to (e.g., contact) the buried metal layer 208, while the non-functional metal pads 214 extend from the top surface 216 and terminate at a shallower location than the functional metal pads 212. The metal contact pads 212, 214 can have different cross-sectional shapes and dimensions, e.g., different sized widths or diameters, e.g., square, triangular, circular, polygonal, etc., when viewed at the top surface 216. In some embodiments, the functional metal pads 212 can have the same first shape with the same first dimension, and the non-functional metal pads 214 can have the same second shape with the same second dimension. In some embodiments, the functional and non-functional metal pads 212, 214 can have the same shape with the same dimension. In other embodiments, the functional metal pads 212 and the non-functional metal pads 214 can have different shapes and / or different dimensions. 2, the depth D2a of the non-functionalized metal pad 214 is less than the depth D2b of the functionalized metal pad 212. As such, the non-functionalized pad 214 terminates upward and does not contact or electrically connect to the buried metal layer 208.In this way, the non-functional metal pads 214 do not short out the metal traces of the conductive metal layer 208. Thus, in various embodiments, the non-functional pads 214 (and functional pads 212) can be positioned vertically above the conductive metal layer 208, with the functional pads connected to the metal layer 208 and the non-functional pads 214 not connected to the metal layer 208.

[0015] Accordingly, in various embodiments disclosed herein, the functional conductive pads 212 can be electrically connected to electrical functional components of the semiconductor device 200, such as traces (e.g., buried metal layer 208) that in turn connect to devices (e.g., circuit 201) or any other suitable electrical functional components (e.g., interconnects in an interposer, passive device, or any other suitable functional component). The dummy or electrically non-functional pads 214 can be electrically inactive such that they are electrically isolated within the semiconductor device 200 (e.g., the dummy pads 214 do not electrically connect to functional components or circuits within the semiconductor device 200). As described herein in connection with FIGS. 14-15 , the functional pads 212 and the non-functional pads 214 can be directly bonded to opposing conductive features (e.g., opposing pads or opposing exposed through vias) on a second semiconductor device (see FIGS. 14-15 ). In some embodiments, the functional pads 212 can be directly bonded to opposing functional pads. In some embodiments, functional pad 212 can be bonded directly to an opposing non-functional pad if a particular function of the functional pad is deactivated. In some embodiments, non-functional or dummy pad 214 can be bonded directly to an opposing non-functional or dummy pad. In some embodiments, non-functional or dummy pad 214 can be bonded directly to an opposing functional pad if a particular function of the opposing functional pad is deactivated.

[0016] In comparison with the structure of the semiconductor device 100 of FIG. 1 , the functional or active metal pad 212 and the non-functional metal pad 214 can be formed by a single damascene process. As such, the functional metal pad 212 does not have a separate or distinct via portion and can be characterized by a continuous or unitary sidewall. The sidewall of the functional metal pad 212 can form an angle with a vertical reference line due to the etching process, but the angle can be small. In the illustrated embodiment, the sidewall does not have abrupt discontinuities or corners, such as the corners 118 and 120 in FIG. 1 formed by the dual damascene process. A significant advantage of the single damascene process for fabricating the functional metal pad 212 of FIG. 2 is that it is simpler than the dual damascene process for fabricating the functional metal pad 112 and the connection via 110 of FIG. 1 . This is because fabricating the functional metal pad 212 of FIG. 2 does not utilize the more expensive or more complex masking used in the structure of FIG. 1 . Another advantage of the functional metal pad 212 of Figure 2 is that the thick cross-sectional dimension of the metal pad results in lower electrical resistance and improved performance of the semiconductor device 200 compared to the performance of the semiconductor device 100 of Figure 1. Furthermore, because the contact pad 212 is not connected to an underlying via and extends through the thickness of the bonding layer 206, the thickness D2b of the bonding contact pad 212 of Figure 2 (and the thickness D2a of the dummy pad 214) can be made thicker than the contact pad 112 of Figure 1. On the other hand, the thickness of the bonding layer 216 of Figure 2, which is the same as the thickness D2b of the contact pad 212, can be made thinner than the bonding layer 106 of Figure 1 for the same reason, and the bonding layer 106 can be made thick enough to fill both the contact pad 112 and the underlying via 110. By thinning the bonding layer 206 and thickening the contact pad 212 as described above, stresses in the second dielectric layer or bonding layer 206, which can cause distortion and warping of the semiconductor device 200, are certainly reduced and better controlled compared to the situation in FIG.Due to the thicker pad 212, the hybrid direct bonding annealing process for the device of Figure 2 can then be performed at a lower temperature anneal compared to the process used to form the device of Figure 1. The reduced stress in the second dielectric layer 206 can reduce warpage in the semiconductor device, which in turn can reduce the risk of void formation at the bonding interface and improve direct bonding quality.

[0017] Another exemplary embodiment of the present disclosure, using a single damascene process to build functional and non-functional metal pads in a bonding layer, is depicted in FIG. 3 . In FIG. 3 , a schematic cross-sectional view of a semiconductor device 300 is shown, including a device layer or device portion 302 and a first dielectric layer 304 disposed on the device layer 302. An interconnect conductive layer or underlying interconnect 308 is embedded in the first dielectric layer 304. A second non-conductive or dielectric layer or bonding layer 306 can be deposited on the first non-conductive or dielectric layer 304. The second dielectric layer 306 and conductive pads 312, 314 can function as bonding structures for the semiconductor device 300. A functional or active metal pad 312 extends from a top surface 316 through the second dielectric layer 306 to connect with the interconnect conductive portion or metal layer 308 embedded in the first dielectric layer 304. Similar to the semiconductor device 200 shown in FIG. 2 , the non-functional or dummy metal pads 314 extend from the top surface 316 through the second dielectric layer 306 but terminate at the second dielectric layer 306 above the buried conductive layer 308. Both the functional conductive pads 312 and the non-functional conductive pads 314 can be made of the same material as the buried metal layer 308. Alternatively, the pads 312, 314 can be made of different materials. For example, in some embodiments, the buried conductive layer 308 can include aluminum and the pads 312, 314 can include copper, or vice versa. As described with respect to the device 200 of FIG. 2 , the pads 312, 314 can have different arrangements of shapes and dimensions as viewed at the top surface 316, such as squares, triangles, circles, polygons, and shapes of various dimensions. For example, in the same embodiment, the active metal pads 312 can have one shape with one dimension and the dummy metal pads 314 can have another shape with another dimension. In some embodiments, the active metal pads 312 and the dummy metal pads 314 can have various shapes with various dimensions. As can be seen in Figure 3, the depth D3a of the dummy metal pads 314 is shallower than the depth D3b of the active metal pads 212.Also, similar to the semiconductor device 200 of FIG. 2, the active metal pads 312 and 314 can be formed by a single damascene process, which can be simpler than the process used to form the semiconductor device 100 of FIG. 1.

[0018] Compared to FIG. 2 , two or more functional contact pads 312 may be formed and connected to each buried metal trace 308. Each of the multiple contact pads 312 may be thinner than the single contact pad 212 connected to each buried metal trace 208 in FIG. 2 . However, such redundancy may improve the quality and reliability of the functional contact pads 312. As shown in FIG. 3 , the dummy pads 314 may have different widths, as opposed to the uniform width of the dummy pads 214 in FIG. 2 . The width of each dummy pad 314 may be related to the density of the functional pads 312 around it. The placement and different widths of the metal pads 312 and 314 may, in some embodiments, result in a substantially uniform distribution of the metal pads 312 and 314 in the second dielectric layer 306, thereby minimizing stress in the dielectric layer 306, as described above with reference to FIG. 2 . Reducing stress in the interconnect structure or layer 303 may reduce warpage of the dielectric layer 306 and the semiconductor 300.

[0019] 4-10 are schematic cross-sectional views illustrating a method of forming the semiconductor device 300 of FIG. 3. In FIG. 4, the device layer 302 of the semiconductor device 300 can comprise a carrier or substrate, such as a die, wafer, interposer, etc. The device layer 302 can have a circuit 301 disposed thereon and is covered by a first dielectric layer 304. A conductive (e.g., metal) layer 308 is embedded in the first dielectric layer 304 and connects to the circuit 301 in the device layer 302 through a via 305. The embedded metal layer 308 can be covered by a non-conductive layer (e.g., a portion of the dielectric layer 304 or another dielectric layer, such as a passivation layer, disposed on layer 304). The non-conductive layer (e.g., a portion of layer 304) can be etched to expose metal traces 308a connected to the devices or circuit 301 in the device layer 302. In other embodiments, the traces 308a can be part of an interposer and may not be directly connected to the devices. In some embodiments, the first dielectric layer 304 and metal layer 308 may be fabricated as part of microelectronic device fabrication, such as wafer fabrication, where a passivation layer may be coated on the wafer surface for protection, leaving only certain metal traces exposed for external connection. The semiconductor device 300 of FIG. 4, including the device layer 302 with embedded metal 308 and the first dielectric layer 304, may comprise a complementary metal oxide semiconductor (CMOS) device.

[0020] 5, a second dielectric layer 306 (which may function as part of a bonding layer) may be deposited on the first surface of the semiconductor device 300 shown in FIG. 4, over the first dielectric material 304 and the exposed metal traces 308a. The second dielectric layer 306 may include an inorganic dielectric such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, etc.

[0021] In FIG. 6, a first photoresist layer 320 can be coated on top of the second dielectric layer 306 of FIG. 5. The photoresist layer 320 can then be exposed to radiation of a certain wavelength projected through a mask for patterning. After development, a first opening 322 can be formed in the first photoresist layer 320 to expose the second dielectric layer 306 underneath. The semiconductor device 300 can then be subjected to an etching process to form a first cavity or opening 324 (where the functional metal pads of the second dielectric layer 306 will be located) through the first opening 322 in the first photoresist layer 320. The cavity 324 can stop at the buried metal layer 308, as shown in the schematic cross-sectional view of FIG. 7. As shown in FIG. 7, the first photoresist layer 320 can be stripped to expose the second dielectric layer 306 having the etched first cavity 324 therein.

[0022] Referring to FIG. 8 , a second photoresist layer 326 can be coated and patterned on the top surface of the second dielectric layer 306. However, for the second photoresist layer 326, the second openings 328 patterned in the photoresist layer 326 are in areas where no first cavities 324 for functional metal contact pads exist. In other embodiments, the second openings 328 can be interspersed among the first cavities 324 in the second dielectric layer 306, depending on the density of the first cavities 324 in the area. Generally, if the distribution of the first cavities 324 in the second dielectric layer 306 is not uniform, areas with sparse first cavities 324 can have more second openings 328. Similar to the description for FIG. 7 , the second dielectric layer 306 can be etched through the second openings 328 to form second cavities or openings 330 for non-functional or dummy metal pads, as shown in FIG. 9 . However, the second cavity 330 can be partially etched through the second dielectric layer 306, terminating vertically above the buried conductive layer 308. Alternatively, the second cavity 330 can be etched in any suitable manner, for example, with the same or a different type of etching process as the first cavity 324. The depth of the second cavity 330 can be controlled by a timed etch or by an etch stop layer, such as a silicon nitride layer. In some embodiments, the depth of the second cavity 330 in the second dielectric layer 306 can be etched as deep as possible, but not completely through the second dielectric layer 306 (e.g., not contacting the conductive layer 308 but positioned vertically above the conductive layer 308). In some embodiments, the second dielectric layer 306 can be formed thin so that the ratio of the depth of the second cavity 330 to the thickness of the second dielectric layer 306, D3a / D3b shown in Figure 3, can be greater than 50%, 65%, or 85%, for example. If the cavities 324 and 330 are filled with metal, such as copper, in a future step, the deeper non-functional metal pads perform better to relieve stress and reduce distortion.After the second etching process, the second photoresist layer 326 is stripped to expose the first surface of the second dielectric layer 306 and the first cavity 324 and second cavity 330 formed therein, as shown in FIG.

[0023] As described herein, multiple (e.g., two) etching processes can be performed to form the functionalized metal pads 312 and the non-functionalized metal pads 314, respectively, in the semiconductor device 300 of FIG. 3 . Dual damascene processes also use two etching steps, for example, to form the device of FIG. 1 . However, in dual damascene processes, the masking locations of the two etching steps to form the vias 110 and the functionalized metal pads 112 of FIG. 1 overlap. In other words, the second cavity formed by the second etching step to form the trench for the functionalized pad 112 is above the first cavity formed by the first etching step to form the via 110. However, in the embodiment disclosed and discussed in connection with FIGS. 4-8 , the first cavity 324 created by the first etching step and the second cavity 330 created by the second etching step are at different lateral positions. There is no lateral overlap between the first and second cavities. Thus, each of the first cavity 324 and the second cavity 330 can be formed by a single etching process, such as a single damascene process. Thus, the disclosed embodiments differ significantly from the method used to form the structure of FIG.

[0024] For example, one difference between dual damascene and single damascene processes is illustrated by the sidewall profile of the hole or opening formed by the respective etching process(es), as discussed above in conjunction with FIGS. 1 and 2. FIGS. 11A-11B further illustrate the sidewall structure formed in conjunction with the conductive feature of FIG. 1, and FIGS. 11C-11D illustrate the sidewall and pad structure formed in conjunction with FIGS. 2 and 3. In FIG. 11A, a conductive feature 410 comprises a via portion 412 below a conductive pad portion 414 connected together and embedded in a non-conductive dielectric material 416. Such a conductive feature 410 can be formed by a dual damascene process. As seen in FIG. 11A, the via 412 is significantly narrower than the conductive pad 414. Specifically, the left sidewall 420 is divided into two vertical segments, an upper segment 420a and a lower segment 420b, and a horizontal segment 426. The three line segments are joined by two corners 422 and 424, which may be substantially vertical or formed at another angle that creates an edge or abrupt change in direction between adjacent faces of segments 420a, 420b, and 426. As described above, the separation and disconnection structure of upper pad portion 414 and lower via portion 412 results from the use of a dual damascene process applied to fabricate conductive feature 410. Sidewall segments 420b and 430b in lower via section portion 412 and sidewall segments 430a and 430b in upper pad portion 414 can be vertical or substantially vertical. This substantially vertical structure can be formed by certain etching processes, such as reactive ion etching (RIE). In other embodiments, the conductive features can be formed by other etching methods, such as wet etching and other dry etching methods.

[0025] The conductive feature 450 shown in FIG. 11B can be substantially similar to the structure shown in FIG. 11B, except that one or more of the sidewalls can be angled or curved, and sidewall segments can be angled at a non-perpendicular angle. The conductive feature 450 can be formed by any suitable etching technique, including, for example, a wet etching method. The conductive feature 450 is embedded in a dielectric material 456 and includes a small via portion 452 and a large conductive pad portion 454 connected together. The sidewalls 460 and 470 of the conductive feature 450 can be slightly sloped due to the etching method and form a small angle with a vertical reference line or plane. The sloped etching can result from the upper portion of the etch channel being exposed to the etchant for a longer period of time than the lower portion. Similar to the conductive feature 410 with vertical sidewalls shown in FIG. 11A, the via portion 452 of the conductive feature 450 is significantly narrower than the conductive pad portion 454. Because of the small slope angle, there is a clear separation or discontinuity between the via 452 and the pad 454. Similarly, jagged wall 460 is characterized by two angled segments 460a and 460b and a horizontal segment 466 joined by two corners 462 and 464. Jagged wall 470 has two angled segments 470a and 470b and a horizontal segment 476 joined by two corners 472 and 474. In practice, corners 422, 424, 432, 434, 462, 464, 472, and 474 may not be as sharp as shown in Figures 11A and 11B and may include a radius, although such a radius is preferably quite small compared to the dimensions of the sidewall segments. The sharp corner structure between upper pad portion 454 and lower via portion 452 results from the dual damascene process applied to fabricate conductive feature 450.

[0026] On the other hand, conductive features formed by the single damascene process described herein do not have the jagged or discontinuously angled sidewalls characteristic of conductive features formed by dual damascene processes, as discussed above with reference to FIGS. 11A and 11B. In FIG. 11C, conductive feature 510 is formed in an opening in dielectric material 516 by a single damascene process, which may be formed by reactive ion etching (RIE) or other suitable techniques. Thus, in FIG. 11C, sidewalls 520 and 530 of conductive feature 510 can be vertical or substantially vertical. For conductive features created by dual damascene processes, the structure is unitary, continuous, or cornerless, without a step or discontinuity separating the upper and lower portions, as shown in FIGS. 11A and 11B. Similarly, in FIG. 11D, conductive feature 550 formed by a single damascene process embedded in an opening in dielectric material 556 has unitary, continuous, or cornerless sidewalls 560 and 570. Compared to the vertical sidewalls 520 and 530 in FIG. 11C , the sidewalls 560 and 570 can be sloped, at a slight angle relative to a vertical reference line or plane. The sloped sidewalls 560 and 570 can be formed due to the wet etching process (or any other suitable material removal technique) used to create the trench for forming the conductive feature 550. In some embodiments, the sloped sidewalls can have some curvature, but can nevertheless be continuous so that the sidewalls do not include corners. In conclusion, the conductive features 510 and 550 shown in FIGS. 11C and 11D formed by a single damascene process can be formed in a simpler manner than the conductive features 410 and 450 shown in FIGS. 11A and 11B formed by a dual damascene process.

[0027] 9, after the first cavity 324 for the functional or active metal pad 312 and the second cavity 330 for the non-functional metal pad 314 are formed as shown in FIG. 9, a conductive material 332 (e.g., a metal material, e.g., copper) can be deposited (e.g., plated) to fill the first cavity 324 and the second cavity 330, such that a functional conductive pad 312 is formed in the first cavity 324 and a non-functional conductive pad 314 is formed in the second cavity 330, as shown in FIG. 10. In some embodiments, prior to the metal filling process of FIG. 10, a barrier layer and a metal seed layer can be deposited to cover the entire surface of the semiconductor device 300, including the cavities shown in FIG.

[0028] After the metal fill process, a planarization process, such as CMP, is applied to remove excess metal material to form a smooth upper metal surface 316 of the second dielectric layer 306, as shown in FIG. 3 . The planarization process may include removing portions of the barrier layer between the metal material and the second dielectric layer 306, and possibly portions of the second dielectric layer 306 as well. The smooth upper surface 316 of the second dielectric layer 306 may be configured for bonding (e.g., direct hybrid bonding) to another semiconductor element or microelectronic device. As described below, in various embodiments, additional processes (such as an activation process and / or a termination process) may be performed to prepare the upper surface 316 for direct bonding.

[0029] 3, the functional metal pads 312 and the non-functional metal pads 314 may have different cross-sectional dimensions because the cross-sectional dimensions of the functional metal pads 312 may be constrained by the dimensions of the metal traces 308. The density of the metal pads 312 and 314 in the second dielectric layer 306 can be determined in various ways, such as areal density, which is the ratio of the area of ​​the exposed metal pads 312 and 314 to the total area of ​​the top surface 316 when viewed perpendicular to the top surface 316, and volumetric density, which is the ratio of the volume of the metal pads 312 and 314 in the second dielectric layer 306 to the volume of the second dielectric layer 306 containing the metal pads. If the sidewalls of the metal pads 312 and 314 are formed nearly vertically, the areal density can approach the volumetric density when the depth of the non-functional metal pads approaches the depth of the functional metal pads. Referring back to FIG. 3 , the pad areal density of the metal pads 312 and 314, as viewed perpendicular to the top metal surface 316 of the semiconductor device 300, can be designed to be uniform or nearly uniform across the entire surface 316 to effectively control stresses due to direct bonding. In some embodiments, if an area of ​​the surface 316 does not have functional metal pads 312, non-functional metal pads 314 can be placed to match the pad density of the areas with functional metal pads 312. In some embodiments, if an area of ​​the surface 316 has a lower pad density than other areas, non-functional metal pads 314 can be added to that area so that the pad density of that area is nearly the same as (or large enough to balance the stresses) the pad density of the other areas. In some embodiments, the pad areal density on the surface 316 can be controlled by adjusting the size or cross-sectional dimensions of the non-functional metal pads 314. For example, smaller non-functional metal pads 314 can be placed in areas with more functional metal pads 312, and larger non-functional metal pads 314 can be placed in areas with fewer functional metal pads 312.

[0030] As shown in FIG. 3 , the non-functional metal pads 314 located in the central region can be wider than the non-functional pads 314 located in the peripheral regions around the central region. This arrangement can be used to balance the size difference of the functional metal pads 312 when viewed perpendicular to the top surface 316. Furthermore, the ratio D3a / D3b of the depth of the non-functional metal pads 314 to the depth of the functional metal pads 312 can be made deeper by forming the non-functional metal pads 314 deeper but not reaching the underlying metal layer 308, or by forming a bonding layer. The stress in the dielectric layer 306 is reduced, and distortion of the semiconductor device 300 due to the placement of the non-functional metal pads 314 is minimized, allowing the semiconductor surface 316 to be bonded to other devices with a reduced risk of bonding voids at the interface.

[0031] 12 and 13, a fabrication process for producing the semiconductor device 200 shown in FIG. 2 is illustrated in schematic cross-sectional views. In FIG. 12, the semiconductor device 200 at this stage includes a second dielectric layer 206 formed on a first dielectric layer 204 having an embedded metal layer 208. The first dielectric layer 204 is disposed on a device portion 202 having an embedded circuit 201. In this embodiment, the layer of second dielectric material 206 on the metal layer can be deposited after the metal layer 208 is formed. FIG. 12 shows that a first cavity 224 is formed in the second dielectric layer 206 for a functional metal pad, for example, through patterning and etching similar to the process described for the semiconductor device 300 with reference to FIGS. 6 and 7. In FIG. 13, a second cavity 230 is formed in the second dielectric layer 206 for a non-functional metal pad, for example, through patterning and etching similar to the process described for the semiconductor device 300 with reference to FIGS. 8 and 9. Thus, first cavity 224 and second cavity 230 are formed according to a two-step single damascene etching process that differs significantly from the dual damascene process used to form semiconductor device 100 of Figure 1. Cavities 224 and 230 can be filled with a conductive material (e.g., a metal) and planarized similar to the process shown in Figure 10 for semiconductor device 300 to form semiconductor device 200 shown in Figure 2. When viewed perpendicular to top surface 216, functional metal pads 212 and non-functional metal pads 214 can be uniformly or nearly uniformly distributed to minimize stress in dielectric layer 206. Furthermore, as shown in FIG. 2, the ratio D2a / D2b of the depth of the non-functional metal pad 214 to the depth of the functional metal pad 212 can be increased by making the non-functional metal pad 214 deeper but not reaching the underlying metal layer 208, or by making the bonding layer that includes at least a portion of the dielectric layer 206 thinner, in order to reduce stress and strain in the dielectric layer 206.

[0032] Various embodiments disclosed herein relate to direct bonding structures in which two or more elements can be directly bonded to one another without an intervening adhesive. Such processes and structures are referred to herein as "direct bonding" processes or "directly bonded" structures. Direct bonding can include bonding one material on one element to one material on another element (also referred to herein as "homogeneous" direct bonding), where the materials on the different elements need not be identical, without traditional adhesive materials. Direct bonding can also include bonding multiple materials on one element to multiple materials on another element (e.g., hybrid bonding).

[0033] In some embodiments (not shown), each bonding layer comprises one material. In these homogeneous direct bonding processes, only one material on each component is directly bonded. An example of a homogeneous direct bonding process is ZIBOND® technology, commercially available from Adeia, Inc., San Jose, California. The materials of opposing bonding layers on different components can be the same or different and can comprise elemental or compound materials. For example, in some embodiments, a non-conductive bonding layer can be blanket deposited on a base substrate portion without being patterned with conductive features (e.g., without pads). In other embodiments, bonding layers can be patterned on one or both components, and can be the same or different from each other, with one layer of material from each component directly bonded across the surface of the component (or across the surface of the smaller component if the components are sized differently) without adhesive. In another embodiment of homogeneous direct bonding, one or both non-conductive bonding layers can include one or more conductive features, but the conductive features do not participate in the bonding. For example, in some embodiments, opposing non-conductive bonding layers can be uniformly bonded directly to one another, and through-substrate vias (TSVs) can be formed through one device after bonding to provide electrical communication to the other device.

[0034] In various embodiments, bonding layers 808a and / or 808b can comprise a non-conductive material, such as a dielectric material or an undoped semiconductor material, such as undoped silicon, which may include a native oxide. Suitable direct-bonded dielectric bonding surfaces or materials include, but are not limited to, inorganic dielectrics, such as silicon oxide, silicon nitride, or silicon oxynitride, or may contain carbon, such as silicon carbide, silicon oxynitride, low-K dielectric materials, SiCOH dielectrics, silicon carbonitride, or materials containing diamond-like carbon or diamond surfaces. Such carbon-containing ceramic materials may be considered inorganic materials, despite containing carbon. In some embodiments, the dielectric material at the bonding surface does not comprise a polymeric material, such as an epoxy (e.g., an epoxy adhesive, a cured epoxy, or an epoxy composite material such as FR-4 material), a resin, or a molding compound.

[0035] In other embodiments, the bonding layer may include a conductive material such as a deposited conductive oxide material, e.g., indium tin oxide (ITO), as disclosed in U.S. Provisional Patent Application No. 63 / 524,564 ( ), filed June 30, 2023, the entire contents of which are incorporated herein by reference in their entirety to provide examples of conductive bonding layers without shorting contact layers through an interface.

[0036] In direct bonding, the first and second elements can be bonded directly to each other without an adhesive, which differs from deposition processes and results in a structurally different interface compared to that produced by deposition. In some applications, the width of the first element in the bonding structure is similar to the width of the second element. In some other embodiments, the width of the first element in the bonding structure is different from the width of the second element. The width or area of ​​the larger element in the bonding structure may be at least 10% larger than the width or area of ​​the smaller element. Furthermore, the interface between directly bonded structures, unlike the interface beneath the deposited layer, may contain defective regions where nanometer-scale voids (nanovoids) exist. The nanovoids can form due to activation of one or both of the bonding surfaces (e.g., exposure to plasma, as described below).

[0037] The bonding interface between the non-conductive bonding surfaces may contain a higher material concentration from the activation and / or final chemical treatment process compared to the bulk of the bonding layer. For example, in embodiments utilizing nitrogen plasma for activation, a nitrogen concentration peak may form at the bonding interface. In some embodiments, the nitrogen concentration peak may be detectable using secondary ion mass spectrometry (SIMS) techniques. In various embodiments, for example, nitrogen termination (e.g., exposing the bonding surface to a nitrogen-containing plasma) may replace OH groups on a hydrolyzed (OH-terminated) surface with NH molecules, resulting in a nitrogen-terminated surface. In embodiments utilizing oxygen plasma for activation, an oxygen concentration peak may form at the bonding interface between the non-conductive bonding surfaces. In some embodiments, the bonding interface may include silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. Direct bonding may have covalent bonds stronger than van der Waals bonds. The bonding layer may also include a polished surface planarized to a high degree of smoothness.

[0038] In direct bonding processes, such as homogeneous direct bonding and hybrid bonding, two components are bonded without an intervening adhesive. In non-direct bonding processes that utilize adhesive bonding, an intervening material is typically applied to one or both components to achieve a physical connection between the components. For example, in some adhesive-based processes, a flowable adhesive (e.g., an organic adhesive such as an epoxy) that may contain conductive fillers can be applied to one or both components and cured to form a physical (rather than chemical or covalent) connection between the components. Typical organic adhesives do not have strong chemical or covalent bonds with either component. In such processes, the bond between the components is weak and / or easily reversible by reheating or defluxing.

[0039] In contrast, a direct bonding process bonds two elements by forming a strong chemical bond (e.g., a covalent bond) between opposing non-conductive materials. For example, in a direct bonding process between non-conductive materials, one or both non-conductive surfaces of two elements are planarized and chemically prepared (e.g., activated and / or terminated) so that when the elements are brought into contact, a chemical bond (e.g., a covalent bond) stronger than van der Waals or hydrogen bonds is formed. In some embodiments (e.g., between opposing dielectric surfaces, such as opposing silicon oxide surfaces), the chemical bond can form spontaneously at room temperature when brought into contact. In some embodiments, the chemical bond between the opposing non-conductive materials can be strengthened after annealing the elements. As mentioned above, hybrid bonding is a type of direct bonding in which a non-conductive feature is directly bonded to a non-conductive feature and a conductive feature is directly bonded to a conductive feature of the bonded device. The non-conductive bonding materials and interfaces are as described above, while conductive bonds can be formed, for example, as direct metal-to-metal connections. In a traditional metal bonding process, a fusible metal alloy (e.g., solder) is applied between the conductors of two devices, heated to melt the alloy, and cooled to form a connection between the two devices. The resulting bond often has sharp interfaces with the conductors of both devices and is prone to reversal upon reheating. In contrast, the direct bonding employed in hybrid bonding does not require a melt or intermediate fusible metal alloy, can provide strong mechanical and electrical connections, and often exhibits interdiffusion with grain growth across the bonding interface between the devices, even without the much higher temperatures and pressures of thermocompression bonding.

[0040] 14 and 15 schematically illustrate cross-sectional side views of first and second elements 802, 804, respectively, before and after a process for forming a direct-bonded structure, more particularly a hybrid-bonded structure, according to some embodiments. In FIG. 15 , the bonding structure 800 includes first and second elements 802, 804 directly bonded to one another at a bonding interface 818 without an intervening adhesive. A conductive feature 806 a of the first element 802 can be electrically connected to a corresponding conductive feature 806 b of the second element 804. In the illustrated hybrid bonding structure 800, the conductive feature 806 a is directly bonded to the corresponding conductive feature 806 b without solder or an intervening conductive adhesive.

[0041] In the illustrated embodiment, the conductive features 806a and 806b are embedded in and can be considered part of the first bonding layer 808a of the first element 802 and the second bonding layer 808b of the second element 804, respectively. The field regions of the bonding layers 808a and 808b extend between and partially or completely surround the conductive features 806a and 806b. The bonding layers 808a and 808b can include layers of non-conductive material suitable for direct bonding, as described above, and the field regions are bonded directly to each other without adhesive. The non-conductive bonding layers 808a and 808b can be disposed on the front sides 814a and 814b of the base substrate portions 810a and 810b, respectively.

[0042] The first and second elements 802, 804 may include microelectronic elements such as semiconductor elements including, for example, integrated device dies, wafers, passive devices, discrete active devices such as power switches, MEMS, etc. In some embodiments, the base substrate portion may comprise device portions, such as bulk semiconductor (e.g., silicon) portions of the elements 802, 804, and backing layers (BEOL) over such semiconductor portions. The bonding layers 808 a, 808 b may be provided as part of such BEOL layers during device fabrication, as part of a redistribution layer (RDL), or as specific bonding layers added to an existing device having bond pads extending from underlying contacts. Active devices and / or circuitry may be patterned and / or otherwise disposed in or on the base substrate portions 810 a, 810 b and may be in electrical communication with at least some of the conductive features 806 a, 806 b. Active devices and / or circuitry can be located on or near the front sides 814a, 814b of base substrate portions 810a, 810b and / or on or near the opposite back sides 816a, 816b of base substrate portions 810a, 810b. In other embodiments, base substrate portions 810a, 810b do not include active circuitry and instead can comprise dummy substrates, passive interposers, passive optical elements (e.g., glass substrates, diffraction gratings, lenses), etc. Although bonding layers 808a, 808b are shown on the front sides of the elements, similar bonding layers can additionally or alternatively be provided on the back sides of the elements.

[0043] In some embodiments, the base substrate portions 810a, 810b can have significantly different coefficients of thermal expansion (CTE), and bonding elements including such different base substrate portions can form a heterogeneous bonding structure. The CTE difference between the base substrate portions 810a, 810b, and particularly between the bulk semiconductor (typically single crystalline) portions of the base substrate portions 810a, 810b, can be greater than 5 ppm / °C or greater than 10 ppm / °C. For example, the CTE difference between the base substrate portions 810a, 810b can be in the range of 5 ppm / °C to 100 ppm / °C, 5 ppm / °C to 40 ppm / °C, 10 ppm / °C to 100 ppm / °C, or 10 ppm / °C to 40 ppm / °C.

[0044] In some embodiments, one of the base substrate portions 810a, 810b can comprise an optoelectronic single crystal material, including perovskite materials useful for opto-piezoelectric or pyroelectric applications, while the other of the base substrate portions 810a, 810b can comprise a more conventional substrate material. For example, one of the base substrate portions 810a, 810b can comprise lithium tantalate (LiTaO) or lithium niobate (LiNbO), while the other of the base substrate portions 810a, 810b can comprise silicon (Si), quartz, fused silica, sapphire, or glass. In other embodiments, one of the base substrate portions 810a, 810b can comprise a single III-V semiconductor material, such as gallium arsenide (GaAs) or gallium nitride (GaN), while the other of the base substrate portions 810a, 810b can comprise a non-III-V semiconductor material, such as silicon (Si), or another material with a similar CTE, such as quartz, fused silica, sapphire, or glass. In yet other embodiments, one of the base substrate portions 810a, 810b comprises a semiconductor material and the other of the base substrate portions 810a, 810b comprises a packaging material, such as a glass, organic, or ceramic substrate.

[0045] In some arrangements, the first element 802 may comprise a single crystal element, such as a single crystal integrated device die. In other embodiments, the first element 802 may comprise a carrier or substrate (e.g., a semiconductor wafer) including a plurality (e.g., tens, hundreds, or more) of device regions, and such a carrier may be a package substrate or a passive or active interposer. Similarly, the second element 804 may comprise a singulated element, such as a singulated integrated device die. In other arrangements, the second element 804 may comprise a carrier or substrate (e.g., a semiconductor wafer). The embodiments disclosed herein may be applied to wafer-to-wafer (W2W), die-to-die (D2D), or die-to-wafer (D2W) bonding processes, as appropriate. In a W2W process, two or more wafers are directly bonded together (e.g., direct bonding) and may be singulated using an appropriate singulation process. After singulation, the side edges of the singulated structure (e.g., the side edges of the two bonded elements) may be substantially flush (substantially aligned in x and y dimensions) and / or the edges of the bonding interface of both the bonded and singulated elements may be coplanar and may include markings indicative of the common singulation process of the bonded structures (e.g., sawtooth markings if a sawtooth singulation process is used).

[0046] Although only two elements 802, 804 are shown, any suitable number of elements can be stacked on the bonding structure 800. For example, a third element (not shown) can be stacked on the second element 804, and a fourth element (not shown) can be stacked on the third element. In such implementations, through-substrate vias (TSVs) can be formed to provide vertical electrical communication between the vertically stacked elements and / or between the elements. Additionally or alternatively, one or more additional elements (not shown) can be stacked laterally adjacent to each other along the first element 802. In some embodiments, the laterally stacked additional elements can be smaller than the second element. In some embodiments, the bonding structure can be encapsulated with a thermal insulating material, such as an inorganic dielectric (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.). One or more insulating layers can be provided on the bonding structure. For example, in some embodiments, a first insulating layer can be conformally deposited on the bonding structure, and a second insulating layer (which may be the same material as the first insulating layer or may comprise a different material) can be provided on the first insulating layer.

[0047] To effect direct bonding between the bonding layers 808a, 808b, the bonding layers 808a, 808b can be prepared for direct bonding. Non-conductive bonding surfaces 812a, 812b on the upper or outer surfaces of the bonding layers 808a, 808b can be prepared for direct bonding by polishing, for example, by chemical mechanical polishing (CMP). The roughness of the polished bonding surfaces 812a, 812b can be less than 30 Å rms. For example, the roughness of the bonding surfaces 812a, 812b can be in the range of approximately 0.1 Å rms to 15 Å rms, 0.5 Å rms to 10 Å rms, or 1 Å rms to 5 Å rms. The polishing can also be adjusted to leave the conductive features 806a, 806b recessed relative to the field areas of the bonding layers 808a, 808b.

[0048] Preparation for direct bonding can also include cleaning one or both of the bonding surfaces 812a, 812b and exposing them to a plasma and / or an etchant to activate at least one of the bonding surfaces 812a, 812b. In some embodiments, one or both of the surfaces 812a, 812b can be terminated with chemical species after or during activation (e.g., during a plasma and / or etch process). Without being limited by theory, in some embodiments, an activation process can be performed to break chemical bonds at the bonding surfaces 812a, 812b, and a termination process can provide the bonding surfaces 812a, 812b with additional chemical species that modify the chemical bonds and / or improve bond energy during direct bonding. In some embodiments, activation and termination are provided in the same step, e.g., plasma to activate and terminate the surfaces 812a, 812b. In other embodiments, one or both of the bonding surfaces 812a, 812b can be terminated in a separate process to provide additional species for direct bonding. In various embodiments, the termination species can include nitrogen. For example, in some embodiments, the bonding surfaces 812a, 812b can be exposed to a nitrogen-containing plasma. Other termination species can be suitable to improve bonding energy, depending on the material of the bonding surfaces 812a, 812b. Furthermore, in some embodiments, the bonding surfaces 812a, 812b can be exposed to fluorine. For example, one or more fluorine concentration peaks can be present at or near the bonding interface 818 between the first and second elements 802, 804. Typically, the fluorine concentration peaks occur at the interface between material layers.Additional examples of activation and / or termination processes are described in U.S. Pat. No. 9,391,143 at column 5, line 55 to column 7, line 3; column 8, line 52 to column 9, line 45; column 10, lines 24 to 36; column 11, lines 24 to 32, lines 42 to 47, lines 52 to 55, and lines 60 to 64; column 12, lines 3 to 14, lines 31 to 33, and No. 10,434,749, the teachings of which are incorporated herein by reference, are set forth in U.S. Pat. No. 10,434,749, lines 55 to 67, column 14, lines 38-40, and lines 44-50, and in column 4, lines 41-50, column 5, lines 7-22, 39, 55-61, column 8, lines 25-31, 35-40, and 49-56, and column 12, lines 46-61.

[0049] Thus, in the direct-bonded structure 800, the bonding interface 818 between the two non-conductive materials (e.g., bonding layers 808a, 808b) can have a very smooth interface with a higher nitrogen (or other termination species) content and / or a fluorine concentration peak at the bonding interface 818. In some embodiments, the nitrogen and / or fluorine concentration peak can be detected using various types of inspection techniques, such as SIMS techniques. The polished bonding surfaces 812a and 812b can be slightly rough (e.g., about 1 Å rms to 30 Å rms, 3 Å rms to 20 Å rms, or possibly rougher) after the activation process. In some embodiments, activation and / or termination can result in a slightly smooth surface before bonding, such that the plasma treatment preferentially erodes the high points of the bonding surface.

[0050] The non-conductive bonding layers 808a and 808b can be directly bonded to one another without adhesive. In some embodiments, the elements 802, 804 are brought together at room temperature without the need to apply a voltage and without the need to apply external pressure or force beyond that used to initiate contact between the two elements 802, 804. Contact alone can result in direct bonding between the non-conductive surfaces of the bonding layers 808a, 808b (e.g., covalent dielectric bonding). Subsequent annealing of the bonded structure 800 can result in direct bonding of the conductive features 806a, 806b.

[0051] In some embodiments, prior to direct bonding, the conductive features 806 a, 806 b are recessed relative to the surrounding field area so that the total gap between opposing contacts after dielectric bonding and before annealing is less than 15 nm, or less than 10 nm. Because the recess depth of the conductive features 806 a, 806 b can vary for each element due to process variations, the gaps listed can represent the maximum or average gap between corresponding conductive features 806 a, 806 b of the two bonding elements (before annealing). Upon annealing, the conductive features 806 a, 806 b expand and can contact each other to form a metal-to-metal direct bond.

[0052] During annealing, the conductive features 806 a, 806 b (e.g., metallic material) can expand such that thermal expansion increases the internal contact pressure between the opposing conductive features, while the direct bond between the surrounding non-conductive material of the bonding layers 808 a, 808 b resists separation of the elements. Annealing can also cause metal grain growth across the bonding interface, such that grains from one element migrate at least partially across the bonding interface to the other element, and vice versa. Thus, in some hybrid bonding embodiments, opposing conductive materials are bonded without heating above the melting temperature of the conductive materials, and bonds can be formed at lower annealing temperatures compared to soldering or thermocompression bonding.

[0053] In various embodiments, the conductive features 806 a, 806 b may comprise discrete pads, contacts, electrodes, or traces at least partially embedded in non-conductive field regions of the bonding layers 808 a, 808 b. In some embodiments, the conductive features 806 a, 806 b may comprise exposed contact surfaces of TSVs (e.g., through silicon vias).

[0054] As mentioned above, in some embodiments, in the devices 802, 804 of FIG. 14 prior to direct bonding, a portion of each conductive feature 806a, 806b can be recessed below the non-conductive bonding surface 812a, 812b by, for example, less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, e.g., in the range of 2 nm to 20 nm, or in the range of 4 nm to 10 nm. Due to process variations, both the dielectric thickness and the conductor recess depth can vary throughout the device. Thus, the recess depth ranges listed above can apply to individual conductive features 806a, 806b or to the average recess depth for a localized non-conductive field region. Even for individual conductive features 806a, 806b, the vertical recess can vary throughout the feature, and therefore can be measured at or near the lateral center of the cavity in which a given conductive feature 806a, 806b is formed, or can be measured on the side of the cavity.

[0055] Advantageously, the use of hybrid bonding technology (such as Direct Bond Interconnect, or DBI®, a technology commercially available from Adeia, Inc., San Jose, California) can enable high density connections (e.g., small or fine pitch for regular arrays) between conductive features 806a, 806b across the direct bonding interface 818.

[0056] In some embodiments, the pitch p of conductive features 806a, 806b, such as conductive traces embedded in the bonding surface of one of the bonded elements, may be less than 40 μm, less than 20 μm, less than 10 μm, less than 5 μm, less than 2 μm, or less than 1 μm. In some applications, it is desirable for the ratio of the pitch of conductive features 806a and 806b to one of the lateral dimensions (e.g., diameter) of the bond pad to be less than 20, or less than 10, or less than 5, or less than 3, and sometimes less than 2. In various embodiments, conductive features 806a, 806b and / or traces can comprise copper or a copper alloy, although other metals such as nickel, aluminum, or alloys thereof are suitable. Conductive features disclosed herein, such as conductive features 806a and 806b, can comprise a fine-grained metal (e.g., fine-grained copper). Additionally, the major lateral dimension (eg, pad diameter) can also be reduced, for example, within a range of about 0.25 μm to 30 μm, within a range of about 0.25 μm to 5 μm, or within a range of about 0.5 μm to 5 μm. For hybrid-bonded elements 802, 804 as shown, the orientation of one or more conductive features 806a, 806b from opposing elements can be opposite to each other. As is known in the art, conductive features can generally be formed with near-vertical sidewalls, particularly when the conductor sidewalls are defined by directional reactive ion etching (RIE), either directly by etching the conductive material or indirectly by etching the surrounding insulator in a damascene process. However, a slight taper may exist in the conductor sidewall, in which case the conductor narrows away from the surface initially exposed to the etch. The taper may be more pronounced when the conductor sidewalls are defined directly or indirectly by an isotropic wet or dry etch. In the illustrated embodiment, at least one conductive feature 806b in the bonding layer 808b of the top element 804 (and / or at least one internal conductive feature, such as a back-end or back-end feature) can taper or narrow upward, away from the bonding surface 812b. In contrast, at least one conductive feature 806a (and / or at least one internal conductive feature, such as a BEOL feature) of the bonding layer 808a of the bottom element 802 may taper or narrow downwardly away from the bonding surface 812a. Similarly, any bonding layer (not shown) on the backside 816a, 816b of the elements 802, 804 may taper or narrow away from the backside in an opposite taper direction relative to the frontside conductive feature 806a, 806b of the same element.

[0057] As described above, during the annealing stage of hybrid bonding, the conductive features 806a, 806b expand and contact each other, enabling direct metal-to-metal bonding. In some embodiments, the materials of the conductive features 806a, 806b of the opposing elements 802, 804 can interdiffuse during the annealing process. In some embodiments, metal grains grow into each other across the bonding interface 818. In some embodiments, the metal is or includes copper, which can have grains oriented along crystal planes 111 to improve copper diffusion across the bonding interface 818. In some embodiments, the conductive features 806a, 806b can include a nanotwin copper grain structure, which can aid in the coalescence of the conductive features during annealing. There is substantially no gap between the non-conductive bonding layers 808a, 808b at or near the bonded conductive features 806a, 806b. In some embodiments, a barrier layer (which may comprise, for example, copper) may be provided beneath and / or laterally surrounding conductive features 806a and 806b, however, in other embodiments, there may not be a barrier layer beneath conductive features 806a and 806b.

[0058] Illustrative Embodiments In various embodiments, the present disclosure provides a device comprising an interconnect structure having an upper surface fabricated for direct bonding, a first contact pad extending to a first depth below the upper surface, and a second contact pad extending to a second depth below the upper surface, the second depth being less than the first depth.

[0059] In one aspect of the present disclosure, the first contact pad comprises an active pad electrically connected to the underlying interconnect, and further, the first contact pad directly connects to the underlying interconnect without an intervening via.

[0060] In another aspect of the present disclosure, the second contact pad includes a dummy pad that is not electrically connected to the interconnect.

[0061] In another aspect of the present disclosure, the first contact pad and the second contact pad are made of metal, and further, the first contact pad and the second contact pad are made of copper.

[0062] In another aspect of the present disclosure, the first contact pad is disposed in an opening having a continuous sidewall. Alternatively, the first contact pad is disposed in an opening having a cornerless sidewall. The first contact pad is formed by a single damascene process.

[0063] In another aspect of the present disclosure, the first pads and the second pads are substantially uniformly distributed on the upper surface of the interconnect structure, or the first pads and the second pads are substantially uniformly distributed within the interconnect structure.

[0064] In another aspect of the present disclosure, the ratio of the second depth to the first depth is greater than 50%. Alternatively, the ratio of the second depth to the first depth is greater than 85%.

[0065] In another aspect of the present disclosure, an interconnect structure comprises a first dielectric layer including an upper surface, with first and second contact pads extending within the first dielectric layer.

[0066] In another aspect of the present disclosure, the underlying interconnect is a redistribution layer (RDL) trace. Further, the underlying interconnect is the outermost metal layer of the microelectronic device.

[0067] In another aspect of the present disclosure, the device further comprises a device layer disposed on the interconnect structure, the device layer comprising circuitry electrically connected to the underlying interconnects.

[0068] In yet another aspect of the present disclosure, the device layer comprises a complementary metal oxide semiconductor (CMOS) device.

[0069] In some embodiments, the present disclosure provides a bonding structure comprising the above device and a second element including a second dielectric layer and a third contact pad at least partially embedded in the second dielectric layer, wherein the first dielectric layer is bonded directly to the second dielectric layer without an adhesive and the first contact pad is bonded directly to the second dielectric layer without an adhesive.

[0070] In some embodiments, the present disclosure provides a device comprising an interconnect structure having a surface prepared for direct bonding and a plurality of pads embedded in the interconnect structure, the plurality of pads comprising a first plurality of active pads and a second plurality of dummy pads, the dummy pads having a thickness less than the active pads.

[0071] In one aspect of the present disclosure, each of the first plurality of active pads electrically connects to the underlying interconnect, and further, each of the first plurality of active pads directly connects to the underlying interconnect without going through a via.

[0072] In another aspect of the present disclosure, each of the second plurality of dummy pads is not electrically connected to an underlying interconnect.

[0073] In another aspect of the present disclosure, the first plurality of active pads are formed by a single damascene process.

[0074] In another aspect of the present disclosure, the pads are made of metal. Further, the pads are made of copper.

[0075] In another aspect of the present disclosure, each active pad has a unitary sidewall, or each active pad has a sidewall without corners.

[0076] In another aspect of the present disclosure, the first plurality of active pads and the second plurality of dummy pads are substantially uniformly distributed over the surface of the interconnect structure, or alternatively, the first plurality of active pads and the second plurality of dummy pads are substantially uniformly distributed within the interconnect.

[0077] In another aspect of the present disclosure, a surface of an interconnect structure comprises a first region having a first areal density of active pads and dummy pads having a first cross-sectional dimension, and a second region having a second areal density of active pads and dummy pads having a second cross-sectional dimension, the first areal density being greater than the second areal density, and the second cross-sectional dimension being greater than the first cross-sectional dimension.

[0078] In yet another aspect of the present disclosure, the ratio of the thickness of the dummy pad to the thickness of the active pad is greater than 50%, and the depth ratio is greater than 85%.

[0079] In some embodiments, the present disclosure provides a method for manufacturing a semiconductor device, comprising: a device portion including a circuit; and an interconnect layer disposed on the device portion and having an upper bonding surface configured for direct hybrid bonding to a second device, the interconnect layer comprising: two or more non-conductive layers on the device portion, the two or more non-conductive layers having a first cavity and a second cavity formed therein; a buried conductive layer electrically connected to the circuit, the buried conductive layer being buried within the two or more non-conductive layers at a first depth below the upper bonding surface; and a buried conductive layer disposed in the first cavity. an electrically functional conductive pad extending from the upper bonding surface through at least a portion of the one or more non-conductive layers and connecting to the buried conductive layer, the first cavity being defined by continuous sidewalls of the one or more non-conductive layers extending from the upper bonding surface; and an electrically non-functional conductive pad disposed in a second cavity and extending from the upper bonding surface through at least a portion of the one or more non-conductive layers, the electrically non-functional conductive pad terminating at a second depth that is less than the first depth.

[0080] In some embodiments, the present disclosure is a method of fabricating a semiconductor device, the method including: forming at least one first cavity in an interconnect layer of the semiconductor device, the at least one first cavity extending from an upper surface of the interconnect layer to a buried conductive layer of the semiconductor device; forming at least one second cavity in the interconnect layer laterally spaced apart from the at least one first cavity, the at least one second cavity extending from the upper surface of the interconnect layer and terminating at a depth in a dielectric layer above the buried conductive layer; providing a conductive material in the first cavity and the second cavity; and preparing the upper surface of the interconnect layer for direct hybrid bonding to another device.

[0081] In one aspect of the present disclosure, the method further includes planarizing the upper surface by removing excess metal material beyond the interconnect layer to form a bonding surface.

[0082] In another aspect of the present disclosure, the conductive material is a metal. Further, the conductive material is copper.

[0083] Unless the context clearly dictates otherwise, throughout this specification and claims, terms such as "comprises," "comprising," and the like are to be construed in an inclusive sense, i.e., "including but not limited to," rather than in a restrictive or exhaustive sense. The term "coupled," as generally used herein, refers to two or more elements that are either directly coupled or coupled via one or more intermediate elements. Similarly, the term "connected," as generally used herein, refers to two or more elements that are either directly connected or connected via one or more intermediate elements. Furthermore, the terms "herein," "above," "below," and similar terms, when used in this application, refer to this application as a whole and not to any particular portions of this application. Furthermore, as used herein, when a first element is described as being "on" or "on" a second element, the first element can be directly on or above the second element such that the first and second elements are in direct contact, or the first element can be indirectly on or above the second element such that one or more elements are interposed between the first and second elements. Where the context allows, words in the above Detailed Description using the singular or plural number may also include the plural or singular number, respectively. The word "or" in reference to a list of two or more items covers all of the following interpretations of that word: any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0084] Additionally, conditional language used herein, such as, among others, "can," "could," "might," "for example," "such as," and the like, is generally intended to convey that certain embodiments include certain features, elements, and / or conditions, and that other embodiments do not include certain features, elements, and / or conditions, unless otherwise specified or understood within the context in which it is used. Thus, such conditional language is generally not intended to imply that a feature, element, and / or condition is in any way required in one or more embodiments.

[0085] While specific embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the present disclosure. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms, and various omissions, substitutions, and modifications in the form of the methods and systems described herein may be made without departing from the spirit of the present disclosure. For example, while blocks are shown in a given arrangement, similar functions may be performed by different components and / or circuit topologies in alternative embodiments, and some blocks may be deleted, moved, added, subdivided, combined, and / or modified. Each of these blocks may be implemented in a variety of different ways. Any suitable combination of elements and acts in the various embodiments described above may be combined to provide further embodiments. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the present disclosure. [Explanation of symbols]

[0086] 200 Semiconductor elements 201 Active users 202 Device part 203 Interconnect Structure 204 Dielectric layer 205 Beer 206 Dielectric Layer 208 Lower Interconnect 212 Active Metal Pad 214 Non-functional metal pads 216 Top surface

Claims

1. an interconnect structure having an upper surface adapted for direct bonding; a first contact pad extending to a first depth below the upper surface; a second contact pad extending to a second depth below the upper surface, the second depth being less than the first depth; and 1. A device comprising:

2. The device of claim 1 , wherein the first contact pad comprises an active pad electrically connected to an underlying interconnect.

3. 3. The device of claim 2, wherein the first contact pad is directly connected to the underlying interconnect without an intervening via.

4. The device of claim 2 , wherein the second contact pad comprises a dummy pad that is not electrically connected to the underlying interconnect.

5. The device of claim 1 , wherein the first contact pad and the second contact pad are metallic.

6. The device of claim 5 , wherein the first contact pad and the second contact pad are made of copper.

7. The device of claim 1 , wherein the first contact pad is disposed in an opening having continuous sidewalls.

8. The device of claim 1 , wherein the first contact pad is disposed in an opening having sidewalls without corners.

9. The device of claim 1 , wherein the first contact pad is formed by a single damascene process.

10. The device of claim 1 , wherein the first pads and the second pads are substantially uniformly distributed on the upper surface of the interconnect structure.

11. The device of claim 1 , wherein the first pads and the second pads are substantially uniformly distributed in the interconnect structure.

12. The device of claim 1 , wherein a ratio of the second depth to the first depth is greater than 50%.

13. The device of claim 12 , wherein the ratio of the second depth to the first depth is greater than 85%.

14. 10. The device of claim 1, wherein the interconnect structure comprises a first dielectric layer including the upper surface, and the first and second contact pads extend into the first dielectric layer.

15. 15. A bonding structure comprising the device of claim 14 and a second element including a second dielectric layer and a third contact pad at least partially embedded in the second dielectric layer, A bonding structure, wherein the first dielectric layer is bonded directly to the second dielectric layer without an adhesive, and the first contact pad is bonded directly to the third contact pad without an adhesive.

16. The device of claim 2 , wherein the underlying interconnects are redistribution layer (RDL) traces.

17. The device of claim 2 , wherein the underlying interconnect is an outermost metal layer of a microelectronic device.

18. The device of claim 2 further comprising a device layer disposed over the interconnect structure, the device layer including circuitry electrically connected to the underlying interconnects.

19. 20. The device of claim 18, wherein the device layer comprises a complementary metal oxide semiconductor (CMOS) device.

20. an interconnect structure having a surface adapted for direct bonding; a plurality of pads embedded within the interconnect structure, The plurality of pads include: a first plurality of active pads; a second plurality of dummy pads, the dummy pads having a thickness less than that of the active pads; Including, the device.

21. 21. The device of claim 20, wherein each of the first plurality of active pads is electrically connected to an underlying interconnect.

22. 22. The device of claim 21, wherein each of the first plurality of active pads is directly connected to the underlying interconnect without an intervening via.

23. 23. The device of claim 22, wherein each of the second plurality of dummy pads is not electrically connected to the underlying interconnect.

24. 23. The device of claim 22, wherein the first plurality of active pads are formed by a single damascene process.

25. 21. The device of claim 20, wherein a plurality of the pads are metallic.

26. 21. The device of claim 20, wherein a plurality of said pads are made of copper.

27. 21. The device of claim 20, wherein each active pad has a unitary sidewall.

28. 21. The device of claim 20, wherein each active pad has sidewalls without corners.

29. 21. The device of claim 20, wherein the first plurality of active pads and the second plurality of dummy pads are substantially uniformly distributed over a surface of the interconnect structure.

30. 21. The device of claim 20, wherein the first plurality of active pads and the second plurality of dummy pads are substantially uniformly distributed in the interconnect structure.

31. 21. The device of claim 20, wherein the first plurality of active pads includes two or more cross-sectional dimensions.

32. 21. The device of claim 20, wherein the second plurality of dummy pads includes two or more cross-sectional dimensions.

33. 21. The device of claim 20, wherein the surface of the interconnect structure comprises a first region having a first areal density of the active pads and dummy pads having a first cross-sectional dimension, and a second region having a second areal density of the active pads and dummy pads having a second cross-sectional dimension, the first areal density being greater than the second areal density, and the second cross-sectional dimension being greater than the first cross-sectional dimension.

34. 21. The device of claim 20, wherein the ratio of the thickness of the dummy pads to the thickness of the active pads is greater than 50%.

35. 35. The device of claim 34, wherein the depth ratio is greater than 85%.

36. 21. The device of claim 20, wherein the interconnect structure comprises a first dielectric layer including the surface, and wherein the first plurality of active pads and second plurality of dummy pads extend into the first dielectric layer.

37. 37. A bonding structure comprising the device of claim 36 and a second element including a second dielectric layer and a third plurality of contact pads at least partially embedded in the second dielectric layer, a bonding structure, wherein the first dielectric layer is bonded directly to the second dielectric layer without an adhesive, and at least a portion of the first plurality of active pads is bonded directly to at least a portion of the third plurality of contact pads without an adhesive.

38. 22. The device of claim 21, wherein the underlying interconnects are redistribution layer (RDL) traces.

39. 40. The device of claim 38, wherein the direct connections from each active pad to the RDL trace include those from two or more active pads.

40. 22. The device of claim 21, wherein the underlying interconnect is an outermost metal layer of a microelectronic device.

41. a device layer disposed with the interconnect structure; 22. The device of claim 21, wherein the device layer includes circuitry electrically connected to interconnects in the underlying layer.

42. 42. The device of claim 41, wherein the device layer comprises a complementary metal oxide semiconductor (CMOS) device.

43. A device, a device portion including a circuit; an interconnect layer disposed over the device portion and having an upper bonding surface configured for direct hybrid bonding to a second device; Equipped with The interconnect layer comprises: one or more non-conductive layers on the device portion, wherein a first cavity and a second cavity are formed in the one or more non-conductive layers; and a buried conductive layer electrically connected to the circuitry and buried in the one or more non-conductive layers at a first depth below the upper bonding surface; an electrically functional conductive pad disposed in the first cavity and extending from the upper bonding surface through at least a portion of the one or more non-conductive layers to connect to the buried conductive layer, the first cavity being defined by continuous sidewalls of the one or more non-conductive layers extending from the upper bonding surface; and an electrically non-functional conductive pad disposed in the second cavity and extending from the upper bonding surface through at least a portion of the one or more non-conductive layers, the electrically non-functional conductive pad terminating at a second depth that is less than the first depth; Including, the device.

44. 44. The device of claim 43, wherein said electrically functional conductive pads are directly connected to said buried conductive layer without intervening vias.

45. 44. The device of claim 43, wherein the electrically functional conductive pads and the electrically non-functional conductive pads are metallic.

46. 46. ​​The device of claim 45, wherein the electrically functional conductive pads and the electrically non-functional conductive pads are made of copper.

47. 44. The device of claim 43, wherein said electrically functional conductive pads have unitary sidewalls.

48. 44. The device of claim 43, wherein said electrically functional conductive pads have sidewalls without corners.

49. 44. The device of claim 43, wherein each of the first cavity and the second cavity is formed by a single damascene process.

50. 44. The device of claim 43, wherein the functional conductive pads and the non-functional conductive pads are substantially uniformly distributed on the upper bonding surface.

51. 44. The device of claim 43, wherein the functional conductive pads and the non-functional conductive pads are substantially uniformly distributed in the interconnect layer.

52. 44. The device of claim 43, wherein a ratio of the second depth to the first depth is greater than 50%.

53. 53. The device of claim 52, wherein a ratio of the second depth to the first depth is greater than 85%.

54. 44. The device of claim 43, wherein the interconnect structure comprises a first dielectric layer including the upper surface, the first and second contact pads extending into the first dielectric layer.

55. 44. A bonding structure comprising: the device of claim 43; and a second element including a second non-conductive layer and a third conductive pad at least partially embedded in the second non-conductive layer, 10. A bonding structure wherein the one or more non-conductive layers are bonded directly to the second non-conductive layer without an adhesive, and the electrically functional conductive pad is bonded directly to the third conductive pad without an adhesive.

56. 44. The device of claim 43, wherein the buried conductive layer is a redistribution layer (RDL) trace.

57. 44. The device of claim 43, wherein the buried conductive layer is an outermost metal layer of a microelectronic device.

58. 44. The device of claim 43, wherein the device portion comprises a complementary metal oxide semiconductor (CMOS) device.

59. 1. A method of fabricating a semiconductor device, comprising: forming at least one first cavity in an interconnect layer of the semiconductor device, the at least one first cavity extending from an upper surface of the interconnect layer to a buried conductive layer of the semiconductor device; forming at least one second cavity in the interconnect layer laterally spaced apart from the at least one first cavity, the at least one second cavity extending from an upper surface of the interconnect layer and terminating at a depth in a dielectric layer above the buried conductive layer; providing a conductive material to the first cavity and the second cavity; preparing the upper surface of the interconnect layer for direct hybrid bonding to another device; A method comprising:

60. 60. The method of claim 59, further comprising planarizing the upper surface by removing excess metal material beyond the interconnect layer to form a bonding surface.

61. 60. The method of claim 59, wherein the conductive material is a metal.

62. 62. The method of claim 61 , wherein the conductive material is copper.

63. 60. The method of claim 59, further comprising directly hybrid bonding the top surface of the interconnect layer to another device.

64. 60. The method of claim 59, wherein forming the at least one first cavity comprises forming the at least one first cavity by a single damascene process.

65. 60. The method of claim 59, wherein forming the at least one second cavity comprises forming the at least one second cavity by a single damascene process.

66. 60. The method of claim 59, wherein the at least one first cavity has sidewalls without corners.

67. 60. The method of claim 59, wherein the at least one first cavity has a continuous sidewall.

68. 61. The method of claim 60, wherein the conductive material provided to the at least one first cavity and the at least one second cavity is distributed substantially uniformly on the bonding surface.

69. 61. The method of claim 60, wherein the conductive material provided to the at least one first cavity and the at least one cavity is substantially uniformly distributed in the interconnect layer.

70. 61. The method of claim 60, wherein the ratio of the depth of the second cavity to the depth of the first cavity is greater than 50%.

71. 71. The method of claim 70, wherein the ratio of the depth of the second cavity to the depth of the first cavity is greater than 70%.

72. 60. The method of claim 59, wherein the buried conductive layer is a redistribution layer (RDL) trace.

73. 60. The method of claim 59, wherein the buried conductive layer is an outermost metal layer of a microelectronic device.

74. 60. The method of claim 59, wherein the semiconductor device comprises a CMOS device.

75. 1. A method of forming a bonding layer on a semiconductor device having an outermost metallization layer having at least one metal trace, comprising: depositing a dielectric layer on the metallization layer, the dielectric layer having an upper surface; patterning a top surface of the dielectric layer in a first region; etching the dielectric layer to form at least one first cavity, the at least one first cavity reaching the at least one metal trace of the metallization layer; patterning the top surface of the dielectric layer in a second region; etching the dielectric layer to form at least one second cavity, the at least one second cavity extending partially through the dielectric layer and terminating above the metallization layer; filling the first cavity and the second cavity with a metal; A method comprising:

76. 76. The method of claim 75, further comprising planarizing the semiconductor device by removing excess metal material above the dielectric layer to form a bonding surface.

77. 77. The method of claim 76, further comprising directly hybrid bonding the semiconductor device to another semiconductor device.

78. 77. The method of claim 76, wherein the metal filled in the at least one first cavity and the at least one second cavity is distributed substantially uniformly on the bonding surface.

79. 77. The method of claim 76, wherein the metal filled in the at least one first cavity and the at least one cavity is substantially uniformly distributed within an interconnect layer.

80. 76. The method of claim 75, wherein the metal is copper.

81. 76. The method of claim 75, wherein the depth of the second cavity is greater than 50% of the depth of the first cavity.

82. 76. The method of claim 75, wherein the depth of the second cavity is greater than 85% of the depth of the first cavity.

83. 76. The method of claim 75, wherein the metallization layer is a redistribution layer (RDL) trace.

84. 84. The method of claim 83, wherein the connections from each first cavity to the RDL trace include connections from two or more cavities.

85. 76. The method of claim 75, wherein the semiconductor element comprises a CMOS device.

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