Multilayer ceramic capacitor

Abstract

To provide a highly reliable multilayer ceramic capacitor in which deterioration of insulation resistance is suppressed.SOLUTION: The multilayer ceramic capacitor includes an inner layer portion 16 including a main surface and an end surface, an outer layer portion 18a covering the main surface in a stacking direction, and a side margin covering the 18b and the inner layer portion from one side in an outer layer portion widthwise direction. The dielectric particles constituting the inner layer portion and the side margin portion have pores therein, and the intragranular pore ratio in the center portion of the inner layer portion (N [inner layer center portion]) and the intragranular pore ratio in the side margin portion (N [side margin portion]) satisfy a relationship of an expression N [inner layer center portion] <N [side margin portion]. The D50 size (D5 [(inner layer W end)]) of the dielectric particles at the width-direction end (inner layer W end) of the inner layer portion and the D50 size (D50 [inner layer center]) of the dielectric particles at the center (inner layer center) of the inner layer portion satisfy the relationship of 1.00 ≤ D50 [inner layer W end] / D50 [inner layer center] ≤ 1.40.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a multilayer ceramic capacitor. [Background technology]

[0002] As electronic devices such as mobile phones become smaller and CPU speeds increase, the demand for multilayer ceramic capacitors (MLCCs) is increasing. Multilayer ceramic capacitors have thin, high-permittivity dielectric layers. This allows them to have large capacitance despite their small size. While multilayer ceramic capacitors made from a variety of materials are known, those that use ceramic dielectrics such as barium titanate (BaTiO3) for the dielectric layers and base metals such as nickel (Ni) for the internal electrode layers are widely used due to their low cost and high performance.

[0003] A multilayer ceramic capacitor comprises an inner layer portion in which dielectric layers formed of ceramic dielectrics and internal electrode layers are alternately laminated, outer layer portions covering the top and bottom of the inner layer portion, and side margin portions covering the inner layer portion and the outer layer portion in the width direction. The inner layer portion functions as a capacitance element. The outer layer portion and side margin portions are areas surrounding the inner layer portion that do not include internal electrode layers. They can be said to function to protect the inner layer portion, which functions as a capacitance element, from the external environment.

[0004] Multilayer ceramic capacitors are required to have a high capacitance per unit volume (volumetric capacitance) and a high rated voltage. To increase volumetric capacitance, it is effective to reduce the thickness of each dielectric layer and internal electrode layer and increase the number of layers as much as possible so that they are electrically connected in parallel, i.e., to increase the number of layers. It is also effective to reduce the volume of the components of a multilayer ceramic capacitor, such as the outer layer, side margin, and internal electrode lead-out portions. This increases the relative volume of the internal layer, which functions as a capacitive element, making it possible to increase volumetric capacitance.

[0005] The ceramic dielectrics in multilayer ceramic capacitors are produced by firing dielectric powders such as BaTiO3 powder. Dielectric powders are synthesized using methods such as the solid-state method, hydrothermal method, sol-gel method, alkoxide method, solvothermal method, or oxalate method. Among these, the hydrothermal method (hydrothermal synthesis method) is a method for synthesizing inorganic powders using a high-temperature, high-pressure aqueous solution. It has the advantage of producing fine powders with uniform particle size at relatively low cost. Therefore, when multilayer ceramic capacitors are manufactured using dielectric powders synthesized by the hydrothermal method (hydrothermally synthesized powders), it is possible to reduce the thickness of the dielectric layers and increase the capacitance. Furthermore, because the particle size variation of the dielectric particles is reduced, it is possible to improve the dielectric constant and reliability.

[0006] The hydrothermal method uses hydroxides as raw materials. For example, a Ba source such as barium hydroxide (Ba(OH)2) is reacted with a Ti source such as metatitanate (TiO(OH)2) or titanium oxide (TiO2) in high-temperature, high-pressure water, and the resulting reaction product is heat-treated to obtain BaTiO3 powder. The OH groups contained in the hydroxide are released from the raw material during the heat treatment, which forms voids (intragranular voids) inside the particles that make up the dielectric powder. When a multilayer ceramic capacitor is manufactured using a dielectric powder with intragranular voids, the intragranular voids remain in the resulting capacitor. In contrast, no intragranular voids are formed when using dielectric powder synthesized by methods other than the hydrothermal method.

[0007] Patent Document 1 discloses the use of hydrothermally synthesized powder for the dielectric layers of multilayer ceramic capacitors. Specifically, it discloses a method for producing a ceramic capacitor, which includes a step of producing a green sheet using a ceramic slurry containing a first ceramic powder synthesized by a hydrothermal method and a second ceramic powder synthesized by a method other than the hydrothermal method, and a step of firing the obtained green sheet (claim 5 of Patent Document 1). Patent Document 1 also describes that pores (vacancies) present in the ceramic particles relieve piezoelectric strain, which leads to crack suppression (paragraph

[0031] of Patent Document 1). [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Publication No. 2019-102655 Summary of the Invention [Problem to be solved by the invention]

[0009] With advances in electronic components and electronic equipment, further miniaturization and increased capacitance of multilayer ceramic capacitors are expected. Furthermore, as the applications of multilayer ceramic capacitors expand, there is an increasing demand for improved reliability. Therefore, there is a demand for the development of multilayer ceramic capacitors that are highly reliable and exhibit minimal degradation in insulation resistance while still achieving thinner layers. However, while previously proposed technologies have achieved a certain level of effectiveness, there is still room for improvement.

[0010] The present inventors have conducted extensive research in light of these problems and have discovered that a highly reliable multilayer ceramic capacitor in which degradation of insulation resistance is suppressed can be obtained by providing internal voids in the dielectric particles in the inner layer portions and side margin portions of the multilayer ceramic capacitor and controlling the internal porosity and the D50 diameter of the dielectric particles.

[0011] The present invention was completed based on these findings, and an object of the present invention is to provide a highly reliable multilayer ceramic capacitor in which degradation of insulation resistance is suppressed. [Means for solving the problem]

[0012] The present invention encompasses the following embodiments. In this specification, the expression "to" includes both the numerical values ​​of the two ends. That is, "X to Y" is synonymous with "X or more and Y or less." In addition, in this specification, any combination of suitable embodiments can be adopted as long as technical consistency can be achieved. For example, one of the suitable numerical ranges can be combined with the other.

[0013] According to one aspect of the present invention, a first internal electrode layer and a second internal electrode layer are alternately laminated through a dielectric layer formed of a ceramic dielectric, a first main surface which is a surface in the lamination direction, a second main surface which is a surface opposite to the first main surface, a first side surface which is a surface in the width direction orthogonal to the first main surface and the second main surface and from which the first internal electrode layer and the second internal electrode layer are drawn out, a second side surface which is a surface opposite to the first side surface and from which the first internal electrode layer and the second internal electrode layer are drawn out, a first end surface which is a surface in the length direction orthogonal to the first main surface, the second main surface, the first side surface, and the second side surface and from which the first internal electrode layer is drawn out, and a second end surface which is a surface opposite to the first end surface and from which the second internal electrode layer is drawn out, an inner layer part having A first outer layer part formed of a ceramic dielectric and covering the first main surface from the lamination direction, A second outer layer part formed of a ceramic dielectric and covering the second main surface from the lamination direction, A first side margin part formed of a ceramic dielectric and covering the inner layer part, the first outer layer part, and the second outer layer part from one side in the width direction, A second side margin part formed of a ceramic dielectric and covering the inner layer part, the first outer layer part, and the second outer layer part from the other side in the width direction, and A pair of external electrodes provided on the first end surface and the second end surface and connected to each of the first internal electrode layer and the second internal electrode layer, having Each of the dielectric particles constituting the ceramic dielectric constituting the inner layer part, the first side margin part, and the second side margin part includes dielectric particles having voids inside, The intragranular void ratio (N[inner layer central part]) in the central part (inner layer central part) of the inner layer part and the intragranular void ratio (N[side margin part]) in the first side margin part and the second side margin part satisfy the relationship of the formula: N[inner layer central part]<N[side margin part], A multilayer ceramic capacitor is provided in which the D50 diameter of the dielectric particles at the width direction end (inner layer W end) of the inner layer portion (D50[inner layer W end]) and the D50 diameter of the dielectric particles at the center (inner layer center) of the inner layer portion (D50[inner layer center]) satisfy the relationship of the formula: 1.00≦D50[inner layer W end] / D50[inner layer center]≦1.40. [Effects of the Invention]

[0014] According to the present invention, a highly reliable multilayer ceramic capacitor in which degradation of insulation resistance is suppressed is provided. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 2 is a perspective view showing the external shape of the multilayer ceramic capacitor. [Figure 2] FIG. 1 is a cross-sectional view schematically showing the internal structure of a multilayer ceramic capacitor. [Figure 3] FIG. 1 is a cross-sectional view schematically showing the internal structure of a multilayer ceramic capacitor. [Figure 4] 1 is a diagram illustrating the central portion of the inner layer and the W end portion of the inner layer. [Figure 5] 1 is a diagram showing the distribution of intragranular voids in a dielectric layer. [Figure 6] 1 is a diagram illustrating polar IR generation rate measurement. [Figure 7] 1 is a diagram illustrating a deflection test. DETAILED DESCRIPTION OF THE INVENTION

[0016] A specific embodiment of the present invention (hereinafter referred to as "the present embodiment") will be described. Note that the present invention is not limited to the following embodiment, and various modifications are possible within the scope of the present invention.

[0017] <<1. Multilayer ceramic capacitors>> The multilayer ceramic capacitor of this embodiment has an inner layer portion, a first outer layer portion, a second outer layer portion, a first side margin portion, a second side margin portion, and a pair of external electrodes. The inner layer portion is a region in which a first internal electrode layer and a second internal electrode layer are alternately laminated via a dielectric layer formed of a ceramic dielectric. The inner layer portion has a first main surface, a second main surface, a first side surface, a second side surface, a first end surface, and a second end surface. The first main surface is a surface in the lamination direction of the dielectric layer, the first internal electrode layer, and the second electrode layer. The second main surface is a surface opposite to the first main surface. The first side surface is a surface in the width direction orthogonal to the first main surface and the second main surface. The second side surface is a surface opposite to the first side surface. The first end surface is a surface in the length direction orthogonal to the first main surface, the second main surface, the first side surface, and the second side surface, and is a surface from which the first internal electrode layer is drawn out. The second end surface is a surface opposite to the first end surface and is a surface from which the second internal electrode layer is drawn out. The first outer layer portion is formed of a ceramic dielectric and covers the first main surface from the lamination direction. The second outer layer portion is formed of a ceramic dielectric and covers the second main surface from the lamination direction. The first side margin portion is formed of a ceramic dielectric and covers the inner layer portion, the first outer layer portion, and the second outer layer portion from one side in the width direction. The second side margin portion is formed of a ceramic dielectric and covers the inner layer portion, the first outer layer portion, and the second outer layer portion from the other side in the width direction. The pair of external electrodes are provided on the first end surface and the second end surface and are connected to either the first internal electrode layer or the second internal electrode layer. The dielectric particles constituting each of the inner layer portion, the first side margin portion, and the second side margin portion include dielectric particles having voids inside. The intragranular void ratio (N[inner layer central portion]) in the central portion of the inner layer portion and the intragranular void ratio (N[side margin portion]) in the first side margin portion and the second side margin portion satisfy the relationship: N[inner layer central portion] < N[side margin portion]. The D50 diameter (D50[inner layer W end portion]) of the dielectric particles at the width direction end portion (inner layer W end portion) of the inner layer portion and the D50 diameter (D50[inner layer central portion]) of the dielectric particles at the central portion (inner layer central portion) of the inner layer portion satisfy the relationship: 1.00 ≦ D50[inner layer W end portion] / D50[inner layer central portion] ≦ 1.40.

[0018] One embodiment of the multilayer ceramic capacitor will be described with reference to Fig. 1 to Fig. 3. Fig. 1 is a perspective view showing the outer shape of the multilayer ceramic capacitor. Fig. 2 is a cross-sectional view of the multilayer ceramic capacitor shown in Fig. 1 taken along line II-II, and Fig. 3 is a cross-sectional view of the multilayer ceramic capacitor shown in Fig. 1 taken along line III-III.

[0019] The multilayer ceramic capacitor 100 includes an element body 6 and a pair of external electrodes 8a, 8b provided on both end surfaces 14a, 14b of the element body 6. The multilayer ceramic capacitor 100 and the element body 6 have a substantially rectangular parallelepiped shape. The term "substantially rectangular parallelepiped" includes not only rectangular parallelepipeds but also rectangular parallelepipeds with rounded corners and / or ridges.

[0020] The multilayer ceramic capacitor 100 and the element body 6 have a first outer main surface 10a and a second outer main surface 10b that face each other in the thickness direction T, a first outer side surface 12a and a second outer side surface 12b that face each other in the width direction W, and a first outer end surface 14a and a second outer end surface 14b that face each other in the length direction L. Here, the thickness direction T is the direction in which the dielectric layers 2 and the internal electrode layers 4 included in the element body 6 are stacked. The length direction L is orthogonal to the thickness direction T and is the direction in which the outer end surfaces 14a, 14b face each other. The width direction W is the direction orthogonal to the thickness direction T and the length direction L. A plane including the thickness direction T and the width direction W is defined as a WT plane, a plane including the width direction W and the length direction L is defined as an LW plane, and a plane including the length direction L and the thickness direction T is defined as an LT plane.

[0021] The element body (6) is composed of an inner layer (16), a first outer layer (18a), a second outer layer (18b), a first side margin (20a), and a second side margin (20b).

[0022] The inner layer portion (16) is a region in which the internal electrode layers (4) are alternately stacked with the dielectric layers (2) interposed therebetween. The dielectric layers (2) are made of a ceramic dielectric. The internal electrode layers (4) are composed of a plurality of first internal electrode layers (4a) and a plurality of second internal electrode layers (4b).

[0023] The inner layer portion (16) has a first main surface, a second main surface, a first side surface, a second side surface, a first end surface, and a second end surface. The first main surface is a surface perpendicular to the stacking direction of the dielectric layer (2) and the internal electrode layers (4a, 4b). The second main surface is a surface (opposing surface) opposite to the first main surface. The first side surface is a surface orthogonal to the first main surface and the second main surface, i.e., a surface perpendicular to the width direction W. The second side surface is a surface (opposing surface) opposite to the first side surface. The first end surface is a surface orthogonal to the first main surface, the second main surface, the first side surface, and the second side surface, i.e., a surface perpendicular to the length direction L. The second end surface is a surface (opposing surface) opposite to the first end surface. The internal electrode layers (4a, 4b) are drawn out to the first side surface and the second side surface. In other words, the ends of the internal electrode layers are exposed on both the first side surface side and the second side surface side. The first internal electrode layer (4a) is extended to the first end face, but the second internal electrode layer (4b) is not extended, and the second internal electrode layer (4b) is extended to the second end face, but the first internal electrode layer (4a) is not extended.

[0024] The first outer layer portion (18a) is a region that covers the first main surface of the inner layer portion (16) in the stacking direction (thickness direction T). The second outer layer portion (18b) is a region that covers the second main surface of the inner layer portion (16) in the stacking direction. The first side margin portion (20a) is a region that covers the inner layer portion (16), the first outer layer portion (18a), and the second outer layer portion (18b) from one side in the width direction (first side surface side). The second side margin portion (20a) is a region that covers the inner layer portion (16), the first outer layer portion (18a), and the second outer layer portion (18b) from the other side in the width direction (second side surface side). The first outer layer portion (18a), the second outer layer portion (18b), the first side margin portion (20a), and the second side margin portion (20b) are formed of ceramic dielectrics.

[0025] The external electrodes (8a, 8b) are composed of a first external electrode (8a) provided on a first outer end surface (14a) of the element body 6 and a second external electrode (8b) provided on a second outer end surface (14b). The first external electrode (8a) and the second external electrode (8b) are not in contact with each other and are electrically separated from each other.

[0026] The size of the multilayer ceramic capacitor (100) or the element part (6) is not particularly limited. For example, the length direction L dimension is 0.2 mm or more and 3.2 mm or less, the width direction W dimension is 0.1 mm or more and 2.5 mm or less, and the stacking direction T dimension is 0.1 mm or more and 2.5 mm or less. Although FIGS. 1 to 3 show the length direction L dimension as being larger than the width direction W dimension, the multilayer ceramic capacitor of this embodiment is not limited to those having such dimensions. The length direction L dimension may be smaller than the width direction W dimension.

[0027] <Inner layer - dielectric layer> The inner layer portion is a region in which internal electrode layers (first internal electrode layer, second internal electrode layer) are alternately laminated via dielectric layers made of ceramic dielectrics. The dielectric layers are made of ceramic dielectrics produced by firing green sheets for the inner layers containing dielectric raw materials. Ceramic dielectrics consist of a sintered polycrystalline body (ceramic) in which numerous dielectric particles are bonded via grain boundaries and triple junctions. In other words, they contain dielectric particles (dielectric grains) as the main component. The main component is the component with the largest content in the ceramic dielectric, i.e., a component that accounts for 50% or more by mass.

[0028] The dielectric particles are composed of a perovskite oxide. Perovskite oxides have a composition represented by the general formula ABO3 and have a cubic-like crystal structure, such as a cubic, tetragonal, orthorhombic, or rhombohedral crystal structure, at room temperature. A-site element atoms (hereinafter referred to as "A-site atoms") and B-site element atoms (hereinafter referred to as "B-site atoms") are ionized to occupy the A and B sites of the perovskite structure. Examples of A-site elements include elements with relatively large ionic sizes, such as barium (Ba), calcium (Ca), and strontium (Sr), while examples of B-site elements include elements with relatively small ionic sizes, such as titanium (Ti), zirconium (Zr), and hafnium (Hf). The combination of A-site and B-site elements is not particularly limited as long as the perovskite structure is maintained. Each of the A-site and B-site elements may contain only one element or a combination of multiple elements. Furthermore, the molar ratio of A-site elements to B-site elements may deviate from 1:1 as long as the perovskite structure is maintained.

[0029] Specific examples of perovskite oxides include barium titanate (BaTiO3)-based compounds, calcium titanate (CaTiO3)-based compounds, strontium titanate (SrTiO3)-based compounds, and mixed crystals and solid solutions thereof. Preferably, the A-site element contains barium (Ba) and the B-site element contains titanium (Ti). That is, the perovskite oxide is preferably a barium titanate (BaTiO3)-based compound. BaTiO3-based compounds have a high dielectric constant. Therefore, they are particularly suitable for increasing the capacitance of multilayer ceramic capacitors. Note that BaTiO3-based compounds include not only BaTiO3 but also compounds in which part of the Ba in BaTiO3 is replaced with other A-site elements such as Sr and / or Ca, or part of the Ti is replaced with other B-site elements such as Zr and / or Hf.

[0030] The ceramic dielectric may contain a secondary component. Examples of the secondary component include, but are not limited to, rare earth elements (RE), magnesium (Mg), manganese (Mn), iron (Fe), chromium (Cr), cobalt (Co), nickel (Ni), silicon (Si), aluminum (Al), vanadium (V), and compounds thereof. Dysprosium (Dy) is preferred as the rare earth element (RE). The secondary component may contain any of the above components alone or in combination. The secondary component may be present in any of the dielectric particles, grain boundaries, and triple points.

[0031] The dielectric particles may include core-shell particles. Core-shell particles are particles having a structure (core-shell structure) in which at least a portion of the secondary component is dissolved in a high concentration in the surface layer (shell portion) of the particle and the secondary component is dissolved in a low concentration or not dissolved in the center (core portion) of the particle. Alternatively, the dielectric particles may include dielectric particles in which the secondary component is dissolved throughout the entire particle.

[0032] The thickness of the dielectric layers constituting the inner layer portion is preferably 0.6 μm or more and 3.0 μm or less. By making the thickness of the dielectric layers equal to or greater than a predetermined value, it is possible to suppress the occurrence of dielectric breakdown and deterioration of the lifespan of the multilayer ceramic capacitor when it is used. Furthermore, by making the thickness of the dielectric layers equal to or less than a predetermined value, the dielectric layers are made thinner, enabling the multilayer ceramic capacitor to have a greater capacitance. The number of dielectric layers is not particularly limited. Preferably, the number of dielectric layers constituting the inner layer portion is 100 to 2000.

[0033] <Inner layer - internal electrode layer> The internal electrode layers (first internal electrode layer, second internal electrode layer) are composed of a counter electrode portion and an extraction electrode portion, and together with the dielectric layer, form the internal layer portion. The counter electrode portion sandwiches the dielectric layer and functions as a capacitive element. The extraction electrode portion electrically connects the counter electrode portion to the external electrode. The internal electrode layers contain a conductive metal. As the conductive metal, known electrode materials such as nickel (Ni), copper (Cu), silver (Ag), palladium (Pd), silver (Ag)-palladium (Pd) alloy and / or gold (Au) may be used. The internal electrode layers are produced by sintering a conductive paste layer printed on the surface of the internal layer green sheet.

[0034] The internal electrode layers may contain components other than conductive metals. Examples of such components include ceramic components that function as co-materials. The thickness of the internal electrode layers is preferably 0.40 μm or more and 1.5 μm or less. By making the internal electrode thickness greater than a predetermined value, problems such as electrode discontinuities can be prevented. By making the thickness less than a predetermined value, a decrease in the proportion of the dielectric layer in the capacitor can be prevented, contributing to increased capacitance. The number of internal electrode layers is preferably 100 or more and 2000 or less.

[0035] <Outer layer> The outer layer portions (first outer layer portion, second outer layer portion) are provided above and below the inner layer portion. The outer layer portions are made of ceramic dielectric and are regions that do not include internal electrode layers. The outer layer portions are made by firing outer layer green sheets that contain dielectric raw materials.

[0036] <Side margin> The side margins (first side margin and second side margin) are provided along the sides of the multilayer ceramic capacitor, sandwiching the inner layer and outer layer. The side margins are also called side gaps or sides. The side margins are made of ceramic dielectric and are areas that do not contain internal electrode layers. The provision of side margins prevents moisture from penetrating into the inner layer from the sides.

[0037] The side margins are formed separately from the inner and outer layer portions during the manufacture of the multilayer ceramic capacitor. Specifically, a green element portion is prepared by attaching a side margin green body to the side surface of the multilayer chip that will become the inner and outer layer portions, and then this green element portion is fired. In this case, the ceramic dielectric that constitutes the side margins may not have a continuous composition and / or microstructure with the ceramic dielectric that constitutes the inner and / or outer layer portions. Therefore, a physical or chemical boundary may exist between the side margins and the inner and / or outer layer portions.

[0038] <External electrode> The external electrodes (first external electrode, second external electrode) function as input / output terminals of the multilayer ceramic capacitor. The first external electrode and second external electrode are provided on both end surfaces of the multilayer ceramic capacitor. The first external electrode is connected to the first internal electrode layer, and the second external electrode is connected to the second internal electrode layer. A known configuration can be adopted for the external electrodes. For example, they may include a base electrode layer and a plating layer disposed thereon. Alternatively, the external electrodes may be formed only by a plating layer without providing a base electrode layer.

[0039] <Intragranular void ratio> In the multilayer ceramic capacitor of this embodiment, the ceramic dielectrics constituting the inner layer portion, the first side margin portion, and the second side margin portion each contain dielectric particles having voids (intragranular voids) therein. That is, intragranular voids exist in at least some of the dielectric particles constituting the ceramic dielectric. Here, intragranular voids are voids present inside the dielectric particles. In other words, they are regions present inside the dielectric particles that do not contain solid components such as the main components constituting the dielectric particles or intentionally added minor components. Therefore, they are distinguished from extragranular voids present at interparticle interfaces or triple junctions. Dielectric particles having voids therein are called void-containing particles. Ceramic dielectrics having such void-containing particles are produced from hydrothermally synthesized powder.

[0040] By including void-containing particles in the ceramic dielectric that constitutes the inner layer (hereinafter sometimes referred to as "inner layer ceramic"), it is possible to suppress deterioration of the insulation resistance (IR) of the multilayer ceramic capacitor and improve reliability. Although this should not be interpreted in a limited way, the following points are thought to be the reasons for this.

[0041] When dielectric layers and internal electrode layers are multilayered to increase the capacitance per unit volume, i.e., the volumetric capacitance, the interfacial area between these layers increases. If the smoothness of this interface is impaired, the electric field concentrates when voltage is applied, making it easier for the IR to deteriorate. This makes it difficult to achieve high rated voltages for multilayer ceramic capacitors. On the other hand, hydrothermally synthesized powder, with its nearly spherical shape, smooths the interface between the dielectric layer and the internal electrode before firing and maintains this state after firing. Therefore, it is desirable to use hydrothermally synthesized powder as the dielectric layer material for the inner layer, and in particular, hydrothermally synthesized powder primarily composed of BaTiO3-based compounds, which exhibit a high dielectric constant. Using hydrothermally synthesized powder results in the formation of void-containing particles in the ceramic dielectric.

[0042] Furthermore, by incorporating void-containing particles into the ceramic dielectric (hereinafter sometimes referred to as "side margin ceramic") that constitutes the side margin portions (first side margin portion, second side margin portion), it becomes possible to improve volumetric capacitance and further suppress IR degradation. While this should not be interpreted in a limited manner, the following points are thought to be the reasons for this.

[0043] In order to increase the volumetric capacitance of a multilayer ceramic capacitor, it is effective to reduce the thickness in the width (W) direction of the side margin portion. Then, by adopting a process in which the inner layer part precursor and the side margin part precursor are prepared separately and integrally fired after bonding them, such a multilayer ceramic capacitor can be easily manufactured. At this time, as the raw material of the side margin portion, it is desirable to use a hydrothermal synthesis powder, particularly a hydrothermal synthesis powder mainly composed of the same BaTiO3-based compound as the inner layer portion. Since the hydrothermal synthesis powder has high fluidity, using this powder makes it possible to enhance the adhesiveness between the side margin precursor and the inner layer part precursor, which leads to suppression of IR degradation.

[0044] As described above, it is known that adopting a hydrothermal synthesis powder for the inner layer part and the side margin part leads to suppression of IR degradation. In addition to this, the inventors have intensively studied from the viewpoint of suppressing IR degradation, and have found a relationship in which IR degradation can be more suitably suppressed by appropriately controlling the intragranular pore ratio remaining in the inner layer part and the side margin part after firing. Specifically, in the multilayer ceramic capacitor of the present embodiment, the intragranular pore ratio (N[inner layer central part]) in the central part of the inner layer part (inner layer central part) and the intragranular pore ratio (N[side margin part]) in the side margin part (first side margin part and second side margin part) satisfy the relationship of the formula: N[inner layer central part] < N[side margin part]. That is, it is to control the porcelain structure so that the intragranular pore ratio of the ceramic dielectric in the side margin part is larger than the intragranular pore ratio of the ceramic dielectric in the inner layer central part. The inner layer central part is a region occupying the vicinity of the center of the inner layer part and is determined by the method described later. The intragranular pore ratio is the number of intragranular pores per unit area in a cross section (WT surface) crossing the central part in the length direction of the multilayer ceramic capacitor and is measured by the method described later.

[0045] The inventors have experimentally found that by controlling the intragranular pore ratio in the inner layer central part and the side margin part so as to satisfy the above-described relationship, it becomes possible to more effectively suppress the degradation of insulation resistance (IR).

[0046] In the multilayer ceramic capacitor of this embodiment, the D50 diameter of the dielectric particles at the width direction ends (inner layer W ends) of the inner layer portion (D50[inner layer W end]) and the D50 diameter of the dielectric particles at the center portion (inner layer center portion) of the inner layer portion (D50[inner layer center portion]) satisfy the relationship of the formula: 1.00≦D50[inner layer W end] / D50[inner layer center portion]≦1.40. That is, the difference between the D50 diameter of the dielectric particles at the inner layer center portion and the D50 diameter of the dielectric particles at the inner layer W ends is relatively small. This makes it possible to more effectively suppress IR degradation. Although this should not be interpreted in a limited manner, the following points are considered to be the reasons for this. The inner layer center portion is a region occupying the vicinity of the center of the inner layer portion, and the inner layer W ends are regions occupying the width (W) direction ends of the inner layer portion. These are determined by the method described below.

[0047] As described above, grain growth is more likely at the W end portions of the inner layer than at the center portion. Furthermore, as grain growth progresses at the W end portions, the number of dielectric particles in the thickness direction of the dielectric layer decreases, inducing IR degradation. In contrast, controlling the ratio of the D50 diameter at the W end portions to the D50 diameter at the center portion of the inner layer so as to satisfy the above-described relationship suppresses grain growth at the W end portions of the inner layer. As a result, the number of dielectric particles in the thickness direction of the dielectric layer can be secured, which leads to suppression of IR degradation. From the viewpoint of suppressing IR degradation, it is preferable that D50[W end portions of the inner layer] and D50[center portion of the inner layer] satisfy the relationship of the formula: 1.00≦D50[W end portions of the inner layer] / D50[center portion of the inner layer]≦1.17, and more preferably that D50[W end portions of the inner layer] / D50[center portion of the inner layer]≦1.06.

[0048] As long as D50 [center of inner layer] and D50 [end of inner layer W] satisfy the above-mentioned relationship, their respective values ​​are not limited. However, by appropriately increasing the particle size, the crystallinity of the particles and the associated improvement in various properties can be fully demonstrated. On the other hand, by appropriately reducing the particle size, the dielectric layer can be made even thinner. D50 [center of inner layer] is preferably 150 nm or more and 360 nm or less. Furthermore, D50 [end of inner layer W] is preferably 150 nm or more and 500 nm or less. Note that the above-mentioned D50 diameters (D50 [center of inner layer], D50 [end of inner layer W]) refer to the D50 diameters of all dielectric particles, including not only particles with voids but also particles without voids.

[0049] The inner layer center is defined as follows: In the element part of the multilayer ceramic capacitor, after removing the external electrodes, the dielectric layer located at approximately half the thickness T is specified. In this specified dielectric layer, the area located at approximately half the length L and width W of the element part is defined as the inner layer center (Figure 4).

[0050] The number of intragranular voids in the central portion of the inner layer is determined by observation with a transmission electron microscope (TEM). Specifically, a field of view is selected from within a region defined by 10 μm (W direction) × 10 μm (L direction) × dielectric layer thickness (T direction) in the central portion of the inner layer, and TEM observation is performed. The D50 diameter of the dielectric particles in the central portion of the inner layer (D50 [central portion of inner layer]) is determined by observation with a scanning electron microscope (SEM). Specifically, a region defined by 3 μm (W direction) × dielectric layer thickness (T direction) in the central portion of the inner layer is determined on the WT surface, and the particle diameters of the dielectric particles contained in this region are measured, and the average value is calculated as D50. SEM observation may be performed, for example, at a magnification of 25,000 times. Furthermore, when measuring the particle diameters, not only the particle diameters with voids but also the particle diameters of particles without voids are measured.

[0051] The inner layer W end is defined as follows: Focusing on the dielectric layer specified when defining the inner layer center, the boundary between the internal electrode layer and the side margin for this dielectric layer is defined. Specifically, the W-direction ends of a pair of internal electrode layers facing each other across the aforementioned dielectric layer are defined as the boundary. In this case, if the ends of the pair of internal electrode layers are misaligned in the W direction, the end closest to the inner layer center is defined as the boundary. Then, starting from this boundary, the portion of the dielectric layer within a distance of 3 μm toward the inner layer center is defined as the inner layer W end (Figure 4).

[0052] The number of intragranular voids at the W inner layer end is determined by TEM observation of the W inner layer end. The D50 diameter (D50 [W inner layer end]) is determined by SEM observation of the W inner layer end. The SEM observation may be performed, for example, at a magnification of 25,000 times. In addition, when measuring particle size, not only the particle size of void-containing particles but also the particle size of particles without voids are measured.

[0053] Preferably, the intragranular void ratio (N[inner layer center]) in the inner layer center is 10 / μm 2 The following explains why polarity IR can be reduced by reducing N [center of inner layer]. Polarity IR is the phenomenon in which the insulation resistance (IR) value changes depending on the direction (polarity) of the applied voltage. In a multilayer ceramic capacitor, the external and internal electrodes are connected. Therefore, reversing the polarity of the voltage applied to the external electrodes reverses the direction of the voltage applied to the dielectric ceramic in the inner layer. In this case, the IR value may change depending on the direction of the voltage. This is called polarity IR. If polarity IR is large enough to be significant, the IR value will change significantly depending on the mounting direction of the multilayer ceramic capacitor. In actual operation, it is desirable to minimize polarity IR, as it can cause variations in IR values.

[0054] The reason why polar IR can be suppressed by reducing N [the central part of the inner layer] is thought to be the following, although this should not be interpreted in a limiting sense.

[0055] As mentioned above, using hydrothermally synthesized powders results in a smooth interface between the dielectric layer and the internal electrode layer, which is advantageous for suppressing IR degradation. However, when using hydrothermally synthesized powders, particles with voids remain in the dielectric layer. While there is no problem if these voids are located equidistant from both of the pair of internal electrodes facing each other across the dielectric layer, if they are located closer to either of them, polarized IR occurs. This occurs because the electric field around the voids changes, which changes the electric field strength distribution when the voltage application direction is changed. Voids tend to remain in dielectric particles that do not undergo grain growth during firing. In the dielectric layer (inner layer), dielectric particles with a small degree of grain growth can be distributed in clumps (Figure 5). With this type of particle size distribution of dielectric particles, the distribution of intragranular voids also becomes uneven, which causes differences in electric field strength when the voltage application direction is changed, resulting in polarized IR.

[0056] In contrast, when the intragranular void ratio (N[center of inner layer]) in the center of the inner layer is small, the voids can be considered to be randomly distributed (Figure 5). Also, because the number of voids themselves is small, the change in the electric field around the voids is negligibly small. As a result, the polar IR is significantly suppressed.

[0057] When the thickness of the dielectric layer is 3.0 μm or less, in order to suppress the polar IR generation rate, N [center of inner layer] is 0 / μm 2 Super 10 pieces / μm 2 Less than 0 particles / μm is preferable. 2 Super 7 pieces / μm 2 Less than 0 particles / μm is more preferable. 2 Super 4 / pcsμm 2 More preferably, N [central part of inner layer] is 1 / μm 2 It may be more than that.

[0058] In addition, as long as the relationship between the N[inner layer central portion] and N[side margin portion] is satisfied, the intragranular void ratio of the side margin portion (N[side margin portion]) is not limited. However, from the viewpoint of further exerting the effect of suppressing IR degradation, N[side margin portion] is set to 5 / μm 2 More than 26 pieces / μm2 Preferably less than 10 particles / μm 2 More than 26 pieces / μm 2 Less than 15 particles / μm is more preferable. 2 More than 26 pieces / μm 2 The following is even more preferred:

[0059] The side margin portion includes a first side margin portion and a second side margin portion. The intragranular void ratio of the first side margin portion and the intragranular void ratio of the second side margin portion may be the same or different. However, it is desirable that both are greater than the intragranular void ratio of the central portion of the inner layer.

[0060] Preferably, the ceramic dielectric (hereinafter sometimes collectively referred to as "outer layer ceramic") constituting the outer layer portions (first outer layer portion, second outer layer portion) contains void-containing particles. This can effectively suppress the occurrence of cracks in the multilayer ceramic capacitor. While this should not be interpreted in a restrictive manner, the following points are considered to be the reasons for this.

[0061] During the firing process when manufacturing multilayer ceramic capacitors, dielectric particles in not only the side margins but also the outer layers are more susceptible to grain growth than those in the inner layers. When grain growth occurs, not only does the D50 diameter of the dielectric particles increase, but the particle size distribution also broadens. In a sintered ceramic body, high mechanical strength is maintained by balancing the stress received from adjacent particles as a whole. In a sintered body with a particle size distribution, the coordination number and diameter of adjacent particles differ for each dielectric particle, which, when viewed microscopically, causes strength variations. Due to this, when multilayer ceramic capacitors are subjected to a bending test on a mounting board, cracks are more likely to occur.

[0062] In contrast, if the dielectric particles in the outer layer are provided with internal voids to suppress grain growth and minimize the grain size distribution, the microscopic mechanical strength is leveled, and as a result, crack generation is effectively suppressed.

[0063] Preferably, the intragranular pore ratio (N[inner layer central part]) in the central part of the inner layer part (inner layer central part) and the intragranular pore ratio (N[outer layer part]) in the first outer layer part and the second outer layer part satisfy the relationship of the formula: N[inner layer central part] < N[outer layer part]. Thereby, the crack generation of the multilayer ceramic capacitor can be suppressed more remarkably. Although it should not be construed as a limitation, the following points are considered as the reasons.

[0064] When the multilayer ceramic capacitor is mounted on a printed circuit board, in the case of a vertical substrate where the outer layer part (W direction) is perpendicular to the substrate surface, when the substrate is bent, tensile stress is applied to the side margin part. On the other hand, in the case of a horizontal substrate where the outer layer part (W direction) is parallel to the substrate surface, when the substrate is bent, tensile stress is applied to the outer layer part. Usually, since the mounting direction is random, tensile stress due to substrate bending is applied to both the outer layer part and the side margin part. When the intragranular pore ratio of the side margin part is larger than the intragranular pore ratio of the inner layer part and the intragranular pore ratio of the outer layer part is larger than the intragranular pore ratio of the inner layer part, even if tensile stress is applied to both the side margin part and the outer layer part, the microscopic mechanical strength is averaged by the presence of intragranular pores with a relatively high ratio, which leads to crack prevention.

[0065] Since the particle size of the dielectric particles with intragranular pores is relatively small, the grain interface area of the side margin part and the outer layer part containing such dielectric particles increases. This means an increase in the strengthened grain interface area, and thus also leads to crack prevention from this perspective. That is, by making the intragranular pore ratio of the side margin part larger than the intragranular pore ratio of the inner layer part and making the intragranular pore ratio of the outer layer part larger than the intragranular pore ratio of the inner layer part, it becomes possible to suppress crack generation more remarkably. Specifically, in the bending test with a bending amount of 2.5 mm, the crack generation rate can be suppressed to 5% or less.

[0066] From the perspective of reducing the crack generation rate in the bending test of the mounting substrate, the intragranular pore ratio (N[outer layer part]) of the outer layer part is preferably 1 piece / μm 2 or more and 25 pieces / μm 2 or less, and more preferably 8 pieces / μm 225 particles / μm or more 2 Less is more preferable, 12 particles / μm 2 25 particles / μm or more 2 Less is even more preferable. The outer layer portion includes a first outer layer portion and a second outer layer portion. The intragranular pore ratio of the first outer layer portion and the intragranular pore ratio of the second outer layer portion may be the same or different. However, when N[inner layer central portion] and N[outer layer portion] satisfy the above-described relationship (N[inner layer central portion] < N[outer layer portion]), it is preferable that both the internal pore ratio of the first outer layer and the intragranular pore ratio of the second outer layer portion satisfy this relationship.

[0067] According to a preferred embodiment, the zirconium concentration (Zr[inner layer portion]) of the ceramic dielectric constituting the inner layer portion and the zirconium concentration (Zr[side margin portion]) of the ceramic dielectric constituting the side margin portion satisfy Zr[side margin portion] < Zr[inner layer portion]. As will be described later, when a grain growth promoting material such as Zr is added to the inner layer green sheet or the side margin green body during the manufacture of the multilayer ceramic capacitor and the amount thereof is controlled, the intragranular pore ratio can be adjusted. Also, in that case, in the finally obtained multilayer ceramic capacitor, the concentration of the grain growth promoting material (such as Zr) in the inner layer portion becomes higher than that in the side margin portion.

[0068] According to another preferred embodiment, the dielectric particles included in the inner layer portion and the side margin portion are composed of a perovskite-type oxide having a composition represented by ABO3. And preferably, the molar ratio (A / B ratio) of the dielectric particles included in the side margin portion is larger than the molar ratio (A / B ratio) of the dielectric particles included in the inner layer portion. As will be described later, when the molar ratio (A / B ratio) of the main component powder included in the inner layer green sheet or the side margin green body is controlled during the manufacture of the multilayer ceramic capacitor, the intragranular pore ratio can be adjusted. Also, in that case, in the finally obtained multilayer ceramic capacitor, the molar ratio of the dielectric particles included in the side margin portion becomes larger than the molar ratio of the dielectric particles included in the inner layer portion.

[0069] The multilayer ceramic capacitor of this embodiment contains dielectric particles with internal voids (pore-containing particles) in the inner layer and side margin portions, and the intragranular void ratio (N [inner layer center], N [side margin]) is controlled to satisfy a predetermined relationship. This has the advantage of suppressing insulation resistance (IR) degradation and providing high reliability. For example, but not limited to, the mean time to failure (MTTF) in a highly accelerated life test (HALT) can be set to 30 hours or more, 50 hours or more, or 70 hours or more. The mean time to failure can be determined by the method described in the Examples below or a method similar thereto.

[0070] Although not limited thereto, the multilayer ceramic capacitor of this embodiment can suppress polar IR by controlling the intragrain void ratio (N[center of inner layer]) in the center of the inner layer within a predetermined range. For example, the polar IR occurrence rate can be set to 3% or less, or 1% or less. The polar IR occurrence rate can be calculated as follows. First, a forward voltage is applied to the multilayer ceramic capacitor to calculate the insulation resistance (IR). Next, a reverse voltage is applied to calculate the insulation resistance (IR) (FIG. 6). The IR (insulation resistance) values ​​measured while changing the direction of voltage application are converted to common logarithmic values ​​and the difference is calculated. The polar IR occurrence rate is calculated as the percentage of samples whose absolute value of the division exceeds 0.3 (the number of digits of the antilogarithm exceeds 0.3). More specifically, the polar IR occurrence rate can be calculated using the method described in the Examples below or a method similar thereto.

[0071] Although not limited thereto, the multilayer ceramic capacitor of this embodiment can effectively suppress cracking by including void-containing particles in the outer layer portion and further controlling the intragranular void ratio (N [center of inner layer], N [outer layer]). For example, it is possible to set the crack occurrence rate to 5% or less, 3% or less, or 1% or less in a deflection test in which the mounting substrate is deflected 2.5 mm. The deflection test is performed using the method described in the Examples below or a method similar thereto.

[0072] <<2. Manufacturing method of multilayer ceramic capacitors>> The manufacturing method of the multilayer ceramic capacitor of the present embodiment is not limited as long as it satisfies the above-mentioned requirements. However, a suitable manufacturing method includes the following steps: a step of synthesizing the main component powder for the ceramic dielectric (synthesis step), a step of mixing the sub-component raw material with the main component powder to obtain a dielectric raw material (mixing step), a step of adding and mixing a binder and a solvent to the dielectric raw material to form a slurry, and forming a green sheet for the inner layer and a green sheet for the outer layer from the obtained slurry (forming step), a step of forming a patterned conductive paste layer on the surface of the green sheet for the inner layer using a conductive paste for the internal electrode (printing step), a step of laminating a plurality of green sheets for the inner layer on which the conductive paste layer is formed, laminating green sheets for the outer layer above and below them, and pressing the whole to produce a laminated block (laminating step), a step of cutting the obtained laminated block into laminated chips (cutting step), a step of attaching a side margin green body to the side surface of the obtained laminated chip to produce a green body part (side margin part forming step), a step of subjecting the obtained green body part to a debinding treatment and a firing treatment to form a body part (firing step), and a step of forming an external electrode on the obtained body part to produce a multilayer ceramic capacitor (external electrode forming step). Further, in the obtained multilayer ceramic capacitor, each of the ceramic dielectrics constituting the inner layer part and the side margin parts (the first side margin part and the second side margin part) contains porous particles, and the relationship of N[inner layer central part]<N[side margin part] is satisfied, and the manufacturing conditions are controlled so as to satisfy the relationship of 1.00≦D50[inner layer W end] / D50[inner layer central part]≦1.40. Details of each step will be described below.

[0073] <Synthesis step> In the synthesis step, the main component powder used for forming the ceramic dielectric is synthesized. The main component powder is a dielectric powder having a perovskite structure (ABO3) such as a BaTiO3-based compound. As the main component powder of the ceramic dielectric, a hydrothermal synthesis powder is used. This makes it possible to produce a multilayer ceramic capacitor containing dielectric particles with pores (porous particles) inside.

[0074] Hydrothermally synthesized powder is synthesized by hydrothermally reacting raw materials containing A-site elements (A-site raw materials) and B-site elements (B-site raw materials) that constitute the perovskite structure under high temperature and pressure. Specifically, the raw materials are placed in a sealed container such as an autoclave with water and heated to cause the hydrothermal reaction. Hydroxides such as barium hydroxide (Ba(OH)2) are used as the A-site raw materials. Oxides such as titanium oxide (TiO2) and metatitanic acid (TiO(OH)2) or their hydrates are used as the B-site raw materials. The heating temperature is not limited, but may be between 150°C and 250°C. The product obtained by the hydrothermal reaction is dried to obtain a dielectric powder. The product may also be heat-treated to enhance the crystallinity of the dielectric powder. The heat treatment may be performed at a temperature of, for example, between 800°C and 1000°C.

[0075] <Mixing process> In the mixing process, the dielectric material is obtained by mixing the main component powder with the auxiliary component (Ni, RE, Mg, Mn, Si, Al, V, etc.) raw materials. The auxiliary component raw materials may be known ceramic raw materials such as oxides, carbonates, hydroxides, nitrates, organic acid salts, alkoxides, and / or chelate compounds. A composition control agent for the main component powder may be added in addition to the auxiliary component raw materials. For example, if the main component powder is barium titanate (BaTiO3) powder, adding a Ba raw material such as barium carbonate (BaCO3) can control the main component composition (A / B ratio) of the ceramic dielectric contained in the multilayer ceramic capacitor. The mixing method is not particularly limited. For example, the main component powder and the auxiliary component raw materials may be wet mixed and pulverized using a ball mill with milling media and pure water. If wet mixing is performed, the mixture may be dried.

[0076] <Forming process> In the molding process, a binder and a solvent are added to and mixed with the dielectric raw material to form a slurry, and the resulting slurry is molded into green sheets for the inner and outer layers. A known organic binder such as a polyvinyl butyral binder may be used as the binder. A known organic solvent such as toluene or ethanol may be used as the solvent. Additives such as a plasticizer may be added as needed. Molding may be performed by a known method such as the lip method. The thickness of the molded sheet is, for example, 4 μm or less.

[0077] <Printing process> In the printing process, a conductive paste is used to form a patterned conductive paste layer on the surface of the inner layer green sheet. The conductive paste layer becomes the internal electrode layer after firing. The conductive metal contained in the conductive paste may be a conductive material such as nickel (Ni), copper (Cu), silver (Ag), palladium (Pd), or an alloy containing these. A ceramic component that acts as a co-material may also be added to the conductive paste. The main component powder of the dielectric layer may be used as the ceramic component. The method for forming the conductive paste layer is not particularly limited. Examples include screen printing and gravure printing.

[0078] <Lamination process> In the lamination process, multiple inner layer green sheets with conductive paste layers formed thereon are laminated, and outer layer green sheets are laminated above and below them. The entire assembly is then pressed together to create a laminated block. The inner layer green sheets undergo a firing process to become the ceramic dielectric (inner layer ceramic) that will form the inner layer portion of the multilayer ceramic capacitor. The outer layer green sheets become the ceramic dielectric (outer layer ceramic) that will form the outer layer portion. The number of green sheets to be laminated can be adjusted to obtain the required capacity.

[0079] <Cutting process> In the cutting step, the obtained laminated block is cut into laminated chips. The cutting may be performed so that chips of a predetermined size are obtained and the conductive paste layers are exposed on the end faces and side faces of the laminated chips.

[0080] <Side margin forming process> In the side margin forming process, a side margin green body is attached to the side of the laminated chip to create a green element. The side margin green body covers the conductive paste layer exposed on the side of the laminated chip. After firing, the side margin green body becomes the side margin of the multilayer ceramic capacitor. The raw material for the side margin green body (side margin raw material powder) can be the main component powder and subcomponent raw material used to create the inner layer green sheets.

[0081] The preparation and attachment of the side margin green body may be performed by known methods. For example, a method may be used in which a green sheet is prepared from a dielectric material that will serve as the raw material for the side margin portion and then this green sheet is adhered to the side surface of the laminated chip. In this case, to ensure the adhesion of the green sheet, an adhesive aid such as an organic solvent may be applied to the side surface of the laminated chip in advance. Alternatively, a method may be used in which a paste is prepared from the dielectric material and then this paste is applied to the side surface of the laminated chip and dried. The side margin green body may be a single layer, or may be a laminate consisting of multiple layers. A side margin green body consisting of a laminate can be obtained by stacking multiple green sheets on the side surface of the laminated chip or by repeatedly applying and drying a paste.

[0082] If necessary, the obtained green element part may be subjected to barrel polishing, which makes it possible to round the corners and / or ridges of the green element part.

[0083] <Firing process> In the firing process, the green element part is subjected to a debindering process and a firing process to form the element part. The firing process co-sinters the conductive paste layer and the inner layer green sheet to form the internal electrode layer and ceramic dielectric that make up the inner layer part. The outer layer green sheet is sintered to form the ceramic dielectric that makes up the outer layer part. The side margin green body is sintered to form the ceramic dielectric that makes up the side margin part.

[0084] The conditions for the binder removal process may be determined depending on the type of organic binder contained in the green sheet and conductive paste layer. The firing process may be carried out at a temperature at which the laminated chip is sufficiently densified. For example, the firing process may be carried out at a temperature of 1200°C to 1400°C, with the temperature maintained for 0 to 10 minutes. The firing process may be carried out in an atmosphere where the main component compounds such as BaTiO3 are not reduced and the oxidation of the conductive material is suppressed. For example, the firing process may be carried out at an oxygen partial pressure of 1.7 x 10 -7 ~5.8×10 -10 The firing can be performed in a N2-H2-H2O gas flow at 100 MPa. Annealing may also be performed after firing.

[0085] <External electrode formation process> In the external electrode formation process, external electrodes are formed on the element body to create a multilayer ceramic capacitor. The external electrodes can be formed using a known method. For example, a conductive paste containing a conductive component such as Cu or Ni is applied and baked to form a base layer on the end surfaces of the element body where the internal electrodes are drawn out. The base layer can also be formed by applying a conductive paste to both end surfaces of the green element body before firing, followed by a firing process. After the base layer is formed, electroplating can be performed to form a plating film of Ni, Sn, or the like on the surface of the base layer. This completes the multilayer ceramic capacitor.

[0086] <Control of intragranular void ratio> In the manufacturing method of this embodiment, the manufacturing conditions are controlled so that the ceramic dielectrics constituting the inner layer portion and the side margin portion (first side margin portion and second side margin portion) of the obtained multilayer ceramic capacitor each contain particles with holes. Specifically, a hydrothermally synthesized powder is used as the main component powder contained in at least the inner layer green sheet and the side margin green body. As the main component powder, only the hydrothermally synthesized powder may be used, or a combination of the hydrothermally synthesized powder and a powder synthesized by a method other than the hydrothermal method may be used. Examples of methods other than the hydrothermal method include, but are not limited to, a solid-phase method, a sol-gel method, an alkoxide method, a solvothermal method, and an oxalate method. Furthermore, the particle size of the main component powder may be adjusted by pulverizing it after synthesis.

[0087] On the one hand, as the main component powder contained in the outer layer green sheet, hydrothermally synthesized powder may be used, or dielectric powder synthesized by a method other than the hydrothermal method may be used. However, it is preferable to use hydrothermally synthesized powder. This makes it possible to provide the ceramic dielectric constituting the outer layer portion with porous particles.

[0088] Also, in the manufacturing method of the present embodiment, in the obtained multilayer ceramic capacitor, the intragranular pore ratio (N[inner layer central portion]) at the inner layer central portion and the intragranular pore ratio (N[side margin portion]) at the side margin portions (the first side margin portion and the second side margin portion) satisfy the relationship of the formula: N[inner layer central portion]<N[side margin portion], and further, the D50 diameter (D50[inner layer W end portion]) of the dielectric particles at the inner layer W end portion and the D50 diameter (D50[inner layer central portion]) of the dielectric particles at the inner layer central portion satisfy the relationship of the formula: 1.00≦D50[inner layer W end portion] / D50[inner layer central portion]≦1.40, and the manufacturing conditions are controlled.

[0089] The method for controlling the intragranular pore ratio and the D50 diameter is not limited. For example, a method of adding a grain growth promoting material or a grain growth inhibiting material to the main component powder and adjusting the amount thereof can be mentioned. Examples of the grain growth promoting material include zirconium (Zr), silicon (Si), vanadium (V), and / or aluminum (Al). Dielectric particles grow in size during the firing process. At that time, as the grain growth progresses, the intragranular pores become smaller and may disappear in some cases. Therefore, by adding a grain growth promoting material to the inner layer green sheet, the outer layer green sheet, or the side margin green body and adjusting the amount thereof, the intragranular pore ratio in each part can be controlled.

[0090] Another method is to adjust the composition of the main component powder. The main component powder is a perovskite oxide with a composition represented by the formula ABO3, such as BaTiO3. In perovskite oxides, the smaller the molar ratio (A / B ratio) of A-site elements (such as Ba) to B-site elements (such as Ti), the more accelerated is the grain growth. Therefore, by adjusting the molar ratio (A / B ratio) of the main component powder contained in the inner layer green sheet, outer layer green sheet, or side margin green body, the intragranular void ratio in each part can be controlled.

[0091] Another method is to adjust the particle size of raw material particles such as the main component powder. The smaller the raw material particles, the more rapidly they grow. Therefore, by adjusting the particle size of the main component powder in the inner layer green sheets, outer layer green sheets, or side margin green body, the intragranular void ratio in each part can be controlled.

[0092] Another method is to add a dielectric powder synthesized by a method other than the hydrothermal method, such as a solid-phase method, to the main component powder. As mentioned above, hydrothermally synthesized powder has intragranular voids, whereas dielectric powder synthesized by a method other than the hydrothermal method does not have intragranular voids. Therefore, by using a combination of hydrothermally synthesized powder and a dielectric powder synthesized by a method other than the hydrothermal method and adjusting the ratio between them, the intragranular void ratio in each part can be controlled.

[0093] There are no particular limitations on the method used as long as the intragranular void ratio and D50 diameter of the inner layer portion, outer layer portion, and side margin portion can be controlled so as to satisfy a predetermined relationship in the final multilayer ceramic capacitor. [Example]

[0094] The present embodiment will be described in more detail with reference to the following examples, but the present invention is not limited to the following examples.

[0095] (1) Fabrication of multilayer ceramic capacitors [Example 1] In Example 1, inner layer green sheets, outer layer green sheets, and side margin green bodies were fabricated using barium titanate (BaTiO) powder synthesized by hydrothermal method as the main component powder, and multilayer ceramic capacitors were fabricated using these. The specific fabrication procedure is shown below.

[0096] <Synthesis of main component powder> Barium titanate (BaTiO3) powder was synthesized by a hydrothermal method. First, titanium oxide (TiO2) powder and barium hydroxide (Ba(OH)2) powder were weighed and then pure water was added to prepare a slurry. The prepared slurry was then placed in a sealed container, and the temperature of the slurry was raised to 200-250°C while stirring. The temperature was then maintained at 200-250°C for 4-24 hours to allow the liquid-phase reaction to proceed. After that, the internal pressure of the sealed container was returned to atmospheric pressure, and the heating of the sealed container was stopped, leaving the slurry. After cooling, the slurry was removed from the sealed container and placed in a dryer to evaporate the water. In this way, hydrothermally synthesized BaTiO3 powder with an average particle size of 130 nm was obtained.

[0097] <Preparation of green sheets for inner layers> In addition to the hydrothermally synthesized BaTiO3 powder, dysprosium oxide (Dy2O3), magnesium carbonate (MgCO3), manganese carbonate (MnCO3), silicon oxide (SiO2), and vanadium oxide (VO5) were prepared as secondary ingredient materials. Additionally, barium carbonate (BaCO3) and zirconium oxide (ZrO2) were prepared. These secondary ingredient materials, BaCO3, and ZrO2, were added to BaTiO3 powder (average particle size 130 nm). The resulting mixture was wet-ground (blended) in water using a ZrO2 ball mill for 24 hours and then dried to prepare the dielectric material for the inner layer. The amount of BaCO3 added was adjusted so that the ceramic dielectric (inner layer ceramic) that constitutes the inner layer of the final multilayer ceramic capacitor had a Ba / Ti ratio of 1.0027. Note that the Ba / Ti ratio is expressed in molar terms. The amount of ZrO2 added was 0.55 mass% relative to the BaTiO3 powder. Next, a polyvinyl butyral binder and ethanol, an organic solvent, were added to the obtained dielectric raw material and wet-mixed in a ball mill for a predetermined time to prepare a slurry, which was then formed into a sheet to prepare an inner layer green sheet.

[0098] <Preparation of outer layer green sheets> In addition to the hydrothermally synthesized BaTiO3 powder, dysprosium oxide (Dy2O3), magnesium carbonate (MgCO3), manganese carbonate (MnCO3), silicon oxide (SiO2), and vanadium oxide (VO5) were prepared as secondary ingredient materials. Additionally, barium carbonate (BaCO3) and zirconium oxide (ZrO2) were prepared. These secondary ingredient materials, BaCO3, and ZrO2, were added to BaTiO3 powder (average particle size 130 nm). The resulting mixture was wet-ground (blended) in water using a ZrO2 ball mill for 24 hours and then dried to prepare the outer layer dielectric material. The amount of BaCO3 added was adjusted so that the Ba / Ti ratio of the ceramic dielectric (outer layer ceramic) that constitutes the outer layer of the final multilayer ceramic capacitor was 1.0027. The amount of ZrO2 added was 0.55 mass% relative to the BaTiO3 powder. Next, a polyvinyl butyral binder and ethanol as an organic solvent were added to the obtained dielectric raw material, and the mixture was wet mixed in a ball mill for a predetermined time to prepare a slurry, which was then formed into a sheet to prepare an outer layer green sheet.

[0099] <Preparation of side margin green body> In addition to the hydrothermally synthesized BaTiO powder, dysprosium oxide (DyO), magnesium carbonate (MgCO), manganese carbonate (MnCO), silicon oxide (SiO), and vanadium oxide (VO) were prepared as secondary ingredient raw materials. Barium carbonate (BaCO) was also prepared. These secondary ingredient raw materials and BaCO were added to BaTiO powder (average particle size 130 nm). The resulting mixture was wet-milled (blended) in water using a ZrO ball mill for 12 hours and then dried to prepare a dielectric raw material for the side margin green body. The amount of BaCO was adjusted so that the ceramic dielectric (side margin ceramic) that would ultimately constitute the side margin portion of the multilayer ceramic capacitor had a Ba / Ti ratio of 1.0040. Next, a polyvinyl butyral binder and an organic solvent, ethanol, were added to the resulting dielectric raw material and wet-mixed using a ball mill for a predetermined time to produce a slurry. This slurry was then formed into a sheet to produce a side margin green body.

[0100] <Preparation of laminate> A Ni-based conductive paste was screen-printed on the surface of the obtained inner layer green sheet to form a pattern of conductive paste layers that would become internal electrode layers. Subsequently, multiple inner layer green sheets with conductive paste layers formed thereon were stacked, and outer layer green sheets without conductive paste layers were placed above and below them, and the whole was pressed together to produce a laminated block. The obtained laminated block was then cut with a dicing saw into laminated chips. The stacking was performed so that the ends where the conductive paste layers were drawn out were staggered. The cutting was also performed so that the conductive paste layers were exposed on the side surfaces and the drawn-out portions of the conductive paste layers were exposed on the end surfaces.

[0101] A side margin green body was attached to both sides of the cut laminated chip where the conductive paste layer was exposed, to prepare a green element portion.

[0102] The obtained green element was heat-treated in an N2 gas flow at a maximum temperature of 270°C, and further heat-treated in an N2-H2O-H2 gas flow at a maximum temperature of 800°C. It was then sintered in an N2-H2O-H2 gas flow. The sintering was carried out at a maximum temperature of 1250-1320°C, with a temperature rise rate of 20-60°C / sec, a hold time of 60 minutes, and an oxygen partial pressure of 3.2 × 10 -9 ~6.4×10 -10 The test was carried out under the conditions of MPa. Then, the alloy was heat-treated in a N2-H2O-H2 gas flow at a maximum temperature of 1050°C for 60 minutes. This resulted in the formation of an element part.

[0103] A copper (Cu)-based conductive paste was applied to the end faces of the fired element, from which the internal electrode layers were drawn. The applied conductive paste was then baked at 900°C to form the base layer of the external electrode. Furthermore, Ni plating and Sn plating were applied to the surface of the base layer in that order using wet plating. In this way, a multilayer ceramic capacitor was produced.

[0104] The fabricated multilayer ceramic capacitor had a length L of 1.0 mm, a width W of 0.5 mm, and a thickness T of 0.5 mm. The thickness of the dielectric layer in the inner layer portion was 0.80 μm, the thickness of the internal electrode layer was 0.47 μm, and the number of dielectric layers was 345.

[0105] [Example 2] In Example 2, when preparing the green sheets for the inner layers, the amount of BaCO3 added was adjusted so that the Ba / Ti ratio of the inner layer ceramic was 1.0015. The amount of ZrO2 added was changed from 0.55% by mass to 0.3% by mass. Furthermore, the amount of ZrO2 added when preparing the green sheets for the outer layers was changed from 0.55% by mass to 0.3% by mass. Otherwise, a multilayer ceramic capacitor was prepared in the same manner as in Example 1.

[0106] [Example 3] In Example 3, when preparing the side margin green body, the amount of BaCO3 added was adjusted so that the Ba / Ti ratio of the side margin ceramic was 1.0027. ZrO2 was also added along with BaCO3, and the amount added (ZrO2 added amount) was 0.3 mass% relative to the BaTiO3 powder. Furthermore, the grinding time was changed from 12 hours to 24 hours. Otherwise, a multilayer ceramic capacitor was prepared in the same manner as in Example 1.

[0107] [Example 4] In Example 4, when the side margin green body was produced, the amount of BaCO3 added was adjusted so that the Ba / Ti ratio of the side margin ceramic was 1.0027. ZrO2 was also added together with BaCO3, and the amount added (ZrO2 added amount) was 0.3 mass% relative to the BaTiO3 powder. Otherwise, a multilayer ceramic capacitor was produced in the same manner as in Example 1.

[0108] [Example 5] In Example 5, the amount of ZrO2 added when preparing the ceramic green sheets for the inner layer was changed from 0.55 mass % to 0.4 mass %. Otherwise, a multilayer ceramic capacitor was prepared in the same manner as in Example 1.

[0109] [Example 6] In Example 6, the amount of ZrO2 added when preparing the ceramic green sheets for the inner layer was changed from 0.55 mass % to 0.3 mass %. Otherwise, a multilayer ceramic capacitor was prepared in the same manner as in Example 1.

[0110] [Example 7] In Example 7, the amount of ZrO2 added when preparing the outer layer ceramic green sheets was changed from 0.55 mass % to 0.3 mass %. Otherwise, a multilayer ceramic capacitor was prepared in the same manner as in Example 1.

[0111] [Example 8] In Example 8, the amount of ZrO2 added when preparing the outer layer ceramic green sheets was changed from 0.55 mass % to 0.4 mass %. Otherwise, a multilayer ceramic capacitor was prepared in the same manner as in Example 1.

[0112] [Example 9] In Example 9, hydrothermally synthesized BaTiO3 powder (average particle size 160 nm) was used instead of hydrothermally synthesized BaTiO3 powder (average particle size 130 nm) when preparing the outer layer green sheets. Except for this, a multilayer ceramic capacitor was prepared in the same manner as in Example 1. The hydrothermally synthesized BaTiO3 powder (average particle size 160 nm) was synthesized using the same procedure as the hydrothermally synthesized BaTiO3 powder (average particle size 130 nm) except that the slurry temperature during hydrothermal heating was increased.

[0113] [Example 10] In Example 10, when preparing the outer layer green sheets, the amount of BaCO3 added was adjusted so that the Ba / Ti ratio of the outer layer ceramic was 1.0040. Furthermore, no ZrO2 was added. Furthermore, the grinding time was changed from 24 hours to 12 hours. Otherwise, a multilayer ceramic capacitor was prepared in the same manner as in Example 1.

[0114] [Example 11] In Example 11, when preparing the outer layer green sheets, the amount of BaCO3 added was adjusted so that the Ba / Ti ratio of the outer layer ceramic was 1.0040, and no ZrO2 was added. Furthermore, the grinding time was changed from 24 hours to 12 hours.

[0115] Furthermore, when preparing the side margin green body, hydrothermally synthesized BaTiO powder (average particle size 130 nm) was replaced with hydrothermally synthesized BaTiO powder (average particle size 100 nm). Furthermore, the amount of BaCO added was adjusted so that the Ba / Ti ratio of the side margin ceramic was 1.0045. Otherwise, multilayer ceramic capacitors were prepared in the same manner as in Example 1. The hydrothermally synthesized BaTiO powder (average particle size 100 nm) was synthesized using the same procedure as the hydrothermally synthesized BaTiO powder (average particle size 130 nm), except that the slurry temperature during hydrothermal heating was lowered.

[0116] [Example 12] In Example 12, when preparing the outer layer green sheets, hydrothermally synthesized BaTiO powder (average particle size 100 nm) was used instead of hydrothermally synthesized BaTiO powder (average particle size 130 nm). The amount of BaCO added was adjusted so that the Ba / Ti ratio of the outer layer ceramic was 1.0045, and no ZrO was added. Furthermore, the grinding time was changed from 24 hours to 12 hours. A multilayer ceramic capacitor was otherwise prepared in the same manner as in Example 1.

[0117] [Example 13] In Example 13, the amount of ZrO2 added when preparing the ceramic green sheets for the inner layer was changed from 0.55 mass % to 0.2 mass %. Otherwise, a multilayer ceramic capacitor was prepared in the same manner as in Example 1.

[0118] [Comparative Example 1] In Comparative Example 1, when preparing the side margin green body, hydrothermally synthesized BaTiO3 powder (average particle size 150 nm) was used instead of hydrothermally synthesized BaTiO3 powder (average particle size 130 nm). Also, the addition amount of BaCO3 was adjusted so that the Ba / Ti ratio of the side margin ceramic became 1.0027. Furthermore, ZrO2 was added together with BaCO3, and the addition amount (ZrO2 addition amount) was set to 0.55 mass% with respect to the BaTiO3 powder. In addition, the grinding time was changed from 12 hours to 24 hours. A multilayer ceramic capacitor was produced in the same manner as in Example 1 except for this. The hydrothermally synthesized BaTiO3 powder (average particle size 150 nm) was synthesized in the same procedure as the hydrothermally synthesized BaTiO3 powder (average particle size 130 nm) except that the slurry temperature during hydrothermal treatment was increased.

[0119] The manufacturing conditions of the multilayer ceramic capacitors of Examples 1 to 13 and Comparative Example 1 are summarized in Table 1 below.

[0120]

Table 1

[0121] (2) Evaluation Regarding the multilayer ceramic capacitors produced in Examples 1 to 13 and Comparative Example 1, evaluations of various characteristics were performed as follows.

[0122] <TEM Observation> Using an electron microscope (TEM), the intragranular porosity of the central part of the inner layer, the W end part of the inner layer, the side margin part, and the outer layer of the multilayer ceramic capacitor was examined as follows. First, the sample was polished until the dimension in the length L direction of the multilayer ceramic capacitor became about 1 / 2 to expose the WT surface. Next, a dielectric layer located at about 1 / 2 of the thickness T dimension in the body part after polishing was specified, and a region located at about 1 / 2 of the width W dimension was defined as the central part of the inner layer (Fig. 4). Also, for the specified dielectric layer, the boundary between the internal electrode layer and the side margin part was determined, and starting from this boundary, the dielectric layer portion included in the distance up to 3 μm toward the central part of the inner layer was defined as the W end part of the inner layer (Fig. 4). At this time, when the ends of each of the pair of internal electrode layers were shifted in the W direction, the end closer to the central part of the inner layer was used as the boundary (Fig. 4). Samples for the central part of the inner layer and the W end part of the inner layer were separately cut out so as to include each of the regions specified as described above, and each was sliced to 100 nm or less to obtain TEM observation samples for examining the intragranular porosity of the central part of the inner layer and the W end part of the inner layer. For the side margin part, a sample was cut out from the body part after polishing at a position that was about 1 / 2 of the thickness T dimension and about 1 / 2 of the side margin width, and sliced to 100 nm or less to obtain a TEM sample for examining the intragranular porosity. For the outer layer part, a sample was cut out from the body part after polishing at a position that was about 1 / 2 of the width W dimension and about 1 / 2 of the outer layer thickness, and sliced to 100 nm or less to obtain a TEM sample for examining the intragranular porosity.

[0123] Then, TEM observations were performed on each of the central part of the inner layer, the W end part of the inner layer, the outer layer part, and the side margin part. From within the prepared TEM observation sample, the number of pores present in the dielectric particles was counted, and the obtained number was divided by the area of the ceramic part (10 μm 2 or more as a guide) to calculate the number per unit area (1 μm 2 ). The same operation was performed at three locations (n = 3) for each of the central part of the inner layer, the W end part of the inner layer, the side margin part, and the outer layer part, and the average value of the number of intragranular pores per unit area was determined as the intragranular pore ratio.

[0124] <SEM Observation> The WT surface of the multilayer ceramic capacitor was observed using a scanning electron microscope (SEM) to examine the thickness of the dielectric layer. Specifically, the multilayer ceramic capacitor was polished to the center in the L direction to expose the cross section (WT surface). Next, on the exposed cross section, the thickness of the dielectric layer of the inner layer located near the center in the thickness direction was measured along a total of five lines: the center line in the W direction and two lines drawn equally spaced on both sides of this center line in the W direction, and the average value was taken as the thickness of the dielectric layer.

[0125] SEM images of dielectric particles in the dielectric layer at the WT cross section near the center in the L direction were also taken under conditions of 25,000x magnification, 15 kV acceleration voltage, and a field of view of 4 μm × 5 μm. Images were taken to include the dielectric layer portion in the center of the inner layer near the center in the W and T directions, as well as the inner layer W edge of the same dielectric layer. Next, image processing software was used to identify the edges (equivalent to grain boundaries) of all dielectric particles contained within an area defined by a length of 3 μm in the W direction and the dielectric layer thickness. The cross-sectional area of ​​each identified particle was calculated, and a virtual circle equal to this area was created. The diameter of this virtual circle (equivalent circle diameter) was defined as the particle diameter. The equivalent circle diameters of all dielectric particles contained within the imaged area were measured, excluding dielectric particles with portions extending outside the designated area. The D50 diameter at the center of the inner layer (D50 [inner layer center]) and the D50 diameter at the inner layer W edge (D50 [inner layer W edge]) were then calculated. The D50 diameter is the cumulative 50% diameter based on the cross-sectional area of ​​the dielectric particle. That is, the cross-sectional areas of all measured dielectric particles are added together to determine the total cross-sectional area, and the cross-sectional area is normalized so that this is 100%. Next, the cross-sectional areas of particles are added together in order from the smallest to the largest cross-sectional area to determine the cumulative cross-sectional area, and the circle-equivalent diameter of the particle when the cumulative cross-sectional area reaches 50% of the total cross-sectional area is determined as the D50 diameter.

[0126] <halt> A highly accelerated life test (HALT) was conducted using multilayer ceramic capacitor samples to determine the mean time to failure (MTTF). In the test, a load of 150°C temperature and 50V voltage was applied to the sample. The time to failure was defined as the time when the insulation resistance (IR) fell to 200kΩ or less. The time to failure was measured for 72 samples fabricated under the same conditions.

[0127] The obtained data was then plotted on Weibull probability paper to obtain a Weibull distribution. In the obtained Weibull distribution, the relationship between failure time and cumulative failure rate was linearly regressed, and the slope was determined as the shape parameter m. The failure time at which the cumulative failure rate reached 63.2% was then read, and the mean time to failure (MTTF) was determined using this failure time and the shape parameter m, which corresponds to the slope of the regression line.

[0128] <Polarity IR> A voltage of 25 V was applied to 100 samples at room temperature for 60 seconds, and the current flowing through the sample was measured at that point. The forward IR was calculated using Ohm's law. The voltage application method was then reversed, and a voltage of 25 V was applied to the sample at room temperature for 60 seconds. The current flowing through the sample was measured at that point. The reverse IR was calculated using Ohm's law. The common logarithms of the forward IR and reverse IR were calculated, and the absolute value of the difference between the two (IR difference) was calculated. The number of samples with an absolute IR difference greater than 0.3 was counted, and the percentage of the measured samples was calculated as the polar IR occurrence rate (%).

[0129] <Deflection test> The multilayer ceramic capacitor was solder-mounted (vertical mounting) to a glass epoxy substrate (FR-4, 1.6 mm thick) with the outer layers perpendicular to the substrate surface (Figure 7). A load was applied from above to the center of the ceramic body of the multilayer ceramic capacitor at a rate of 1.0 mm / sec. This load was maintained for 5±1 seconds, starting from the points where the deflection reached 2.0 mm and 2.5 mm. The LW surface of the held multilayer ceramic capacitor was then polished in the T direction, perpendicular to this surface, until it was half the T direction dimension. The polished surface was observed to check for the presence of cracks, and the results were recorded. Ten samples were used for this vertically mounted deflection test.

[0130] Next, another multilayer ceramic capacitor was prepared and soldered (horizontally mounted) so that the outer layers were parallel to the surface of the glass epoxy substrate (Figure 7). A load was applied from above to the center of the ceramic body of the multilayer ceramic capacitor at a rate of 1.0 mm / sec. This load was maintained for 5±1 seconds, starting from the points at which the capacitor reached a deflection of 2.0 mm and 2.5 mm. The LT surface of the held multilayer ceramic capacitor was then polished in the W direction, perpendicular to this surface, until it was half the W dimension. The polished surface was observed to check for the presence of cracks, and the results were recorded. Ten samples were used for this horizontally mounted deflection test.

[0131] The crack occurrence rate was calculated from the results of the vertical mounting test and the horizontal mounting test according to the following formula (1): where n [vertical] represents the number of samples in which cracks occurred in the vertical mounting test, and n [horizontal] represents the number of samples in which cracks occurred in the horizontal mounting test. Also, N [total] is the total number of samples (20) used in the tests (vertical mounting test, horizontal mounting test).

[0132]

number

[0133] (3) Evaluation results The evaluation results obtained for Examples 1 to 13 and Comparative Example 1 are summarized in Table 2.

[0134] In Examples 1 to 13, the intragranular void ratio in the side margin portion (N[side margin portion]) was larger than the intragranular void ratio in the inner layer central portion (N[inner layer central portion]). Furthermore, the ratio of the average particle diameter of the dielectric particles in the inner layer central portion to the D50 diameter of the dielectric particles at the inner layer W end portion (D50[inner layer W end portion] / D50[inner layer central portion]) satisfied a relationship of 1.00 or more and 1.40 or less. Therefore, the mean time to failure (MTTF) was relatively long, at 30 hours or more.

[0135] In addition to the above-mentioned effects, Examples 1 to 12 also had suppressed polar IR. The intragranular void ratio in the center of the inner layer is 10 / μm 2 Therefore, the polar IR incidence rate was low at 3% or less.

[0136] In addition to the above-mentioned effects, Examples 7, 8, and 10 to 12 also suppressed cracking. Specifically, the intragranular void ratio (N[outer layer]) in the outer layer portion was greater than the intragranular void ratio (N[outer layer]) in the central portion of the inner layer. Therefore, the cracking rate in a deflection test with a deflection of 2.5 mm was low, at 5% or less.

[0137] In contrast, in Comparative Example 1, the intragranular void ratio in the side margin portion (N[side margin portion]) was smaller than the intragranular void ratio in the central portion of the inner layer (N[central portion of the inner layer]), resulting in a relatively short MTTF of 27 hours.

[0138] [Table 2]

[0139] From the above results, it can be seen that this embodiment provides a highly reliable multilayer ceramic capacitor in which degradation of insulation resistance is suppressed. [Explanation of symbols]

[0140] 2. Dielectric layer 4 Internal electrode layer 6 Body 8a 1st external electrode 8b 2nd external electrode 10a First outer principal surface 10b 2nd outer principal surface 12a 1st outer surface 12b Second outer surface 14a First outer end surface 14b Second outer end surface 16 Inner layer 18a 1st outer layer 18b 2nd outer layer 20a First side margin 20b Second side margin 22 Internal area 100 Multilayer ceramic capacitors< / halt>

Claims

1. an inner layer portion in which first internal electrode layers and second internal electrode layers are alternately stacked with dielectric layers formed of ceramic dielectrics interposed therebetween, the inner layer portion having a first main surface which is a surface in the stacking direction, a second main surface which is a surface opposite to the first main surface, a first side surface which is a surface in the width direction perpendicular to the first main surface and the second main surface and from which the first internal electrode layers and the second internal electrode layers are drawn out, a second side surface which is a surface opposite to the first side surface and from which the first internal electrode layers and the second internal electrode layers are drawn out, a first end surface which is a surface in the length direction perpendicular to the first main surface, the second main surface, the first side surface, and the second side surface and from which the first internal electrode layers are drawn out, and a second end surface which is a surface opposite to the first end surface and from which the second internal electrode layers are drawn out; a first outer layer portion formed of a ceramic dielectric and covering the first main surface in the stacking direction; a second outer layer portion formed of a ceramic dielectric and covering the second main surface in the stacking direction; a first side margin portion formed of a ceramic dielectric and covering the inner layer portion, the first outer layer portion, and the second outer layer portion from one side in the width direction; a second side margin portion formed of a ceramic dielectric and covering the inner layer portion, the first outer layer portion, and the second outer layer portion from the other side in the width direction; and a pair of external electrodes provided on the first end surface and the second end surface and connected to the first internal electrode layer and the second internal electrode layer, respectively; the dielectric particles constituting each of the ceramic dielectrics constituting the inner layer portion, the first side margin portion, and the second side margin portion include dielectric particles having voids therein, an intragranular void ratio (N[inner layer central portion]) in a central portion (inner layer central portion) of the inner layer portion and an intragranular void ratio (N[side margin portion]) in the first side margin portion and the second side margin portion satisfy the relationship of the formula: N[inner layer central portion]<N[side margin portion]; A multilayer ceramic capacitor, wherein the D50 diameter of the dielectric particles at the width direction ends (inner layer W ends) of the inner layer portion (D50 [inner layer W ends]) and the D50 diameter of the dielectric particles at the center (inner layer center portion) of the inner layer portion (D50 [inner layer center portion]) satisfy the relationship of the formula: 1.00≦D50 [inner layer W ends] / D50 [inner layer center portion]≦1.

40.

2. The intragranular void ratio (N [inner layer center]) in the inner layer center portion is 10 / μm ２ 2. The multilayer ceramic capacitor according to claim 1, wherein:

3. the ceramic dielectric constituting the first outer layer portion and the second outer layer portion includes dielectric particles having voids therein, 3. The multilayer ceramic capacitor according to claim 1, wherein an intragranular void ratio (N[inner layer central portion]) in a central portion (inner layer central portion) of the inner layer portion and an intragranular void ratio (N[outer layer portion]) in the first outer layer portion and the second outer layer portion satisfy the relationship of the formula: N[inner layer central portion]<N[outer layer portion].

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