Memory system, memory controller, and control method

Abstract

To execute error correction (decoding) with higher accuracy.SOLUTION: The memory system includes a nonvolatile memory that stores an error correction code, and a memory controller. The memory controller reads read information from the nonvolatile memory using a first read voltage, executes a decoding process using first input information that is one of the read information and likelihood information obtained by converting the read information with first conversion information, further executes, when the decoding process fails, the decoding process using second input information obtained by correcting the first input information so as to be a value when read with a second read voltage different from the first read voltage, and estimates a third read voltage based on reliability information indicating reliability of the decoding process.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The following embodiments relate to a memory system, a memory controller, and a control method. [Background technology]

[0002] In general, in a memory system, data is stored in an error correction coded format to protect the data stored therein, and therefore, when data stored in the memory system is read, the error correction coded data is decoded. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2023-040796 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of one embodiment of the present invention is to provide a memory system, a memory controller, and a control method that are capable of performing error correction (decoding) with higher accuracy. [Means for solving the problem]

[0005] According to an embodiment, the memory system includes a nonvolatile memory that stores an error correction code and a memory controller. The memory controller reads read information from the nonvolatile memory using a first read voltage, performs a decoding process using first input information that is either the read information or likelihood information obtained by converting the read information using the first conversion information, and if the decoding process fails, further performs a decoding process using second input information that corrects the first input information so that the first input information has a value that would be obtained if read using a second read voltage that is different from the first read voltage, and estimates a third read voltage based on reliability information that indicates the reliability of the decoding process. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram of a memory system according to a first embodiment. [Figure 2] FIG. 1 is a block diagram showing an example of the schematic configuration of a decoder. [Figure 3] FIG. 10 is a diagram illustrating an example of a sign shift function. [Figure 4] FIG. 10 is a diagram illustrating an example of a sign shift function. [Figure 5] FIG. 10 is a diagram for explaining an example of an estimation process of an optimal read voltage. [Figure 6] 10 is a flowchart of a decoding process performed by the memory system according to the first embodiment. [Figure 7] FIG. 10 is a diagram for explaining an outline of a decoding process according to the first modification. [Figure 8] FIG. 10 is a diagram showing an example of iterative processing of a sine shift function in Modification 1. [Figure 9] FIG. 10 is a diagram showing an example of iterative processing of a sign shift function in Modification 2. [Figure 10] FIG. 10 is a diagram for explaining a comparative example in which decoding fails. [Figure 11] FIG. 10 is a diagram for explaining a processing example according to the second embodiment. [Figure 12] 10 is a flowchart of a decoding process performed by the memory system according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A memory system according to an embodiment will be described in detail below with reference to the accompanying drawings. However, the present invention is not limited to the following embodiments.

[0008] (First embodiment) Fig. 1 is a block diagram showing a schematic configuration example of a memory system according to the first embodiment. As shown in Fig. 1, the memory system 1 includes a memory controller 10 and a nonvolatile memory 20. The memory system 1 can be connected to a host 30, and Fig. 1 shows the memory system 1 connected to the host 30. The host 30 may be, for example, an electronic device such as a personal computer or a mobile terminal.

[0009] The nonvolatile memory 20 is a nonvolatile memory that stores data nonvolatilely, such as a NAND memory. In the following description, a case where a NAND memory is used as the nonvolatile memory 20 will be exemplified, but it is also possible to use storage devices other than a NAND memory, such as a three-dimensional structure flash memory, a ReRAM (Resistance Random Access Memory), or an FeRAM (Ferroelectric Random Access Memory), as the nonvolatile memory 20. Furthermore, it is not essential that the nonvolatile memory 20 be a semiconductor memory, and this embodiment can also be applied to various storage media other than semiconductor memories.

[0010] The memory system 1 may be a memory card or the like in which the memory controller 10 and the nonvolatile memory 20 are configured as one package, or may be an SSD (Solid State Drive) or the like.

[0011] The memory controller 10 controls writing to the nonvolatile memory 20 in accordance with a write request from the host 30. The memory controller 10 also controls reading from the nonvolatile memory 20 in accordance with a read request from the host 30. The memory controller 10 includes a host I / F (host interface) 15, a memory I / F (memory interface) 13, a control unit 11, an encoding / decoding unit (codec) 14, and a data buffer 12. The host I / F 15, the memory I / F 13, the control unit 11, the encoding / decoding unit 14, and the data buffer 12 are interconnected by an internal bus 16.

[0012] The host I / F 15 is a circuit that performs processing in accordance with the interface standard with the host 30 and outputs commands received from the host 30, user data to be written, etc. to the internal bus 16. The host I / F 15 also transmits user data that has been read and restored from the nonvolatile memory 20, responses from the control unit 11, etc. to the host 30.

[0013] The memory I / F 13 is a circuit that performs a write process to the nonvolatile memory 20 based on an instruction from the control unit 11. The memory I / F 13 also performs a read process from the nonvolatile memory 20 based on an instruction from the control unit 11.

[0014] The control unit 11 performs overall control of each component of the memory system 1. The control unit 11 may be realized by a processor such as a CPU (Central Processing Unit) executing firmware, or may be realized by a hardware circuit. When the control unit 11 receives an instruction from the host 30 via the host I / F 15, it performs control in accordance with the instruction. For example, the control unit 11 instructs the memory I / F 13 to write user data and parity to the nonvolatile memory 20 in accordance with the instruction from the host 30. Furthermore, the control unit 11 instructs the memory I / F 13 to read user data and parity from the nonvolatile memory 20 in accordance with the instruction from the host 30.

[0015] Furthermore, when the control unit 11 receives a write request for user data from the host 30, it accumulates the user data in the data buffer 12 and determines a storage area (memory area) for the user data in the nonvolatile memory 20. That is, the control unit 11 manages the write destination of the user data. The correspondence between the logical address of the user data received from the host 30 and the physical address indicating the storage area on the nonvolatile memory 20 where the user data is stored is stored as an address conversion table.

[0016] Furthermore, when the control unit 11 receives a read request from the host 30, it converts the logical address specified by the read request into a physical address using the address conversion table described above, and instructs the memory I / F 13 to read from the physical address.

[0017] In NAND memory, data is generally written and read in units of data called pages, and erased in units of data called blocks. In this embodiment, a plurality of memory cells connected to the same word line are called a memory cell group. If the memory cells are single-level cells (SLC), one memory cell group corresponds to one page. If the memory cells are multi-level cells (MLC), one memory cell group corresponds to multiple pages. Each memory cell is connected to both a word line and a bit line. Therefore, each memory cell can be identified by an address that identifies the word line and an address that identifies the bit line.

[0018] In response to a read instruction from the memory controller 10, the NAND memory applies a read voltage to the word lines, thereby reading data from a plurality of memory cells and transmitting the read data to the memory controller 10.

[0019] The memory cells are, for example, field-effect transistors. Each memory cell includes a semiconductor layer, a gate insulating film, and a gate electrode. The gate insulating film includes a charge storage layer (insulating film or conductive film). The amount of charge in the charge storage layer falls into one of a number of distributions (threshold distributions). When reading data from a number of memory cells, the voltage to be applied to the word line varies depending on the amount of charge in the charge storage layer.

[0020] For simplicity, we will use an example of a 1-bit / cell where one memory cell stores one bit. In the case of a 1-bit / cell, one of two threshold distributions corresponds to "0" and the other corresponds to "1." When a voltage is applied to a word line, a voltage value corresponding to the amount of charge in the memory cell is used as a boundary, and current may or may not flow when the voltage is applied. This boundary voltage is determined by the amount of charge in the memory cell. This voltage determined by the amount of charge in the memory cell is called the threshold voltage or reference read voltage. By applying a reference read voltage to the word line, NAND memory can determine whether the data stored in this memory cell is 1.

[0021] Hereinafter, reading data from a memory cell as a hard decision value of 1 or 0 is referred to as a hard bit read. In a hard bit read by the memory controller 10, a reference read voltage is applied as a read voltage to a word line connected to the memory cell, and it is determined whether the data stored in the memory cell is 1 or 0, and the determination result is output as read data to the memory controller 10. In addition, in a hard bit read, the read voltage may be changed from the reference read voltage, and in this case, the difference between the read voltage and the reference read voltage is specified by a read instruction from the memory controller 10.

[0022] The data buffer 12 temporarily stores user data received by the memory controller 10 from the host 30 before storing the data in the nonvolatile memory 20. The data buffer 12 also temporarily stores user data read from the nonvolatile memory 20 before transmitting the data to the host 30. The data buffer 12 may be implemented using general-purpose memory such as an SRAM (Static Random Access Memory) or a DRAM (Dynamic Random Access Memory).

[0023] User data transmitted from the host 30 is transferred to the internal bus 16 and temporarily stored in the data buffer 12. The encoding / decoding unit 14 encodes the user data to generate code words. The encoding / decoding unit 14 also decodes received words read from the non-volatile memory 20 to restore the user data. Therefore, the encoding / decoding unit 14 includes an encoder 17 and a decoder 18. The encoding / decoding unit 14 may be realized by a processor such as a CPU executing firmware, or may be realized by a hardware circuit. Note that the data encoded by the encoding / decoding unit 14 may include control data used inside the memory controller 10 in addition to the user data.

[0024] Next, the write process of this embodiment will be described. When writing user data to the nonvolatile memory 20, the control unit 11 instructs the encoder 17 to encode the user data. At that time, the control unit 11 determines a storage location (storage address) of the codeword in the nonvolatile memory 20, and also instructs the memory I / F 13 about the determined storage location.

[0025] The encoder 17 generates code words by encoding the user data stored in the data buffer 12 based on instructions from the control unit 11. Examples of encoding methods that can be used include BCH (Bose-Chandhuri-Hocquenghem) codes, RS (Reed-Solomon) codes, and concatenated codes with at least one of BCH and RS codes as component codes. Concatenated codes are codes created by combining multiple codes, and include, for example, product codes.

[0026] An error-correcting code is composed of at least one or more symbols as building blocks. One symbol is composed of, for example, one bit (an element of a binary field) or an element of the alphabet in a finite field other than a binary field. For ease of explanation, the following explanation will use an example of a binary error-correcting code in which one symbol is composed of one bit. In the explanation, there may be places where the terms symbol and bit are used interchangeably, but both mean the same thing.

[0027] In the first embodiment, an example will be described in which one type of error correction code (BCH code, RS code, etc.) is used. The memory I / F 13 controls the storage of code words in a storage location on the nonvolatile memory 20 instructed by the control unit 11.

[0028] Next, a description will be given of the processing performed when reading from the nonvolatile memory 20 in this embodiment. When reading from the nonvolatile memory 20, the control unit 11 specifies an address on the nonvolatile memory 20 and instructs the memory I / F 13 to read. The control unit 11 also instructs the decoder 18 to start decoding. In accordance with the instruction from the control unit 11, the memory I / F 13 reads the received word from the specified address in the nonvolatile memory 20 and inputs the read received word to the decoder 18. The decoder 18 decodes the received word read from the nonvolatile memory 20.

[0029] The decoder 18 decodes the received word read from the nonvolatile memory 20. Fig. 2 is a block diagram showing a schematic configuration example of the decoder 18. The decoder 18 includes a HIHO (hard-input hard-output) decoding unit 181 that receives a hard decision value as input, performs decoding, and outputs the hard decision value as a result, and a SISO (soft-input soft-output) decoding unit 182 that receives a soft decision value (soft decision input value), performs decoding, and outputs a soft decision value (soft decision output value) as a result.

[0030] Generally, SISO decoding has the characteristic that it has higher error correction capability than HIHO decoding, but requires a longer processing time. Therefore, in this embodiment, the HIHO decoding unit 181 is configured to first perform HIHO decoding on received words read out as hard-decision values ​​from the nonvolatile memory 20, and read out received words that could not be decoded by hard-decision decoding as soft-decision values. Then, the SISO decoding unit 182 is configured to perform SISO decoding on the received words read out as soft-decision values. However, this configuration is not limited to this, and various modifications are possible, such as a configuration in which HIHO decoding is omitted and SISO decoding is performed on all received words.

[0031] The SISO decoding unit 182 may include a memory (read information memory) that stores read information (received words) read from the nonvolatile memory 20 by soft decision. Of the read information, data corresponding to hard decision values, which are binary information that determine whether each bit is 0 or 1, may be called hard bit data. Also, data corresponding to a portion of the read information excluding the hard bit data may be called soft bit data. The read information memory may include a hard bit memory (HMEM) that stores hard bit data and a soft bit memory (CMEM) that stores soft bit data.

[0032] The decoding process may require data called channel values. The channel values ​​indicate log-likelihood ratio (LLR) values ​​corresponding to pairs of hard bit data and soft bit data. The channel values ​​may be called channel LLR data. The channel values ​​are determined, for example, by an LLR table that associates pairs of hard bit data and soft bit data with channel values. The channel values ​​are an example of soft-decision input values ​​based on soft-decision read information read from the nonvolatile memory 20.

[0033] For example, in a readout by soft decision (soft bit read), one hard bit data and multiple soft bit data are obtained. The one hard bit data is obtained using the same read voltage (hereinafter referred to as VrH) as the readout voltage used in the readout by hard decision (hard bit read). The multiple soft bit data are obtained using multiple read voltages including a read voltage smaller than VrH and a read voltage larger than VrH. The LLR table is, for example, a table in which a channel value is associated with each pair of one hard bit data and multiple soft bit data. The SISO decoding unit 182 can determine the corresponding channel value from the one hard bit data and multiple soft bit data included in the readout information using such an LLR table.

[0034] In this embodiment, where a symbol is an element of a binary field, the LLR represents probability information regarding whether a bit is 0 or 1. In the following, the LLR is assumed to be positive when the probability that the bit is 0 is high, and negative when the probability that the bit is 1 is high. In addition, in this embodiment, the soft-decision input value and the soft-decision output value are also assumed to be expressed by the LLR.

[0035] The LLR can be expressed by contracting it to binary information of 0 or 1 depending on whether the value is positive or negative. Hereinafter, such binary information may be referred to as the hard decision value of the LLR. Also, below, if the LLR is positive, the hard decision value is set to 0, if the LLR is negative, the hard decision value is set to 1, and if the LLR is 0, the hard decision value is determined according to a predetermined rule (for example, the hard decision value is set to 0).

[0036] The "hard decision value of the channel value" corresponds to information in which the channel value represented by the LLR is expressed as a binary value depending on whether the value is positive or negative, as described above. Similarly, the "hard decision value of the soft decision input value" corresponds to information in which the soft decision input value represented by the LLR is expressed as a binary value depending on whether the value is positive or negative, as described above.

[0037] As described above, when data is read from a memory cell, a read voltage is applied to the word line connected to the memory cell. If the read voltage is not set to an appropriate value, in other words, if the read voltage deviates from the appropriate value, the data may not be read correctly and decoding may fail. Therefore, various countermeasures have been proposed to address the situation where the read voltage is deviated.

[0038] As one of the countermeasures, when the decoding process using the read data (read information) fails, there is a function that corrects the read information so that it has the value that would be obtained if read using the new read voltage, rather than reading the data using a new read voltage, and then performs the decoding process again using the corrected read information. Hereinafter, such a function will be referred to as a sign shift function.

[0039] Fig. 3 is a diagram illustrating an example of the sign shift function. Hereinafter, hard bit data and soft bit data may be referred to as HB data and SB data, respectively. Fig. 3 shows an example in which one HB data and one SB data are obtained by soft bit read.

[0040] The threshold distribution VD0 represents the threshold distribution corresponding to "0", and the threshold distribution VD1 represents the threshold distribution corresponding to "1". The read voltages y1, y2, and y3 represent read voltages whose values ​​are set in increasing order. The read voltage y2 corresponds to the read voltage VrH used in hard bit read, for example.

[0041] Process 301 represents the initial decoding process for read information including HB data and SB data. In process 301, the SISO decoding unit 182 performs the decoding process using the HB data and SB data included in the read information as is. That is, in process 301, the read information considered to be a value read by the read voltage y2 is used as is for the decoding process.

[0042] If the decoding process of process 301 fails, process 302 is executed. Process 302 represents a process of correcting the read information so that it becomes the value read by read voltage y3, and re-executing the decoding process using the corrected read information. In the example of FIG. 3, the SISO decoding unit 182 executes the decoding process using read information including corrected HB data in which the HB data has been corrected. The corrected HB data corresponds to data in which the HB data value of the bit in the (HB data, SB data) pair (0,0) among the bits of the HB data has been corrected to 1. Process 302 shows an example in which the HB data value of bit 311 is corrected to 1.

[0043] If the decoding process of process 302 fails, process 303 is executed. Process 303 represents a process of correcting the read information so that it becomes the value read by read voltage y1, and re-executing the decoding process using the corrected read information. In process 303, the corrected HB data corresponds to data in which the HB data value of the bit where the pair (HB data, SB data) is (1, 0) among the bits of the HB data has been corrected to 0. In process 303, an example is shown in which the HB data value of bit 312 is corrected to 0.

[0044] In this way, the HB data is corrected so that its value switches between 1 and 0, with the switched read voltage as the boundary. The SB data can be interpreted as data representing the reliability (likelihood) of the corresponding HB data. In the example of FIG. 3, the SB data values ​​0 and 1 represent decreasing reliability in that order. Correcting the HB data corresponds to a process of obtaining corrected HB data by inverting the value of the HB data corresponding to the SB data representing low reliability.

[0045] 3 shows an example in which the value of the HB data is corrected in a pair of (HB data, SB data). The value of the SB data may be corrected in addition to the HB data. FIG. 4 is a diagram illustrating an example of the sign shift function in this configuration.

[0046] In the example of Fig. 4, processes 302-2 and 303-2 are changed from processes 302 and 303 in Fig. 3. Also, in the example of Fig. 4, the SISO decoding unit 182 performs decoding processes using read information including corrected HB data obtained by correcting HB data and corrected SB data obtained by correcting SB data. The method of generating the corrected HB data is the same as in Fig. 3.

[0047] In process 302-2, the corrected SB data corresponds to data in which the value of the SB data of the bit where the pair (HB data, SB data) is (1, 0) among the bits of the SB data has been corrected to 1. In process 302-2, an example is shown in which the value of the SB data of bit 411 is corrected to 1.

[0048] In process 302-3, the corrected SB data corresponds to data in which the value of the SB data of the bit where the pair (HB data, SB data) is (0,0) among the bits of the SB data has been corrected to 1. In process 302-3, an example is shown in which the value of the SB data of bit 412 is corrected to 1.

[0049] The modification of the SB data by the SISO decoding unit 182 corresponds to a process of modifying bit data including HB data of the same value as the HB data whose value has been inverted and SB data representing low reliability, to SB data representing high reliability. For example, in process 302-2, bit data corresponding to the pair (1,0) of HB data of value 1, the same as the HB data of bit 311 inverted to 1, and SB data representing value 0 (low reliability), is modified to (1,1). In process 302-3, bit data corresponding to the pair (0,0) of HB data of value 0, the same as the HB data of bit 312 inverted to 0, and SB data representing value 0 (low reliability) is modified to (0,1).

[0050] In this way, in the sign shift function, the read voltage at which the read information is considered to have been read is switched (shifted), and the decoding process for the read information is repeatedly executed. Note that the read information is not corrected in the first decoding process, but in the following, the sign shift function will be considered to include the first decoding process. In the examples of Figures 3 and 4, the decoding process that is repeated up to three times corresponds to the sign shift function. The number of repetitions is not limited to three.

[0051] In a situation where the deviation in the read voltage is large and the number of error bits exceeds the range that can be corrected by the decoder 18, the decoding process may fail even if the sign shift function is used. On the other hand, even if the decoding process using the sign shift function fails, if the number of error bits is relatively small, it is expected that the correction of the error bits (correction process) will progress. Therefore, for example, the reliability (progress) of the decoding process can be evaluated by the number of corrected bits, which indicates the number of bits corrected in the decoding process, and the read voltage used in a decoding process with a higher reliability can be estimated to be a more appropriate read voltage.

[0052] In this embodiment, an optimum read voltage is estimated based on reliability information that indicates the reliability of the decoding process using the sign shift function. The reliability information (reliability) is, for example, the number of corrected bits.

[0053] The decoder 18 (SISO decoding unit 182) first performs a decoding process using input information ID1 (first input information), which is read information read from the nonvolatile memory 20 using a read voltage Vr1 (first read voltage). This decoding process corresponds to the first iteration of the sign shift function (initial decoding process) in Figures 3 and 4.

[0054] If the decoding process fails, the decoder 18 performs further decoding using input information ID2 (second input information) obtained by correcting the input information ID1 so that the value is the same as when read using a read voltage Vr2 (second read voltage) different from the read voltage Vr1. This decoding process corresponds to the second or subsequent iterations of the sign shift function. The decoder 18 repeats this process until the decoding process is successful or the maximum number of iterations of the decoding process is reached.

[0055] The decoder 18 estimates the optimum read voltage (third read voltage) based on reliability information that indicates the reliability of the decoding process that is executed one or more times.

[0056] 5 is a diagram illustrating an example of a process for estimating an optimal read voltage when the number of corrected bits is used as reliability information. Processes 501, 502, and 503 in FIG. 5 correspond to the first, second, and third iterations of the sign shift function, respectively.

[0057] In process 501, the SISO decoding unit 182 outputs decoded word data 521 representing a decoded word obtained by the decoding process. The SISO decoding unit 182 calculates the number of correction bits, for example, based on the Hamming distance between the HB data before decoding (pre-decoding information) and the HB data after decoding (post-decoding information). For example, the HB data 511 corresponds to the pre-decoding information, and the decoded word data 521 corresponds to the post-decoding information.

[0058] The method for calculating the number of corrected bits is not limited to this, and any method may be used. For example, the decoder 18 may have a function for calculating the number of corrected bits by adding 1 each time a bit is corrected during the decoding process. When the same bit is corrected two or more times, the method of simply adding 1 each time a bit is corrected may result in the calculated number of corrected bits being larger than the correct value. Therefore, when a bit at the same position is corrected to return its value to its original value, the decoder may be configured to subtract 1. For example, if the value of the HB data of a certain bit in the read information is 0, and the value is corrected to 1 by correction, and then the value is again corrected to 0 by another correction, the number of corrected bits is subtracted by 1. This improves the accuracy of calculating the number of corrected bits.

[0059] A situation where the number of corrected bits is small, as in process 501, corresponds to a situation where the decoding process does not progress, i.e., the reliability of the decoding process is low. If the decoding process fails, process 502, which corresponds to the next iteration, is executed.

[0060] In process 502, the SISO decoding unit 182 executes a decoding process using, as input information ID2, read information (modified read information) including modified HB data 512 obtained by modifying HB data 511, and outputs decoded word data 522. In process 502, the modified HB data 512 corresponds to pre-decoding information, and the decoded word data 522 corresponds to post-decoding information.

[0061] If the number of corrected bits is small even in process 502 and the decoding process fails, process 503 corresponding to the next iteration is executed.

[0062] In process 503, the SISO decoding unit 182 executes a decoding process using, as input information ID2, read information (modified read information) including modified HB data 513 obtained by modifying HB data 511, and outputs decoded word data 523. In process 503, the modified HB data 513 corresponds to pre-decoding information, and the decoded word data 523 corresponds to post-decoding information.

[0063] If the number of corrected bits in process 503 (third iteration) is the maximum, the decoder 18 estimates the read voltage that was used as the basis for correcting the corrected HB data 513 in process 503 as the optimal read voltage. For example, if process 503 is a process for correcting the read information (HB data) so that it becomes the value read by read voltage y1, similar to process 303 in Figure 3, the decoder 18 estimates that the optimal read voltage is read voltage y1.

[0064] The reliability information is not limited to the number of corrected bits, and may be any other information that indicates the reliability of the decoding process. For example, when a multidimensional error correcting code is used as the error correcting code, a statistical value of the reliability of the decoding process for each component code may be used as the overall reliability of the decoding process.

[0065] A multidimensional error-correcting code is one in which at least one symbol, the building block of the error-correcting code, is multiply protected by multiple smaller component codes, such as BCH codes.

[0066] Each component code for each dimension includes one or more component codes defined for that dimension. Hereinafter, a component code corresponding to each dimension, including one or more component codes, may be referred to as a component code group. For example, in the case of a two-dimensional error correcting code in which each symbol is protected by two component codes that can be grouped into dimension 1 and dimension 2, the component code group for dimension 1 and the component code group for dimension 2 include n1 and n2 component codes, respectively. Applicable error correcting codes are not limited to this, and may be an N-dimensional error correcting code in which at least one symbol constituting the code is protected by N component code groups (N is an integer equal to or greater than 2). When expressed in terms of the number of component codes included in each component code group, an N-dimensional error correcting code is protected by M component codes (M is the sum of n i (1≦i≦N), N is an integer equal to or greater than 2, and n i is the number of component codes in the i-th dimension).

[0067] The decoder 18 outputs, for example, a decoding reliability indicating the accuracy of the most likely decoded word found during the decoding process for each component code. The decoding reliability is expressed, for example, by a probability value between 0 and 1. The expression format of the decoding reliability is not limited to this, and any other format may be used. For example, the decoding reliability may be expressed as a value quantized based on a predetermined quantization bit width.

[0068] The decoder 18 calculates a statistical value of the decoding reliability of each component code that is the target of the decoding process as reliability information of the decoding process. The statistical value is, for example, a sum or an average value. The average value is the sum of the decoding reliability divided by the number of component codes.

[0069] The reliability information may be the number of bits (hereinafter, Max LLR Count) at which the absolute value of the posterior value of likelihood information obtained by decoding (hereinafter, posterior LLR) is equal to or greater than a predetermined threshold Th (first threshold).

[0070] L represents the a posteriori LLR of the jth bit (j is an integer greater than or equal to 1 and less than or equal to the code length). j is expressed by the following formula (1): j Let y denote the j-th bit value of the transmitted word, and y denote the received word.

number

[0071] Max LLR Count is expressed by, for example, the following equation (2): n represents the code length, and I represents an indicator function that takes 1 when the conditional expression in parentheses is true and takes 0 when it is false.

number

[0072] Next, a description will be given of the flow of the decryption process by the memory system 1 of the first embodiment. Fig. 6 is a flowchart showing an example of the decryption process by the memory system 1 of the first embodiment.

[0073] The control unit 11 reads the error correction code from the nonvolatile memory 20 and obtains read information (step S101). The control unit 11 transfers and stores the obtained read information, for example, to a read information memory in the SISO decoding unit 182. The read information includes, for example, HB data and SB data.

[0074] The SISO decoding unit 182 executes initialization processing of various information used for decoding (step S102). For example, the SISO decoding unit 182 initializes an iteration counter, a sign shift value, a maximum number of corrected bits, and an optimal sign shift value to 0. The iteration counter is a counter for counting the number of iterations of the sign shift function. The sign shift value is information for specifying a read voltage used in each iteration of the sign shift function. The correspondence relationship between the sign shift value and the read voltage is determined in advance. The maximum number of corrected bits represents the maximum value among the calculated numbers of corrected bits. The optimal sign shift value represents a sign shift value corresponding to an optimal read voltage.

[0075] In the following, the initial value of the sine shift value is set to 0, and 1 is added for each iteration. For example, when the number of iterations is three as shown in FIG. 3, the sine shift value is 0, 1, or 2, which correspond to values ​​specifying the read voltages y2, y3, and y1, respectively. Note that in this example, since the sine shift value and the iteration counter value match, the iteration counter may also be used as the sine shift value.

[0076] The SISO decoding unit 182 performs decoding processing according to the sign shift function. That is, the SISO decoding unit 182 performs decoding processing using read information including HB data and SB data as input information ID1 (step S103). The first decoding processing corresponds to the first iteration of the sign shift function.

[0077] The SISO decoding unit 182 calculates the number of corrected bits in the decoding process (step S104). The SISO decoding unit 182 determines whether the number of corrected bits is greater than the maximum number of corrected bits (step S105).

[0078] If the number of corrected bits is greater than the maximum number of corrected bits (step S105: Yes), the SISO decoding unit 182 updates the maximum number of corrected bits with the value of the number of corrected bits, and updates the optimal sign shift value with the current sign shift value (step S106).

[0079] After the update process, or if it is determined in step S105 that the number of corrected bits is equal to or less than the maximum number of corrected bits (step S105: No), the SISO decoding unit 182 determines whether the decoding is successful (step S107). Successful decoding may mean, for example, that a decoded word that can be determined to be correct has been found.

[0080] If the decoding is not successful (step S107: No), the SISO decoding unit 182 determines whether the iteration counter has reached a maximum counter value (step S108). The maximum counter value is a value defined as the maximum number of iterations of the sign shift function.

[0081] If the iteration counter has not reached the maximum counter value (step S108: No), the SISO decoding unit 182 adds 1 to the iteration counter and the sign shift value (step S109).

[0082] The SISO decoding unit 182 modifies the HB data according to the sign shift value to generate modified HB data (step S110). In the example of Fig. 3, when the sign shift value is 1, the SISO decoding unit 182 generates modified HB data in which the value of the HB data in bit 311 is modified to 1, as in process 302. Then, the process returns to step S103, and the decoding process is repeated using the read information including the modified HB data and SB data as input information ID2.

[0083] If it is determined in step S107 that the decoding is successful (step S107: Yes), the decoder 18 notifies an external control unit or the like of the success of the decoding and the optimal sign shift value (step S111), and ends the decoding process.

[0084] If it is determined in step S108 that the iteration counter has reached its maximum counter value (step S108: Yes), the decoder 18 notifies an external control unit or the like of the failure of decoding and the optimal sign shift value (step S112), and terminates the decoding process.

[0085] As described above, in this embodiment, the optimum sign shift value is output regardless of whether the decoding is successful or unsuccessful. The output optimum sign shift value can be used to determine the optimum read voltage. Furthermore, the optimum read voltage can be used as the read voltage when subsequently reading data from the nonvolatile memory 20. This increases the possibility of correctly reading data, enabling decoding to be performed with higher accuracy. The estimation result output by the decoder 18 is not limited to the optimum sign shift value (optimum read voltage) and may further include, for example, likelihood information (LLR).

[0086] (Variation 1) Up to now, an example has been described in which there is one piece of SB data. There may be two or more pieces of SB data. Below, a modified example in which there are two pieces of SB data will be described. The two pieces of SB data are referred to as SB1 data and SB2 data. The same procedure can be applied in cases in which there are three or more pieces of SB data.

[0087] 7 is a diagram for explaining an outline of the decoding process of this modified example. In this modified example, the SISO decoding unit 182 executes the decoding process using read information including one piece of HB data and two pieces of SB data, SB1 data and SB2 data, as input information ID1.

[0088] 7, in this modification, there are eight combination patterns of HB data, SB1 data, and SB2 data. The maximum number of repetitions of the sign shift function is seven. The sign shift value can take values ​​of 0 to 6, for example, and the seven sign shift values ​​correspond to any of seven read voltages y1 to y7.

[0089] Process 701 corresponds to the first decoding process of the sign shift function, in which the read information, which is considered to be the value read by the read voltage y4, is used as is.

[0090] The SB1 data and SB2 data can be interpreted as data representing the reliability (likelihood) of the corresponding HB data. In the example of Fig. 7, the values ​​of (SB1 data, SB2 data) represent decreasing reliability in the order of (0,1), (0,0), (1,0), and (1,1). These values ​​are merely examples, and other combinations of values ​​may also be used.

[0091] FIG. 8 is a diagram showing an example of iterative processing of the sign shift function in this modification. Processes 801 to 806 correspond to the second to seventh decoding processes of the iterative processing of the sign shift function. In processes 801 to 806, the read information is corrected to the values ​​read by read voltages y5, y6, y7, y3, y2, and y1, respectively. Of the data in each process (HB data, SB1 data, and SB2 data), the data in bold indicates the data to be corrected.

[0092] As in the above embodiment, the HB data is corrected so that its value switches between 1 and 0, with the switched read voltage as the boundary. The SB data (SB1 data, SB2 data) is corrected so that the closer it is to the switched read voltage, the lower its value indicates the reliability. Note that the SB data corresponding to the left and right ends, (SB1 data, SB2 data) = (1, 1), are not subject to correction.

[0093] The method of correcting the SB data is not limited to the above example. Also, the decoder 18 may correct only the HB data without correcting the SB data.

[0094] The flow of the decoding process in this modified example is the same as that in Fig. 6. In the above embodiment using one SB data, the maximum counter value is 2, but in this modified example, the maximum counter value is, for example, 6. It is not necessary to use all seven read voltages y1 to y7. Therefore, the maximum counter value may be a value smaller than 6. For example, five read voltages y2 to y6 may be used, and the maximum counter value may be 4.

[0095] (Variation 2) Up until now, readout information including HB data and SB data has been used as input information (input information ID1, ID2). The input information used by the decoder 18 (SISO decoding unit 182) for decoding is not limited to this. In this modification, an example will be described in which likelihood information obtained by converting readout information using conversion information is used as input information.

[0096] The likelihood information is, for example, the log-likelihood ratio (LLR) described above, and the conversion information is, for example, the LLR table described above.

[0097] 9 is a diagram showing an example of iterative processing of the sign shift function in this modified example. Note that this modified example is an example in which read information including one SB data is used. The same procedure can also be applied when read information including two or more SB data is used.

[0098] Operations 901, 902, and 903 correspond to the first, second, and third iterations of the sine shift function, respectively.

[0099] In this modification, the decoder 18 (SISO decoding unit 182) does not modify the read information (HB data, SB data), but performs each decoding process of the sign shift function so as to use different likelihood information (LLR) depending on the switching of the read voltage.

[0100] For example, in the first iteration 901 of the sign shift function, the SISO decoding unit 182 performs decoding processing using, as input information ID1, LLR data 921 obtained by converting read information (HB data, SB data) using an LLR table 911 (first conversion information). The LLR table 911 corresponds to an LLR table corresponding to a read voltage y2.

[0101] If the decoding process of process 901 fails, process 902 is executed. In process 902, the SISO decoding unit 182 executes the decoding process using, as input information ID2, LLR data 922 obtained by converting read information using an LLR table 912 (second conversion information) different from the LLR table 911. The LLR table 912 corresponds to the LLR table corresponding to the read voltage y3.

[0102] If the decoding process of process 902 fails, process 903 is executed. In process 903, the SISO decoding unit 182 executes the decoding process using, as input information ID2, LLR data 923 obtained by converting read information using an LLR table 913. The LLR table 913 corresponds to the LLR table corresponding to the read voltage y1.

[0103] The LLR tables 911, 912, and 913 are defined to output different LLR values ​​for the same value of read information (HB data, SB data). Each LLR table is defined so that the sign (positive or negative) of the LLR changes with the switched read voltage as a boundary. The LLR tables 912 and 913 (second conversion information) can be interpreted as corresponding to an LLR table obtained by correcting the default LLR table 911 (first conversion information) so as to convert the value into a value when read by the switched read voltage.

[0104] Although FIG. 9 shows that the conversion to LLR data using the LLR table is performed outside the SISO decoding unit 182, this conversion may also be performed inside the SISO decoding unit 182.

[0105] When the number of correction bits is used as reliability information, in this modification, the number of correction bits may be calculated as follows: That is, the SISO decoding unit 182 calculates the number of correction bits, for example, based on the Hamming distance between the hard decision value of the likelihood information (pre-decoding information) and the hard decision value of the ex-post LLR (post-decoding information).

[0106] A hard decision value is a binary value that determines whether each bit is 0 or 1. For example, if the value of likelihood information (LLR, a posteriori LLR) is positive, the hard decision value is 0, and if the value of likelihood information is negative, the hard decision value is 1. If the value of likelihood information is 0, the value of the hard decision value is determined according to a predetermined rule (for example, setting the hard decision value to 0).

[0107] (Variation 3) In the above description, the decoder 18 estimates the optimal read voltage based on the read voltage used in the decoding process when the reliability indicated by the reliability information is maximum. For example, when the number of corrected bits is used as the reliability information, the optimal sign shift value corresponding to the maximum number of corrected bits is estimated and output as the sign shift value corresponding to the optimal read voltage.

[0108] The method of estimating the optimal read voltage using the reliability information is not limited to the above. For example, when the difference between the maximum reliability of the decoding process executed multiple times (decoding process when the sign shift function is repeated two or more times) and the next-largest value is equal to or greater than a threshold (second threshold), the decoder 18 may estimate the optimal read voltage based on the read voltage used in the decoding process when the reliability was maximized. When the difference is smaller than the threshold, the decoder 18 estimates the optimal read voltage based on, for example, a predetermined read voltage (such as the read voltage used initially). Only when the difference is greater than the threshold, it is considered that the read voltage when the reliability was maximized is likely to be optimal, and the decoder 18 can estimate the read voltage as the optimal read voltage.

[0109] When the maximum reliability of the decoding process is equal to or greater than a threshold (third threshold), the decoder 18 may estimate the optimum read voltage based on the read voltage used in the decoding process when the reliability was maximum. When the maximum reliability is smaller than the threshold, the decoder 18 estimates the optimum read voltage based on, for example, a predetermined read voltage (such as the read voltage used initially). Only when the maximum reliability is greater than the threshold, can the decoder 18 interpret the read voltage when the reliability was maximum as being highly likely to be optimum, and estimate the read voltage as the optimum read voltage.

[0110] (Second embodiment) In the second embodiment, another configuration example will be described in which decoding is performed with higher accuracy using the optimal read voltage estimated by the first embodiment. The second embodiment uses a concatenated code of the error correcting code ECC (Error Correcting Code) 1 (first error correcting code) of the first embodiment and an error correcting code ECC2 (second error correcting code) different from the error correcting code ECC1. The error correcting code ECC2 is an error correcting code with a constraint that the exclusive OR of multiple symbols included in a codeword is 0. Examples of error correcting codes with such a constraint include a code using XOR parity and an RS code. In the following, an example will be adopted in which a code using XOR parity is used as the error correcting code ECC2.

[0111] XOR parity is calculated by taking the bitwise exclusive OR (XOR) of multiple ECC frames. An ECC frame is a unit of encoding and decoding using the error correction code ECC1, and corresponds to a codeword encoded using the error correction code ECC1, for example.

[0112] The following describes an example in which XOR parity is calculated for seven ECC frames (frames F0 to F6). A frame containing XOR parity for each bit is used as the XOR frame for XOR parity (frame F7). Data containing the j-th bit of each ECC frame (frames F0 to F6) and the j-th bit of the XOR frame (frame F7) corresponds to a codeword encoded by the error correcting code ECC2.

[0113] In the configuration using the above-described concatenated codes, for example, if decoding of an ECC frame to be decoded (hereinafter referred to as a target frame) fails, an ECC frame other than the target frame is decoded. Then, the target frame is corrected using the decoded ECC frame and the XOR constraint, and the decoding process is performed again using the corrected target frame. This can improve the probability of successful decoding.

[0114] Note that the modification of the target frame based on the XOR constraint is a process different from the process of modifying input information ID1 to input information ID2 as in the first embodiment. Hereinafter, the process of modifying input information ID1 to input information ID2 as in the first embodiment may be referred to as modification Am_A, and the modification based on the XOR constraint used in the second embodiment may be referred to as modification Am_B.

[0115] On the other hand, for example, in a situation where the deviation in the read voltage is large and decoding fails in the ECC frame (frame other than the target frame) that is XORed, uncorrected errors may remain in the target frame, reducing the probability of successful decoding when re-decoding.

[0116] 10 is a diagram for explaining a configuration (comparison example) in which decoding fails. In the example of Fig. 10, the target frame is frame F0. Also, it is assumed that the decoding process for read information 1001 (target read information) of frame F0 has failed.

[0117] In this case, seven frames (frames F1 to F7) other than the target frame (frame F0) and included in the frame group that XORs with the target frame are decoded, as shown on the left side of Fig. 10. Assume that the read information of frames F1, F3, F4, F6, and F7 is successfully decoded, but the read information 1002a and 1002b of frames F2 and F5 is unsuccessful.

[0118] Next, data required for the modified Am_B of the target frame is generated using XOR constraints. Processes 1010 and 1020 show examples of data generation processes. Process 1010 generates XOR data 1011 by calculating a bitwise XOR. The XOR data 1011 is one of the data required for the modified Am_B of the target frame. For frames that are successfully decoded, decoded word data resulting from the decoding process is used to calculate the XOR. On the other hand, for frames that are unsuccessful in decoding, for example, HB data included in the read information is used to calculate the XOR. In the example of FIG. 10, for frames F2 and F5 that are unsuccessful in decoding, HB data 1012a and 1012b are used to calculate the XOR.

[0119] In process 1020, the number of SB data indicating low reliability (e.g., SB data with a value of 0) is counted bit by bit, and low-reliability count data 1021 including a count value for each bit is generated. The low-reliability count data 1021 is one of the data required for correcting Am_B of the target frame. The low-reliability count data 1021 is generated using SB data of frames that have failed to be decoded. In the example of FIG. 10, SB data 1022a and 1022b of frames F2 and F5 that have failed to be decoded are used to count the number of SB data that indicate low reliability.

[0120] Next, the data of the target frame is modified using the XOR data 1011 and the low-reliability count data 1021, and the decoding process is performed again using the modified data. Process 1030 shows an example of modified Am_B and re-decoding of the target frame. Details of modified Am_B of the target frame will be described later. Note that modified HB data and modified SB data in process 1030 represent the data after modification Am_B is performed on the HB data and SB data of the target frame (frame F0), respectively.

[0121] In the comparative example of FIG. 10 , HB data (HB data 1012a, 1012b) is used to generate XOR data 1011, and SB data (SB data 1022a, 1022b) is used to generate low-reliability count data 1021. For this reason, for example, if the deviation in the read voltage is large and the HB data contains many errors, the quality of the generated XOR data may be degraded (errors may be included). Similarly, if the deviation in the read voltage is large and the SB data contains many errors, the quality of the generated low-reliability count data 1021 may be degraded (errors may be included). As a result, many errors may remain even after correction Am_B of the target data in process 1030, and decoding may fail.

[0122] Therefore, the memory system 1 of this embodiment uses the optimal read voltage estimated by the method of the first embodiment to correct the data used to generate the data (XOR data 1011, low-reliability count data 1021) necessary for correcting Am_B of the target frame. This makes it possible to reduce errors contained in the HB data and SB data even when there is a large deviation in the read voltage, thereby improving the probability of successful decoding.

[0123] FIG. 11 is a diagram for explaining a processing example according to this embodiment. As in FIG. 10, the target frame is frame F0. The decoder 18 (SISO decoding unit 182) first executes a decoding process using read information (target read information) for the target frame (frame F0). This decoding process is a decoding process using the sign shift function similar to that of the first embodiment. As shown in FIG. 11, it is assumed that the decoding process for frame F0 has failed.

[0124] In this case, read information for multiple ECC frames other than the target frame (frame F0) (hereinafter referred to as non-target read information) is read from the non-volatile memory. The SISO decoding unit 182 performs decoding processing using a sign shift function for each of the multiple non-target read information. In the example of FIG. 11, the decoding processing is performed using the non-target read information for each ECC frame (frames F1 to F7). As a result, an optimal read voltage is estimated for each ECC frame.

[0125] Next, the data required for the modification Am_B of the target frame is generated using the XOR constraint. Processes 1110 and 1120 in Figure 11 show an example of the process for generating the data.

[0126] In this embodiment, the SISO decoding unit 182 performs a correction process (correction Am_A) to generate one or more pieces of input information ID2 that are corrected from one or more pieces of non-target read information corresponding to one or more pieces of non-target read information that failed the decoding process among the multiple pieces of non-target read information so that they have the value they would have if read using the estimated optimal read voltage.

[0127] In process 1110 of Fig. 11, the SISO decoding unit 182 modifies the HB data 1012a to modified HB data 1112a, which corresponds to data modified to have a value when read using the optimal read voltage. Note that, for example, if the read voltage corresponding to the first iteration of the sign shift function is estimated to be the optimal read voltage, the HB data may be used in the XOR calculation without being modified. HB data 1012b of Fig. 11 is an example of unmodified HB data.

[0128] 11, the SISO decoding unit 182 modifies the SB data 1022a to generate modified SB data 1122a, which corresponds to data modified to have a value when read using an optimal read voltage. As with the HB data, the SB data may be used to generate low-reliability count data without modification. SB data 1022b in FIG. 11 is an example of unmodified SB data.

[0129] The SISO decoding unit 182 uses the plurality of pieces of input information ID2 after the correction process (corrected Am_A) to generate XOR data 1111. The SISO decoding unit 182 also uses the plurality of pieces of input information ID2 after the correction process (corrected Am_A) to generate low-reliability count data 1121.

[0130] Next, the SISO decoding unit 182 performs a modification Am_B of the input information ID1 of the target frame using the XOR data 1111 and the low-reliability count data 1121. The SISO decoding unit 182 performs the decoding process again using the modified input information ID1. Process 1130 shows an example of the modification Am_B and re-decoding of the target frame.

[0131] In this way, the SISO decoding unit 182 of this embodiment uses the optimal read voltage estimated by the method of the first embodiment to perform modified Am_A of the read information (HB data, SB data) of the ECC frame that failed to be decoded among the multiple ECC frames used for modified Am_B based on the XOR constraint. Then, the SISO decoding unit 182 performs modified Am_B based on the XOR constraint using the modified read information. This reduces the influence of deviation in the read voltage and improves the accuracy of the data used for modified Am_B based on the XOR constraint. As a result, the success rate of re-decoding using data modified by modified Am_B based on the constraint can be improved.

[0132] Next, a description will be given of the flow of the decryption process by the memory system 1 of the second embodiment. Fig. 12 is a flowchart showing an example of the decryption process by the memory system 2 of the second embodiment.

[0133] The control unit 11 reads out the error correction code corresponding to the target frame from the nonvolatile memory 20 and obtains the read information of the target frame (target read information) (step S201). The control unit 11 transfers the target read information to, for example, a read information memory in the SISO decoding unit 182 and stores it there.

[0134] The SISO decoding unit 182 executes a decoding process on the target frame (step S202). For example, the SISO decoding unit 182 executes a decoding process using a sign shift function by using the target read information.

[0135] The SISO decoding unit 182 determines whether the decoding is successful (step S203). If the decoding is not successful (step S203: No), the SISO decoding unit 182 executes a decoding process for frames other than the target frame (step S204). For example, the SISO decoding unit 182 executes a decoding process using a sign shift function using each of the non-target read information read for the multiple ECC frames other than the target frame.

[0136] The SISO decoding unit 182 determines whether the number of frames that have failed to be decoded among the multiple ECC frames included in the frame group to be XORed is equal to or less than the number of correctable frames (step S205). The number of correctable frames is the number of frames that can be corrected by the error correcting code ECC2. When XOR is used, the number of correctable frames is, for example, 1.

[0137] If the number of frames that have failed decoding is greater than the number of correctable frames (step S205: No), the SISO decoding unit 182 acquires an optimal read voltage for the ECC frames that have failed decoding (hereinafter, "decoding-failed frames") (step S206). For example, the SISO decoding unit 182 acquires the optimal read voltage estimated by the decoding process using the sign shift function in step S204. If the target frame is also to be modified using the optimal read voltage, the SISO decoding unit 182 may acquire the optimal read voltage estimated by the decoding process using the sign shift function in step S202.

[0138] The SISO decoding unit 182 executes a correction process (correction Am_A) for correcting the HB data and SB data of the decoding-failed frame using the obtained read voltage (step S207).

[0139] The SISO decoding unit 182 generates XOR data using the decoded word data or HB data (including the corrected HB data) of each frame after the correction process (step S208). Also, the SISO decoding unit 182 generates low-reliability count data using the SB data (including the corrected SB data) of the decoding-failed frame after the correction process (step S209).

[0140] The SISO decoding unit 182 executes a correction Am_B of the read information of the target frame using the XOR data and the low-reliability count data (step S210). The SISO decoding unit 182 executes a decoding process on the target frame again using the corrected read information (step S211).

[0141] The SISO decoding unit 182 determines whether the decoding is successful (step S212). If the decoding is not successful (step S212: No), the SISO decoding unit 182 notifies an external control unit or the like of the failure of the decoding (step S213) and ends the decoding process.

[0142] If it is determined in step S205 that the number of frames that have failed to be decoded is equal to or less than the number of correctable frames (step S205: Yes), the SISO decoding unit 182 restores the target frame using the error correcting code ECC2 (step S214).

[0143] After step S214, if it is determined in step S212 that the decoding is successful (step S212: Yes), or if it is determined in step S203 that the decoding is successful (step S203: Yes), the SISO decoding unit 182 notifies an external control unit or the like of the success of the decoding and the decoded word (step S215), and ends the decoding process.

[0144] Next, the details of the correction Am_B of the target frame described in process 1030 in FIG. 10, process 1130 in FIG. 11, and steps S210 and S211 in FIG. 12 will be described.

[0145] First, the input data and output data of the modified Am_B of the target frame will be described below. (input data) Input HB data: HB data of the target frame (corrected HB data after Am_A correction according to the optimal read voltage is performed) Input SB data: SB data of the target frame (corrected SB data after Am_A correction according to the optimal read voltage is performed) XOR data: Data obtained by taking the exclusive OR (XOR) of the hard decision values ​​for each bit of all ECC frames other than the target frame. For ECC frames that are successfully decoded, the hard decision value uses the decoded word data, and for ECC frames that are unsuccessful, the hard decision value uses the modified HB data after executing the modified Am_A. Low-reliability count data: Data that counts the number of bits with low reliability (low-reliability bits) for each bit in all ECC frames that have failed decoding other than the target frame. Number of ECC frames that failed to be decoded: Number of ECC frames that failed to be decoded (including the target frame) (output data) Corrected HB data: HB data obtained by applying correction Am_B to the input HB data of the target frame Corrected SB data: SB data obtained by applying correction Am_B to the input SB data of the target frame

[0146] The procedure for correcting the target frame Am_B is outlined below. (S01) Using the input HB data and input SB data, LLR data L (1) Calculate. (S02) The extrinsic LLR data is calculated using the low-reliability count data and the number of ECC frames for which decoding has failed. (S03) XOR data, L (1) , using the extrinsic value LLR data, LLR data L (2) Calculate. (S04)L (2) The corrected HB data and corrected SB data are calculated using the formula:

[0147] For example, the SISO decoding unit 182 calculates output data (modified HB data, modified SB data) from input data according to the above procedure. The SISO decoding unit 182 may calculate the output data using conversion information (such as a conversion table) that associates the values ​​of output data calculated in advance according to the above procedure with combinations of input data.

[0148] The details of each of the above steps will be further explained. In S01, the SISO decoding unit 182 generates LLR data L for each bit of the ECC frame according to the following equation (3): (1) Hereinafter, the j-th bit may be referred to as bit j. j (1) is the LLR data L of bit j (1) Represents the value of

number

[0149] The high-reliability LLR absolute value R and the low-reliability LLR absolute value U are predetermined non-negative fixed values ​​that satisfy R>U (for example, R=5, L=1). Equation (3) corresponds to an equation that determines whether the LLR is positive or negative based on the HB data value, and determines the absolute value of the LLR based on the SB data value. For example, a value is calculated that indicates that the larger the absolute value of the LLR, the higher the reliability.

[0150] In S02, the SISO decoding unit 182 generates extrinsic LLR data L for each bit of the ECC frame according to the following equation (4): (e) Calculate the value of L j (e) is the extrinsic value of bit j of LLR data L (e) Represents the value of

number

[0151] The high-reliability LLR absolute value R' and the low-reliability LLR absolute value U' are predetermined non-negative fixed values, and satisfy R'>U'. R' and U' may be the same as or different from R and U in equation (3). Equation (4) corresponds to a calculation equation for the extrinsic value LLR under the XOR constraint.

[0152] At bit j, c j corresponds to the number of low-reliability bits, and d-1-c jcorresponds to the number of highly reliable bits. When calculating the extrinsic LLR for the target frame, the contribution of the target frame must be excluded. In addition, for successfully decoded frames, the LLR absolute value L can be considered to be L>>1, so the contribution, tanh(L), is approximately 1 and does not appear in the notation. Therefore, the number of low-reliability bits, c j and the number of reliable bits is d-1-c j The sum of these is d-1.

[0153] In S03, the SISO decoding unit 182 generates LLR data L for each bit of the ECC frame according to the following equation (5): (2) Calculate the value of L j (2) is the LLR data L of bit j (2) Represents the value of

number

[0154] Equation (5) is the LLR data L (1) This corresponds to the process of adding the external value LLR, which has been given a sign calculated from the XOR data, to the value of

[0155] In S04, the SISO decoding unit 182 calculates the values ​​of the modified HB data and modified SB data for each bit of the ECC frame according to the following equation (6): HB j SB ' represents the value of the modified HB data for bit j. j ' represents the value of the modified SB data of bit j.

number

[0156] L j (2) HB when =0 j The value of L' may be determined by a method other than equation (6). For example, j (1) Under the design that does not take 0, L j (1) HB according to the sign j The value of ' may be determined (L j (1) is positive, then HB'=0, if negative, then HB'=1, etc.

[0157] As described above, in the second embodiment, in an error correction technology that uses an error correction code (such as XOR parity) that has the constraint that the exclusive OR of symbols is 0, error correction can be performed with higher accuracy by using data corrected using an estimated optimal read voltage.

[0158] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0159] 1. Memory System 10 Memory Controller 11 Control section 12 Data Buffers 13 Memory I / F 14 Encoding / Decoding Unit 15 Host I / F 16 Internal Bus 17 Encoder 18 Decoder 20 Non-volatile memory 30 hosts

Claims

1. a non-volatile memory that stores an error correction code; reading read information from the nonvolatile memory using a first read voltage; performing a decoding process using first input information, which is either the read information or likelihood information obtained by converting the read information using first conversion information; If the decoding process fails, the decoding process is further performed using second input information obtained by correcting the first input information so that the value obtained is a value that would be obtained if the first input information were read using a second read voltage that is different from the first read voltage; estimating a third read voltage based on reliability information representing the reliability of the decoding process; A memory controller; A memory system comprising:

2. the second input information is either corrected read information obtained by correcting the read information so that the value becomes a value when read by the second read voltage, or the likelihood information obtained by converting the read information by second conversion information obtained by correcting the first conversion information so that the value becomes a value when read by the second read voltage.

10. The memory system of claim 1.

3. The reliability information is a number of corrected bits representing the number of bits corrected in the decoding process.

10. The memory system of claim 1.

4. the second input information is either corrected read information obtained by correcting the read information so that the value becomes a value when read by the second read voltage, or the likelihood information obtained by converting the read information by second conversion information obtained by correcting the first conversion information so that the value becomes a value when read by the second read voltage, The number of correction bits is pre-decoding information, which is any one of the read information, the modified read information, and the hard decision value of the likelihood information; post-decoding information, which is either a decoded word obtained by the decoding process or a hard decision value of a posteriori value of likelihood information obtained by the decoding process; is the Hamming distance between 4. The memory system of claim 3.

5. The memory controller Calculating the number of corrected bits by adding 1 each time a bit is corrected in the decoding process and subtracting 1 each time a bit is corrected so that its value is restored; 4. The memory system of claim 3.

6. the error-correcting code is an N-dimensional error-correcting code in which at least one symbol among symbols constituting the code is protected by N component code groups (N is an integer of 2 or more), The reliability information is a statistical value of reliability of the decoding process for each of M component codes (1≦i≦N, ni is the number of component codes included in the i-th dimension component code group, and M is the sum of ni).

10. The memory system of claim 1.

7. The reliability information is represents the number of bits whose absolute value of the posterior value of the likelihood information obtained by the decoding process is equal to or greater than a first threshold, 10. The memory system of claim 1.

8. The memory controller estimating the third read voltage based on a read voltage used in the decoding process when the reliability indicated by the reliability information is maximized; 10. The memory system of claim 1.

9. The memory controller when a difference between a maximum value of the reliability of the decoding process executed a plurality of times and a value next to the maximum value is equal to or greater than a second threshold, estimating the third read voltage based on a read voltage used in the decoding process when the reliability became maximum; 9. The memory system of claim 8.

10. The memory controller when the maximum value of the reliability of the decoding process is equal to or greater than a third threshold, estimating the third read voltage based on the read voltage used in the decoding process when the reliability is maximized; 9. The memory system of claim 8.

11. The read information includes, for each bit, hard bit data representing a hard decision value and one or more soft bit data representing the reliability of the hard decision value.

10. The memory system of claim 1.

12. the first input information is the read information, the second input information is corrected read information obtained by correcting the read information so that the value is a value when read using the second read voltage; When the decoding process fails, the memory controller inverts the value of the hard bit data corresponding to the soft bit data representing low reliability for each bit included in the read information, thereby obtaining the corrected read information.

12. The memory system of claim 11.

13. the error correction code is a concatenated code including a first error correction code and a second error correction code, the second error-correcting code has a constraint that an exclusive OR of a plurality of symbols included in a code word is 0; The memory controller reading target read information, which is the read information for the first error-correcting code to be decoded, from the nonvolatile memory; When the decryption process using the target read information fails, reading, from the nonvolatile memory, a plurality of pieces of non-target read information, which are the read information for a plurality of the first error-correcting codes other than those to be decoded; performing a correction process to generate one or more pieces of second input information by correcting one or more pieces of first input information corresponding to one or more pieces of non-target read information that have failed in the decoding process among the plurality of pieces of non-target read information so that the second input information has a value that would be obtained if the first input information were read using the estimated third read voltage; Calculating an exclusive OR using one or more pieces of second input information after the correction process has been performed; modifying the first input information corresponding to the target read information using the calculated exclusive OR; performing a decoding process using the modified first input information; 10. The memory system of claim 1.

14. The memory controller Calculating an exclusive OR of decoded word data corresponding to one or more pieces of non-target read information that have been successfully decoded and one or more pieces of second input information after the correction process has been performed corresponding to one or more pieces of non-target read information that have failed to be decoded, modifying the first input information corresponding to the target read information using the calculated exclusive OR; 14. The memory system of claim 13.

15. The memory controller calculating the number of symbols having a lower reliability than other symbols among a plurality of symbols included in the second error-correcting code using the one or more pieces of second input information after the correction process has been performed; correcting the first input information corresponding to the target read information using the calculated exclusive OR and the calculated number; 14. The memory system of claim 13.

16. reading read information from a nonvolatile memory storing an error correction code using a first read voltage; performing a decoding process using first input information, which is either the read information or likelihood information obtained by converting the read information using first conversion information; If the decoding process fails, the decoding process is further performed using second input information obtained by correcting the first input information so that the value obtained is a value that would be obtained if the first input information were read using a second read voltage that is different from the first read voltage; estimating a third read voltage based on reliability information representing the reliability of the decoding process; Memory controller.

17. A control method executed by a memory controller, comprising: reading read information from a nonvolatile memory storing an error correction code using a first read voltage; performing a decoding process using first input information, which is either the read information or likelihood information obtained by converting the read information using first conversion information; If the decoding process fails, the decoding process is further performed using second input information obtained by correcting the first input information so that the value obtained is a value that would be obtained if the first input information were read using a second read voltage that is different from the first read voltage; estimating a third read voltage based on reliability information representing the reliability of the decoding process; Control method.

Images