Semiconductor device

Abstract

To efficiently suppress an increase in access time accompanying read assist in a semiconductor device including an SRAM.SOLUTION: The read assist circuit is configured to be switchable between valid and invalid, and when the read assist circuit is valid, a word line voltage applied to the word line is reduced in order to secure a static noise margin of the memory cell. The SNM detection circuit SNMD includes a replica memory cell RMC configured to have a data holding capability lower than that of the memory cell. The SNM detector SNMD detects the static noise margin of the memory cell in a pseudo manner by using the replica memory cell RMC, and switches the validity / invalidity of the read assist circuit according to the detection result.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, for example, a semiconductor device including an SRAM (Static Random Access Memory). [Background technology]

[0002] Non-Patent Document 1 shows a configuration in which a TATA circuit is applied to an assist circuit for SRAM. The TATA circuit determines the step-down level of the word line voltage using the gate-source voltage of a diode-connected MOS transistor. As a result, the TATA circuit generates a word line voltage that decreases as the temperature increases.

[0003] Non-Patent Document 2 shows a configuration equipped with a PVT monitor sensor to generate a trigger to a read assist circuit for SRAM. The PVT monitor sensor compares the magnitude of the output voltage from a process monitor circuit (PMC) with that from a bandgap reference (BGR) circuit, and controls the on / off of the trigger to the read assist circuit based on the comparison result. [Prior art documents] [Non-patent literature]

[0004] [Non-Patent Document 1] Inhak Lee et al, “A Voltage and Temperature Tracking SRAM Assist Supporting 740mV Dual-Rail Offset for Low-Power and High-Performance Applications in 7nm EUV FinFET Technology”, ISSCC 2019 [Non-patent document 2] Belal Iqbal et al, “Actively Compensated Read Assist Technique for 0.6 V Operation of 16 Mb High Density SRAM in 65nm LSTP”, INDICON 2020 Summary of the Invention [Problem to be solved by the invention]

[0005] For example, in SRAM, increasing manufacturing variability due to miniaturization makes assist control necessary to ensure memory cell operating margins. Specifically, the static noise margin of memory cells is insufficient, especially at high temperatures, making it essential to incorporate a read assist circuit to improve this. A typical read assist circuit is a circuit that slightly lowers the word line voltage during read access of SRAM. However, lowering the word line voltage has the side effect of reducing the memory cell current during read access, which can result in increased access time.

[0006] Here, regarding the read assist circuit, for example, configurations such as those shown in Non-Patent Document 1 and Non-Patent Document 2 are known. In the configuration shown in Non-Patent Document 1, the read assist circuit changes the amount of assistance depending on the temperature. However, since the read assist circuit operates constantly while changing the amount of assistance, an increase in access time may also occur constantly.

[0007] On the other hand, in the configuration shown in Non-Patent Document 2, a PVT monitor sensor can be used to turn the read assist circuit on / off, i.e., enable / disable. However, the PVT monitor sensor requires a relatively large circuit area. Also, the PVT monitor sensor may take some time to detect the temperature. As such, the configurations shown in Non-Patent Document 1 and Non-Patent Document 2 may not be able to efficiently suppress the increase in access time associated with read assist.

[0008] The embodiments described below have been made in consideration of the above, and other problems and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0009] A semiconductor device according to one embodiment includes an SRAM and a detection circuit that detects a static noise margin in the SRAM. The SRAM has a memory array and a read assist circuit. The memory array has word lines, bit line pairs, and memory cells connected to the word lines and bit line pairs. The read assist circuit is configured to be switchable between enabled and disabled, and when enabled, reduces a word line voltage applied to the word lines to ensure the static noise margin of the memory cells. The detection circuit has replica memory cells configured to have a lower data retention capability than the memory cells. The detection circuit uses the replica memory cells to pseudo-detect the static noise margin of the memory cells and switches the read assist circuit between enabled and disabled depending on the detection result. [Effects of the Invention]

[0010] According to the embodiment, in a semiconductor device including an SRAM, an increase in access time due to read assist can be efficiently suppressed. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a block diagram showing a schematic configuration example of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a block diagram showing a schematic configuration example of the volatile memory in FIG. [Figure 3] FIG. 3 is a circuit diagram showing an example of the configuration of the memory cell in FIG. [Figure 4] FIG. 4 is a block diagram showing a schematic configuration example of the SNM detection circuit in FIG. [Figure 5] FIG. 5 is a schematic diagram illustrating an example of the operation of the replica memory cell in FIG. [Figure 6] FIG. 6 is a schematic diagram illustrating the effect of using replica memory cells in FIG. [Figure 7] FIG. 7 is a schematic diagram showing an example of the general operation of the SNM detection circuit in FIG. [Figure 8] FIG. 8 is a circuit diagram showing a more detailed configuration example of the SNM detection circuit in FIG. [Figure 9] FIG. 9 is a timing chart showing an example of the operation of the SNM detection circuit in FIG. [Figure 10A] FIG. 10A is a diagram showing an example of different components of the replica memory cells in FIG. [Figure 10B] FIG. 10B is a diagram showing an example of different components of the replica memory cells in FIG. [Figure 10C] FIG. 10C is a diagram showing an example of different components of the replica memory cells in FIG. [Figure 10D] FIG. 10D is a diagram showing an example of different components of the replica memory cells in FIG. [Figure 10E] FIG. 10E is a diagram showing an example of different components of the replica memory cells in FIG. [Figure 11] FIG. 11 is a schematic diagram showing an example of the layout of the SNM detection circuit in FIG. [Figure 12] FIG. 12 is a schematic diagram showing another example of the arrangement of the SNM detection circuit in FIG. [Figure 13] FIG. 13 is a circuit diagram showing a more detailed configuration example of the SNM detection circuit shown in FIG. 4 in the semiconductor device according to the second embodiment. [Figure 14] FIG. 14 is a timing chart showing a schematic example of the operation of the SNM detection circuit in FIG. [Figure 15] FIG. 15 is a circuit diagram showing a detailed configuration example of the SNM detection circuit different from that of FIG. 8 in the semiconductor device according to the third embodiment. [Figure 16]FIG. 16 is a truth table showing an example of the operation of the majority decision circuit in FIG. [Figure 17] FIG. 17 is a schematic diagram showing an example of application of an SNM detection circuit to write assist in a semiconductor device according to the fourth embodiment. [Figure 18] FIG. 18 is a diagram illustrating an example of the operation of the write assist circuit in FIG. [Figure 19] FIG. 19 is a diagram illustrating the static noise margin (SNM) of the memory cell shown in FIG. [Figure 20] FIG. 20 is a diagram showing an example of various characteristics of the static noise margin (SNM). [Figure 21] FIG. 21 is a diagram showing an example of the operation of the read assist circuit in FIG. 2 and an example of a problem that accompanies read assist. DETAILED DESCRIPTION OF THE INVENTION

[0012] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments, but unless otherwise specified, they are not unrelated to each other, and one is a partial or complete modification, detail, supplementary explanation, etc. of the other. Furthermore, in the following embodiments, when the number of elements, etc. (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to that specific number, and may be more or less than the specific number, unless otherwise specified or when it is clearly limited in principle to a specific number.

[0013] Furthermore, in the following embodiments, it goes without saying that the components (including element steps, etc.) are not necessarily essential unless otherwise specified or considered to be clearly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., it is intended to include those that are substantially similar or similar to the shape, etc., unless otherwise specified or considered to be clearly not essential in principle. The same applies to the above numerical values ​​and ranges.

[0014] In the following embodiments, a p-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and an n-channel MOSFET will be referred to as a pMOS transistor and an nMOS transistor, respectively. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings used to explain the embodiments, the same components are generally designated by the same reference numerals, and repeated explanations will be omitted.

[0015] (First embodiment) <Outline of semiconductor device> Fig. 1 is a block diagram showing a schematic configuration example of a semiconductor device according to a first embodiment. The semiconductor device DEV shown in Fig. 1 is, for example, a SoC (System on Chip) configured with one semiconductor chip, or a microcontroller. The semiconductor device DEV includes a processor PRC, a volatile memory RAM, a nonvolatile memory NVM, various peripheral circuits PERI, and a bus BS connecting these to each other. The semiconductor device DEV also includes a power supply circuit PWG, a clock generation circuit CLKG, etc.

[0016] The volatile memory RAM includes at least an SRAM. The nonvolatile memory NVM is, for example, a magnetoresistive random access memory (MRAM) or a flash memory. The processor PRC includes a central processing unit (CPU) and may also include a digital signal processor (DSP) and a graphics processing unit (GPU). The processor PRC executes a predetermined program stored in the MRAM or copied from a flash memory or the like to the volatile memory RAM. At this time, the processor PRC can use the SRAM as a working memory.

[0017] The various peripheral circuits PERI are circuits corresponding to the functions of the semiconductor device DEV. Examples of the various peripheral circuits PERI include an analog-digital converter, a digital-analog converter, a serial-parallel interface, a serial communication circuit, an external memory interface, and the like. The power supply circuit PWG receives an external power supply (not shown) and generates various power supply voltages, including a power supply voltage VDD for the SRAM. The clock generation circuit CLKG uses a PLL (Phase Locked Loop) circuit or the like to generate various clock signals, including a clock signal CLK for the SRAM.

[0018] <Outline of Volatile Memory (SRAM)> Fig. 2 is a block diagram showing a schematic configuration example of the volatile memory RAM in Fig. 1. Fig. 3 is a circuit diagram showing a configuration example of the memory cell MC in Fig. 2. The volatile memory RAM shown in Fig. 2, more specifically, the SRAM, includes a memory array MARY, a word line control circuit WLC, a read / write circuit RWC, a memory control circuit MCTL, and a static noise margin detection circuit SNMD. In the specification, static noise margin may be abbreviated as SNM.

[0019] The memory array MARY includes word lines WL, bit line pairs (BLt, BLb) consisting of complementary bit lines BLt and BLb, and memory cells MC connected to the word lines WL and the bit line pairs (BLt, BLb). In detail, the memory array MARY is provided with a plurality of word lines WL and a plurality of bit line pairs (BLt, BLb), and a memory cell MC is provided at the intersection of each word line WL and each bit line pair (BLt, BLb).

[0020] The memory control circuit MCTL receives a clock signal CLK, an address signal ADR, and a command signal CMD, and controls the word line control circuit WLC and the read / write circuit RWC according to the input contents. The command signal CMD may include, for example, a chip select signal CS, a write enable signal WE, etc.

[0021] The word line control circuit WLC includes a word decoder circuit WDEC, a word driver circuit WD, and a read assist circuit RAC. The word decoder circuit WDEC selects one of the word lines WL by decoding an address signal ADR input via the memory control circuit MCTL. The word driver circuit WD activates the selected word line WL using a word line voltage Vwl.

[0022] The read assist circuit RAC is configured to be switchable between on / off, i.e., enabled / disabled, based on the read assist off signal RAOFF. For example, when the read assist off signal RAOFF is at 'H' level or '1' level, the read assist circuit RAC is off, i.e., disabled. On the other hand, when the read assist off signal RAOFF is at 'L' level or '0' level, the read assist circuit RAC is on, i.e., enabled.

[0023] When the read assist circuit RAC is enabled based on the read assist off signal RAOFF, the read assist circuit RAC reduces the word line voltage Vwl applied to the word line WL by a predetermined amount. As a result, the read assist circuit RAC ensures SNM of the memory cell MC. The static noise margin (SNM) detection circuit SNMD outputs the read assist off signal RAOFF. Details of the SNM detection circuit SNMD will be described later.

[0024] The read / write circuit RWC performs write access or read access via the bit line pair (BLt, BLb) to the memory cell MC connected to the selected word line WL, or to a memory cell MC further selected from the selected word line WL based on an instruction from the memory control circuit MCTL. During a write access, the read / write circuit RWC writes an input data signal Din to the target memory cell MC. During a read access, the read / write circuit RWC reads an output data signal Dout from the target memory cell MC.

[0025] More specifically, the read / write circuit RWC includes, for example, a column selection circuit, a sense amplifier circuit, and a write buffer circuit. The column selection circuit selects a portion of the bit line pairs (BLt, BLb) from among the plurality of bit line pairs (BLt, BLb) based on an instruction from the memory control circuit MCTL. The write buffer circuit drives the selected bit line pair (BLt, BLb) based on an input data signal Din. The sense amplifier circuit amplifies the signal read out to the selected bit line pair (BLt, BLb) and outputs it to the outside as an output data signal Dout.

[0026] As shown in Figure 3, the memory cell MC, i.e., an SRAM memory cell, comprises two pMOS transistors MPu1 and MPu2 and four nMOS transistors MNd1, MNd2, MNp1, and MNp2. The pMOS transistors MPu1 and MPu2 are pull-up transistors that pull up the storage nodes SNt and SNb to the power supply voltage VDD, respectively. The nMOS transistors MNd1 and MNd2 are pull-down transistors that pull down the storage nodes SNt and SNb to the ground voltage VSS, respectively.

[0027] The nMOS transistors MNp1 and MNp2 are pass gate transistors that connect the storage nodes SNt and SNb to the bit line pair (BLt, BLb) when the word line WL is activated. The nMOS transistor MNp1 connects the storage node SNt on the positive (True) side to one of the bit line pair (BLt, BLb), which is the positive bit line BLt in this case. The nMOS transistor MNp2 connects the storage node SNb on the negative (Bar) side to the negative bit line BLb, which is the other of the bit line pair (BLt, BLb).

[0028] The pMOS transistor MPu1 and nMOS transistor MNd1 form a CMOS inverter circuit CIV1 that uses the inverting storage node SNb as its input and the non-inverting storage node SNt as its output. Meanwhile, the pMOS transistor MPu2 and nMOS transistor MNd2 form a CMOS inverter circuit CIV2 that uses the non-inverting storage node SNt as its input and the inverting storage node SNb as its output. This forms a CMOS latch circuit.

[0029] <Static Noise Margin (SNM)> FIG. 19 is a diagram illustrating the static noise margin (SNM) of the memory cell MC shown in FIG. 3. FIG. 19 shows an example of the input / output characteristics of the CMOS inverter circuits CIV1 and CIV2, with the voltage of the non-inverting storage node SNt on the horizontal axis and the voltage of the inverting storage node SNb on the vertical axis. Each input / output characteristic is called a butterfly curve. As shown in FIG. 19, the SNM is defined as the distance between the two butterfly curves. The larger this distance is, the more sufficient the SNM becomes.

[0030] SNM is particularly problematic during read access. As a specific example, consider a case where a read access is performed on a memory cell MC that has a 'L' level held at the non-inverting storage node SNt and a 'H' level held at the inverting storage node SNb. During a read access, for example, after both bit line pairs (BLt, BLb) are precharged to the 'H' level, the word line WL is activated. At this time, a disturbance, i.e., noise, occurs from the 'H' level bit line BLt to the 'L' level storage node SNt via the nMOS transistor MNp1.

[0031] When SNM is insufficient, that is, when the interval shown in FIG. 19 is small, this disturbance may cause the storage node SNb to invert from 'H' level to 'L' level, and as a result, the storage node SNt may also invert from 'L' level to 'H' level. Note that the interval shown in FIG. 19 may usually become smaller as miniaturization progresses. Therefore, the problem of such disturbance may become more pronounced as miniaturization progresses.

[0032] FIG. 20 is a diagram showing an example of various static noise margin (SNM) characteristics. FIG. 20 shows an example of the relationship between the threshold voltage of the pass gate (PG) transistor and the threshold voltage of the pull-up transistor (PU) in FIG. 3. The upper left region of FIG. 20, based on the upward-sloping boundary line, is a region where SNM is insufficient. Meanwhile, the SNM becomes more sufficient as it moves further away from the boundary line toward the lower right.

[0033] As shown in Figure 20, the SNM problem becomes more pronounced at higher temperatures. In other words, the SNM problem is less likely to occur at lower temperatures. Also, due to manufacturing variations, the SNM problem becomes more pronounced under FS conditions and less pronounced under SF conditions. For example, under FS conditions, the speed of nMOS transistors is "fast" due to their low threshold voltage, while the speed of pMOS transistors is "slow" due to their high threshold voltage.

[0034] 21 is a diagram showing an example of the operation of the read assist circuit RAC in FIG. 2 and an example of a problem associated with read assist. When the read assist circuit RAC is on, i.e., enabled, based on the read assist off signal RAOFF, it reduces the word line voltage Vwl by a drop ΔVwl. For example, the drop ΔVwl is about several tens of mV for a word line voltage Vwl of about 1.0 V under normal circumstances.

[0035] Thus, by reducing the word line voltage Vwl, in the above-described specific example, the disturbance amount from the bit line BLt to the memory node SNt via the nMOS transistor MNp1 can be reduced. As a result, the SNM of the memory cell MC can be ensured. However, as a side effect, the memory cell current Icell during read access becomes small. The memory cell current Icell flows from the bit line BLb precharged to the 'H' level to the memory node SNb holding the 'L' level via the nMOS transistor MNp2 with an increased on-resistance in the example shown in FIG. 21.

[0036] Also, during read access, after a predetermined waiting time elapses since the word line WL is activated, the potential difference of the bit line pair (BLt, BLb) is amplified by the sense amplifier circuit. When the memory cell current Icell becomes small, the waiting time required to obtain a sufficient potential difference becomes long. As a result, the access time of the SRAM increases, and accordingly, the processing speed of the processor PRC may decrease. Further, the problem of such an increase in access time may become more prominent particularly at low temperatures where the threshold voltage of the MOS transistor becomes large and thus the speed may decrease. Therefore, the SNM detection circuit SNMD shown in FIG. 1 is provided.

[0037] <Schematic of SNM detection circuit> FIG. 4 is a block diagram showing a schematic configuration example of the SNM detection circuit SNMD in FIG. 1. FIG. 5 is a schematic diagram for explaining an operation example of the replica memory cell RMC in FIG. 4. The SNM detection circuit SNMD shown in FIG. 4 includes a replica memory cell RMC, a sequence control circuit SEQCT, and a latch circuit FF. The replica memory cell RMC includes a replica word line RWL, a replica bit line pair (RBLt, RBLb), and a dummy memory cell MCD connected thereto. The dummy memory cell MCD has a configuration that mimics the normal memory cell MC shown in FIG. 3.

[0038] That is, the dummy memory cell MCD includes two pMOS transistors MPu3 and MPu4, four nMOS transistors MNd3, MNd4, MNp3, and MNp4, and complementary storage nodes MEMt and MEMb. The pMOS transistors MPu3 and MPu4 pull up the complementary storage nodes MEMt and MEMb to a power supply voltage (high-potential power supply voltage) VDD. The pMOS transistor (first pull-up transistor) MPu3 pulls up the non-inverting storage node MEMt. The pMOS transistor (second pull-up transistor) MPu4 pulls up the inverting storage node MEMb.

[0039] The nMOS transistors MNd3 and MNd4 respectively pull down the complementary storage nodes MEMt and MEMb to the ground voltage (low-potential power supply voltage) VSS. The nMOS transistor (first pull-down transistor) MNd3 pulls down the non-inverting storage node MEMt. The nMOS transistor (second pull-down transistor) MNd4 pulls down the inverting storage node MEMb.

[0040] The nMOS transistors MNp3 and MNp4 connect the complementary storage nodes MEMt and MEMb to the complementary replica bit lines (RBLt and RBLb), respectively, when the replica word line RWL is activated. The nMOS transistor (first pass gate transistor) MNp3 connects the non-inverting storage node MEMt to the non-inverting replica bit line RBLt. The nMOS transistor (second pass gate transistor) MNp4 connects the inverting storage node MEMb to the inverting replica bit line RBLb.

[0041] Here, the replica memory cell RMC is configured to have a lower data retention capability than the normal memory cell MC. As one such method, the replica memory cell RMC shown in FIG. 4 includes an nMOS transistor MNr3 and a pMOS transistor MPr4. The nMOS transistor (first limiting transistor) MNr3 is inserted in the current path between the nMOS transistor MNd3 and the ground voltage VSS. The pMOS transistor (second limiting transistor) MPr4 is inserted in the current path between the pMOS transistor MPu4 and the power supply voltage VDD.

[0042] The nMOS transistor MNr3 has a larger gate length (L) than the nMOS transistor MNd3, in other words, a gate electrode with a wider width. The nMOS transistor MNr3 is always on when the power supply voltage VDD is applied to its gate. Similarly, the pMOS transistor MPr4 has a larger gate length (L) than the pMOS transistor MPu4, in other words, a gate electrode with a wider width. The pMOS transistor MPr4 is always on when the ground voltage VSS is applied to its gate.

[0043] 5, the replica memory cell RMC includes an nMOS transistor MNr3 that limits the pull-down current, thereby reducing the ability to hold a low level at the non-inverting storage node MEMt. Similarly, the replica memory cell RMC includes a pMOS transistor MPr4 that limits the pull-up current, thereby reducing the ability to hold a high level at the non-inverting storage node MEMb. As a result, when a high-level disturbance, i.e., noise, is applied to the non-inverting replica bit line RBLt, the replica memory cell RMC is more susceptible to data inversion, i.e., SNM deficiency, than a normal memory cell MC.

[0044] Returning to FIG. 4, the SNM detection circuit SNMD uses such replica memory cells RMC to pseudo-detect SNMs in normal memory cells MC. Then, depending on the detection result, the SNM detection circuit SNMD switches the read assist circuit RAC on / off, i.e., enabled / disabled, using a read assist off signal RAOFF. At this time, the sequence control circuit SEQCT controls various sequences associated with the detection of SNMs using the replica memory cells RMC. As will be described in detail later, the sequence control circuit SEQCT performs an initialization operation and a detection operation, for example, for each clock cycle based on the input clock signal CLK.

[0045] The latch circuit FF, i.e., a flip-flop circuit, holds the detection result using the replica memory cell RMC. Specifically, the latch circuit FF latches the logic level of the inverted replica bit line RBLb in response to a trigger signal from the sequence control circuit SEQCT. The latch circuit FF then outputs the latched logic level as a read assist off signal RAOFF.

[0046] 6 is a schematic diagram illustrating the effect of using replica memory cells RMC in FIG. 4. In normal memory cells MC, memory cells MC with the worst SNM, that is, memory cells MC where SNM deficiency may occur, occur with a probability of 5σ to 6σ due to manufacturing variations, i.e., random variations. For this reason, it is difficult to determine whether SNM is good or bad using normal memory cells MC.

[0047] The data retention capability of the replica memory cells RMC is determined to reflect the data retention capability of memory cells MC that occur with a probability of existence of 5σ to 6σ, with a margin added toward the worst case scenario. In other words, in the case of Figure 4, the gate length (L) of the limiting transistors (MNr3, MPr4) is determined to have such a data retention capability. This allows one replica memory cell RMC to be used to virtually detect SNM in the worst memory cell MC among multiple memory cells MC.

[0048] However, in this case, it is assumed that the replica memory cell RMC itself is not easily affected by manufacturing variations. For this reason, it is desirable that the replica memory cell RMC is configured using transistors with a larger gate length (L) or gate width (W) than the transistors that configure the normal memory cell MC. Usually, the influence of manufacturing variations becomes smaller as the gate length (L) or gate width (W) becomes larger.

[0049] FIG. 7 is a schematic diagram showing an example of the general operation of the SNM detection circuit SNMD in FIG. 4. As shown in FIG. 7, the SNM detection circuit SNMD executes a series of operations consisting of a standby operation, an initialization operation, and a detection operation. In detail, the SNM detection circuit SNMD sequentially executes an initialization operation and a detection operation in response to the clock signal CLK, and then returns to standby operation. The sequence control circuit SEQCT controls the entire SNM detection circuit SNMD so that this series of operations is performed.

[0050] In standby operation, the sequence control circuit SEQCT controls the replica word line RWL to an inactive state, i.e., to the 'L' level. As a result, the storage nodes MEMt and MEMb hold data at an indeterminate 'X' level, specifically, the data at the previous clock cycle. Subsequently, in initialization operation, the sequence control circuit SEQCT activates the replica word line RWL, i.e., sets it to the 'H' level. Then, the sequence control circuit SEQCT writes the 'L' level and the 'H' level to the non-inverting storage node MEMt and the inverting storage node MEMb, respectively, via the replica bit line pair (RBLt, RBLb).

[0051] Next, in the detection operation, the sequence control circuit SEQCT activates the replica word line RWL, controls the inverted replica bit line RBLb to a floating state, and applies a 'H' level to the non-inverted replica bit line RBLt. After that, the sequence control circuit SEQCT latches the logic level of the inverted replica bit line RBLb in the latch circuit FF. This allows the SNM detection circuit SNMD to detect whether the inverted replica bit line RBLb is in a pass state where it can maintain a 'H' level, or in a fail state where it inverts to a 'L' level.

[0052] A pass state is a state in which the SNM is sufficient, and a fail state is a state in which the SNM is insufficient. In the pass state, the latch circuit FF outputs an 'H' level, i.e., assert level, as the read assist off signal RAOFF. This causes the SNM detection circuit SNMD to turn off, i.e., disable, the read assist circuit RAC. On the other hand, in the fail state, the latch circuit FF outputs an 'L' level, i.e., negate level, as the read assist off signal RAOFF. This causes the SNM detection circuit SNMD to turn on, i.e., enable, the read assist circuit RAC.

[0053] As can be seen from FIG. 20, the detection result of the SNM detection circuit SNMD is more likely to be in the pass state at lower temperatures and more likely to be in the fail state at higher temperatures. On the other hand, as noted in FIG. 21, the access time is more likely to increase at lower temperatures. Therefore, it is beneficial to use the SNM detection circuit SNMD to disable the read assist circuit RAC, particularly at low temperatures. This makes it possible to suppress the increase in access time associated with read assist, particularly at low temperatures.

[0054] Also, by using the SNM detection circuit SNMD, the on / off of the read assist circuit RAC can be controlled without using a PVT monitor sensor including a process monitor circuit (PMC) and a bandgap reference (BGR) circuit as shown in Non-Patent Document 2. Generally, since the PVT monitor sensor is composed of high-voltage-tolerant MOS transistors, its circuit area is larger than that of the SNM detection circuit SNMD. For example, the circuit area of the PVT monitor sensor can be dozens of times or more larger than that of the SNM detection circuit SNMD.

[0055] Furthermore, the PVT monitor sensor requires a certain amount of time, for example, on the order of microseconds, until the operations of circuits such as the BGR circuit become stable. Then, for example, when the semiconductor device DEV returns from the sleep mode to the normal mode, a certain waiting time is required to determine the validity / invalidity of the read assist circuit RAC. Also, if the waiting time is short, the validity / invalidity cannot be correctly determined, so from the perspective of failsafe, it is necessary to activate the read assist circuit RAC even at low temperatures.

[0056] On the other hand, when using the SNM detection circuit SNMD, the detection result of SNM can be obtained at the cycle of the clock signal CLK, that is, the access cycle to the SRAM. Therefore, even when the semiconductor device DEV returns from the sleep mode to the normal mode, a correct detection result can be obtained without particularly requiring a waiting time. From the above, by using the SNM detection circuit SNMD, the increase in access time associated with read assist can be efficiently suppressed. Furthermore, since it is a method of pseudo-detecting SNM, in some cases, the necessity of read assist can be determined more accurately than the method shown in Non-Patent Document 2.

[0057] <Details of the SNM detection circuit> Fig. 8 is a circuit diagram showing a more detailed configuration example of the SNM detection circuit SNMD in Fig. 4. The SNM detection circuit SNMD shown in Fig. 8 includes, in addition to the replica memory cells RMC and latch circuits FF shown in Fig. 4, an initialization circuit INITC, a clock driver circuit CLKD, and various logic gates including delay circuits DLY1 and DLY2. The clock driver circuit CLKD and various logic gates correspond to the sequence control circuit SEQCT in Fig. 4.

[0058] 4 and 7, in the replica memory cell RMC, in the initialization operation, the 'L' level and the 'H' level are written to the non-inverting side storage node MEMt and the inverting side storage node MEMb, respectively. However, the replica memory cell RMC is configured so that the 'L' level data retention capability of the storage node MEMt and the 'H' level data retention capability of the storage node MEMb are low. For this reason, in the initialization operation, it may be difficult to write the 'L' level and the 'H' level to the complementary storage nodes MEMt and MEMb.

[0059] 8, an initialization circuit INITC used in the initialization operation is provided. For convenience of description, the initialization circuit INITC is shown in two separate locations. The initialization circuit INITC includes an nMOS transistor MNiL, a pMOS transistor MPif, and two pMOS transistors MPiL and MPiR.

[0060] The source-drain path of the nMOS transistor (first initial write transistor) MNiL is connected in parallel with the nMOS transistor (first limiting transistor) MNr3 in the replica memory cell RMC. The nMOS transistor MNiL has a gate length shorter than that of the nMOS transistor MNr3 and is configured to allow a sufficient pull-down current to flow. The nMOS transistor MNiL controls the voltage VSL by being turned on during the initialization operation and turned off during the detection operation based on the control signal VSLCT.

[0061] The source-drain path of the pMOS transistor (second initial write transistor) MPiR is connected in parallel with the pMOS transistor (second limiting transistor) MPr4 in the replica memory cell RMC. The pMOS transistor MPiR has a gate length shorter than that of the pMOS transistor MPr4 and is configured to allow a sufficient pull-up current to flow. The pMOS transistor MPiR controls the voltage VDR by turning on during the initialization operation and turning off during the detection operation based on the control signal VDRCT.

[0062] The pMOS transistor MPiL (third initial write transistor) is inserted in a current path between the pMOS transistor MPu3 (first pull-up transistor) in the replica memory cell RMC and the power supply voltage VDD. The pMOS transistor MPiL controls the voltage VDL by being turned off during the initialization operation and turned on during the detection operation based on the control signal VDLCT.

[0063] In this way, by providing the nMOS transistor MNiL and pMOS transistor MPiR, it is possible to eliminate the influence of the current limiting by the nMOS transistor MNr3 and pMOS transistor MPr4. Furthermore, during the initialization operation, by using the pMOS transistor MPiL to cut off the connection path between the non-inverting storage node MEMt and the power supply voltage VDD, it is possible to write the 'L' level to the storage node MEMt more reliably.

[0064] The pMOS transistor MPif is a transistor for initial writing and floating, connected between the inverted replica bit line RBLb and the power supply voltage VDD. The pMOS transistor MPif turns on / off in the same way as the nMOS transistor MNiL, based on the inverted signal of the control signal VSLCT. As a result, the pMOS transistor MPif turns on during the initialization operation, driving the replica bit line RBLb to the 'H' level. On the other hand, the pMOS transistor MPif turns off during the detection operation, putting the replica bit line RBLb into a floating state.

[0065] FIG. 9 is a timing chart showing an example of the operation of the SNM detection circuit SNMD in FIG. 8. As shown in FIG. 9, the SNM detection circuit SNMD performs initialization and detection operations in response to the clock signal CLK, and then returns to standby operation. In response to the rising edge of the clock signal CLK, the clock driver circuit CLKD generates an 'H' pulse signal for activating the replica word line RWL. In addition, the control signal VDRCT is generated by delaying this 'H' pulse signal using the delay circuit DLY1.

[0066] The period of the initialization operation is determined by the period from the rising edge of the replica word line RWL to the rising edge of the control signal VDRCT. That is, the period of the initialization operation is determined based on the delay time of the delay circuit DLY1. The length of the period of the detection operation is determined based on the pulse width of the 'H' pulse signal on the replica word line RWL.

[0067] The control signal VDRCT is at 'L' level during the initialization operation and at 'H' level during the detection operation. Accordingly, the pMOS transistor MPiR supplies the power supply voltage VDD to the pull-up transistor (MPu4) during the initialization operation and cuts off the voltage supply during the detection operation. By cutting off the voltage supply, the data retention capability of the replica memory cell RMC is limited by the pMOS transistor MPr4.

[0068] The control signal VDLCT is at the 'H' level during the period from the rising edge of the replica word line RWL to the rising edge of the control signal VDRCT, i.e., during the initialization operation period. Accordingly, the pMOS transistor MPiL cuts off the supply of the power supply voltage VDD to the pull-up transistor (MPu3) during the initialization operation period, and resumes the voltage supply during the detection operation period.

[0069] The control signal VSLCT is an inverted signal of the control signal VDRCT. Accordingly, the nMOS transistor MNiL supplies the ground voltage VSS to the pull-down transistor (MNd3) during the initialization operation period, and cuts off the voltage supply during the detection operation period. By cutting off the voltage supply, the data retention capability of the replica memory cell RMC is limited by the nMOS transistor MNr3.

[0070] Furthermore, the replica bit line RBLt on the non-inverting side is driven based on the control signal VDRCT. Therefore, the replica bit line RBLt is driven to the 'L' level during the initialization operation, thereby writing the 'L' level to the storage node MEMt. Then, the replica bit line RBLt transitions to the 'H' level when the sensing operation is started, thereby applying a 'H' level disturb to the storage node MEMt to which the 'L' level has been written.

[0071] The inverted replica bit line RBLb is driven by a pMOS transistor MPif that receives a control signal VDRCT. Accordingly, the replica bit line RBLb is driven to the 'H' level during the initialization operation, thereby writing the 'H' level to the storage node MEMb. The replica bit line RBLb is then in a floating state during the detection operation. This determines the logic level of the replica bit line RBLb based on the state of the SNM, which depends on the temperature.

[0072] The latch signal FFLT is generated by performing a logical operation on the control signal VSLCT and a signal obtained by delaying the control signal VSLCT through the delay circuit DLY2. As a result, the latch signal FFLT becomes an 'H' pulse signal that is output after the delay time of the delay circuit DLY2 from the start of the detection operation. At the rising edge of the latch signal FFLT, the latch circuit FF latches the logical data of the inverted replica bit line RBLb and outputs it as a read assist off signal RAOFF.

[0073] <Details of replica memory cells> 10A, 10B, 10C, 10D, and 10E are diagrams showing examples of different components of the replica memory cell RMC in Fig. 4. The replica memory cell RMC is configured using at least one of the components [1]-[5] shown in Fig. 10A-Fig. 10D. The replica memory cell RMC-A shown in Fig. 10A is configured using a transistor having a gate length (L) or gate width (W) larger than that of the transistor constituting the normal memory cell MC.

[0074] In other words, the replica memory cell RMC-A is generally configured using transistors whose gate electrodes have a large horizontal or vertical width in the planar direction. As an example, the gate length (L) or gate width (W) of each transistor constituting the replica memory cell RMC-A may be more than twice that of each transistor constituting the normal memory cell MC. This reduces the influence of manufacturing variations, i.e., random variations, compared to the normal memory cell MC, as described in FIG. 6.

[0075] 10B-10E are elements for reducing the data retention capability, unlike the component [1] for reducing the influence of manufacturing variations shown in Fig. 10A. Therefore, the replica memory cell RMC may be configured by combining the component [1] with any of the components [2]-[5], for example.

[0076] The replica memory cell RMC-B shown in Fig. 10B includes an nMOS transistor (first limiting transistor) MNr3 and a pMOS transistor (second limiting transistor) MPr4, as shown in Fig. 4. The nMOS transistor MNr3 is inserted in the current path between the nMOS transistor (first pull-down transistor) MNd3 and the ground voltage VSS. The pMOS transistor MPr4 is inserted in the current path between the pMOS transistor (second pull-up transistor) MPu4 and the power supply voltage VDD.

[0077] The nMOS transistor MNr3 has a gate length (L) greater than that of the nMOS transistor MNd3. The pMOS transistor MPr4 also has a gate length (L) greater than that of the pMOS transistor MPu4. As an example, the nMOS transistor MNr3 and the pMOS transistor MPr4 may have gate lengths (L) five times or more that of the nMOS transistor MNd3 and the pMOS transistor MPu4, respectively.

[0078] Here, to reduce the data retention capability, it is possible to use a small gate width (W) instead of a large gate length (L). However, in this case, it becomes more susceptible to manufacturing variations. For this reason, it is beneficial to use a large gate length (L). Note that the nMOS transistor MNr3 is always on when the power supply voltage VDD is applied to its gate. The pMOS transistor MPr4 is also always on when the ground voltage VSS is applied to its gate.

[0079] In order to reduce the data retention capability of the replica memory cell RMC, the scheme shown in Figures 10C to 10E may be used in addition to the scheme shown in Figure 10B, i.e., Figure 4. In Figures 10C to 10E, the relative drive capabilities of the transistors constituting the replica memory cell RMC are configured to be different from the relative drive capabilities of the transistors constituting the normal memory cell MC. That is, the replica memory cell RMC is configured so that the balance of drive capabilities is different from that of the normal memory cell MC.

[0080] 10C, first, in an SRAM memory cell, the β ratio is generally defined as an index that simply represents the degree of SNM. The β ratio is given as “W2 / W1,” where “W1” is the gate width of the nMOS transistor (first pass-gate transistor) MNp3, and “W2” is the gate width of the nMOS transistor (first pull-down transistor) MNd3.

[0081] In a normal memory cell MC, the β ratio value is set to, for example, about 1.5 to ensure sufficient SNM. On the other hand, the β ratio value of the replica memory cell RMC-C shown in FIG. 10C is smaller than the β ratio value of the normal memory cell MC. For example, the β ratio value of the replica memory cell RMC-C may be about 1.0. This intentionally reduces the 'L' level data retention capability of the non-inverting storage node MEMt in response to 'H' level disturbance from the non-inverting replica bit line RBLt.

[0082] 10D and 10E, the replica memory cells RMC-D and RMC-E have different drive capabilities for the nMOS transistors MNp3 and MNd3 and the pMOS transistor MPu4 compared to the relative drive capabilities of the normal memory cell MC. That is, the replica memory cells RMC-D and RMC-E are configured to increase the drive capability of the nMOS transistor (first pass-gate transistor) MNp3 and decrease the drive capability of the nMOS transistor (first pull-down transistor) MNd3. Furthermore, the replica memory cells RMC-D and RMC-E are configured to decrease the drive capability of the pMOS transistor (second pull-up transistor) MPu4.

[0083] These driving capabilities are adjusted by the gate width (W) in Fig. 10D, and by the gate length (L) in Fig. 10E. That is, in Fig. 10D, the gate width (W) of nMOS transistor MNp3 is adjusted to be large, the gate width (W) of nMOS transistor MNd3 is adjusted to be small, and the gate width (W) of pMOS transistor MPu4 is adjusted to be small. In Fig. 10E, the gate length (L) of nMOS transistor MNp3 is adjusted to be small, the gate length (L) of nMOS transistor MNd3 is adjusted to be large, and the gate length (L) of pMOS transistor MPu4 is adjusted to be large.

[0084] With such a configuration, the data retention capabilities of the 'L' level in the forward-side memory node MEMt and the 'H' level in the reverse-side memory node MEMb with respect to the 'H' level disturbance from the replica bit line RBLt on the forward side can be intentionally reduced. As described above, when the size of the transistor is reduced, it is more likely to be affected by manufacturing variations. From this perspective, it is beneficial to combine component [1] with component [2] or component [3]. In this case, for example, further fine-tuning may be performed by further combining component [4] or component [5].

[0085] <Arrangement of SNM detection circuit> FIG. 11 is a schematic diagram showing an example of the arrangement configuration of the SNM detection circuit SNMD in FIG. 2. The volatile memory RAM shown in FIG. 11, specifically the SRAM, is composed of a hard macro. And in this example, a plurality of SRAMs composed of hard macros are arranged in the arrangement area AR_HM of the hard macro.

[0086] As described in FIG. 2, each SRAM includes a memory array MARY, a word line control circuit WLC, a read / write circuit RWC, and a memory control circuit MCTL. The word line control circuit WLC has a word decoder circuit WDEC, a word driver circuit WD, and a read assist circuit RAC. The read assist circuit RAC supplies the word line voltage Vwl to the word driver circuit WD.

[0087] <000034​​​​Here, each SRAM configured by a hard macro has a switching terminal PN that switches the read assist circuit RAC on / off, i.e., enabled / disabled. The SNM detection circuit SNMD is placed outside the hard macro placement area AR_HM and is commonly connected to the switching terminal PN of each SRAM via signal wiring LN. Generally, hard macros having such switching terminals PN are widely used. In the method shown in FIG. 11, it is sufficient to newly provide an SNM detection circuit SNMD and wire it to the switching terminal PN of the existing hard macro.

[0089] In this way, by providing one SNM detection circuit SNMD in common for multiple hard macros, the overhead of the circuit area can be reduced. Note that the number of SNM detection circuits SNMD is not limited to one, but multiple circuits may be provided, for example, taking into account the temperature distribution within the chip. In this case, for example, multiple placement areas AR_HM such as those shown in FIG. 11 are provided, and an SNM detection circuit SNMD is provided near each of the multiple placement areas AR_HM.

[0090] FIG. 12 is a schematic diagram showing another example of the layout and configuration of the SNM detection circuit SNMD in FIG. 2. In FIG. 12, unlike the case of FIG. 11, the hard macro constituting the SRAM has the SNM detection circuit SNMD built in. In this example, the SNM detection circuit SNMD is part of the memory control circuit MCTL. When using such a method, for example, when placing and wiring the semiconductor device DEV as shown in FIG. 1, it is not necessary to separately implement the SNM detection circuit SNMD; it is sufficient to simply implement the hard macro. This makes it possible to simplify the design of the semiconductor device DEV.

[0091] <Major Effects of the First Embodiment> As described above, in the first embodiment, a replica memory cell configured to have a low data retention ability is used to pseudo-detect the static noise margin (SNM) of a normal memory cell, and an SNM detection circuit is provided to switch the enable / disable of the read assist circuit according to the detection result. Thereby, typically, in a semiconductor device including an SRAM, an increase in access time associated with read assist can be efficiently suppressed.

[0092] More specifically, by using a replica memory cell, compared with the method shown in Non-Patent Document 2, SNM can be detected in a small area and can be detected in a short time, for example, within a clock cycle. By detecting SNM in this way, particularly at low temperatures, the read assist circuit can be disabled, and a decrease in the memory cell current associated with read assist, and thus an increase in access time, can be suppressed.

[0093] (Second Embodiment) <Details of SNM Detection Circuit> FIG. 13 is a circuit diagram showing a more detailed configuration example of the SNM detection circuit SNMD shown in FIG. 4 in a semiconductor device according to the second embodiment. FIG. 14 is a timing chart showing a schematic operation example of the SNM detection circuit SNMD in FIG. 13. The SNM detection circuit SNMD shown in FIG. 13 further includes anti-chattering circuits CPCl and CPCh in addition to the same configuration as in the case of FIG. 8.

[0094] The anti-chattering circuit CPCl includes two nMOS transistors MNc1 and MNc2. The source-drain paths of the two nMOS transistors MNc1 and MNc2 are connected in series, and the gates are commonly connected. Also, the source-drain paths of the nMOS transistors MNc1 and MNc2 are connected in parallel with an nMOS transistor (first limiting transistor) MNr3 in the replica memory cell RMC.

[0095] Here, each of the nMOS transistors MNc1 and MNc2 has a gate length (L) greater than that of the nMOS transistor (first pull-down transistor) MNd3. The gate length (L) may be, for example, the same as that of the nMOS transistor MNr3. The nMOS transistors MNc1 and MNc2 are controlled to be turned on or off by a read assist off signal RAOFF.

[0096] On the other hand, the chattering prevention circuit CPCh includes two pMOS transistors MPc1 and MPc2. The source-drain paths of the two pMOS transistors MPc1 and MPc2 are connected in series, and their gates are commonly connected. The source-drain paths of the pMOS transistors MPc1 and MPc2 are also connected in parallel with the pMOS transistor (second limiting transistor) MPr4 in the replica memory cell RMC.

[0097] Here, each of the pMOS transistors MPc1 and MPc2 has a gate length (L) greater than that of the pMOS transistor (second pull-up transistor) MPu4. The gate length (L) may be, for example, the same as that of the pMOS transistor MPr4. The pMOS transistors MPc1 and MPc2 are turned on / off by an inverted signal of the read assist off signal RAOFF.

[0098] Fig. 14 shows an example of how the read assist-off signal RAOFF changes depending on the temperature Tj. Also shown here are a case where the chattering prevention circuits CPCh and CPCl are provided, i.e., a case where the configuration shown in Fig. 13 is used, and a case where the chattering prevention circuits CPCh and CPCl are not provided, i.e., a case where the configuration shown in Fig. 8 is used.

[0099] First, when using the configuration shown in FIG. 8, for example, the logic level of the read assist off signal RAOFF may become unstable during a period T1 when the temperature Tj gradually decreases or during a period T2 when the temperature Tj gradually increases. That is, the temperature Tj usually does not change suddenly. Therefore, the detection result of the SNM may change successively between a fail state and a pass state for each clock cycle. As a result, chattering may occur in the read assist off signal RAOFF.

[0100] 13, in this example, a clock cycle occurs in which a pass state is detected instead of a fail state as the temperature Tj drops during period T1, i.e., a clock cycle occurs in which the read assist-off signal RAOFF transitions from the 'L' level to the 'H' level. This enables both of the chattering prevention circuits CPCl and CPCh. As a result, the chattering prevention circuits CPCl and CPCh increase the data retention capability of the replica memory cells RMC by a predetermined amount.

[0101] Specifically, the chattering prevention circuits CPCl and CPCh increase the data retention capability of the storage node MEMt at a low level and the data retention capability of the storage node MEMb at a high level by the amount of the driving capability of the internal transistors. By increasing the data retention capability in this manner, the SNM becomes more likely to enter a pass state. As a result, once the read assist off signal RAOFF transitions from a low level to a high level, it becomes more difficult for it to transition back to a low level. As a result, chattering during the period T1 can be prevented.

[0102] This state of enhanced data retention capability is maintained until a clock cycle occurs in which a fail state is detected thereafter. In this example, during period T2, as the temperature Tj rises, a clock cycle occurs in which a fail state is detected instead of a pass state, i.e., a clock cycle in which the read assist off signal RAOFF transitions from high to low.

[0103] When the read assist off signal RAOFF transitions from the 'H' level to the 'L' level, the anti-chattering circuits CPCl and CPCh are both disabled. As a result, the data retention ability in the replica memory cell RMC is reduced to its original state. Consequently, the SNM becomes more likely to enter a fail state. Thus, once the read assist off signal RAOFF transitions from the 'H' level to the 'L' level, it becomes difficult to transition back to the 'H' level. As a result, chattering during period T2 can be prevented.

[0104] Note that, as shown in FIG. 14, the SNM detection circuit SNMD can detect the SNM for each clock cycle based on the input clock signal CLK and determine the logic level of the read assist off signal RAOFF according to the detection result. However, the temperature Tj usually does not change rapidly. Therefore, the SNM detection circuit SNMD may be configured to operate at a longer interval. That is, the SNM detection circuit SNMD may operate, for example, for every plurality of clock cycles, or may divide the clock signal CLK itself and input it.

[0105] <Main effects according to the second embodiment> As described above, in the second embodiment, by providing the anti-chattering circuit, the data retention ability of the replica memory cell has hysteresis characteristics. As a result, in addition to the various effects described in the first embodiment, chattering that may occur when switching the enable / disable of the read assist circuit can be prevented. By preventing chattering, for example, excessive operating current associated with frequent enable / disable switching can be suppressed.

[0106] (Third embodiment) <Details of the SNM detection circuit> 15 is a circuit diagram showing a detailed configuration example of the SNM detection circuit SNMD in a semiconductor device according to the third embodiment, different from that shown in FIG. 8. FIG. 16 is a truth table showing an operation example of the majority decision circuit MJDC in FIG. 15. The SNM detection circuit SNMD shown in FIG. 15 differs from the configuration example shown in FIG. 8 in the following three points. The first difference is that multiple, more specifically, an odd number of dummy memory cells MCD[1]-MCD[3] are provided, which share the replica word line RWL and the non-inverting replica bit line RBLt.

[0107] In this example, the limiting transistors, nMOS transistor MNr3 and pMOS transistor MPr4, are also shared by multiple dummy memory cells MCD using the component [2] shown in Figure 10B. Therefore, although there are multiple dummy memory cells MCD, based on the component [3] shown in Figure 10C, for example, multiple replica memory cells are actually provided.

[0108] The second difference is that multiple inverted replica bit lines RBLb[1]-RBLb[3] are provided, each connected to multiple dummy memory cells MCD[1]-MCD[3], i.e., multiple replica memory cells. Accordingly, the initialization circuit INITC also includes multiple pMOS transistors MPif1-MPif3, each connected to the multiple replica bit lines RBLb[1]-RBLb[3].

[0109] The third difference is the provision of a majority decision circuit MJDC connected to the multiple replica bit lines RBLb[1]-RBLb[3]. The majority decision circuit MJDC inputs the logic levels of the multiple replica bit lines RBLb[1]-RBLb[3], and thus multiple detection results using the multiple replica memory cells, and calculates a majority decision of the multiple detection results. The majority decision circuit MJDC then outputs the majority decision calculation result to the latch circuit FF.

[0110] The majority decision circuit MJDC can be configured using, for example, a plurality of NAND gates, as shown in Fig. 15. As shown in Fig. 16, the majority decision circuit MJDC outputs a '0' level as the output value VA when the logic levels of the three replica bit lines RBLb[1]-RBLb[3] contain many '0' levels ('L' levels). On the other hand, the majority decision circuit MJDC outputs a '1' level as the output value VA when the logic levels of the three replica bit lines RBLb[1]-RBLb[3] contain many '1' levels ('H' levels).

[0111] <Major Effects of the Third Embodiment> As described above, by using the third embodiment, in addition to the various effects described in the first embodiment, the influence of manufacturing variations in replica memory cells can be further reduced. Specifically, by using the component [1] described in FIG. 10A, the influence of manufacturing variations, for example, variations in the detection accuracy of SNMs, can be reduced. In addition, by applying majority logic as shown in FIGS. 15 and 16, although the circuit area may increase, the influence of manufacturing variations is averaged by multiple replica memory cells, and the variation in the detection accuracy of SNMs can be further reduced.

[0112] (Fourth embodiment) <Application example to Light Assist> Fig. 17 is a schematic diagram showing an example of application of the SNM detection circuit SNMD to write assist in a semiconductor device according to a fourth embodiment. Fig. 18 is a diagram showing an example of operation of the write assist circuit WAC in Fig. 17. As in Fig. 12 etc., Fig. 17 shows a volatile memory RAM, more specifically an SRAM, configured using hard macros. The memory control circuit MCTL includes an SNM detection circuit SNMD. The word line control circuit WLC includes a read assist circuit RAC.

[0113] In this example, the read / write circuit RWC includes a column selection circuit CSEL, a sense amplifier circuit SA, a write buffer circuit WBF, and a write assist circuit WAC. The column selection circuit CSEL selects one of a plurality of bit line pairs (BLt, BLb). The sense amplifier circuit SA differentially amplifies the signals of the selected bit line pair (BLt, BLb) during a read access. The write buffer circuit WBF drives the selected bit line pair (BLt, BLb) during a write access.

[0114] During a write access, the write buffer circuit WBF drives one of the bit line pair (BLt, BLb) to a 'H' level, for example, the level of the power supply voltage VDD, and the other to a 'L' level, for example, the level of the ground voltage VSS. The write assist circuit WAC is configured to be switchable between on and off, i.e., enabled and disabled, based on a write assist on signal WAON. When the write assist circuit WAC is enabled, for example, it sets the 'L' level voltage level of the write buffer circuit WBF to a voltage level lower than the ground voltage VSS.

[0115] Here, the quality of SNM and the quality of write characteristics are usually in a contradictory relationship. For example, as shown in FIG. 20, SNM is worst under high temperature and FS conditions. On the other hand, the write characteristics, although not shown, are worst under low temperature and SF characteristics. Based on this relationship, the read assist off signal RAOFF can also be used as the write assist on signal WAON.

[0116] That is, as shown in FIG. 18, when the read assist off signal RAOFF is at '0' level ('L' level), the write assist on signal WAON is also at '0' level. As a result, the read assist circuit RAC is enabled. On the other hand, the write assist circuit WAC is disabled or controlled to a weak assist amount. Also, when the read assist off signal RAOFF is at '1' level ('H' level), the write assist on signal WAON is also at '1' level. As a result, the read assist circuit RAC is disabled. On the other hand, the write assist circuit WAC is enabled or controlled to a strong assist amount.

[0117] <Major Effects of the Fourth Embodiment> As described above, by using the fourth embodiment, in addition to the various effects described in the first embodiment, it is possible to appropriately control the enable / disable of not only the read assist circuit but also the write assist circuit using a common SNM detection circuit. By controlling the enable / disable of the write assist circuit, unnecessary operation of the write assist circuit can be omitted, and for example, it is possible to reduce the operating current, etc.

[0118] The invention made by the inventor has been specifically described above based on the embodiments, but the present invention is not limited to the above embodiments and can be modified in various ways without departing from the spirit of the invention. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and the present invention is not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations. [Explanation of symbols]

[0119] AR_HM Hard macro placement area BLt,BLb bit lines CLK Clock signal CPC Anti-chattering circuit DEV Semiconductor device FF latch circuit INITC initialization circuit MARY Memory Array MC memory cell MJDC Majority Decision Circuit MN nMOS transistor MP pMOS transistor PN switching terminal RAC lead assist circuit RAM Volatile memory (SRAM) RAOFF Lead assist off signal RBLt, RBLb replica bit lines RMC replica memory cell RWL Replica Word Line SEQCT Sequence control circuit SNMD Static Noise Margin (SNM) detection circuit VDD power supply voltage VSS Ground voltage Vwl Word line voltage WL Word Line

Claims

1. SRAM (Static Random Access Memory), a detection circuit for detecting a static noise margin in the SRAM; Equipped with The SRAM is a memory array having word lines, bit line pairs, and memory cells connected to the word lines and the bit line pairs; a read assist circuit configured to be switchable between enabled and disabled, and which, when enabled, reduces a word line voltage applied to the word line in order to ensure a static noise margin of the memory cell; and the detection circuit has replica memory cells configured to have a lower data retention capability than the memory cells, and is configured to use the replica memory cells to artificially detect the static noise margin of the memory cells, and switch between enabling and disabling the read assist circuit according to the detection result. Semiconductor device.

2. 2. The semiconductor device according to claim 1, The replica memory cell a replica word line; a complementary bit line pair including a first replica bit line and a second replica bit line; a first storage node and a second storage node that are complementary storage nodes; a first pull-up transistor and a second pull-up transistor for pulling up the first storage node and the second storage node to a high potential power supply voltage, respectively; a first pull-down transistor and a second pull-down transistor for pulling down the first storage node and the second storage node to a low potential power supply voltage, respectively; a first pass gate transistor and a second pass gate transistor that connect the first storage node and the second storage node to the first replica bit line and the second replica bit line, respectively, when the replica word line is activated; Equipped with Semiconductor device.

3. 3. The semiconductor device according to claim 2, The replica memory cell further includes: a first limiting transistor inserted in a current path between the first pull-down transistor and the low potential side power supply voltage; a second limiting transistor inserted in a current path between the second pull-up transistor and the high-potential power supply voltage; Equipped with the first limiting transistor has a gate length greater than that of the first pull-down transistor; the second limiting transistor has a gate length greater than that of the second pull-up transistor; Semiconductor device.

4. 4. The semiconductor device according to claim 3, The replica memory cell is configured using a transistor having a gate length or a gate width larger than that of a transistor configuring the memory cell. Semiconductor device.

5. 4. The semiconductor device according to claim 3, The detection circuit a sequence control circuit that performs an initialization operation and a detection operation subsequent to the initialization operation using the replica memory cells; a latch circuit for holding a detection result using the replica memory cell; Equipped with The sequence control circuit In the initialization operation, the replica word line is activated, and an 'L' level and an 'H' level are written to the first storage node and the second storage node, respectively; In the detection operation, while the replica word line is activated, an 'H' level is applied to the first replica bit line, and the logic level of the second replica bit line is latched in the latch circuit, thereby detecting whether the second replica bit line is in a pass state where it can maintain the 'H' level or in a fail state where it is inverted to an 'L' level, and disabling the read assist circuit in the pass state, and enabling the read assist circuit in the fail state. Semiconductor device.

6. 6. The semiconductor device according to claim 5, the sequence control circuit performs the initialization operation and the detection operation for each clock cycle based on an input clock signal; Semiconductor device.

7. 7. The semiconductor device according to claim 6, the detection circuit further includes a chattering prevention circuit for, when a clock cycle occurs in which the pass state is detected instead of the fail state, increasing the data retention capability of the replica memory cells by a predetermined amount until a clock cycle occurs in which the fail state is detected thereafter. Semiconductor device.

8. 6. The semiconductor device according to claim 5, the detection circuit further includes an initialization circuit used in the initialization operation; The initialization circuit a first initial writing transistor connected in parallel with the first limiting transistor, having a gate length smaller than that of the first limiting transistor, being turned on during the initialization operation and turned off during the detection operation; a second initial writing transistor connected in parallel with the second limiting transistor, having a gate length smaller than that of the second limiting transistor, being turned on during the initialization operation and turned off during the detection operation; having Semiconductor device.

9. 9. The semiconductor device according to claim 8, the initialization circuit further includes a third initial writing transistor that is inserted in a current path between the first pull-up transistor and the high-potential power supply voltage, that is turned off during the initialization operation, and that is turned on during the detection operation. Semiconductor device.

10. 3. The semiconductor device according to claim 2, The replica memory cell has a lower data retention capability than the memory cell, and therefore the relative driving capability between the transistors constituting the replica memory cell is configured to be different from the relative driving capability between the transistors constituting the memory cell. Semiconductor device.

11. 11. The semiconductor device according to claim 10, a gate width of the first pass gate transistor is "W1" and a gate width of the first pull-down transistor is "W2", and a β ratio value given by "W2 / W1" is smaller than a β ratio value in the memory cell; Semiconductor device.

12. 11. The semiconductor device according to claim 10, the replica memory cell is configured to increase the drive capability of the first pass-gate transistor, decrease the drive capability of the first pull-down transistor, and decrease the drive capability of the second pull-up transistor compared to the relative drive capabilities of the memory cell; Semiconductor device.

13. 2. The semiconductor device according to claim 1, the SRAM is configured by a hard macro having a switching terminal for switching between enable and disable of the read assist circuit, the detection circuit is arranged outside the placement area of ​​the hard macro and is connected to the switching terminal; Semiconductor device.

14. 2. The semiconductor device according to claim 1, The detection circuit a plurality of the replica memory cells; a majority decision circuit that calculates a majority decision of a plurality of detection results using the plurality of replica memory cells; Equipped with Semiconductor device.

15. SRAM (Static Random Access Memory), a detection circuit for detecting a static noise margin in the SRAM; Equipped with The SRAM is a memory array having word lines, bit line pairs, and memory cells connected to the word lines and the bit line pairs; a read assist circuit configured to be switchable between enabled and disabled, and which, when enabled, reduces a word line voltage applied to the word line in order to ensure a static noise margin of the memory cell; and the detection circuit has a replica memory cell, and is configured to use the replica memory cell to pseudo-detect a static noise margin of the memory cell, and switch between enabled and disabled states of the read assist circuit according to a detection result; The replica memory cell is configured to have a lower data retention capability than the memory cell, and is configured using a transistor having a gate length or a gate width larger than that of a transistor constituting the memory cell. Semiconductor device.

16. 16. The semiconductor device according to claim 15, The replica memory cell a replica word line; a complementary bit line pair including a first replica bit line and a second replica bit line; a first storage node and a second storage node that are complementary storage nodes; a first pull-up transistor and a second pull-up transistor for pulling up the first storage node and the second storage node to a high potential power supply voltage, respectively; a first pull-down transistor and a second pull-down transistor for pulling down the first storage node and the second storage node to a low potential power supply voltage, respectively; a first pass gate transistor and a second pass gate transistor that connect the first storage node and the second storage node to the first replica bit line and the second replica bit line, respectively, when the replica word line is activated; Equipped with Semiconductor device.

17. 17. The semiconductor device according to claim 16, The replica memory cell further includes: a first limiting transistor inserted in a current path between the first pull-down transistor and the low potential side power supply voltage; a second limiting transistor inserted in a current path between the second pull-up transistor and the high-potential power supply voltage; Equipped with the first limiting transistor has a gate length greater than that of the first pull-down transistor; the second limiting transistor has a gate length greater than that of the second pull-up transistor; Semiconductor device.

18. 17. The semiconductor device according to claim 16, The replica memory cell has a lower data retention capability than the memory cell, and therefore the relative driving capability between the transistors constituting the replica memory cell is configured to be different from the relative driving capability between the transistors constituting the memory cell. Semiconductor device.

19. 19. The semiconductor device according to claim 18, a gate width of the first pass gate transistor is "W1" and a gate width of the first pull-down transistor is "W2", and a β ratio value given by "W2 / W1" is smaller than a β ratio value in the memory cell; Semiconductor device.

20. 19. The semiconductor device according to claim 18, the replica memory cell is configured to increase the drive capability of the first pass-gate transistor, decrease the drive capability of the first pull-down transistor, and decrease the drive capability of the second pull-up transistor compared to the relative drive capabilities of the memory cell; Semiconductor device.

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