Semiconductor device

Abstract

To provide a semiconductor device having a small characteristic variation due to an operating temperature.SOLUTION: In a semiconductor device in which odd-numbered stages of inverter circuits 810 are connected in a ring, each of the inverter circuits includes a first transistor and a second transistor, a gate of the first transistor is electrically connected to one of a source and a drain of the first transistor, a high power supply potential is supplied to the one of the source and the drain of the first transistor, and the other of the source and the drain of the first transistor is electrically connected to an output terminal out. A gate of the second transistor is electrically connected to the input terminal (in), one of a source and a drain of the second transistor is electrically connected to the output terminal (out), and a low power supply potential is supplied to the other of the source and the drain of the second transistor. The first transistor and the second transistor include an oxide semiconductor in a semiconductor layer. The first transistor and the second transistor each include a back gate.SELECTED DRAWING: Figure 26

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a transistor, a semiconductor device, and an electronic device. One embodiment relates to a method for manufacturing a semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field relates to an article, a method, or a manufacturing method. is a process, machine, manufacture, or composition of matter. This concerns the

[0003] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and memory devices. The present invention is also applicable to display devices (liquid crystal display devices, light-emitting display devices, etc.), Projection devices, lighting devices, electro-optical devices, power storage devices, storage devices, imaging devices, electronic devices, etc. Therefore, the display device, the projection device, the lighting device, etc. may include a semiconductor element or a semiconductor circuit. semiconductor devices, electro-optical devices, power storage devices, memory devices, imaging devices, and electronic equipment. It is sometimes called. [Background technology]

[0004] A technology for constructing transistors using semiconductor thin films formed on substrates with insulating surfaces is The transistor is being used in integrated circuits (ICs) and image display devices (simply called display devices). It is widely applied to electronic devices such as transistors. Silicon-based semiconductor materials are widely known as semiconductor thin films, but other materials include oxides. Semiconductors are attracting attention.

[0005] In oxide semiconductors, there are c-axis alignins (CAAC) that are neither single crystal nor amorphous. ned crystalline) structure and nc (nanocrystalline) The structure has been found (see Non-Patent Documents 1 and 2).

[0006] In Non-Patent Documents 1 and 2, a transistor is formed using an oxide semiconductor having a CAAC structure. Techniques for fabricating transistors are disclosed. [Prior art documents] [Non-patent literature]

[0007] [Non-Patent Document 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, p.183-186 [Non-patent document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, p.04ED18-1-04ED18-10 Summary of the Invention [Problem to be solved by the invention]

[0008] An object of one embodiment of the present invention is to provide a semiconductor device with little variation in transistor characteristics. Another embodiment of the present invention is to provide a semiconductor device with a large on-state current. Another object of the present invention is to provide a semiconductor device having favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of the present invention is to provide a semiconductor device having high reliability. Another object of the present invention is to provide a semiconductor device having low power consumption. Another object of the present invention is to provide a semiconductor device having an operating temperature of It is an object of the present invention to provide a semiconductor device that operates stably even when the temperature changes.

[0009] The description of these problems does not preclude the existence of other problems. It is not necessary for the present invention to solve all of these problems. The above will be made clear from the description, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0010] One embodiment of the present invention is a semiconductor device in which an odd number of inverter circuits are connected in a ring, The output of one inverter circuit is electrically connected to the input of the next inverter circuit. The input of one inverter circuit is electrically connected to the output of the previous inverter circuit. The inverter circuit has a first transistor and a second transistor, and the gate of the first transistor The gate is electrically connected to one of the source and the drain of the first transistor. A high power supply potential is supplied to either the source or drain of the first transistor. The other of the source and drain is electrically connected to the output terminal out. The gate of the second transistor is electrically connected to the input terminal in, and the source or drain of the second transistor is One of the terminals is electrically connected to the output terminal out, and the other terminal is the source or drain of the second transistor. The other of the first and second transistors is supplied with a low power supply potential. The first transistor and the second transistor each include an oxide semiconductor. It has a gate.

[0011] Another aspect of the present invention is a semiconductor device including an n-stage (n is an odd number of 3 or more) inverter circuit. The output of the inverter circuit in the i-th stage (i is a natural number between 2 and n-1) is the i+1th stage. The output of the (i-1)th inverter circuit is electrically connected to the input of the (i-1)th inverter circuit. The input of the i-th inverter circuit is electrically connected, and the output of the n-th inverter circuit is The input of the first stage inverter circuit is electrically connected to the input of each of the n stages of inverter circuits. It has a first transistor and a second transistor, and the gate of the first transistor is , electrically connected to one of the source and drain of the first transistor, One of the source and drain of the first transistor is electrically connected to the first terminal. The other of the source and the drain is electrically connected to the output terminal, and the gate of the second transistor The first transistor is electrically connected to the input terminal, and one of the source and drain of the second transistor is connected to the output terminal. the other of the source and drain of the second transistor is electrically connected to the second terminal. and the first transistor has a first back gate and the second transistor is electrically connected to the has a second back gate, and the first transistor and the second transistor are The semiconductor device includes an oxide semiconductor in a semiconductor layer.

[0012] The oxide semiconductor preferably contains at least one of In and Zn. The semiconductor preferably has a CAAC structure.

[0013] The channel width of the second transistor is preferably larger than the channel width of the first transistor. I wish.

[0014] The semiconductor device has a function of adjusting the voltage supplied to the second back gate according to the operating temperature. It is preferred that the compound has the following structure: [Effects of the Invention]

[0015] According to one embodiment of the present invention, a semiconductor device with little variation in transistor characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with large on-state current can be provided. According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. In this manner, a semiconductor device that can be miniaturized or highly integrated can be provided. In this manner, a highly reliable semiconductor device can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device with low power consumption can be provided even when the operating temperature changes. A semiconductor device that operates stably can be provided.

[0016] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these may be included in the description, This becomes clear from the description, drawings, claims, etc. From any description, it is possible to extract effects other than these. [Brief explanation of the drawings]

[0017] [Figure 1] Fig. 1A is a top view of the semiconductor device, and Fig. 1B to Fig. 1D are cross-sectional views of the semiconductor device. [Figure 2] FIG. 2 is a cross-sectional view of the semiconductor device. [Figure 3] 3A and 3B are perspective views of the semiconductor device. [Figure 4] 4A to 4D are diagrams illustrating a method for manufacturing a semiconductor device. [Figure 5] 5A to 5D are diagrams illustrating a method for manufacturing a semiconductor device. [Figure 6] 6A to 6D are diagrams illustrating a method for manufacturing a semiconductor device. [Figure 7] 7A to 7D are diagrams illustrating a method for manufacturing a semiconductor device. [Figure 8] 8A to 8D are diagrams illustrating a method for manufacturing a semiconductor device. [Figure 9] 9A to 9D are diagrams illustrating a method for manufacturing a semiconductor device. [Figure 10] 10A to 10D are diagrams illustrating a method for manufacturing a semiconductor device. [Figure 11] 11A to 11D are diagrams illustrating a method for manufacturing a semiconductor device. [Figure 12] 12A is a top view of the semiconductor device, and FIGS. 12B to 12D are cross-sectional views of the semiconductor device. [Figure 13] 13A and 13B are cross-sectional views of the semiconductor device. [Figure 14] FIG. 14 is a cross-sectional view of the semiconductor device. [Figure 15] FIG. 15 is a cross-sectional view of the semiconductor device. [Figure 16] Fig. 16A is a block diagram showing an example of the configuration of a storage device, and Fig. 16B is a perspective view of the storage device. [Figure 17] 17A to 17H are circuit diagrams showing examples of the configuration of a memory cell. [Figure 18] 18A to 18D are diagrams showing circuit symbols for transistors. [Figure 19] 19A and 19B are schematic diagrams of a semiconductor device. [Figure 20] 20A to 20E are schematic diagrams of a storage device. [Figure 21] 21A to 21H are diagrams showing electronic devices. [Figure 22] 22A and 22B are cross-sectional TEM photographs of the transistor. [Figure 23] FIG. 23 shows the measurement results of the Id-Vg characteristics of the transistor. [Figure 24] 24A and 24B show the results of measuring the gate and drain breakdown voltages of the transistors. [Figure 25] Fig. 25A is a circuit diagram of an inverter circuit, and Fig. 25B shows the measurement results of the DC characteristics of the inverter circuit. [Figure 26] Figure 26A is a circuit diagram of the ring oscillator, and Figure 26B is a die photograph of the ring oscillator. [Figure 27] FIG. 27 shows the output waveform of the ring oscillator. [Figure 28] FIG. 28 is a diagram showing the temperature dependency of the delay time. DETAILED DESCRIPTION OF THE INVENTION

[0018] Hereinafter, embodiments will be described with reference to the drawings. It is possible to implement the invention in various ways without departing from the spirit and scope of the invention. It will be readily apparent to those skilled in the art that various changes can be made in the mode and details. However, the present invention should not be construed as being limited to the description of the following embodiments.

[0019] Also, in the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The figures are merely schematic representations of the various elements, and are not limited to the shapes or values ​​shown in the drawings. During the manufacturing process, layers and resist masks may be unintentionally damaged by processes such as etching. However, to make it easier to understand, this may not be reflected in the diagram. In the drawings, the same parts or parts having similar functions are designated by the same reference numerals in different drawings. In addition, when referring to similar functions, In some cases, the hatch patterns are the same and no particular symbols are assigned.

[0020] In addition, in particular, top views (also called "plan views") and perspective views are used to make the invention easier to understand. In order to avoid this, some components may be omitted. may be omitted.

[0021] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring." Furthermore, the terms "electrode" and "wiring" are used interchangeably to refer to the plural "electrodes" and "wirings." This also includes cases where the "line" is formed as a single unit.

[0022] In this specification, a "terminal" in an electric circuit refers to an input or output of a current, It refers to the part where pressure is input or output, or where a signal is received or transmitted. In some cases, a part of the wiring or electrode functions as a terminal.

[0023] In addition, in this specification, ordinal numbers such as "1st" and "2nd" are used for convenience and do not indicate the order of steps. Therefore, for example, "first" should not be replaced with "second" or " "third" and so on. The ordinal numbers used to identify an aspect of the present invention may not match the ordinal numbers used to identify an aspect of the present invention. .

[0024] In addition, in this specification and the like, terms indicating arrangement such as "above" and "below" refer to the relationship between components. It is used for convenience to explain the positional relationship of the components, and the positional relationship of the components is directly above or It is not limited to being directly under and in direct contact with the insulating layer A. If the expression is "electrode B", electrode B does not need to be formed directly on insulating layer A, This does not exclude the case where other components are included between the insulating layer A and the electrode B. The positional relationship changes depending on the direction in which each component is depicted. The student is not limited to the words and phrases explained in the book, but can use appropriate phrases depending on the situation.

[0025] Furthermore, for example, even if it is explicitly stated in this specification that X and Y are connected, When X and Y are electrically connected, there is a difference between when X and Y are functionally connected. The case where X and Y are directly connected and the case where X and Y are directly connected are disclosed in the present specification. Therefore, a predetermined connection relationship, for example, a connection relationship shown in a diagram or text, Without being limited thereto, connections other than those shown in the drawings or text may also be disclosed in the drawings or text. Here, X and Y are the objects (e.g., devices, elements, circuits, wiring, electrodes, terminal, conductive film, layer, etc.

[0026] In this specification, a transistor includes a gate, a drain, and a source. It is an element with at least three terminals. And, the drain (drain terminal, drain Between the source (source terminal, source region or drain electrode) and the source (source terminal, source region or source electrode) It has a region where a channel is formed (hereinafter also referred to as a channel forming region), A current can be passed between the source and drain through the hole formation region. In this specification and the like, the channel formation region refers to a region through which current mainly flows.

[0027] The source and drain functions may differ depending on the type of transistor used, or the circuit operation. This may be reversed if the direction of the current changes during operation. In some documents, the terms source and drain may be used interchangeably. .

[0028] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. When the transistor is in the on state, the gate electrode overlaps with the semiconductor (the part where current flows). The source (source region or source electrode) and drain This refers to the distance between the drain (drain region or drain electrode) of one transistor. In a stator, the channel length does not necessarily have the same value in all regions. The channel length of a transistor may not be determined to a single value. The channel length is any one value, maximum value, minimum value or The average value is used.

[0029] The channel width is, for example, the width of the semiconductor (or transistor) in a top view of the transistor. The area where the gate electrode overlaps with the semiconductor (the part of the semiconductor where current flows when the semiconductor is on). , or the channel shape in the vertical direction based on the channel length direction in the channel formation region The length of the region where the channel width is the same as that ... In other words, the channel width of a transistor does not necessarily have the same value. Therefore, in this specification, the channel width is defined as the width in the channel forming region. The value to be used is either one of the values, the maximum value, the minimum value or the average value.

[0030] In this specification and the like, depending on the structure of the transistor, the channel may not actually be formed. The channel width in the region where the transistor is located (hereinafter also referred to as the "effective channel width") is The channel width shown in a top view of the capacitor (hereinafter also referred to as the "apparent channel width") For example, if the gate electrode covers the side of the semiconductor, the effective channel In some cases, the channel width becomes larger than the apparent channel width, and the effect of this becomes unnegligible. For example, in a miniaturized transistor in which the gate electrode covers the side of the semiconductor, In this case, the ratio of the channel formation region formed on the surface may become larger. The effective channel width is larger than the channel width of the semiconductor device.

[0031] In such a case, it may be difficult to estimate the effective channel width through actual measurements. For example, to estimate the effective channel width from the design value, the shape of the semiconductor must be known. Therefore, if the shape of the semiconductor is not known exactly, it is difficult to estimate the effective chip size. Channel width is difficult to measure accurately.

[0032] In this specification, when simply referring to the channel width, it may refer to the apparent channel width. In this specification, when simply referring to the channel width, it means the effective channel width. It may refer to the channel length, channel width, effective channel width, apparent channel The channel width and other parameters can be determined by analyzing cross-sectional TEM images. Cut.

[0033] The impurities in a semiconductor refer to, for example, substances other than the main components that make up the semiconductor. For example, the concentration Elements with a concentration of less than 0.1 atomic percent can be considered impurities. This may result in an increase in the defect level density of the conductor or a decrease in crystallinity. When the semiconductor is an oxide semiconductor, examples of impurities that change the characteristics of the semiconductor include: Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, oxide semiconductors There are transition metals other than the main component, such as hydrogen, lithium, sodium, silicon, and phosphite. These include urin, phosphorus, carbon, and nitrogen. Water can also act as an impurity. For example, impurities can cause oxygen vacancies (V O :oxygen vac In some cases, a cyst (also called an ancy) may form.

[0034] In this specification and the like, silicon oxynitride refers to a material having a composition containing more oxygen than nitrogen. Silicon nitride oxide is a material that contains more nitrogen than oxygen. It has a high content of elements.

[0035] In this specification, the term "insulator" may be replaced with "insulating film" or "insulating layer." The term "conductor" can also be replaced with "conductive film" or "conductive layer." The term "semiconductor" can be replaced with "semiconductor film" or "semiconductor layer." Cut.

[0036] In addition, in this specification, "parallel" means that two straight lines are at an angle of -10 degrees or more and 10 degrees or less. Therefore, it includes the case where the angle is between -5 degrees and 5 degrees. "Almost parallel" means that two straight lines are arranged at an angle between -30 degrees and 30 degrees. "Perpendicular" means that two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases where the angle is between 85 degrees and 95 degrees. This refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0037] In this specification, metal oxide refers to a metal oxide in a broad sense. Metal oxides are oxides. Metal oxides are oxide insulators and oxide conductors (including transparent oxide conductors). ), oxide semiconductor (also called oxide semiconductor or simply OS). For example, when a metal oxide is used in the semiconductor layer of a transistor, Metal oxides are sometimes called oxide semiconductors, i.e., OS transistors. In this case, the transistor may be referred to as a transistor having a metal oxide or an oxide semiconductor. can.

[0038] In this specification, normally-off means that no potential is applied to the gate or When a ground potential is applied to the port, the drain current per 1 μm of channel width that flows through the transistor is The current is 1×10 at room temperature. -20 A or less, 1 x 10 at 85°C -18 Below A, or 1×10 at 125°C -16 This means that it is A or below.

[0039] In this specification and the like, a high power supply potential Vdd (hereinafter simply referred to as "Vdd", "H potential", or The low power supply potential Vss (hereinafter simply referred to as "Vss", "L potential", or Vss refers to a power supply potential that is higher than Vdd. The ground potential can also be used as Vdd or Vss. For example, if Vdd is at ground potential, Vss is at a potential lower than ground potential, and V If the stable voltage is at ground potential, Vdd is at a potential higher than ground potential.

[0040] (Embodiment 1) In this embodiment, an example of a semiconductor device including a transistor 200 according to one embodiment of the present invention will be described. This article explains:

[0041] <Configuration example of semiconductor device> FIG. 1A is a top view and a cross-sectional view of a semiconductor device having a transistor 200. 1B to 1D are cross-sectional views of the semiconductor device. Here, FIG. 1B is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. 1A, 1A. Also, FIG. 1C is a cross-sectional view of the transistor 200 in the channel length direction. 1A is a cross-sectional view of the portion indicated by the dashed line in FIG. 1A4, and is a cross-section in the channel width direction of the transistor 200. FIG. 1D is a cross-sectional view of the portion indicated by the dashed line A5-A6 in FIG. 1A. In the top view of FIG. 1A, some elements are omitted for clarity.

[0042] The semiconductor device according to one embodiment of the present invention includes an insulator 212 on a substrate (not shown) and a semiconductor layer 213 on the insulator 212. the insulator 214, the transistor 200 on the insulator 214, and the insulator on the transistor 200. Insulator 280, insulator 282 on insulator 280, insulator 283 on insulator 282, and The insulating member 274 is disposed on the edge 283, and the insulating member 281 is disposed on the edge 283. 12, insulator 214, insulator 280, insulator 282, insulator 283, insulator 274, and The insulator 281 functions as an interlayer film. The conductor 240 (conductor 240a and conductor 240b) functions as a plug. In addition, the insulator 241 (insulator 241) is in contact with the side surface of the conductor 240 that functions as a plug. a and insulator 241b). On the top, a conductor 246 (conductor 24) is electrically connected to the conductor 240 and functions as a wiring. 6a, and conductor 246b).

[0043] Also, the insulator 254, the insulator 280, the insulator 282, the insulator 283, the insulator 274, and The insulator 241a is provided in contact with the inner wall of the opening of the insulator 281, and the side surface of the insulator 241a The first conductor of the conductor 240a is provided in contact with the first conductor of the conductor 240a, and the second conductor of the conductor 240a is provided further inward. In addition, the insulator 254, the insulator 280, the insulator 282, the insulator 283, insulator 274, and insulator 241b are provided in contact with the inner wall of the opening of insulator 281. a first conductor of the conductor 240b is provided in contact with the side surface of the insulator 241b; and A second conductor of the conductor 240b is provided inside. The height of the insulator 281 can be made approximately the same as the height of the upper surface of the insulator 281. Regarding the configuration in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked For example, the conductor 240 may be formed as a single layer or Alternatively, the structure may have a laminated structure of three or more layers. In some cases, ordinal numbers are assigned to indicate the order of their formation to distinguish them.

[0044] [Transistor 200] As shown in FIG. 1, transistor 200 includes an insulator 216 on insulator 214 and an insulator 216 on insulator 214. 16, the conductors 205 (conductor 205a and conductor 20 5b), on the insulator 216 and on the conductor 205, on the insulator 222, The insulator 224, the oxide 230a on the insulator 224, and the oxide 230 on the oxide 230a. b, conductor 242a on oxide 230b, conductor 242b, and oxide 230c; an insulator 250 on the oxide 230c; and a layer 250 located on the insulator 250 and overlapping the oxide 230c. The conductor 260 (the conductor 260a and the conductor 260b) and a part of the upper surface of the insulator 224 , a portion of the side of the oxide 230a, a portion of the side of the oxide 230b, a side of the conductor 242a, The upper surface of the conductor 242a, the side surface of the conductor 242b, and the insulating layer in contact with the upper surface of the conductor 242b The oxide 230c is formed on the side of the insulator 254, the conductor 242, and the like. 1B, the side surfaces of the conductive body 242a and the side surfaces of the conductive body 242b are in contact with each other. The upper surface of the conductor 260 is arranged so as to be substantially coincident with the upper surface of the insulator 250 and the upper surface of the oxide 230c. The insulator 282 is formed by the conductor 260, the insulator 250, the oxide 230c, and and insulator 280.

[0045] Insulator 280 and insulator 254 are provided with openings that reach oxide 230b. The oxide 230c, the insulator 250, and the conductor 260 are disposed within the opening. , the conductor 242a and the conductor 242b in the channel length direction of the transistor 200. Between them, a conductor 260, an insulator 250, and an oxide 230c are provided. 50 has an area overlapping the side surface of the conductor 260 and an area overlapping the bottom surface of the conductor 260. In addition, in the region where the oxide 230c overlaps with the oxide 230b, the oxide 230c overlaps with the oxide 230b. a region that overlaps with the side of the conductor 260 via the insulator 250; 0 and a region overlapping the bottom surface of the conductor 260.

[0046] The transistor 200 includes an oxide 230 (oxide 230a, oxide 230b) including a channel formation region. 230b and oxide 230c), a metal oxide (hereinafter, oxide It is preferable to use a semiconductor.

[0047] The metal oxide that functions as a semiconductor has a band gap of 2 eV or more, preferably 2 It is preferable to use metals with a wide band gap of 0.5 eV or more. By using an oxide, the off-state current of a transistor can be reduced.

[0048] A transistor that uses a metal oxide in the channel formation region has a leakage current when it is off. Since the metal oxide has an extremely small surface area, it is possible to provide a semiconductor device with low power consumption. Since the film can be formed using a quartz crystal deposition method, it can be used for transistors that constitute highly integrated semiconductor devices. It can be used for

[0049] The oxide 230 may be, for example, an In-M-Zn oxide having indium, element M, and zinc. oxides (element M is aluminum, gallium, yttrium, tin, copper, vanadium, beryllium Smoke, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum Tungsten, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium It is preferable to use a metal oxide such as one or more selected from the following. The layer 30 may be made of In-Ga oxide or In-Zn oxide.

[0050] The oxide 230 is made up of an oxide 230a disposed on the insulator 224 and a thin film 230b disposed on the oxide 230a. and an oxide 230b disposed on the oxide 230b and at least partially oxidized. and an oxide 230c in contact with the upper surface of the object 230b. By having the oxide 230a below, the structure formed below the oxide 230a can be This can suppress the diffusion of impurities into the oxide 230b. By having the oxide 230c, the oxide can be removed from the structure formed above the oxide 230c. This can suppress the diffusion of impurities into the oxide 230b.

[0051] In the transistor 200, the oxide 230 is made up of oxides 230a, 230b, and Although the present invention is not limited to this, the present invention is not limited to this. For example, a single layer of oxide 230b, a double layer of oxide 230a and oxide 230b, A two-layer structure of oxide 230b and oxide 230c, or a laminated structure of four or more layers is provided. Alternatively, each of the oxide 230a, the oxide 230b, and the oxide 230c may be It may have a laminated structure.

[0052] In addition, the oxide 230a and the oxide 230b, and the oxide 230b and the oxide 230c are formed of a material other than oxygen. It is preferable that the oxide 230a and the oxide 230b have a common element as a main component. Defect levels at the interface with oxide 230b and the interface between oxide 230b and oxide 230c The density can be reduced, so the effect of interface scattering on carrier conduction is small. As a result, the transistor 200 can achieve a large on-state current and high frequency characteristics. .

[0053] Conductors 242 (conductors 242a and 242b) are provided on the oxide 230b. The conductor 242a and the conductor 242b are connected to the source of the transistor 200, respectively. It functions as a drain electrode.

[0054] The conductor 260 has a conductor 260a and a conductor 260b. The conductor 260a is disposed so as to wrap around the top and sides of the transistor 20. It functions as the first gate (also called top gate) electrode of MOSFET 0.

[0055] FIG. 2 shows an enlarged cross-sectional view of a portion of the transistor 200 shown in FIG. 1B. As shown, oxide 230 is a region that serves as a channel forming region for transistor 200. region 234 and region 231 (region 231a, and region 231b). Region 231 has a high carrier density and a low resistance. The region 234 has a lower carrier density than the region 231. At least a part of the region 231a and at least a part of the region 231b are The conductive layer 242 has a region in contact with the conductor 242a and the conductor 242b.

[0056] In FIG. 2, the region 231 and the region 234 are formed in the oxide 230b. However, the present invention is not limited to this example. For example, the area 231 or the area 234 , oxide 230a and oxide 230b, or oxide 230b and oxide The oxide 230a, the oxide 230b, and the oxide 230c may be formed. 30c.

[0057] 2, the boundary between the region 231 and the region 234 is approximately perpendicular to the bottom surface of the oxide 230b. Although the area is displayed vertically, the present embodiment is not limited to this. For example, the area 23 4 spreads toward the conductor 240 near the surface of the oxide 230b, and In the vicinity, the shape may become narrower.

[0058] In a transistor using an oxide semiconductor for a channel formation region, When the low resistance region is formed, the source electrode and the drain electrode of the transistor are formed in the low resistance region. A leakage current (parasitic channel) is likely to occur between the , transistor normally-on, leakage current increase, threshold voltage decrease due to stress application This can lead to transistor characteristic defects such as voltage fluctuations (shifts). If the processing precision of the transistor is low, the parasitic channel will vary from transistor to transistor, This causes variations in resistor characteristics.

[0059] In addition, in a transistor using an oxide semiconductor, impurities are formed in a channel formation region of the oxide semiconductor. When such a material and oxygen vacancy exist, the resistance of the oxide semiconductor may be reduced. The electrical characteristics are prone to fluctuation, which can lead to poor reliability. Aluminum (Al), silicon (Si), etc. The impurity is mixed into the channel formation region. This may result in the formation of defect levels or oxygen vacancies.

[0060] Aluminum and silicon have higher bond energies with oxygen than indium and zinc. For example, when an In-M-Zn oxide is used as an oxide semiconductor, the oxide When aluminum is mixed into a semiconductor, oxygen contained in the oxide semiconductor is converted into aluminum. This loss can lead to the formation of oxygen vacancies near the indium or zinc. .

[0061] If the channel formation region in the metal oxide contains oxygen vacancies, the transistor will not function normally. Furthermore, if hydrogen enters the oxygen vacancy in the metal oxide, the oxide The electron vacancy and hydrogen bond to V O H may be formed. A defect where hydrogen enters an oxygen vacancy (V O H) can act as a donor, generating electrons as carriers. Some of these may bond with oxygen, which bonds with metal atoms, to generate electrons that act as carriers. Therefore, transistors using metal oxides containing a lot of hydrogen are normally-on transistors. In addition, hydrogen in metal oxides tends to move due to stresses such as heat and electric fields. Therefore, if the metal oxide contains a large amount of hydrogen, the reliability of the transistor may deteriorate. There is also this.

[0062] Therefore, the impurities and It is preferable that the amount of oxygen deficiency is reduced as much as possible.

[0063] Therefore, the channel formation region of the transistor and the structure in its vicinity are shaped as described below. It is preferable that the structure constituting the transistor has a shape as described below. This reduces the low resistance region formed in the hole formation region and suppresses the occurrence of parasitic channels. Therefore, it is possible to suppress variations in transistor characteristics caused by parasitic channels. Here, the transistor characteristics are the current value in the on state (on current value) and the Current value (off-state current value), threshold voltage, subthreshold swing value (S value) , field-effect mobility, etc. The impurity concentration can be reduced, and the reliability of the transistor can be improved.

[0064] <Preferred shapes of the channel formation region and structures in its vicinity> The following describes preferred shapes of the channel formation region and the structures in its vicinity. For ease of explanation, the transistor 200 is formed in a region that functions as a channel formation region. Regions are assumed to be formed in oxide 230b.

[0065] FIG. 3A is a perspective view of the transistor 200 shown in FIG. 1. FIG. 3B shows an enlarged perspective view of a portion of the star 200. In the perspective view, some elements have been omitted for clarity of illustration.

[0066] The oxide 230b is formed in the region 231a (shown in FIG. 3B) in contact with at least a portion of the conductor 242a. 3B), and a region 231b (not shown in FIG. 3B) that contacts at least a portion of the conductor 242b. The channel shape of the transistor 200 is formed between the region 231a and the region 231b. The region 234 functions as a compound region. There is an area where the oxide 230b and the conductor 260 overlap. That is, the region where the oxide 230b and the conductor 242a overlap can be referred to as the region 231a. The region where the oxide 230b and the conductor 242b overlap is referred to as the region 231b. It is possible.

[0067] As shown in FIGS. 1C and 3B, in a cross-sectional view of the transistor 200 in the channel width direction, In the region 234, a curved portion is formed between the side surface of the oxide 230b and the top surface of the oxide 230b. In other words, the edge of the side surface and the edge of the top surface are curved. (hereinafter also referred to as round shape).

[0068] Here, as shown in FIGS. 2 and 3B, when viewed in a cross section in the channel length direction of the transistor 200, In the figure, the distance between the side end of the conductor 242a and the side end of the conductor 242b facing each other is is defined as L. Note that L is the conductor length in a cross-sectional view of the transistor 200 in the channel length direction. It can also be said to be the length of the upper surface of the oxide 230b in the region that does not overlap with the conductor 242.

[0069] 3B, in a cross-sectional view of the transistor 200 in the channel width direction, The upper surface of the oxide 230b in the region where the oxide 230b and the conductor 260 overlap is Let W be the length of the region that does not have a curved surface.

[0070] The radius of curvature of the curved surface is defined as La. In a cross-sectional view in the channel width direction, the oxide 230 is The height of the upper surface of the oxide 230b in the region where the oxide 230b overlaps with the conductor 260 and the height of the upper surface of the oxide 230b are 0b, it may be considered as the difference between the height of the lower end of the curved surface area and

[0071] La is greater than 0 nm and smaller than the thickness of the oxide 230b in the region overlapping the conductor 242. It is preferable that La is equal to or smaller than half of the above W. Specifically, La is greater than 0 nm. At most 20 nm or less, preferably 1 nm to 15 nm, and more preferably 2 nm or more By making it into such a shape, the electric field between the side surface and the top surface is This suppresses the concentration of the metal oxides and the fluctuation of the transistor characteristics. This can prevent a decrease in the on-state current and mobility of the transistor 200. Therefore, a semiconductor device having good electrical characteristics can be provided.

[0072] In addition, by forming the above-mentioned shape, the effective channel of the side surface of the oxide 230b in the region 234 is The effective channel length of the oxide 230b is larger than the effective channel length of the upper surface of the oxide 230b, so that the flow Therefore, the influence of the parasitic channel formed on the side surface is suppressed, and the current It is possible to reduce the S value of the transistor 200. The influence of variations in the characteristics of each transistor in the channel is reduced. It is possible to provide a semiconductor device with little adhesion.

[0073] In a cross-sectional view of the transistor 200 in the channel width direction, the oxide 230b and the conductor 260 The length of the region of the side surface of the oxide 230b that does not have a curved surface in the region where the , Lb. In the region where the oxide 230b and the conductor 260 overlap, If the side of oxide 230b has a tapered shape, Lb is the length of the tapered portion of oxide 230b. In other words, Lb is the distance from the bottom surface of the insulator 224 to the center of gravity. the height of the upper end of the region not having a curved surface, and the height of the lower end of the region not having a curved surface; Lb is the difference between La, the thickness of the oxide 230b, and the thickness of the oxide 230b. Here, the taper angle is determined by the relationship between the side surface of the film having a tapered shape and the film. This refers to the angle between the base of the

[0074] In addition, the oxide 230b is formed on the upper surface of the oxide 230b in the region where the oxide 230b and the conductor 260 overlap. The amount of film loss is denoted by Lc. Lc is, for example, the cross section of the transistor 200 in the channel width direction. When viewed from the perspective of the insulator 222, the oxidation of the area overlapping with the conductor 242 is The height of the upper surface of the oxide 230b in the region overlapping with the conductor 260 is , can be calculated as the difference.

[0075] As will be described later, the elements contained in the conductive layer 242B provided on the oxide 230b in contact with the oxide 230b However, when the oxide 230b has a function of absorbing oxygen, the oxide 230b and the conductive layer 242 A low resistance region may be formed between B or near the surface of the oxide 230b. In addition, an insulating film provided in contact with the side surface of the channel forming region of the oxide 230b When the element contained in 254A has a function of absorbing oxygen of the oxide 230b, the oxide Between 230b and the insulating film 254A, or near the side of the channel forming region of the oxide 230b In other words, the element may partially form a low-resistance region in the oxide semiconductor. In this case, the low resistance region contains impurities or oxygen vacancies. The incorporated impurities (hydrogen, nitrogen, metal elements, etc.) act as donors, increasing the carrier density. This may occur.

[0076] Furthermore, when impurities are mixed into an oxide semiconductor, defect states or oxygen vacancies may be formed. Therefore, when impurities are mixed into the channel formation region of the oxide semiconductor, The electrical characteristics of a transistor using such a material may be easily changed, resulting in poor reliability. If oxygen vacancies are present in the channel formation region, the transistor will have normally-on characteristics ( A characteristic in which a channel exists and current flows through a transistor even when no voltage is applied to the gate electrode. ) is likely to occur.

[0077] Therefore, the top surface of oxide 230b in region 234 is For example, Lc is preferably greater than 0 nm. It is preferable that Lc is smaller than the thickness of the oxide 230b in the region overlapping with the conductor 242. Specifically, it is greater than 0 nm and not greater than 15 nm, preferably greater than 0.5 nm and not greater than 10 nm. More preferably, the thickness is 1 nm or more and 5 nm or less. The impurities are removed to reduce the low resistance region formed near the top surface of the region 234, and the parasitic channel The effective channel length at the top surface of the region 234 is L+ 2×Lc. Therefore, by reducing Lc, the decrease in the on-current of the transistor can be suppressed. It can be controlled.

[0078] In addition, in the region where the oxide 230b and the conductor 260 overlap, The film loss is represented by We. We is, for example, the cross section of the transistor 200 in the channel width direction. In this view, the side surface of the oxide 230b in the region overlapping with the conductor 242 and the surface not having the curved surface are It can be calculated as the difference between the side of the oxide 230b in the thin area and the In a cross-sectional view of the transistor 200 in the channel width direction, the region overlapping with the conductor 242 is oxidized. The length of the bottom surface of the oxide 230b in the region that does not overlap with the conductor 242 It can be calculated as half the difference between the width and the height.

[0079] We is greater than 0 nm and is equal to or less than the thickness of the oxide 230b in the region overlapping the conductor 242. Specifically, We is greater than 0 nm and less than 20 nm, preferably 1 nm or more and 15 nm or less, and more preferably 2 nm or more and 10 nm or less. By making it larger, impurities near the side of the region 234 are removed, and the low resistance region is reduced. The occurrence of parasitic channels can be suppressed.

[0080] As a result, the low-resistance region formed in the channel formation region is reduced, and the occurrence of a parasitic channel is suppressed. Therefore, the variation in transistor characteristics caused by the parasitic channel can be suppressed. In addition, the impurity concentration in the channel formation region of the oxide semiconductor and its vicinity can be controlled. This reduces the degree of breakdown and improves the reliability of the transistor.

[0081] By forming the channel formation region of the transistor 200 and the structures in its vicinity into the above-described shapes, This can reduce the variation in transistor characteristics. For example, the variation in Vsh can be reduced. In this specification, Vsh is the voltage drop in the Id-Vg curve of a transistor. The drain current Id = 1.0 × 10-12 It is defined as the gate voltage Vg at time A. Vs The variation of h can be evaluated using, for example, the standard deviation σ. The standard deviation σ of Vsh for the n (n) transistors is expressed by the following formula:

[0082]

number

[0083] In the above equation, x i is the Vs of the i-th transistor (i is an integer between 1 and n). is the value of h, and μ is the average value of Vsh of n transistors.

[0084] In the Id-Vg characteristics of the transistor 200, the standard deviation σ of Vsh is, specifically, 60 m V or less, preferably 40 mV or less, and more preferably 20 mV or less.

[0085] In addition, the channel formation region of the transistor 200 and the structures in the vicinity thereof are formed in the above-described shape. This makes it possible to reduce the impurity concentration in the channel formation region of the oxide semiconductor and in the vicinity thereof. Specifically, a secondary inductor can be formed in the channel formation region of the oxide semiconductor and in the vicinity thereof. Secondary Ion Mass Spectrometry (SIMS) The concentration of impurities obtained by the method is 1 × 10 18 atoms / cm 3 Below, I prefer Or 2 x 10 16 atoms / cm 3 Or, the channel shape of the oxide semiconductor Energy dispersive X-ray spectroscopy (EDX) was used in and around the formation region. elemental analysis using dispersive X-ray spectroscopy The concentration of the impurities obtained is set to 1.0 atomic % or less. When an oxide containing element M is used, the channel formation region of the oxide semiconductor and its vicinity In this case, the concentration ratio of the impurity to the element M is less than 0.10, preferably less than 0.05. Here, the concentration of element M used to calculate the concentration ratio is the region where the impurity concentration is calculated. The concentration may be the same as that in the oxide semiconductor.

[0086] The impurity concentration on the side of the oxide 230b in the channel formation region is The impurity concentration is set to be smaller than that on the side of the oxide 230b in the region overlapping with the gate electrode 2. is the concentration ratio of the impurity to the element M on the side of the oxide 230b in the channel formation region. is the impurity concentration of the element M on the side of the oxide 230b in the region overlapping with the conductor 242. In addition, the concentration ratio of the upper surface of the oxide 230b in the channel formation region is set to be smaller than the concentration ratio of the upper surface of the oxide 230b in the channel formation region. The concentration ratio of the impurity to the element M is The concentration ratio of the impurity to the element M is set to be smaller than the concentration ratio of the impurity to the element M in the above.

[0087] <Detailed configuration of semiconductor device> Hereinafter, a semiconductor device according to one embodiment of the present invention and a transistor included in the semiconductor device will be described. The detailed configuration of the controller 200 will be described below.

[0088] Insulator 212, insulator 214, insulator 254, insulator 282, insulator 283 and insulator 281 indicates impurities such as water and hydrogen that enter from the substrate side or from above the transistor 200. It is preferable that the insulating film functions as a barrier insulating film that prevents the diffusion of the metal oxide from the metal oxide into the transistor 200. Therefore, the insulators 212, 214, 254, 282, and 283 are 83 and insulator 281 are hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitric oxide. It has the function of suppressing the diffusion of impurities such as elementary molecules (N2O, NO, NO2, etc.) and copper atoms. It is preferable to use an insulating material that is impervious to the impurities mentioned above. For example, it has a function of suppressing the diffusion of at least one of oxygen atoms, oxygen molecules, etc. (the above-mentioned oxygen It is preferable to use an insulating material (which is difficult for elements to penetrate).

[0089] For example, the insulators 212, 283, and 281 may be made of silicon nitride or the like. The insulators 214, 254, and 282 are made of aluminum oxide or the like. This allows impurities such as water and hydrogen to pass through the insulator 212 and the insulating layer 213. Diffusion from the substrate side to the transistor 200 side can be suppressed via the insulator 214. Alternatively, oxygen contained in the insulator 224 or the like may be absorbed into the insulators 212 and 214. In addition, impurities such as water and hydrogen can be prevented from diffusing to the substrate side. The insulator 254 is connected to the insulator 280, the conductor 246, and the like. Diffusion to the transistor 200 side through the transistor 54 can be suppressed. The transistor 200 has a function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. The insulating material 212, the insulating material 214, the insulating material 254, the insulating material 282, and the insulating material 283 are used. A surrounding structure is preferable.

[0090] It is also preferable to reduce the resistivity of the insulators 212, 283, and 281. For example, the resistivities of the insulators 212, 283, and 281 may be Roughly 1×10 13By achieving a resistance of Ωcm, it is suitable for plasma processing in semiconductor device manufacturing processes. In this case, the insulator 212, the insulator 283, and the insulator 281 are In some cases, it may be possible to reduce the charge buildup of the insulator 242 or the conductor 260. The resistivity of 12, insulator 283, and insulator 281 is preferably 1×10 10 Ωcm More than 1×10 15 Ωcm or less.

[0091] In addition, the insulators 216, 280, and 274 have a dielectric constant lower than that of the insulator 214. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance between the wirings can be reduced. For example, the amount of insulator 216, insulator 280, and insulator 274 can be reduced. As the silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine doped silicon oxide, carbon doped silicon oxide, carbon and nitrogen doped silicon oxide Silicon, silicon oxide having voids, etc. may be used appropriately.

[0092] The conductor 205 is disposed so as to overlap the oxide 230 and the conductor 260. The conductor 205 is preferably embedded in the insulator 214 or the insulator 216. .

[0093] Conductor 260 may function as a first gate (also called top gate) electrode. The conductor 205 may also function as a second gate electrode. The potential applied to the body 205 is not linked to the potential applied to the conductor 260 but is changed independently. By doing so, the threshold voltage (Vth) of the transistor 200 can be controlled. In particular, applying a negative potential to the conductor 205 increases the Vth of the transistor 200. Therefore, it is possible to increase the negative potential of the conductor 205 and reduce the off-state current. When a potential is applied to the conductor 260, the potential is 0V. The drain current can be reduced.

[0094] As shown in FIG. 1A, the conductor 205 is formed by the conductor 242a of the oxide 230 and the conductor It is preferable that the area is larger than the area that does not overlap with the body 242b. In this way, the conductor 205 is formed in the region outside the end of the oxide 230 that intersects with the channel width direction. In other words, it is preferable that the oxide 230 extends in the channel width direction. On the outside of the side surface, the conductor 205 and the conductor 260 are overlapped with each other via an insulator. By having this structure, it is preferable that the conductor functioning as the first gate electrode The electric field of 260 and the electric field of the conductor 205, which acts as the second gate electrode, The first insulating film 230 can electrically surround the channel forming region. The electric field of the gate and the second gate electrically surrounds the channel forming region. The structure of the transistor is a surrounded channel (S-channel) structure. It is called.

[0095] In this specification and the like, a transistor having an S-channel structure is a transistor having a pair of gates A transistor in which the electric field of one and the other of the electrodes electrically surrounds the channel forming region. In this specification and the like, the S-channel structure refers to the structure of a source electrode and and oxide 242 in contact with the conductor 242a and the conductor 242b which function as the source and drain electrodes. The side and periphery of 30 are I-shaped, just like the channel forming region. In addition, the side and periphery of the oxide 230 in contact with the conductor 242a and the conductor 242b are insulating. Since the region is in contact with the body 280, it can be I-shaped like the channel forming region. In the above cases, Type I can be treated as the same as the high-purity genuine type described later. The S-channel structure disclosed in the document is different from the fin type structure and the planar type structure. The S-channel structure increases resistance to short channel effects. In other words, a transistor in which the short channel effect is unlikely to occur can be obtained.

[0096] As shown in FIG. 1C, the conductor 205 is extended to function as wiring. However, the present invention is not limited to this, and a conductor that functions as a wiring may be provided under the conductor 205. Also, the conductor 205 does not necessarily have to be provided for each transistor. For example, the conductor 205 may be shared by multiple transistors. .

[0097] In the transistor 200, the conductor 205 includes a conductor 205a and a conductor 205b. Although a stacked structure is shown, the present invention is not limited to this. The conductor 205 may be configured as a single layer or a laminated structure of three or more layers. When the layer has a laminated structure, the layers may be distinguished by giving an ordinal number in the order of formation.

[0098] Here, the conductor 205a is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, or a nitrogen oxide. It has the function of suppressing the diffusion of impurities such as elementary molecules (N2O, NO, NO2, etc.) and copper atoms. It is preferable to use a conductive material that can absorb oxygen (for example, oxygen atoms, oxygen molecules, etc.). It is preferable to use a conductive material that has the function of suppressing the diffusion of at least one of the above.

[0099] By using a conductive material having a function of suppressing oxygen diffusion for the conductor 205a, It is possible to prevent the conductor 205b from being oxidized and the conductivity from decreasing. Examples of conductive materials having the suppressing function include tantalum, tantalum nitride, and ruthenium. Therefore, it is preferable to use ruthenium, ruthenium oxide, or the like as the conductor 205a. The conductive material may be a single layer or a multilayer. For example, the conductive material 205a may be tantalum. , tantalum nitride, ruthenium, or ruthenium oxide and titanium or titanium nitride It may also be a layer.

[0100] The conductor 205b is a conductive material mainly composed of tungsten, copper, or aluminum. Although the conductor 205b is illustrated as a single layer, it may be a laminated structure. For example, a laminate of titanium or titanium nitride and the conductive material may be used.

[0101] Insulator 222 and insulator 224 function as gate insulators.

[0102] The insulator 222 inhibits the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). It is preferable that the insulator 222 has a function of absorbing oxygen (for example, oxygen atoms, It is preferable that the material has a function of suppressing the diffusion of at least one element, such as an elementary molecule. The insulator 222 has a function of suppressing the diffusion of one or both of hydrogen and oxygen more effectively than the insulator 224. It is preferable that the compound has the ability to

[0103] The insulator 222 is made of an oxide of one or both of aluminum and hafnium, which are insulating materials. It is preferable to use an insulator containing an oxide such as aluminum oxide or hafnium oxide. It uses oxides containing aluminum, aluminum, and hafnium (hafnium aluminate), etc. When the insulator 222 is formed using such a material, The oxide 230 is released to the substrate side, and the oxide 230 is released from the periphery of the transistor 200. It functions as a layer that suppresses the diffusion of impurities such as hydrogen into the insulator 230. By providing the insulating layer, impurities such as hydrogen are prevented from diffusing into the inside of the transistor 200. It is possible to suppress the generation of oxygen vacancies in the oxide 230. In addition, the conductor 205 is This can prevent the oxide 224 from reacting with the oxygen contained in the oxide 230.

[0104] Alternatively, the insulator may contain, for example, aluminum oxide, bismuth oxide, germanium oxide, Niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, dioxide Alternatively, these insulators may be nitrided. The insulating layer 222 is made of silicon oxide, silicon oxynitride, or silicon nitride. They may also be used in a laminated state.

[0105] The insulator 222 may be, for example, aluminum oxide, hafnium oxide, tantalum oxide, or oxide. Zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTi Insulating materials including so-called high-k materials such as (Ba,Sr)TiO3 (BST) As transistors become smaller and more highly integrated, Thinning the gate insulator can cause problems such as leakage current. By using a high-k material as an insulator that functions as a This makes it possible to reduce the gate potential during transistor operation.

[0106] The insulator 224 in contact with the oxide 230 preferably releases oxygen when heated. For example, the insulator 224 may be made of silicon oxide, silicon oxynitride, or the like. By providing an insulator containing the oxide 230 in contact with the oxide 230, oxygen vacancies in the oxide 230 are reduced. This also improves the reliability of the transistor 200.

[0107] Specifically, the insulator 224 is an oxide material from which part of the oxygen is released by heating, in other words, Therefore, it is preferable to use an insulating material having an excess oxygen region. The oxides that are present are those measured by TDS (Thermal Desorption Spectroscopy). opy) analysis showed that the amount of oxygen molecules released was 1.0 x 10 18 molecules / cm 3 Below above, preferably 1.0 x 10 19 molecules / cm 3 More preferably, 2 .0×10 19 molecules / cm 3 or more, or 3.0 x 10 20 molecu les / cm 3 The oxide film is as above. Note that the surface temperature of the film during the TDS analysis The temperature is preferably in the range of 100°C to 700°C, or 100°C to 400°C. .

[0108] In addition, the insulator having the excess oxygen region is brought into contact with the oxide 230 and then subjected to heat treatment. One or more of: microwave processing, RF (Radio Frequency) processing By performing this treatment, water or hydrogen in the oxide 230 can be removed. For example, in the oxide 230, a defect (V O A reaction occurs in which the bond of V O H→V O + H reaction occurs. Some of the hydrogen generated at this time combines with oxygen to form H2 O may be removed from the oxide 230 or from the insulator adjacent to the oxide 230. In addition, some of the hydrogen may be diffused or captured (also called gettered) in the conductor 242. There is a match.

[0109] The microwave treatment may be performed using, for example, a device having a power source that generates high-density plasma, or It is preferable to use an apparatus having a power source that applies RF to the substrate side. By using gas and high density plasma, high density oxygen radicals can be generated. By applying RF to the substrate side, oxygen radiative transfer is achieved by the high density plasma. The cations can be efficiently introduced into the oxide 230 or into the insulator near the oxide 230. The microwave treatment is carried out at a pressure of 133 Pa or more, preferably 200 Pa or more. The pressure should be set to 400 Pa or more, more preferably 400 Pa or more. The gases to be introduced are, for example, oxygen and argon, and the oxygen flow ratio (O2 / (O2 +Ar)) is preferably 50% or less, and more preferably 10% or more and 30% or less.

[0110] In addition, during the manufacturing process of the transistor 200, when the surface of the oxide 230 is exposed, The heat treatment is preferably performed at a temperature of 100° C. or higher and 450° C. or lower. More preferably, the temperature is 350° C. or higher and 400° C. or lower. or an inert gas atmosphere, or an oxidizing gas of 10 ppm or more, 1% or more, or 1 For example, it is preferable to carry out the heat treatment in an oxygen atmosphere. By this, oxygen is supplied to the oxide 230, and oxygen vacancies (V O ) can be reduced. The heat treatment may be carried out under reduced pressure or in an atmosphere of nitrogen gas or inert gas. After heat treatment in an oxidizing gas atmosphere, 10ppm of oxidizing gas was added to compensate for the oxygen that was removed. The oxidation may be carried out in an atmosphere containing 1% or more, 1% or more, or 10% or more. After heat treatment in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more, The heat treatment may be performed in a nitrogen gas or inert gas atmosphere.

[0111] In addition, by performing an oxygen addition treatment on the oxide 230, oxygen vacancies in the oxide 230 are filled by supplying oxygen. In other words, "V O +O→null reaction Furthermore, the supplied oxygen reacts with the hydrogen remaining in the oxide 230. This allows the hydrogen to be removed as H2O (dehydration). The hydrogen remaining in 230 recombines with the oxygen vacancy and V O Inhibiting the formation of H This can be done.

[0112] The insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In this case, the laminate structure is not limited to the same material, but may be a laminate structure made of different materials. stomach.

[0113] The oxide 230 preferably has a layered structure of multiple oxide layers with different chemical compositions. Specifically, in the metal oxide used for the oxide 230a, the metal element that is the main component The atomic ratio of the element M to be used in the oxide 230b is the same as that of the metal oxide that is the main component. It is preferable that the atomic ratio of the element M to the element is larger than that of the element M. In the metal oxide used in the oxide 230b, the atomic ratio of element M to In is In the metal oxide, the atomic ratio of element M to In is preferably larger than that of element M. In the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is In the metal oxide used in 30a, the atomic ratio of In to element M is preferably larger than that of In. In addition, the oxide 230c can be used for the oxide 230a or the oxide 230b. Any metal oxide that can be used can be used.

[0114] In order to increase the on-state current of the transistor 200, the oxide 230 may be doped with In. In the case where In-Zn oxide is used as the oxide 230, for example, For example, oxide 230a is made of In-Zn oxide, and oxides 230b and 230c are made of In-Zn oxide. a laminated structure using In-M-Zn oxide for the oxide 230a, or a laminated structure using In-M-Zn oxide for the oxide 230b In-Zn oxide is used as the oxide 230b or the oxide 230c. Examples of the laminated structure include:

[0115] Moreover, it is preferable that the oxide 230b and the oxide 230c have crystallinity. , CAAC-OS (c-axis aligned crystalline It is preferable to use a CAAC-OS. Oxides with any crystallinity have few impurities and defects (such as oxygen vacancies), and are highly crystalline. Therefore, the oxide 230 formed by the source electrode or the drain electrode This prevents oxygen from being extracted from b. Since oxygen extraction from the structure 230b can be reduced, the transistor 200 can be manufactured It is stable against high temperatures (so-called thermal budget) in the process.

[0116] It is also preferable to use CAAC-OS as the oxide 230c. The c-axis of the crystal of the oxide 230c is oriented in a direction substantially perpendicular to the surface on which the oxide 230c is formed or the upper surface of the oxide 230c. It is preferable that the CAAC-OS has a property of easily transferring oxygen in the direction perpendicular to the c-axis. Therefore, the oxygen contained in the oxide 230c can be efficiently supplied to the oxide 230b. It is possible.

[0117] The conduction band minimums of the oxides 230a and 230c are lower than the conduction band minimum of the oxide 230b. In other words, the oxide 230a and the oxide 23 The electron affinity of 0c is preferably smaller than the electron affinity of oxide 230b. The oxide 230c is preferably made of a metal oxide that can be used for the oxide 230a. At this time, the main path of the carriers is the oxide 230b.

[0118] Here, at the junctions of oxide 230a, oxide 230b, and oxide 230c, In other words, the oxide 230a, the oxide 230b, and The conduction band edge at the junction of the oxide 230c is also called a continuous junction. To achieve this, the interface between the oxide 230a and the oxide 230b, and reducing the defect level density of the mixed layer formed at the interface between the oxide 230b and the oxide 230c. It is recommended to do so.

[0119] Specifically, oxide 230a and oxide 230b, and oxide 230b and oxide 230c are oxides. By having a common element other than the element as the main component, a mixed layer with a low defect level density is formed. For example, when the oxide 230b is an In-Ga-Zn oxide, the oxide 230 As oxides 230a and oxide 230c, In-Ga-Zn oxide, Ga-Zn oxide, Gallium oxide Um may also be used.

[0120] Specifically, the oxide 230a is composed of In:Ga:Zn=1:3:4 [atomic ratio], A metal oxide having an atomic ratio of In:Ga:Zn=1:1:0.5 may be used. The oxide 230b is In:Ga:Zn=1:1:1 [atomic ratio], or In:Ga A metal oxide having an atomic ratio of Zn=4:2:3 can be used. The atomic ratio of In:Ga:Zn is 1:3:4, and the atomic ratio of In:Ga:Zn is 4:2:3. atomic ratio], Ga:Zn=2:1 [atomic ratio], or Ga:Zn=2:5 [atomic ratio] A metal oxide may be used.

[0121] When a metal oxide film is formed by sputtering, the above atomic ratio is The atomic ratio of the metal oxide is not limited to the atomic ratio of the metal oxide. The atomic ratio may be the ratio of the number of atoms of the cations to the number of atoms of the cations.

[0122] By configuring the oxide 230a and the oxide 230c as described above, the oxide 230a and the oxide 230c Defect state density at the interface with oxide 230b and the interface between oxide 230b and oxide 230c Therefore, the influence of interface scattering on carrier conduction is reduced. Thus, the transistor 200 can achieve a large on-state current and high frequency characteristics.

[0123] The conductor 242 (conductor 242a and conductor 242b) may be, for example, tantalum. Nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten , nitrides containing tantalum and aluminum, nitrides containing titanium and aluminum, etc. In one embodiment of the present invention, nitrides containing tantalum are particularly preferred. Also, for example, ruthenium oxide, ruthenium nitride, strontium and ruthenium An oxide containing lanthanum, an oxide containing lanthanum and nickel, etc. may also be used. It is a conductive material that is resistant to oxidation, or a material that maintains its conductivity even when it absorbs oxygen. preferable.

[0124] When the conductor 242 comes into contact with the oxide 230b, the oxygen in the oxide 230b becomes conductive. The conductor 242 may be oxidized by the diffusion of the conductor 242. Therefore, the conductivity of the conductor 242 is likely to decrease. The diffusion of the oxygen into the conductive material 242 is referred to as the absorption of oxygen from the oxide 230b by the conductive material 242. It can be replaced.

[0125] In addition, oxygen in the oxide 230b diffuses into the conductor 242a and the conductor 242b. , between the conductor 242a and the oxide 230b, and between the conductor 242b and the oxide 230b. A layer may be formed between the conductor 242a or the conductor 242b. Since the conductor 242 also contains a large amount of oxygen, it is presumed that the layer has insulating properties. The three-layer structure of the a or conductor 242b, the layer, and the oxide 230b is a metal-insulator- It can be considered as a three-layer structure made of semiconductors, and is called MIS (Metal-Insulator -Semiconductor) structure or diode junction structure mainly consisting of MIS structure This can be seen as follows.

[0126] In addition, hydrogen contained in the oxide 230b etc. is diffused into the conductor 242a or the conductor 242b. In particular, when the conductor 242a and the conductor 242b are made of nitride containing tantalum, By using the material, hydrogen contained in the oxide 230b etc. is transferred to the conductor 242a or the conductor The diffused hydrogen is easily diffused into the conductor 242a or the conductor 242b. In other words, hydrogen contained in the oxide 230b etc. can bond with nitrogen contained in the conductor 2 42a or conductor 242b.

[0127] In addition, there may be a curved surface between the side surface of the conductor 242 and the top surface of the conductor 242. That is, the edges of the side surfaces and the edges of the top surface may be curved. At the end of the body 242, the radius of curvature is 3 nm or more and 10 nm or less, preferably 5 nm or less. The thickness is 6 nm or less. By not having sharp edges, the film coverage in the subsequent film formation process is improved. Improve.

[0128] As shown in FIG. 1B, the insulator 254 is disposed on the top and side surfaces of the conductor 242a and the conductor 242 The top and side surfaces of oxide 230b, the side surfaces of oxide 230a, the side surfaces of oxide 230b, and insulator 2 It is preferable that the insulator 280 contacts a part of the upper surface of the insulator 280. The insulating layer 254 separates the insulating layer 224, the oxide 230a, and the oxide 230b. It has been done.

[0129] In addition, the insulator 254, like the insulator 222, has a property of preventing the diffusion of one or both of hydrogen and oxygen. For example, the insulator 254 has a function of suppressing the insulator 224 and and the insulator 280 has a function of suppressing the diffusion of one or both of hydrogen and oxygen. This is preferable. The hydrogen contained in the insulator 280 is then converted into the oxide 230a and the oxide 230b. Furthermore, the insulator 222 and the insulator 254 surrounds the insulator 224, oxide 230, etc., thereby preventing impurities such as water and hydrogen. Impurities can be prevented from diffusing from the outside into the insulator 224 and the oxide 230. Therefore, the transistor 200 can have good electrical characteristics and reliability. .

[0130] The insulator 254 is preferably formed by sputtering. The insulator 224 is formed by sputtering in an atmosphere containing oxygen. Oxygen can be added to the area adjacent to the contact area with 254. Oxygen can be supplied to the oxide 230 through the insulator 224. 4 has a function of suppressing the upward diffusion of oxygen, so that oxygen is insulated from the oxide 230. The insulator 222 can prevent oxygen from diffusing downward. The diffusion suppression function prevents oxygen from diffusing from the oxide 230 to the substrate side. In this way, oxygen is supplied to the channel forming region of the oxide 230. This reduces the oxygen vacancy in the oxide 230 and suppresses the transistor from becoming normally on. It is possible.

[0131] The insulator 254 may be, for example, an oxide of aluminum or hafnium or both. In this case, the insulator 254 is formed by atomic layer deposition (ALD). It is preferable to deposit the film using the Atomic Layer Deposition method. The ALD method is a film formation method with good coating properties, so unevenness of the insulator 254 does not cause any step or discontinuity. can be prevented from being formed.

[0132] The insulator 254 may be, for example, an insulator containing aluminum nitride. This allows the film to have excellent insulating properties and thermal conductivity, making it suitable for transistors. This can improve the heat dissipation performance of the heat generated when the actuator 200 is driven. Silicon nitride, silicon oxide, etc. may also be used.

[0133] Alternatively, the insulator 254 may be, for example, an oxide containing gallium. Oxides containing hydrogen and / or oxygen may have the function of suppressing diffusion. In addition, examples of oxides containing gallium include gallium oxide and gallium zinc oxide. Insulator 254 and indium gallium zinc oxide can be used. When using indium gallium zinc oxide, the atomic number of gallium relative to indium is The larger the atomic ratio, the higher the insulating properties of the oxide. It is possible.

[0134] The insulator 254 may have a multi-layer structure of two or more layers. In the case of a laminated structure, the lower layer and the upper layer of the insulator 254 are formed by the above method. The lower and upper layers of the insulator 254 may be formed by the same method. Different methods may be used, for example, sputtering in an oxygen-containing atmosphere as the insulator 254. The lower layer of the insulator 254 is formed using a ring method, and then the upper layer of the insulator 254 is formed using an ALD method. The ALD method is a film formation method with good coating properties, so the unevenness of the first layer , it is possible to prevent the formation of discontinuities and the like.

[0135] The above-mentioned materials can be used for the lower and upper layers of the insulator 254. The lower and upper layers may be made of the same material or different materials. Silicon, silicon oxynitride, silicon nitride oxide, or silicon nitride, and impurities such as hydrogen It may also have a laminated structure with an insulator having a function of suppressing the permeation of substances and oxygen. As an insulator having the function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, aluminum Insulators containing oxides of aluminum and / or hafnium can be used. .

[0136] The insulator 250 functions as a gate insulator. The insulator 250 is preferably made of silicon oxide, oxynitride, or the like. Silicon, silicon oxynitride, silicon nitride, silicon oxide doped with fluorine, and carbon doped silicon oxide doped with carbon and nitrogen, silicon oxide with vacancies In particular, silicon oxide and silicon oxynitride are highly resistant to heat. It is preferred because it is stable.

[0137] The insulator 250 is formed using an insulator that releases oxygen when heated, similar to the insulator 224. It is preferable to use an insulator that releases oxygen when heated as the insulator 250. By providing the oxide 230b in contact with at least a portion of the oxide 230c, the channel shape of the oxide 230b is This effectively supplies oxygen to the channel formation region of the oxide 230b, thereby reducing oxygen vacancies in the channel formation region of the oxide 230b. Therefore, the fluctuation of the electrical characteristics can be suppressed, and the electrical characteristics can be stabilized. In addition, a transistor with improved reliability can be provided. Similarly, it is preferable that the concentration of impurities such as water and hydrogen in the insulator 250 is reduced. The thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

[0138] Although the insulator 250 is illustrated as a single layer in FIG. 1, it may have a laminated structure of two or more layers. When the insulator 250 has a two-layer laminated structure, oxygen is released from the lower layer of the insulator 250 by heating. The upper layer of the insulator 250 has a function of suppressing the diffusion of oxygen. It is preferable to form the insulating layer 25 using an insulating material having a high insulating property. It is possible to prevent oxygen contained in the layer below 0 from diffusing into the conductor 260. This can suppress the decrease in the amount of oxygen supplied to the oxide 230. It is possible to suppress oxidation of the conductor 260 due to oxygen contained in the lower layer. The lower layer of the insulator 250 is formed using the material that can be used for the insulator 250 described above. The top layer of 250 can be provided using a material similar to that of the insulator 222 .

[0139] When silicon oxide or silicon oxynitride is used as the lower layer of the insulator 250, The upper layer of 250 may be made of an insulating material, such as a high-k material with a high dielectric constant. The heat insulating material is made of a laminated structure of a lower layer of the insulating material 250 and an upper layer of the insulating material 250. Therefore, it is possible to obtain a laminated structure that is stable against the gate insulating layer and has a high dielectric constant. It is possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the insulator. In addition, the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator can be reduced. This becomes possible.

[0140] The upper layer of the insulator 250 may be specifically made of hafnium, aluminum, gallium, or yttrium. Sodium, Zirconium, Tungsten, Titanium, Tantalum, Nickel, Germanium, Metal oxides containing one or more metals selected from magnesium, etc., or oxides Metal oxides can be used as the material 230. In particular, aluminum It is preferable to use an insulator containing oxides of one or both of tungsten and hafnium.

[0141] Furthermore, a metal oxide may be provided between the insulator 250 and the conductor 260. In this case, it is preferable to suppress the diffusion of oxygen from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses the diffusion of oxygen from the insulator 250 to the conductor 260, In other words, the decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. Moreover, oxidation of the conductor 260 due to oxygen in the insulator 250 can be suppressed.

[0142] It is preferable that the metal oxide functions as a part of the first gate electrode. For example, the metal oxide that can be used as the oxide 230 is In this case, the conductor 260a can be formed by sputtering. The electrical resistance of the metal oxide can be reduced to make it a conductor. For example, the oxide 230 can be used as a By reducing the resistance of oxide semiconductors that can be used as the metal oxides, Cut.

[0143] By having an upper layer of the insulator 250 and / or the metal oxide, the The on-state current of the transistor 200 can be improved without weakening the effect of the electric field. In addition, the physical thickness of the insulator 250 and the metal oxide allows the conductor 260 and the oxide By keeping the distance between the conductor 260 and the oxide 230, the leakage current between the conductor 260 and the oxide 230 Furthermore, a laminated structure of the insulator 250 and the metal oxide can be set. By placing the conductor 260 in the oxide 230, the physical distance between the conductor 260 and the oxide 230 and the distance between the conductor 260 and the oxide 230 are reduced. The electric field strength applied to the oxide 230 from the electrode 210 can be easily adjusted appropriately.

[0144] The conductor 260 includes a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, the conductor 260a has a bottom surface and a side surface of the conductor 260b. It is preferable that the conductor 260 is disposed so as to wrap around the surface. Although the two-layer structure of the conductive material 60a and the conductive material 260b is shown, it may be a single-layer structure or a structure having three or more layers. The laminated structure may be:

[0145] The conductor 260a is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitric oxide molecule, It is preferable to use a conductive material that has the function of suppressing the diffusion of impurities such as copper atoms. Or, a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) It is preferable to use a conductive material having the following properties.

[0146] In addition, the conductor 260a has a function of suppressing the diffusion of oxygen, and thus the conductor 260a is included in the insulator 250. The oxygen contained in the conductive material 260b can prevent the conductive material 260b from being oxidized and the conductivity from decreasing. Examples of conductive materials that have the function of suppressing oxygen diffusion include tantalum and nitride. It is preferable to use tantalum, ruthenium, ruthenium oxide, or the like.

[0147] In addition, since the conductor 260 also functions as wiring, a conductor with high conductivity can be used. For example, the conductor 260b is preferably made of tungsten, copper, or aluminum. The conductor 260b may have a laminated structure. For example, a laminated structure of titanium or titanium nitride and the above conductive material may be used.

[0148] In addition, in the transistor 200, the conductor 260 is formed on an opening such as an insulator 280. The conductor 260 is formed in a self-aligned manner so as to fill the opening. Therefore, the conductor 260 is aligned in the region between the conductors 242a and 242b. It can be positioned reliably without any problems.

[0149] 1B, the upper surface of the conductor 260 is connected to the upper surface of the insulator 250 and the oxide 2 It is roughly aligned with the top surface of 30c.

[0150] 1C, in the channel width direction of the transistor 200, the insulator 22 2 is used as a reference, the conductor 260 and the oxide 230b overlapping The height of the bottom surface of the non-gap region is preferably lower than the height of the bottom surface of the oxide 230b. A conductor 260 functioning as a gate electrode is connected to the oxide 230b via an insulator 250 or the like. By covering the side and top surfaces of the channel forming region, the electric field of the conductor 260 is Therefore, the transistor 200 The on-current can be increased, and the frequency characteristics can be improved. In this case, the oxide 230a and the oxide 230b do not overlap with the conductor 260. The difference between the height of the bottom surface of the conductor 260 and the height of the bottom surface of the oxide 230b in the region is 0. nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, more preferably 5n The thickness is between m and 20 nm.

[0151] The insulator 280 includes the insulator 224, the oxide 230a, the oxide 230b, the conductor 242, and The upper surface of the insulator 280 may be flattened. .

[0152] The insulator 280 that functions as an interlayer film preferably has a low dielectric constant. By using the insulator 280 as an interlayer film, the parasitic capacitance occurring between wirings can be reduced. It is preferable that the insulating layer 214 is made of the same material as the insulating layer 216. Silicon and silicon oxynitride are preferred because they are thermally stable. Materials such as silicon oxynitride and silicon oxide with vacancies release oxygen when heated. This is preferable because the region containing the metal oxide can be easily formed.

[0153] It is also preferable that the concentration of impurities such as water and hydrogen in the insulator 280 is reduced. In addition, the insulator 280 preferably has a low hydrogen concentration and an excess oxygen region or excess oxygen. For example, the insulator 280 may be made of the same material as the insulator 216. The above materials may be laminated, for example, a silicon oxide film formed by sputtering. The CVD (Chemical Vapor Deposition) The silicon oxynitride film may be formed by a silicon oxynitride deposition method. Silicon nitride may be further laminated on top.

[0154] The insulator 282 or the insulator 283 prevents impurities such as water and hydrogen from penetrating into the insulator 280 from above. It is preferable that the insulator 282 functions as a barrier insulating film to suppress diffusion. Alternatively, the insulator 283 preferably functions as a barrier insulating film that suppresses oxygen permeation. The insulators 282 and 283 may be made of, for example, aluminum oxide or silicon nitride. For example, the insulator 282 may be an insulator such as silicon nitride or silicon oxide. Aluminum oxide, which has high blocking properties against hydrogen, is used as an insulator 283. Silicon nitride, which has a high blocking property, may be used.

[0155] In addition, it is preferable to provide an insulator 274 that functions as an interlayer film on the insulator 282. The insulator 274, like the insulator 224, has a low impurity concentration such as water or hydrogen in the film. It is preferably reduced.

[0156] The conductors 240a and 240b are mainly composed of tungsten, copper, or aluminum. It is preferable to use a conductive material that has a high conductivity. b may have a laminated structure.

[0157] When the conductor 240a and the conductor 240b are formed in a laminated structure, the insulator 281 and the insulating layer 282 are formed in a laminated structure. In contact with the edge 274, the insulator 283, the insulator 282, the insulator 280, and the insulator 254 Conductive materials that have the function of suppressing the permeation of impurities such as water and hydrogen are used for the conductor. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, oxide It is preferable to use ruthenium chloride or the like. In addition, in order to suppress the permeation of impurities such as water and hydrogen, The conductive material having the function of forming a conductive film may be used in a single layer or a multilayer structure. As a result, the oxygen added to the insulator 280 is absorbed by the conductors 240a and 240b. In addition, impurities such as water and hydrogen contained in the layer above the insulator 281 can be prevented from being leaked. The conductor 240a and the conductor 240b are formed on the oxide 230. It is possible.

[0158] The insulators 241a and 241b may be, for example, silicon nitride or aluminum oxide. An insulator such as silicon nitride oxide or silicon nitride oxide may be used. Since b is provided in contact with the insulator 254, water, hydrogen, etc. contained in the insulator 280 etc. The impurities are prevented from being mixed into the oxide 230 through the conductors 240a and 240b. In particular, silicon nitride is preferred because it has a high blocking property against hydrogen. In addition, oxygen contained in the insulator 280 is transferred to the conductors 240a and 240b. It can prevent absorption.

[0159] Also, the conductive material 240a and the conductive material 240b are in contact with each other and function as wiring. The conductor 246 (conductor 246a and conductor 246b) may be arranged. 6 may be made of a conductive material mainly composed of tungsten, copper, or aluminum. The conductor may also have a laminated structure, for example, titanium or titanium nitride. The conductive material may be a laminate of an insulating material and the conductive material. It may be configured to be implanted in the mouth.

[0160] <Materials for semiconductor devices> The following describes constituent materials that can be used in semiconductor devices.

[0161] <<Substrate>> The substrate on which the transistor 200 is formed may be, for example, an insulating substrate, a semiconductor substrate, or A conductive substrate may be used. Examples of insulating substrates include glass substrates, quartz substrates, and surface treatment substrates. Fiber substrate, stabilized zirconia substrate (yttria-stabilized zirconia substrate, etc.), resin substrate The semiconductor substrate may be made of silicon, germanium, or the like. Semiconductor substrates, or silicon carbide, silicon germanium, gallium arsenide, indium phosphide Compound semiconductor substrates made of indium, zinc oxide, and gallium oxide are also available. The semiconductor substrate having an insulating region inside the semiconductor substrate, for example, SOI (Silicon on Insulator) Conductive substrates include graphite substrates and metal substrates. Plates, alloy substrates, conductive resin substrates, etc. Also, substrates with metal nitrides, metal Furthermore, there are substrates having an oxide, etc. Furthermore, there are substrates having a conductor or semiconductor on an insulating substrate. a substrate in which a conductor or an insulator is provided on a semiconductor substrate; a substrate in which a conductor or an insulator is provided on a conductive substrate; There are also substrates with insulators provided. The elements provided on the substrate may include a capacitance element, a resistance element, a switch element, a light emitting element, and the like. elements, memory elements, etc.

[0162] <<Insulators>> The insulators include oxides, nitrides, oxynitrides, nitride oxides, and metal oxides that have insulating properties. , metal oxide nitrides, metal nitride oxides, etc.

[0163] For example, as transistors become smaller and more highly integrated, the gate insulator becomes thinner. , leakage current and other problems may occur. By using igh-k materials, the voltage required for transistor operation can be reduced while maintaining the physical film thickness. On the other hand, the insulator that functions as the interlayer film should be made of a material with a low dielectric constant. Therefore, depending on the function of the insulator, the parasitic capacitance between the wiring can be reduced. It is advisable to select materials accordingly.

[0164] Insulators with high dielectric constants include gallium oxide, hafnium oxide, and zirconium oxide. oxides containing aluminum, aluminum and hafnium, oxides containing aluminum and hafnium oxides with silicon and hafnium, oxides with silicon and hafnium or nitrides with silicon and hafnium.

[0165] Insulators with low dielectric constants include silicon oxide, silicon oxynitride, and silicon nitride oxide. silicon nitride, silicon oxide with fluorine, silicon oxide with carbon, silicon oxide with added hydrogen and nitrogen, silicon oxide with pores, or resin. do.

[0166] In addition, transistors using metal oxides have the advantage of suppressing the permeation of impurities such as hydrogen and oxygen. By surrounding the transistor with an insulator that has the function of stabilizing the electrical characteristics of the transistor, Examples of insulators that have the function of suppressing the permeation of impurities such as hydrogen and oxygen include For example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, and lithium. Nitrogen, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum Insulators containing tantalum, neodymium, hafnium, or tantalum are used in single or multilayer configurations. Specifically, an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen is used. As aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, oxide Yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, oxide Metal oxides such as tantalum, aluminum nitride, silicon nitride oxide, silicon nitride, etc. Metal nitrides can be used.

[0167] The insulator that functions as the gate insulator has a region containing oxygen that is desorbed by heating. For example, an insulator having a region containing oxygen that is desorbed by heating is preferable. By forming a structure in which silicon nitride or silicon oxynitride is in contact with oxide 230, oxide 2 The oxygen deficiency of 30 can be compensated for.

[0168] <<Conductors>> Conductors include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, and titanium. Niobium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium Sodium, zirconium, beryllium, indium, ruthenium, iridium, strontium a metal element selected from the group consisting of ruthenium, lanthanum, etc., or an alloy containing the above-mentioned metal element; It is preferable to use an alloy or the like that combines the above-mentioned metal elements. For example, tantalum nitride , titanium nitride, tungsten, nitrides containing titanium and aluminum, tantalum and aluminum Ruthenium nitrides, ruthenium oxides, ruthenium nitrides, strontium and ruthenium It is preferable to use oxides containing lanthanum and nickel, or oxides containing lanthanum and nickel. titanium nitride, titanium and aluminum nitride, tantalum and aluminum nitride Ruthenium nitrides, ruthenium oxides, ruthenium nitrides, oxides containing strontium and ruthenium Oxides containing lanthanum and nickel are conductive materials that are resistant to oxidation or absorb oxygen. It is preferable because it is a material that maintains conductivity even after the addition of impurity elements such as phosphorus. Highly conductive semiconductors, such as polycrystalline silicon, and silicon silicides, such as nickel silicide, A reside may also be used.

[0169] Alternatively, a plurality of conductive layers made of the above materials may be stacked. Alternatively, a laminated structure may be used in which a material containing a metal element and a conductive material containing oxygen are combined. In addition, a laminated structure combining a material containing the above-mentioned metal element and a conductive material containing nitrogen is also available. Also, the material containing the metal element, the conductive material containing oxygen, and the nitrogen A laminated structure in which a conductive material containing the above is combined may also be used.

[0170] When an oxide is used for the channel formation region of a transistor, The conductor that functions as a conductive material is a combination of the material containing the metal element and a conductive material containing oxygen. In this case, it is preferable to use a laminated structure in which an oxygen-containing conductive material is used as a chalcogenide. It is preferable to provide the conductive material containing oxygen on the channel formation region side. As a result, oxygen released from the conductive material is more easily supplied to the channel formation region.

[0171] In particular, the metal oxide in which the channel is formed is used as a conductor that functions as a gate electrode. It is preferable to use a conductive material containing the metal element and oxygen. Conductive materials containing elements such as titanium nitride and tantalum nitride may also be used. Any conductive material containing nitrogen may be used. Indium tin oxide, tungsten oxide, etc. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide Alternatively, silicon-doped indium tin oxide may be used. Gallium zinc oxide may also be used. By using such a material, a channel is formed. In some cases, the metal oxides surrounding the outer insulating layer can trap hydrogen. It may be possible to capture hydrogen that enters the body, etc.

[0172] <<Metal oxides>> As the oxide 230, a metal oxide (oxide semiconductor) that functions as a semiconductor can be used. Metal oxides applicable to the oxide 230 according to the present invention will be described below. do.

[0173] The metal oxide preferably contains at least indium or zinc. In addition to these, aluminum, gallium, It is preferable that yttrium, tin, etc. are contained. Also, boron, titanium, iron, nickel, etc. Kel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium One or more selected from the group consisting of tungsten, magnesium, tantalum, and tungsten It may be included.

[0174] Here, the metal oxide is an In-M-Zn oxide having indium, element M, and zinc. Here, the element M is aluminum, gallium, yttrium, or Other elements that can be used for element M include boron, titanium, iron, and nickel. , germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium However, the element M is the same as the above. In some cases, a combination of multiple elements may be used.

[0175] In this specification and the like, metal oxides containing nitrogen are also referred to as metal oxides. Nitrogen-containing metal oxides are also called metal oxynitrides (met). It may also be called hydroxybenzoxanthate (hydroxybenzoxanthate).

[0176] [Metal oxide structures] Oxide semiconductors (metal oxides) are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include CAAC-OS and polycrystalline Oxide semiconductor, nc-OS (nanocrystalline oxide semiconductor) conductor), pseudo-amorphous oxide semiconductor (a-like OS) s-like oxide semiconductor), and amorphous oxide semiconductor etc.

[0177] CAAC-OS has a c-axis orientation and multiple nanocrystals are connected in the ab-plane direction. The crystal structure has distortion. The distortion is the area where multiple nanocrystals are connected. In the region, the lattice arrangement is changed between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement. Indicates the point where the direction is changing.

[0178] Nanocrystals are basically hexagonal, but they are not limited to regular hexagonal shapes and may be non-regular hexagonal. In addition, the distortion may have a lattice arrangement such as a pentagon or heptagon. In CAAC-OS, clear grain boundaries are observed even near the strain. ) is difficult to confirm. In other words, the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the CAAC-OS has oxygen atoms in the ab-plane direction. The arrangement is not dense, and the bond distance between atoms does not change due to the substitution of metal elements. This is because distortion can be tolerated by using the above method.

[0179] In addition, the CAAC-OS has a layer containing indium and oxygen (hereinafter referred to as an In layer) and an element A layered crystal structure in which layers containing M, zinc, and oxygen (hereinafter referred to as (M, Zn) layers) are stacked. It is noted that indium and element M tend to have a layered structure. It is possible, and when the element M in the (M,Zn) layer is replaced with indium, (In,M,Zn) Also, when indium in the In layer is replaced with element M, (In,M ) layer.

[0180] CAAC-OS is a metal oxide with high crystallinity. Since it is difficult to identify grain boundaries, the decrease in electron mobility caused by grain boundaries is unlikely to occur. In addition, the crystallinity of metal oxides can be reduced by the incorporation of impurities or the generation of defects. Therefore, CAAC-OS is a metal oxide with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of the metal oxide having the CAAC-OS are stable. Therefore, metal oxides having CAAC-OS are heat-resistant and highly reliable.

[0181] nc-OS is a material that can be used in microscopic areas (e.g., areas between 1 nm and 10 nm, especially areas between 1 nm and 3 nm). The nc-OS has periodic atomic arrangement in the nanometer range (nm or less). There is no regularity in the crystal orientation between the crystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be distinguished from a-like OS or amorphous oxide semiconductor. It may be difficult to distinguish between the two.

[0182] In addition, In-G, a type of metal oxide containing indium, gallium, and zinc, α-Zn oxide (hereinafter referred to as IGZO) can take on a stable structure by forming it into the above-mentioned nanocrystals. In particular, IGZO tends to have difficulty growing crystals in the atmosphere, so it is difficult to grow large crystals. (Here, crystals of a few mm or a few cm) In some cases, it may be structurally more stable to form the crystals as a solid.

[0183] The a-like OS is a metal oxide semiconductor with a structure between the nc-OS and amorphous oxide semiconductor. A-like OS has voids or low density areas. e-OS has lower crystallinity than nc-OS and CAAC-OS.

[0184] Oxide semiconductors (metal oxides) have a variety of structures, each with different properties. The oxide semiconductor of one embodiment of the present invention is an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-lik The crystalline structure may have two or more of e-OS, nc-OS, and CAAC-OS.

[0185] [impurities] Here, the influence of each impurity in the metal oxide will be described.

[0186] When impurities are mixed into an oxide semiconductor, defect states or oxygen vacancies may be formed. Therefore, when impurities are mixed into the channel formation region of the oxide semiconductor, The electrical characteristics of the transistors may be easily changed, resulting in poor reliability. If oxygen vacancies are present in the channel formation region, the transistor is likely to exhibit normally-on characteristics. water.

[0187] Transistors using metal oxides are subject to impurities and oxygen vacancies in the metal oxides. The electrical characteristics change, and the channel becomes normally on (even without applying voltage to the gate electrode). In addition, the presence of an appropriate amount of When the transistor is operated in a state where excess oxygen exceeds the value, the excess oxygen atoms The valence of the ions changes, and the electrical characteristics of the transistor fluctuate, which can lead to a decrease in reliability. be.

[0188] Therefore, a metal oxide with a low carrier concentration is used in the channel formation region of a transistor. In the case where the carrier concentration of the metal oxide is reduced, it is preferable that the metal oxide In this specification and the like, the impurity concentration in the semiconductor layer is reduced to reduce the defect level density. A low concentration and a low defect level density are called high purity intrinsic or substantially high purity intrinsic. In this specification, the carrier concentration of the metal oxide in the channel formation region is 1×10 1 6 cm -3 The following cases are defined as substantially high purity and authentic:

[0189] The carrier concentration of the metal oxide in the channel formation region is 1×10 18 cm -3 Below is It is preferable to use 1×10 17 cm -3 More preferably, it is 1×10 or less. 16 cm -3 More preferably, it is 1×10 or less. 13 cm -3 It is even more 1×10 12 cm -3 It is more preferable that the channel shape is less than 1 / 2 mm. The lower limit of the carrier concentration of the metal oxide in the compound region is not particularly limited. For example, x10 -9 cm -3 It can be said that:

[0190] Impurities in metal oxides include, for example, hydrogen, nitrogen, alkali metals, alkaline earth metals, and the like. In particular, hydrogen contained in metal oxides is It reacts with oxygen that bonds with the molecule to form water, which can cause oxygen vacancies in the metal oxide. If there is oxygen vacancy in the channel formation region of the metal oxide, the transistor will not function properly. Furthermore, when hydrogen enters the oxygen vacancy in the metal oxide, , oxygen vacancies and hydrogen bonds to form V O H may be formed. A defect in which hydrogen enters an oxygen vacancy. (V O H) can act as a donor, generating electrons as carriers. Some of the hydrogen may combine with oxygen, which combines with metal atoms, to generate electrons, which act as carriers. Therefore, a transistor using a metal oxide containing a large amount of hydrogen In addition, hydrogen in metal oxides is easily degraded by stress such as heat and electric field. Because hydrogen is mobile, if metal oxides contain a lot of hydrogen, the reliability of transistors will deteriorate. There is also a risk.

[0191] In one embodiment of the present invention, V in the oxide 230 O Reduce H as much as possible and use high purity intrinsic It is preferable to make it substantially intrinsic or of high purity. O Gold with sufficiently reduced H To obtain metal oxides, impurities such as water and hydrogen must be removed from the metal oxides (dehydration, desorption). This is sometimes referred to as hydrogenation treatment.) and the supply of oxygen to the metal oxide to compensate for the oxygen deficiency. It is important to do this (sometimes referred to as oxygenation treatment). O Impurities such as H are not By using a metal oxide that has been reduced to a minimum in the channel formation region of a transistor, stable Electrical properties can be imparted.

[0192] A defect where hydrogen has entered an oxygen vacancy (V O H) can function as a donor for the metal oxide. However, it is difficult to quantitatively evaluate the defects. is sometimes evaluated by the carrier concentration rather than the donor concentration. Assuming that the state in which no electric field is applied is used as a parameter of the metal oxide, rather than the donor concentration, In other words, the "carrier concentration" described in this specification etc. can be rephrased as "donor concentration." "Carrier concentration" can be rephrased as "density."

[0193] Therefore, it is preferable that the amount of hydrogen in the metal oxide is reduced as much as possible. In metal oxides, the hydrogen concentration obtained by SIMS is 1×10 20 atoms / c m 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 1 8 atoms / cm 3 less than 1×10 18 atoms / cm 3 Less than The metal oxide in which impurities such as hydrogen are sufficiently reduced is used as the channel forming region of the transistor. By using this, stable electrical properties can be imparted.

[0194] The defect levels may include trap levels. Charges trapped at the potential take a long time to dissipate and vibrate as if they were fixed charges. Therefore, metal oxide with a high trap density is used in the channel formation region. A transistor having such a gate electrode may have unstable electrical characteristics.

[0195] Furthermore, when impurities exist in the channel formation region of the oxide semiconductor, the crystallinity of the channel formation region increases. In addition, the crystallinity of the oxide provided in contact with the channel forming region may be deteriorated. If the crystallinity of the channel formation region is low, the stability or In addition, the reliability of the oxide crystals formed in contact with the channel forming region tends to deteriorate. If the conductivity is low, interface states may form, which may deteriorate the stability or reliability of the transistor. be.

[0196] Therefore, in order to improve the stability or reliability of a transistor, it is necessary to It is effective to reduce the impurity concentration in the channel forming region and its vicinity. , hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, etc. Metal oxides with reduced impurity concentration have a low defect level density, and therefore a low trap level density. This may be the case.

[0197] <<Other semiconductor materials>> The semiconductor materials that can be used for the oxide 230 are not limited to the metal oxides mentioned above. As the object 230, a semiconductor material having a band gap (a semiconductor that is not a zero-gap semiconductor) For example, semiconductors of elemental elements such as silicon, gallium arsenide, etc. Compound semiconductors, layered materials (also called atomic layer materials, two-dimensional materials, etc.) that function as semiconductors It is preferable to use a layered material that functions as a semiconductor. It is suitable for use in semiconductor materials.

[0198] In this specification, the term "layered material" is a general term for a group of materials having a layered crystal structure. The layered crystal structure is formed by layers formed by covalent bonds and ionic bonds, It is a structure in which layers are stacked through bonds weaker than covalent or ionic bonds, such as rubbing forces. Layered materials have high electrical conductivity within the unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, As a result, a transistor with a large on-state current can be provided.

[0199] Layered materials include graphene, silicene, and chalcogenides. Chalcogen is a general term for elements belonging to Group 16. They contain oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Examples of chalcogenides include transition metal chalcogenides and group 13 chalcogenides.

[0200] For example, a transition metal chalcogenide that functions as a semiconductor may be used as the oxide 230. Specific examples of transition metal chalcogenides that can be used as the oxide 230 include: are molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe 2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS 2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), zirconium selenide (typically Examples include ZrSe2).

[0201] <Method for manufacturing semiconductor device> Next, a manufacturing method of the semiconductor device shown in FIG. 1, which is one embodiment of the present invention, will be described with reference to FIGS. and explain.

[0202] 4 to 11, A in each figure indicates a top view. B in each figure indicates the A1- 2 is a cross-sectional view corresponding to the portion indicated by the dashed line in A2, and shows the channel length of the transistor 200. Also, C in each figure corresponds to the part indicated by the dashed line A3-A4 in A. 1 and 2. The cross-sectional view of the transistor 200 is taken along the channel width direction. D is a cross-sectional view of the part indicated by the dashed line A5-A6 in A of each figure. In the plan view, some elements have been omitted for clarity.

[0203] First, a substrate (not shown) is prepared, and an insulator 212 is formed on the substrate. The deposition of 12 films is performed by sputtering, CVD, and molecular beam epitaxy (MBE). ular beam epitaxy (PLD), pulsed laser deposition (PLD) This can be done using a laser deposition method, an ALD method, or the like.

[0204] The CVD method is a plasma CVD (PECVD) method that uses plasma. enhanced CVD method, thermal CVD (TCVD) D) method, and photo-CVD (Photo CVD) method, which uses light. Depending on the source gas, metal CVD (MCVD) and metal organic CVD ( MOCVD (Metal Organic CVD) method.

[0205] The plasma CVD method can produce high-quality films at relatively low temperatures. This is a film formation method that can reduce plasma damage to the processed object because it does not use a plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device These may become charged up by receiving electric charges from the plasma. The accumulated charge can destroy the wiring, electrodes, elements, etc. contained in the semiconductor device. On the other hand, in the case of thermal CVD methods that do not use plasma, such plasma damage does not occur. In addition, the thermal CVD method does not require the use of a metal oxide film, which increases the yield of semiconductor devices. Since no plasma damage occurs inside the film, a film with few defects can be obtained.

[0206] In addition, the ALD method utilizes the self-regulating properties of atoms to deposit atoms one layer at a time. This allows for ultra-thin film deposition, film deposition on structures with high aspect ratios, and pinholes. It is possible to form films with few defects, excellent coating properties, and low temperature film formation. In addition, the ALD method uses plasma, which is called PEALD (Plasma E ALD). This includes the enhanced ALD method, which uses plasma to form films at lower temperatures. In addition, the precursors used in the ALD method do not contain impurities such as carbon. Therefore, films formed by the ALD method may be different from films formed by other film formation methods. The amount of impurities may be higher than that of the film that has been removed. , X-ray Photoelectron Spectroscopy (XPS) This can be done using oscopy.

[0207] The CVD and ALD methods are film formation methods in which particles emitted from a target are deposited. Unlike the conventional method, this is a film formation method in which a film is formed by a reaction on the surface of the object to be treated. This is a film forming method that is less affected by the shape of the workpiece and has good step coverage. The ALD method has excellent step coverage and thickness uniformity, making it suitable for the production of thin films with high aspect ratios. It is suitable for coating the surface of high openings. However, the ALD method has a relatively low film formation rate. Because the deposition rate is slow, it cannot be used in combination with other deposition methods such as CVD, which has a high deposition rate. In some cases, this is preferable.

[0208] In the CVD and ALD methods, the composition of the resulting film can be controlled by the flow rate ratio of the source gases. For example, in the CVD and ALD methods, the flow rate ratio of the source gases can be adjusted to any desired value. In addition, for example, in the CVD method and the ALD method, it is possible to form a film having a composition. By changing the flow rate ratio of the source gases while When forming a film while changing the flow rate ratio of the source gases, multiple film forming chambers can be used. Compared to forming a film by using a vacuum pump, the time required for film formation is shorter because there is no time required for transportation or pressure adjustment. Therefore, the productivity of the semiconductor device can be improved. be.

[0209] In this embodiment, a silicon nitride film is formed as the insulator 212 by the CVD method. As described above, an insulator that is difficult for copper to penetrate, such as silicon nitride, is used as the insulator 212. Therefore, a metal that easily diffuses, such as copper, is used for the conductor in the layer (not shown) below the insulator 212. Even if the metal is present in the insulating layer 212, the metal can be prevented from diffusing upward through the insulating layer 212. In addition, by using an insulator that is difficult for impurities such as water and hydrogen to penetrate, This makes it possible to suppress the diffusion of impurities such as water and hydrogen contained in the layer below the insulator 212. do.

[0210] Next, the insulator 214 is deposited on the insulator 212. The deposition of the insulator 214 is carried out by sputtering. This can be done by using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, aluminum oxide is used as the insulator 214 .

[0211] Next, the insulator 216 is deposited on the insulator 214. The insulator 216 is deposited by sputtering. The deposition can be carried out by using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0212] Next, an opening is formed in the insulator 216, reaching the insulator 214. The opening may be, for example, a groove or a slot. It also includes lits, etc. The opening may refer to a region where an opening is formed. The openings may be formed by wet etching, but dry etching is more effective. Insulator 214 is preferable for fine processing. Also, insulator 216 is etched to form grooves. It is preferable to select an insulator that functions as an etching stopper film when the insulating layer is removed. When silicon oxide is used for the insulator 216 forming the groove, the insulator 214 is silicon nitride. , aluminum oxide, and hafnium oxide are preferably used.

[0213] The dry etching equipment is a capacitively coupled plasma (CCP) with parallel plate electrodes. Capacitively Coupled Plasma etching equipment is used. The capacitively coupled plasma etching apparatus having parallel plate electrodes can Alternatively, a high frequency voltage may be applied to one of the electrodes. A configuration in which a plurality of different high frequency voltages are applied to the electrodes may also be used. Alternatively, a high frequency voltage of the same frequency may be applied to each of the parallel plate electrodes. Alternatively, a high-frequency voltage having a high-density plasma source may be applied. Dry etching equipment with a high density plasma source can be used. The device may be, for example, an inductively coupled plasma (ICP) d Plasma etching equipment or the like can be used.

[0214] After the opening is formed, a conductive film that will become the conductor 205a is formed. The conductive film has properties that prevent oxygen from passing through. It is desirable to include a conductor having a function of controlling the temperature. For example, tantalum nitride, tungsten nitride, etc. Stainless steel, titanium nitride, etc. can be used. Alternatively, a material that has the function of suppressing oxygen permeation can be used. Conductors that are compatible with the tantalum, tungsten, titanium, molybdenum, aluminum, copper, and molybdenum The conductive film can be formed as a laminated film with a tungsten-bonded alloy. The deposition can be carried out by using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0215] In this embodiment, the conductive film that becomes the conductor 205a has a multi-layer structure. A tantalum nitride film is formed by a coating method, and titanium nitride is then laminated on the tantalum nitride. By using such a metal nitride as the lower layer of the conductor 205b, the conductor 205 Even if a metal that easily diffuses, such as copper, is used as the conductive film that becomes the conductor 205a, the metal It can prevent the spread of bacteria from the outside.

[0216] Next, a conductive film that will become the conductor 205b is formed. The conductive film can be formed by plating, sputtering, or the like. This can be done using methods such as the laser deposition method, CVD method, MBE method, PLD method, and ALD method. In the embodiment, a low-resistance conductive material such as copper is deposited as the conductive film that becomes the conductor 205b. do.

[0217] Next, a conductive film that will become the conductor 205a and a conductive film that will become the conductor 205b are formed by CMP treatment. A portion of the conductive film is removed to expose the insulator 216. As a result, the conductive film is only present in the opening. Thus, the conductor 205 has a flat top surface. By this CMP process, one part of the insulator 216 can be formed (see FIG. 4). Parts may be removed.

[0218] In the above description, the conductor 205 is formed so as to be embedded in the opening of the insulator 216. However, the present embodiment is not limited to this. For example, a conductor 205 is formed on an insulator 214. Then, an insulator 216 is formed on the conductor 205, and a CMP process is performed on the insulator 216. In this way, a part of the insulator 216 is removed to expose the surface of the conductor 205 .

[0219] Next, the insulator 222 is formed on the insulator 216 and the conductor 205. and depositing an insulator containing oxides of one or both of aluminum and hafnium. In addition, the insulator containing oxide of one or both of aluminum and hafnium is Examples include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium. It is preferable to use aluminum and hafnium (hafnium aluminate). Insulators containing oxides of one or both of these materials provide barrier properties to oxygen, hydrogen, and water. The insulator 222 has a barrier property against hydrogen and water, and thus the transistor The hydrogen and water contained in the structure provided around 200 are transferred through the insulator 222. Diffusion into the inside of the transistor 200 is suppressed, and the generation of oxygen vacancies in the oxide 230 is prevented. It can be suppressed.

[0220] The insulator 222 can be formed by a method such as sputtering, CVD, MBE, PLD, or ALD. This can be done using, for example.

[0221] Subsequently, it is preferable to carry out a heat treatment. The heat treatment is preferably carried out at a temperature of 250° C. or higher and 650° C. or lower. The temperature is preferably 300°C or higher and 500°C or lower, more preferably 320°C or higher and 450°C or lower. The heat treatment is carried out in an atmosphere of nitrogen gas or inert gas, or in an atmosphere of oxidizing gas. The heat treatment is carried out in an atmosphere containing more than pm, more than 1%, or more than 10%. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere. After that, to replace the oxygen that has been removed, oxidizing gas is added at 10 ppm or more, 1% or more, or 1 The heat treatment may be carried out in an atmosphere containing 0% or more of Cr.

[0222] In this embodiment, the heat treatment is performed at 400° C. in a nitrogen atmosphere after the insulator 222 is formed. After treatment at 400°C for 1 hour, the sample was subsequently treated in an oxygen atmosphere at 400°C for 1 hour. By this heat treatment, impurities such as water and hydrogen contained in the insulator 222 are removed. The heat treatment can be performed after the insulator 224 is formed. You can also do this.

[0223] Next, the insulator 224 is deposited on the insulator 222. The deposition of the insulator 224 is carried out by sputtering. This can be done by using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon oxynitride film is formed as the insulator 224 by a CVD method.

[0224] Here, in order to form an excess oxygen region in the insulator 224, a plasma containing oxygen is used under reduced pressure. The oxygen-containing plasma treatment may be performed using, for example, a high-density plasma treatment using microwaves. It is preferable to use a device with a power source that generates a pulse. Alternatively, RF is applied to the substrate side. By using high density plasma, high density oxygen radicals can be generated. By applying RF to the substrate side, high density plasma is generated. The oxygen radicals can be efficiently guided into the insulator 224. After performing plasma treatment containing an inert gas, a plasma containing oxygen was added to compensate for the desorbed oxygen. Plasma treatment may be performed. By appropriately selecting the conditions for the plasma treatment, Impurities such as water and hydrogen contained in the insulator 224 can be removed. No processing is required.

[0225] Here, aluminum oxide is formed on the insulator 224 by, for example, a sputtering method. After the film is formed, a CMP process may be performed until the insulator 224 is reached. By this, the surface of the insulator 224 can be flattened and smoothed. By placing aluminum on the insulator 224 and performing the CMP process, it is easy to detect the end point of the CMP process. Furthermore, the CMP process polishes a part of the insulator 224, and the insulator 224 The film thickness may be thin, but this can be adjusted when forming the insulator 224. 24 Planarizing and smoothing the surface prevents deterioration of the coverage of the oxide film that will be formed later. Therefore, it may be possible to prevent a decrease in the yield of the semiconductor device. The insulator 224 is formed by forming an aluminum oxide film by a sputtering method. This is preferable because oxygen can be added.

[0226] Next, an oxide film 230A and an oxide film 230B are formed in this order on the insulator 224 (see FIG. 4). The oxide film 230A and the oxide film 230B are formed successively without being exposed to the atmospheric environment. By forming the oxide film 230A without exposing it to the atmosphere, the oxide film 230B and the oxide film 230C are formed. 30B, impurities or moisture from the atmospheric environment can be prevented from adhering to the oxide film 2 The vicinity of the interface between 30A and oxide film 230B can be kept clean.

[0227] The oxide film 230A and the oxide film 230B are formed by sputtering, CVD, or MBE. The deposition can be carried out by using a PLD method, an ALD method, or the like.

[0228] For example, when the oxide film 230A and the oxide film 230B are formed by sputtering, In this case, oxygen or a mixture of oxygen and a rare gas is used as the sputtering gas. By increasing the oxygen content of the tartering gas, the excess oxygen in the oxide film to be formed can be removed. In addition, when the oxide film is formed by sputtering, The above-mentioned In-M-Zn oxide target or the like can be used.

[0229] In particular, when the oxide film 230A is formed, part of the oxygen contained in the sputtering gas is converted into the insulator 2. 24. Therefore, the proportion of oxygen contained in the sputtering gas In this case, the ratio may be 70% or more, preferably 80% or more, and more preferably 100%.

[0230] In addition, when the oxide film 230B is formed by sputtering, the oxide film 230B is formed by sputtering gas containing fluorine. The proportion of oxygen in the air is set to more than 30% and not more than 100%, preferably 70% or more and not more than 100%. When the oxide semiconductor is formed as a film, an oxygen-excess oxide semiconductor is formed. The transistor used in the channel forming region has relatively high reliability. One embodiment is not limited to this. When the oxide film 230B is formed by a sputtering method, The oxygen content of the sputtering gas is set to 1% or more and 30% or less, preferably 5% or more and 20% or less. % or less, an oxygen-deficient oxide semiconductor is formed. Transistors that use semiconductors in the channel formation region have relatively high field-effect mobility. Furthermore, by forming the film while heating the substrate, the crystallinity of the oxide film can be improved. It is possible.

[0231] In this embodiment, the oxide film 230A is formed by sputtering In:Ga:Z The film is formed using an oxide target with an atomic ratio of n=1:3:4. B was prepared by sputtering with In:Ga:Zn=4:2:4.1 [atomic ratio] The oxide film is formed using the oxide target. The film formation conditions and atomic ratio are By appropriately selecting the oxide 230a and the oxide 230b, the shape can be adjusted to suit the desired properties. It would be good to achieve this.

[0232] The insulator 222, the insulator 224, the oxide film 230A, and the oxide film 230B are exposed to the atmosphere. It is preferable to form a film without exposing it to light. For example, a multi-chamber film forming apparatus is used. Just use it.

[0233] Next, a heat treatment may be performed. The heat treatment may be performed under the heat treatment conditions described above. By this heat treatment, water, hydrogen, etc. in the oxide film 230A and the oxide film 230B are removed. In this embodiment, the method is carried out by heating the wafer at 400° C. in a nitrogen atmosphere. After treatment at 400°C for 1 hour, the sample was subsequently treated in an oxygen atmosphere at 400°C for 1 hour. Carry out the process.

[0234] Next, a conductive film 242A is formed on the oxide film 230B (see FIG. 4). Film formation can be performed using methods such as sputtering, CVD, MBE, PLD, and ALD. Note that heat treatment may be performed before the conductive film 242A is formed. The step (a) may be performed under reduced pressure, and the conductive film 242A may be formed continuously without exposure to the atmosphere. By carrying out such a treatment, the moisture and the like adsorbed on the surface of the oxide film 230B are removed. and hydrogen are removed, and the moisture concentration and water content in the oxide film 230A and the oxide film 230B are measured. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower. In this embodiment, the temperature of the heat treatment is 200° C.

[0235] Next, the oxide film 230A, the oxide film 230B, and the conductive film 24 are formed by lithography. 2A is processed into an island shape to form oxide 230a, oxide 230b, and conductive layer 242B. (See Figure 5.) This processing is performed using dry etching or wet etching. Dry etching is suitable for microfabrication. The film 230A, the oxide film 230B, and the conductive film 242A are processed under different conditions. In this step, the area of ​​the insulator 224 that does not overlap with the oxide 230a may be The film thickness in the film area may be thin.

[0236] In the lithography method, first, the resist is exposed to light through a mask. The resist mask is formed by removing or leaving the exposed area using a developer. By etching through the resist mask, a conductor, a semiconductor, an insulator, etc. can be formed as desired. For example, KrF excimer laser light, ArF excimer laser light, The resist is removed using ultraviolet light, EUV (Extreme Ultraviolet) light, etc. A resist mask can be formed by exposing the substrate to light. A liquid immersion technique may be used, in which the substrate is exposed to light by filling the substrate with liquid (for example, water). Alternatively, an electron beam or an ion beam may be used. In this case, the mask is not required. dry etching, wet etching, or dry etching followed by wet etching. Etching is performed, or wet etching is performed followed by dry etching. This can be removed.

[0237] Moreover, instead of the resist mask, a hard mask made of an insulator or a conductor may be used. When a hard mask is used, an insulating film or a conductive film that will be a hard mask material is formed on the conductive film 242A. Then, a resist mask is formed on the hard mask, and the hard mask material is etched. A hard mask having a desired shape can be formed. This can be done after removing the resist mask, or with the resist mask still in place. In the latter case, the resist mask may disappear during etching. After etching, the hard mask may be removed by etching. If the material does not affect subsequent processes or can be used in subsequent processes, it is not necessary to use a hard mask. There's no need to remove it.

[0238] Here, the oxide 230a, the oxide 230b, and the conductive layer 242B are at least partially The oxide 230a, the oxide 230b, and the conductor 205 are formed to overlap each other. The side surface of the conductive layer 242B is preferably approximately perpendicular to the upper surface of the insulator 222. The side surfaces of the oxide 230a, the oxide 230b, and the conductive layer 242B contact the top surface of the insulator 222. On the other hand, since the surface is substantially perpendicular, it is possible to reduce the area and increase the density when providing a plurality of transistors 200. In addition, the oxide 230a, the oxide 230b, and the side surfaces of the conductive layer 242B can be The angle between the upper surface of the insulating body 222 and the upper surface of the insulating body 222 may be small. The side surfaces of the object 230a, the oxide 230b, and the conductive layer 242B and the top surface of the insulator 222 The angle is preferably 60 degrees or more and less than 70 degrees. In this process, the covering property of the insulator 254 etc. is improved, and defects such as voids can be reduced. .

[0239] In addition, a curved surface is formed between the side surface of the conductive layer 242B and the upper surface of the conductive layer 242B. Preferably, the end of the side surface and the end of the top surface are curved. At the end of the conductive layer 242B, the radius of curvature is 3 nm or more and 10 nm or less, preferably The thickness is 5 nm to 6 nm. By not having sharp edges, the film thickness in the subsequent film formation process can be improved. Improved coverage.

[0240] Next, on the insulator 224, the oxide 230a, the oxide 230b, and the conductive layer 242B, An insulating film 254A is formed (see FIG. 6).

[0241] The insulating film 254A is formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulating film 254A has a function of suppressing oxygen permeation. It is preferable to use an insulating film. For example, an oxide film is formed by sputtering or ALD. a film of aluminum nitride, silicon nitride, silicon oxide, or gallium oxide is formed; An aluminum oxide film is formed by sputtering, and then AL is deposited on the aluminum oxide. The aluminum oxide film may be formed by Method D.

[0242] Next, an insulating film that will become the insulator 280 is formed on the insulating film 254A. This can be done using methods such as sputtering, CVD, MBE, PLD, and ALD. In this embodiment, the insulating film is formed by a CVD method or a sputtering method. A silicon oxide film is formed by the above process. Note that a heat treatment may be performed before the formation of the insulating film. The heat treatment is carried out under reduced pressure, and the insulating film is continuously formed without exposure to the atmosphere. By carrying out such a treatment, the particles adsorbed on the surface of the insulating film 254A and the like can be removed. Moisture and hydrogen are removed, and oxide 230a, oxide 230b, and insulator 224 are removed. The water and hydrogen concentrations in the molten metal can be reduced by using the heat treatment conditions described above. It is possible.

[0243] The insulating film may have a multi-layer structure. For example, an oxide film may be formed by sputtering. A silicon oxide film is formed on the silicon oxide film by a CVD method. The structure may be such that:

[0244] Next, the insulating film is subjected to CMP processing to form an insulator 280 with a flat upper surface (see FIG. 6). .).

[0245] Here, microwave treatment may be performed. The microwave treatment is performed in an atmosphere containing oxygen and It is preferable to carry out the microwave treatment under reduced pressure. An electric field is applied to the insulator 280, the oxide 230b, the oxide 230a, etc., and the oxide 230b , and V in oxide 230a O H is oxygen vacancy (V O ) and hydrogen (H) At this time, some of the split hydrogen bonds with the oxygen in the insulator 280 to form water molecules. In addition, some of the hydrogen may be removed by passing through the insulating film 254A to the conductor 24. 2.

[0246] Alternatively, after the microwave treatment, the heating treatment may be carried out while maintaining the reduced pressure state. By performing such a treatment, hydrogen in the insulator 280, the oxide 230b, and the oxide 230a is removed. The heat treatment temperature is set to 300°C or higher and 500°C or lower. It is preferable to do so.

[0247] Furthermore, by performing microwave treatment, the film quality of the insulator 280 is improved, and hydrogen, Therefore, the diffusion of water, impurities, etc. can be suppressed after the formation of the insulator 280. By the process or heat treatment, hydrogen, water, impurities, etc. are oxidized through the insulator 280. Diffusion to the object 230 can be suppressed.

[0248] Next, a part of the insulator 280, a part of the insulating film 254A, and a part of the conductive layer 242B are processed. The opening is formed so as to overlap the conductor 205. By forming the opening, the insulator 254, the conductor 242a, And the conductor 242b is formed (see FIG. 7).

[0249] At this time, it is preferable to thin the oxide 230b in the region overlapping the opening. The amount of film loss in this region corresponds to Lc shown in FIG. 3B. This prevents the formation of a low-resistance region near the top surface of the channel formation region, and reduces the parasitic channel. Therefore, the generation of parasitic channels can be suppressed. Variation can be suppressed.

[0250] It is also preferable to remove a portion of the side surface of the oxide 230b in the region overlapping the opening. The amount of film loss in this region corresponds to We shown in FIG. 3B. This prevents the formation of low-resistance regions near the side surfaces and suppresses the occurrence of parasitic channels. Therefore, it is possible to suppress variations in transistor characteristics caused by parasitic channels. Cut.

[0251] Also, processing of a part of the insulator 280, a part of the insulating film 254A, and a part of the conductive layer 242B For example, a part of the insulator 280 may be dry-etched. The insulating film 254A is processed by a wet etching method, and a part of the insulating film 254A is processed by a wet etching method. A part of B may be processed by dry etching.

[0252] Here, impurities attached to the surface of the oxide 230a, the oxide 230b, etc. or diffused inside the oxide 230a, etc. It is preferable to remove the impurities. The impurities include the insulator 280, the insulating film 254A, and and the components contained in the conductive layer 242B, and the components used in the device used to form the openings. This is caused by components contained in the materials used, or components contained in the gas or liquid used in etching. Examples of such impurities include aluminum, silicon, tantalum, and the like. Examples include fluorine, chlorine, etc.

[0253] In order to remove the above impurities, a cleaning treatment may be carried out. There are various cleaning methods, such as wet cleaning using liquids, plasma treatment using plasma, and cleaning by heat treatment. The above cleaning methods may be combined as appropriate.

[0254] Wet cleaning involves mixing ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid, etc. with carbonated water. Alternatively, the cleaning treatment may be carried out using an aqueous solution diluted with pure water, pure water, carbonated water, or the like. Ultrasonic cleaning may be carried out using these aqueous solutions, pure water, or carbonated water. The above cleaning methods may be combined as appropriate.

[0255] Next, a heat treatment may be performed. The heat treatment is preferably performed in an atmosphere containing oxygen. The heat treatment is carried out under reduced pressure, without exposure to the atmosphere, and the oxide film 23 is continuously formed. By performing such a process, an oxide 23 may be formed on the surface of the silicon dioxide film (see FIG. 8). The moisture and hydrogen adsorbed on the surface of 0b are removed, and further the oxide 230a and the acid The moisture concentration and hydrogen concentration in the oxide 230b can be reduced. In this embodiment, the temperature of the heat treatment is set to 200° C. Let's say.

[0256] The oxide film 230C is formed by sputtering, CVD, MBE, PLD, ALD, etc. The oxide film 230A can be formed according to the desired characteristics of the oxide film 230C. Alternatively, the oxide film 230C may be formed using the same film formation method as that for the oxide film 230B. In this embodiment, the oxide film 230C is formed by sputtering In:Ga:Z The film is formed using an oxide target with an atomic ratio of n=4:2:4.1.

[0257] The oxide film 230C may be a laminated film. For example, In :Ga:Zn=4:2:4.1 [atomic ratio] oxide target was used for film formation, and Even if a film is formed using an oxide target with an atomic ratio of In:Ga:Zn=1:3:4, good.

[0258] During the formation of the oxide film 230C, part of the oxygen contained in the sputtering gas is converted into the oxide 230a. and oxide 230b. Some of the oxygen contained in the sputtering gas may be supplied to the insulator 280. Therefore, the proportion of oxygen contained in the sputtering gas for the oxide film 230C is preferably 70% or more. It is preferable that the ratio is 80% or more, and more preferably 100%.

[0259] Next, a heat treatment may be carried out. The heat treatment is carried out under reduced pressure without exposure to the atmosphere. Subsequently, an insulating film 250A may be formed (see FIG. 8). This removes moisture and hydrogen adsorbed on the surface of the oxide film 230C, and further The moisture concentration and hydrogen concentration in the oxide film 230a, the oxide 230b, and the oxide film 230c are reduced. The temperature for the heat treatment is preferably 100°C or higher and 400°C or lower.

[0260] The insulating film 250A can be formed by a method such as sputtering, CVD, MBE, PLD, or ALD. In this embodiment, the insulating film 250A can be formed by a CVD method. The insulating film 250A is formed at a temperature of 3000 K. The temperature is preferably 50° C. or higher and lower than 450° C., and particularly preferably around 400° C. By depositing the film at 400°C, an insulating film with few impurities can be deposited.

[0261] When the insulator 250 has a two-layer laminated structure, the insulating film and the insulating film that are the lower layer of the insulator 250 The insulating film that is the upper layer of the insulator 250 is preferably formed successively without being exposed to the atmospheric environment. By forming the film without exposing it to the atmosphere, the insulating film that becomes the lower layer of the insulator 250 and the insulating Prevents impurities or moisture from the atmospheric environment from adhering to the insulating film that forms the upper layer of the body 250. The insulating film that is the lower layer of the insulator 250 and the insulating film that is the upper layer of the insulator 250 can be formed by the insulating film. The area around the surface can be kept clean.

[0262] Here, after the insulating film 250A is formed, the insulating film 250A is subjected to micro-processing under an oxygen-containing atmosphere and under reduced pressure. By performing microwave treatment, the electric field generated by the microwave is insulated. The oxide film 250A, oxide film 230C, oxide 230b, oxide 230a, etc. are provided, and the oxide film V in 230C, oxide 230b, and oxide 230a O H to V O and hydrogen At this time, some of the hydrogen atoms that are split off combine with oxygen to form H2O, which acts as an insulator. When removed from film 250A, oxide film 230C, oxide 230b, and oxide 230a, In addition, some of the hydrogen may be transferred to the conductor 242 (conductor 242a and conductor 242b). In this way, microwave treatment can be used to getter the insulating film. Hydrogen concentrations in 250A, oxide film 230C, oxide 230b, and oxide 230a In addition, the oxide 230a, the oxide 230b, and the oxide film 2 V in 30C O H to V O V that can exist after splitting into and hydrogen O oxygen is supplied to With V O can be repaired or compensated for.

[0263] Alternatively, after the microwave treatment, the heating treatment may be carried out while maintaining the reduced pressure state. By performing such a process, the insulating film 250A, the oxide film 230C, the oxide 230b, and The hydrogen in the oxide 230a can be efficiently removed. 242 (conductor 242a and conductor 242b). Alternatively, the step of performing heat treatment while maintaining the reduced pressure after microwave treatment may be repeated multiple times. By repeatedly performing the heat treatment, the oxide film 23 in the insulating film 250A is The hydrogen in the oxide 230a, the oxide 230b, and the oxide 230c can be removed more efficiently. The heat treatment temperature is preferably 300°C or higher and 500°C or lower.

[0264] In addition, by performing microwave treatment, the film quality of the insulating film 250A is improved, and hydrogen Therefore, the formation of the conductive film that becomes the conductor 260 can be prevented. By a post-process such as a membrane or a post-treatment such as a heat treatment, hydrogen, water, Impurities and the like can be prevented from diffusing into the oxide 230b, the oxide 230a, and the like. do.

[0265] Next, the conductive film 260A and the conductive film 260B are formed in this order (see FIG. 9). The conductive film 260B is formed by a sputtering method, a CVD method, an MBE method, a PLD method, an A method, or the like. This can be done by using the LD method or the like. In this embodiment, the conductive film 2 is formed by using the ALD method. After forming the film 60A, the conductive film 260B is formed by using the CVD method.

[0266] Next, the oxide film 230C, the insulating film 250A, the conductive film 260A, and The conductive film 260B is polished until the insulator 280 is exposed, thereby forming the oxide 230c. The insulating material 250 and the conductor 260 (the conductor 260a and the conductor 260b) are formed. (See FIG. 10.) As a result, the oxide 230c is formed in the opening that reaches the oxide 230b. The insulator 250 is disposed so as to cover the walls (sidewalls and bottom surface). The conductor 260 is disposed so as to cover the inner wall of the opening through the oxide 2 30c and the insulator 250 are disposed to fill the opening.

[0267] Next, heat treatment may be performed. In this embodiment, heat treatment is performed in a nitrogen atmosphere at a temperature of 400° C. The heat treatment is performed for a certain period of time. and the hydrogen concentration can be reduced.

[0268] Next, on the oxide 230c, on the insulator 250, on the conductor 260, and on the insulator 280, An insulator 282 is formed (see FIG. 11). The insulator 282 is formed by a sputtering method. The insulator 282 can be formed by a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the film, it is preferable to form an aluminum oxide film by, for example, a sputtering method. The insulator 282 is formed by sputtering in an atmosphere containing oxygen. During the deposition, oxygen can be added to the insulator 280. It is preferable to form a film of the insulator 282 while the conductor 260 is in contact with the upper surface of the conductor 260. By forming the insulator 282, the acid contained in the insulator 280 can be removed in the subsequent heat treatment. This is preferable because it can prevent the element from being absorbed into the conductor 260.

[0269] Next, the insulator 283 is deposited on the insulator 282 (see FIG. 11). This is done using methods such as sputtering, CVD, MBE, PLD, and ALD. As the insulator 283, silicon nitride or silicon nitride oxide can be formed. is preferred.

[0270] Next, heat treatment may be performed. In this embodiment, heat treatment is performed in a nitrogen atmosphere at a temperature of 400° C. The heat treatment is performed for a certain time. The oxygen added by the formation of the insulator 282 is removed by the heat treatment. The oxide 230a and the oxide 230b are then diffused into the insulator 280 and then through the oxide 230c. The heat treatment can be performed after the formation of the insulator 283. However, the heat treatment may be performed after the insulator 282 is formed.

[0271] Next, the insulator 274 may be deposited on the insulator 283. The deposition of the insulator 274 may be performed by sputtering. This can be done using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0272] Next, an insulator 281 may be deposited on the insulator 274. The deposition of the insulator 281 may be performed by sputtering. This can be done using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 281 is formed by depositing silicon nitride by, for example, sputtering. It is preferable that:

[0273] Next, insulator 254, insulator 280, insulator 282, insulator 283, insulator 274, and Openings are formed in the insulating material 281 and the conductive material 242a, reaching the conductive material 242b. The openings may be formed by lithography.

[0274] Next, an insulating film that will become the insulator 241 (insulator 241a and insulator 241b) is formed. The insulating film is anisotropically etched to form the insulator 241. The insulating film is formed by a spat This can be done using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, etc. The insulating film that becomes the insulator 241 is an insulating film that has a function of suppressing oxygen permeation. For example, it is possible to form a silicon nitride film using the PEALD method. Silicon nitride is preferred because it has a high blocking property against hydrogen.

[0275] The anisotropic etching of the insulating film that becomes the insulator 241 may be, for example, dry etching. By providing an insulator 241 on the side wall of the opening, oxygen from the outside can be prevented from entering. Suppressing permeation and preventing oxidation of the conductors 240a and 240b to be formed next. Furthermore, impurities such as water and hydrogen can be released from the conductors 240a and 240b. This can prevent the spread of the virus to other areas.

[0276] Next, a conductive film that will become the conductors 240a and 240b is formed. It is desirable to have a laminated structure including a conductor that has the function of suppressing the permeation of impurities such as hydrogen. For example, tantalum nitride, titanium nitride, etc., and tungsten, molybdenum, copper, etc. The conductive film can be formed by a method such as sputtering, CVD, This can be done using MBE, PLD, ALD, or the like.

[0277] Next, a CMP process is performed to remove a portion of the conductive film that will become the conductor 240a and the conductor 240b. The conductive film is then removed to expose the insulator 281. As a result, the conductive film remains only in the opening. By doing so, it is possible to form the conductors 240a and 240b with flat upper surfaces (see FIG. 1.) Note that the CMP process may remove a part of the insulator 281. .

[0278] Next, a conductive film that will become the conductor 246 is formed. The conductive film is formed by a sputtering method, This can be done using a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0279] Next, the conductive film that will become the conductor 246 is processed by lithography to form the conductor 240a. Conductor 246a contacts the upper surface of conductor 240b, and conductor 246b contacts the upper surface of conductor 240b. (See Figure 1.)

[0280] Through the above steps, a semiconductor device including the transistor 200 shown in FIG. 1 can be manufactured. As shown in FIGS. 4 to 11, the semiconductor device can be manufactured by the method for manufacturing the semiconductor device described in this embodiment mode. The transistor 200 can be fabricated in this manner.

[0281] <Modification of Semiconductor Device> An example of a semiconductor device according to one embodiment of the present invention will be described below with reference to FIGS. 12 and 13. I will explain.

[0282] [Semiconductor Device Variation 1] 12A shows a top view of the semiconductor device. Also, FIG. 12B shows a cross-sectional view of the semiconductor device. 12A. Also, FIG. 12C is a cross-sectional view corresponding to the portion indicated by the dashed line. 12A. Also, FIG. 12D is a cross-sectional view corresponding to the portion indicated by the dashed line in FIG. 12A. 12A is a cross-sectional view corresponding to the portion indicated by the dashed line in FIG. For this reason, some elements have been omitted.

[0283] In the semiconductor device shown in FIG. 12, the semiconductor device shown in <Configuration example of semiconductor device> The same reference numerals are used to designate structures that have the same functions as the structures that compose them. The materials used for the construction of the semiconductor device are explained in detail in <Examples of the construction of the semiconductor device>. It is possible.

[0284] The semiconductor device shown in FIG. 12 is a modified example of the semiconductor device shown in FIG. The semiconductor device shown in FIG. 1 differs from the semiconductor device shown in FIG. 1 in the shape of the insulator 283. 43 (oxide 243a and oxide 243b). 30c and the insulator 254 are each provided as a two-layer laminated structure. do.

[0285] In the semiconductor device shown in FIG. 12, the insulators 214, 216, 222, and 22 4, insulator 254, insulator 280, and insulator 282 are patterned, and insulating In other words, the insulator 283 is formed on the insulator 282. the face and side, the side of the insulator 280, the side of the insulator 254, and the side of the insulator 224 , the side of the insulator 222, the side of the insulator 216, the side of the insulator 214, and the insulator 212 This allows the insulators 214, 216, and 217, including the oxide 230, to contact the upper surface of the insulators 214, 216, and 217. The insulators 222, 224, 254, 280, and 282 are insulating The transistor 2 is isolated from the outside by the insulator 283 and the insulator 212. 00 is placed in the area sealed by the insulator 283 and the insulator 212 .

[0286] The insulators 212 and 283 are formed of at least hydrogen (e.g., hydrogen atoms, hydrogen molecules, etc.). For example, the insulator 212 has a high ability to suppress the diffusion of water molecules. The insulator 283 is preferably silicon nitride or silicon nitride oxide, which has a higher hydrogen barrier property. It is preferable to use a recombinant.

[0287] By adopting the above-mentioned configuration, hydrogen contained outside the sealed region is transferred to the sealed region. It is possible to prevent the mixture from being mixed into the

[0288] In addition, in the transistor 200 shown in FIG. 12, the insulators 212, 214, and 28 Although the present invention is not limited to this, the present invention is not limited to this. For example, the insulators 212, 214, and 283 may be configured as a laminated structure of two or more layers. It may be configured so that

[0289] 12, the transistor 200 includes a conductor 242 (a conductor 242a and a conductor Between the oxide 230 and the substrate 242b, an oxide 24 having a function of suppressing oxygen permeation is provided. 3 (oxide 243a and oxide 243b). Between the conductor 242 and the oxide 230b, an oxide having a function of suppressing oxygen permeation is provided. By disposing the oxide 243, the electrical resistance between the conductor 242 and the oxide 230b is reduced. This structure is preferable because it improves the electrical characteristics and This can improve the reliability of the transistor 200.

[0290] The oxide 243 may be a metal oxide containing an element M. In particular, the element M is aluminum. Aluminum, gallium, yttrium, or tin can be used. Oxide 243 is an oxide It is preferable that the concentration of element M is higher than that of oxide 230b. Alternatively, the oxide 243 may be a metal oxide such as In-M-Zn oxide. Specifically, in the metal oxide used for the oxide 243, The atomic ratio of the element M to In in the metal oxide used for the oxide 230b is It is preferable that the atomic ratio of M is larger than that of M. In addition, the thickness of the oxide 243 is 0.5 nm or more. Preferably 5 nm or less, more preferably 1 nm to 3 nm, and even more preferably 1 nm The oxide 243 preferably has a crystallinity. When 3 has crystallinity, the release of oxygen in the oxide 230 can be suitably suppressed. For example, if the oxide 243 has a hexagonal crystal structure, the oxygen in the oxide 230 This may be able to suppress the release of

[0291] In a cross-sectional view of the transistor 200 in the channel length direction, the area overlapping with the conductor 260 The lower surface of the oxide 230c in the region is covered with oxide 243 (oxide 243a and oxide 243b). or under the oxide 243 (oxide 243a and oxide 243b). It is preferable that the oxide 230b and the oxide 230c are lower than the surface. The impurities near the interface with region 30c are removed, and a low resistance region formed near the top surface of region 234 is formed. For example, in a cross-sectional view of the transistor 200 in the channel length direction, , when the lower surface of the insulator 224 is used as a reference, the height of the lower surface of the oxide 243 and the height of the conductor 260 The difference in height between the lower surface of the oxide 230c in the overlapping region and the oxide 230c is preferably 0 nm or more and 10 nm or less. The thickness is preferably 0 nm or more and 5 nm or less, and more preferably 0 nm or more and 3 nm or less.

[0292] In the transistor 200 shown in FIG. 12, the oxide 230c is formed by mixing the oxide 230c1 and the oxide 230c2. 2 shows a configuration in which a layer of a metal oxide 230c1 and a layer of a metal oxide 230c2 are laminated.

[0293] The oxide 230c2 is a metal oxide containing a small amount of the metal element that constitutes the metal oxide used in the oxide 230c1. It is preferable that the metal element contains at least one of the metal elements, and it is more preferable that the metal element contains all of the metal elements. For example, an In-Ga-Zn oxide or an In-Zn oxide is used as the oxide 230c1. The oxide 230c2 may be an In-Ga-Zn oxide, a Ga-Zn oxide, or a gallium oxide. This allows the oxide 230c1 and the oxide 230c2 to be bonded to each other. This can reduce the defect level density.

[0294] The conduction band minimum of the oxide 230a and the oxide 230c2 is higher than that of the oxide 230b and the oxide 230c2. It is preferable that the oxide 230c1 is closer to the vacuum level than the bottom of the conduction band of the oxide 230c1. The electron affinity of oxide 230a and oxide 230c2 is In this case, the oxide 230c2 has an electron affinity smaller than that of the oxide 23 The metal oxide used for oxide 230a is used, and the oxide 230c1 is used for oxide 230b. It is preferable to use a metal oxide that can be used as the main carrier path. In some cases, not only the oxide 230b but also the oxide 230c1 may become the main path of carriers. By using a metal oxide that can be used for the oxide 230b for the oxide 230c1, The effective channel length at the upper surface of the channel forming region is prevented from increasing, and the transistor This can suppress a decrease in the on-current of the capacitor 200.

[0295] Specifically, the oxide 230c1 has an atomic ratio of In:Ga:Zn=4:2:3. Metal oxides with an atomic ratio of In:Ga:Zn=5:1:6, or In-Zn oxides The oxide 230c2 was prepared by mixing In:Ga:Zn=1:3:4 [atomic ratio], Ga: Zn=2:1 [atomic ratio], Ga:Zn=2:5 [atomic ratio] or gallium oxide metal An oxide may be used.

[0296] The oxide 230c2 has a higher resistance to oxygen diffusion or permeation than the oxide 230c1. The oxide 230 is preferably a metal oxide. By providing c2, oxygen contained in the insulator 280 is prevented from diffusing into the insulator 250. Therefore, the oxygen can be transferred to the oxide 230 via the oxide 230c1. b can be efficiently supplied.

[0297] In addition, in the metal oxide used for the oxide 230c2, I with respect to the metal element that is the main component The atomic ratio of n is the metal element that is the main component in the metal oxide used for the oxide 230c1. By making the atomic ratio of In smaller than the atomic ratio of In to In, the diffusion of In into the insulator 250 is suppressed. The insulator 250 functions as a gate insulator, so that In is If oxide 230 is mixed in, it will cause transistor characteristics to deteriorate. By providing the oxide 230c2 between the c1 and the insulator 250, a highly reliable semiconductor device can be obtained. It is possible to provide the following.

[0298] The oxide 230c1 may be provided for each transistor 200. The oxide 230c1 of the transistor 200 and the oxide 230c2 of the transistor 200 adjacent to the transistor 200 The oxide 230c1 of the transistor 200 may not be in contact with the oxide 230c1 of the transistor 200. 0c1, and the oxide 230c1 of the transistor 200 adjacent to the transistor 200. , may be separated. In other words, the oxide 230c1 may separate the transistor 200 and the A configuration in which the transistor 200 is not disposed between adjacent transistors 200 may also be adopted. stomach.

[0299] In a semiconductor device in which a plurality of transistors 200 are arranged in the channel width direction, By this configuration, the oxide 230c is independently provided in the transistor 200. Therefore, the transistor 200 and the transistor 20 adjacent to the transistor 200 0, the occurrence of a parasitic transistor is suppressed, and the occurrence of the above-mentioned leak path is suppressed. Therefore, it has good electrical properties and can be miniaturized or highly integrated. Therefore, it is possible to provide a semiconductor device that can perform the above-described functions.

[0300] For example, the transistors 200 are arranged opposite to each other in the channel width direction. The side edge of the oxide 230c1 of the transistor 200 and the transistor adjacent to the transistor 200 When the distance between the side edge of the oxide 230c1 of the capacitor 200 and the oxide 230c1 is represented as L1, L1 is set to be greater than 0 nm. In addition, in the channel width direction of the transistor 200, The side edge of the oxide 230a of the transistor 200 and the transistor adjacent to the transistor 200 If the distance between the side edge of the oxide 230a of the transistor 200 and the transistor 200 is represented as L2, The value of the ratio of L1 (L1 / L2) is preferably greater than 0 and less than 1, more preferably 0.1 It is more preferable that L2 is 0.2 or more and 0.8 or less. Opposite side edges of the oxide 230b of the transistor 200 and the transistor 200 It may be the distance between the side edge of the oxide 230b of the adjacent transistor 200.

[0301] By reducing the ratio of L1 to L2 (L1 / L2), the oxide 230c1 Between a transistor 200 and a transistor 200 adjacent to the transistor 200 Even if the position of the region where the oxide 230c1 of the transistor 200 is not located is shifted, the oxide 230c1 of the transistor 200 and the region where the oxide 230c1 is located are not shifted. The oxide 230c1 of the transistor 200 adjacent to the transistor 200 is separated. It is possible.

[0302] In addition, by increasing the ratio of L1 to L2 (L1 / L2), the transistor 2 Even if the distance between the transistor 200 and the transistor 200 adjacent to the transistor 200 is narrowed, It is possible to secure a small processing width, which allows for further miniaturization or higher integration of semiconductor devices. It is possible.

[0303] The conductor 260, the insulator 250, and the oxide 230c2 are formed on the adjacent transistor. The conductor 260 of the transistor 200 may be shared among the transistors 200. The conductor 260 of the transistor 200 adjacent to the transistor 200 is set to be continuous. The insulator 250 of the transistor 200 has a region where the insulator 250 is formed. 200 has a region formed continuously with the insulator 250 of the adjacent transistor 200. The oxide 230c2 of the transistor 200 is adjacent to the transistor 200. It has a region that is continuous with the oxide 230c2 of the transistor 200.

[0304] In addition, by adopting the above-described structure, the oxide 230c2 is The insulator 224 is disposed between the adjacent transistors 200. do.

[0305] As with the oxide 230c1, the oxide 230c2 of the transistor 200 and the oxide 230c2 of the transistor The oxide 230c2 of the transistor 200 adjacent to the transistor 200 may be spaced apart. At this time, the insulator 250 is connected to the transistor 200 and the adjacent transistor 200. The insulator 224 is located between the transistor 200 and the insulator 224 .

[0306] In the transistor 200 shown in FIG. 12, the insulator 254 is made up of an insulator 254a and an insulator 254a and 254b are laminated. The material and film forming method of 4b are described in the section on insulator 25 in the <Detailed configuration of the semiconductor device>. The descriptions of the lower layer of insulator 4 and the upper layer of insulator 254 can be referred to.

[0307] Alternatively, the insulator 254 may be omitted, and a barrier layer may be formed between the upper surface of the conductor 242 and the insulator 280. By using such a structure, the insulation by the conductor 242 can be prevented. The absorption of excess oxygen contained in the conductive material 280 can be suppressed. By suppressing this, it is possible to suppress an increase in contact resistance between the transistor 200 and the wiring. Therefore, the transistor 200 can have good electrical characteristics and reliability. do.

[0308] Therefore, it is preferable that the insulator has a function of suppressing the diffusion of oxygen. Preferably, the insulator has a function of suppressing oxygen diffusion more than the insulator 280. .

[0309] The insulator may be, for example, an oxide of one or both of aluminum and hafnium. In particular, it is preferable to form an aluminum oxide film by the ALD method. By forming it using the ALD method, defects such as cracks and pinholes are reduced. In addition, a film having a uniform thickness can be formed as the insulator. For example, an insulator containing aluminum nitride may be used.

[0310] [Variation 2 of the semiconductor device] 13A and 13B show a plurality of transistors (transistors 200_1 to 200_2). The insulator 283 and the insulator 212 are used to enclose and seal the insulator 200. 13A and 13B, the transistors 200_1 to 200_2 are shown. The resistors 200_n appear to be aligned in the channel length direction, but this is not the only possible arrangement. The transistors 200_1 to 200_n are not They may be arranged in a line, in a matrix, or randomly. It may also be used.

[0311] As shown in FIG. 13A, a plurality of transistors (transistor 200_1 to transistor 200_2) are connected to each other. 200_n), the portion where the insulator 283 and the insulator 212 contact each other (hereinafter, the sealing portion The sealing portion 265 is formed on the plurality of transistors. This structure is formed so as to surround the transistor (also called a group of transistors). In this way, the plurality of transistors can be enclosed by the insulator 283 and the insulator 212. That is, the four sides and the top of the plurality of transistors are covered with the insulators 283 and 281. However, the lower part can be enclosed by the insulator 212. A plurality of transistor groups are provided on the substrate.

[0312] Here, the distance between the sealing portion 265 and the oxide 230 closest to the sealing portion 265 is short. For example, the distance between the sealing portion 265 and the oxide 230 closest to the sealing portion 265 is preferably The thickness is preferably 1 μm or less, and more preferably 500 nm or less. Therefore, the volume of the insulator 280 sealed in the insulator 283 can be reduced. The amount of hydrogen contained in the insulating body 280 can be reduced.

[0313] In addition, a dicing line (scribe line, dividing line, or cutting line) is formed on the sealing portion 265. The substrate may be divided at the dicing line. Therefore, the group of transistors enclosed by the sealing portion 265 can be extracted as one chip. becomes.

[0314] In addition, in FIG. 13A, a plurality of transistors (transistor 200_1 to transistor 200_2) are 00_n) is surrounded by one sealing portion 265, but the present invention is not limited to this. As shown in FIG. 13B, a plurality of transistors (transistors 200_1 to 200_2) are connected to the same transistors. In FIG. 13B, the plurality of transistors (transistors 200_n) may be surrounded by a plurality of sealing portions. The transistor is surrounded by a sealing portion 265a and is further surrounded by an outer sealing portion 265b. do.

[0315] In this way, by using a configuration in which a plurality of transistors are surrounded by a plurality of sealing portions, the insulator 283 Since the area where the insulator 283 and the insulator 212 come into contact with each other increases, the adhesion between the insulator 283 and the insulator 212 is improved. This allows the plurality of transistors to be sealed more reliably. This can be done.

[0316] In this case, a dicing line may be provided so as to overlap the sealing portion 265a or the sealing portion 265b. Alternatively, a dicing line may be provided between the sealing portion 265a and the sealing portion 265b.

[0317] 13A and 13B, the insulator 212 is formed by a lower layer of the insulator 212 and an insulator For example, the lower layer of the insulator 212 is Silicon nitride is deposited by PECVD and sputtered as the top layer of the insulator 212. The silicon nitride film is formed by the method. Since the film can be formed at a faster rate than the upper layer, productivity can be improved. The hydrogen concentration in the upper layer of the insulator 212, which is located closer to the oxide 230 than the lower layer of 212, is The thickness of the insulator 212 can be reduced from that of the lower layer. By using an insulator that is difficult for impurities such as water and hydrogen to penetrate, The diffusion of impurities such as water and hydrogen from layers below 212 (not shown) can be suppressed. In addition, the insulator 212 is made of an insulator that is difficult for copper to penetrate, such as silicon nitride. Therefore, even if a metal that easily diffuses, such as copper, is used for the conductor below the insulator 212, the metal The upward diffusion through the insulator 212 can be suppressed.

[0318] The present invention is not limited to the above configuration, and may be applied to any of the lower layer of the insulator 212 and the upper layer of the insulator 212. Alternatively, a single layer structure may be provided with either one of the insulating layers. However, the present invention is not limited to this structure and may be applied to a case where the insulator 214 is not provided. A simple structure may also be used.

[0319] According to one embodiment of the present invention, a semiconductor device with little variation in transistor characteristics is provided. According to one embodiment of the present invention, a semiconductor device with large on-state current can be provided. According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. This can be done.

[0320] The configurations, methods, etc. shown in the present embodiment may be used in conjunction with the configurations, methods, etc. shown in other embodiments, examples, etc. It can be used in combination with other methods as appropriate.

[0321] (Embodiment 2) In this embodiment, one mode of a semiconductor device will be described with reference to FIGS.

[0322] [Storage device 1] An example of a semiconductor device (memory device) according to one embodiment of the present invention is illustrated in FIG. In the semiconductor device, the transistor 200 is provided above the transistor 300, and the capacitance element 1 00 is provided above the transistor 300 and the transistor 200. The transistor 200 may be the transistor 200 described in the previous embodiment. Therefore, for the transistor 200 and the layer including the transistor 200, The description of the previous embodiments can be referred to.

[0323] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. The transistor 200 can be used for a memory device because its off-state current is small. This allows the memory contents to be retained for a long period of time. Since no refresh is required or the frequency of refresh operations is extremely low, the Power consumption can be reduced significantly.

[0324] In the semiconductor device shown in FIG. 14, the wiring 1001 is electrically connected to the source of the transistor 300. , and the wiring 1002 is electrically connected to the drain of the transistor 300. The wiring 1003 is electrically connected to one of the source and drain of the transistor 200. The wiring 1004 is electrically connected to the first gate of the transistor 200, and the wiring 1005 is electrically connected to the first gate of the transistor 200. 06 is electrically connected to the second gate of the transistor 200. The gate of transistor 300 and the other of the source and drain of transistor 200 are connected to a capacitor. The wiring 1005 is electrically connected to one of the electrodes of the capacitor element 100 . It is electrically connected to the

[0325] The memory device shown in FIG. 14 is configured to form a memory cell array by arranging the memory cells in a matrix. It can be achieved.

[0326] <Transistor 300> The transistor 300 is provided on a substrate 311 and includes a conductor 316 that functions as a gate; an insulator 315 that functions as a gate insulator, and a semiconductor region 313 that is part of the substrate 311; , and low resistance region 314a which functions as a source region or a drain region, and low resistance region 314b which functions as a The transistor 300 may be a p-channel or n-channel transistor. Either of the above is acceptable.

[0327] Here, the transistor 300 shown in FIG. 14 has a semiconductor region 313 (substrate) where a channel is formed. The side and top surfaces of the semiconductor region 313 are insulated. The conductor 316 is provided so as to cover the conductor 315. Such a transistor 300 may be formed by forming a protrusion on a semiconductor substrate. It is also called a FIN type transistor because it uses the upper part of the protrusion. In addition, the insulating layer may have an insulating material that functions as a mask for forming the protrusions. In the previous section, we showed how to form a protrusion by processing a part of the semiconductor substrate. A semiconductor film having a convex shape may be formed.

[0328] The transistor 300 shown in FIG. 14 is an example, and the structure is not limited to this. An appropriate transistor may be used depending on the type and driving method.

[0329] <Capacitor element 100> The capacitor 100 is provided above the transistor 200. A conductor 110 functions as an electrode, a conductor 120 functions as a second electrode, and a dielectric and an insulator 130 that functions as a

[0330] Also, for example, the conductor 112 provided on the conductor 240 and the conductor 110 are formed at the same time. Note that the conductor 112 can be formed in the capacitor 100, the transistor 200, or The transistor 300 functions as a plug or wiring that is electrically connected to the transistor 300 .

[0331] In FIG. 14, the conductor 112 and the conductor 110 are shown as single-layer structures, but the present invention is not limited to this structure. For example, a conductive material having a barrier property and a conductive material having a high conductivity may be used. Conductors with barrier properties and high conductivity have good adhesion to the conductor. It may also be made highly conductive.

[0332] The insulator 130 may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, Silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, nitride Aluminum, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride The insulating layer 10 may be formed as a laminated layer or a single layer.

[0333] For example, the insulator 130 may be made of a material with high dielectric strength, such as silicon oxynitride, and a material with high dielectric constant It is preferable to use a laminated structure with a (high-k) material. 100 has a high dielectric constant (high-k) insulator, ensuring sufficient capacitance. By using an insulator with a high dielectric strength, the dielectric strength is improved, and electrostatic breakdown of the capacitance element 100 is reduced. can be suppressed.

[0334] In addition, oxide gas is used as an insulator for high dielectric constant (high-k) materials (materials with high relative dielectric constant). oxides containing aluminum, hafnium oxide, zirconium oxide, aluminum and hafnium oxides with aluminum and hafnium; oxide nitrides with silicon and hafnium oxides having silicon and hafnium, oxide nitrides having silicon and hafnium, Examples include nitrides containing Zn.

[0335] On the other hand, materials with high dielectric strength (materials with low dielectric constant) include silicon oxide and oxynitride. Silicon, silicon oxynitride, silicon nitride, silicon oxide doped with fluorine, and carbon doped silicon oxide doped with carbon and nitrogen, silicon oxide with vacancies Examples include acrylic and resin.

[0336] <Wiring layer> Between each structure, a wiring layer including an interlayer film, wiring, plugs, etc. may be provided. In addition, multiple wiring layers can be provided depending on the design. In the case of a conductor having a function as a In addition, in this specification and the like, the wiring and the plug electrically connected to the wiring are integrated. That is, when a part of the conductor functions as a wiring, or when a part of the conductor functions as a plate, It may also function as a rug.

[0337] For example, an insulator 320, an insulator 322, an insulator 323, and an insulator 324 are formed on the transistor 300 as interlayer films. The insulating material 320, the insulating material 324, and the insulating material 326 are laminated in this order. The insulator 322, the insulator 324, and the insulator 326 are connected to the capacitor element 100 or the transistor. Conductors 328 and 330, which are electrically connected to the capacitor 200, are embedded in the insulating film. The conductors 328 and 330 function as plugs or wiring.

[0338] In addition, the insulator that functions as an interlayer film also functions as a planarizing film that covers the uneven shape underneath. For example, the top surface of the insulator 322 may be subjected to chemical mechanical polishing (C The surface may be planarized by a planarization process using a MP method or the like.

[0339] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. An insulator 350, an insulator 352, and an insulator 354 are stacked in this order. In addition, a conductor 356 is formed in the insulators 350, 352, and 354. The conductor 356 functions as a plug or a wiring.

[0340] Similarly, the insulators 210, 212, 214, and 216 are made of conductive materials. 218, the conductors (conductors 205) that constitute the transistor 200 are embedded. Note that the conductor 218 is electrically connected to the capacitor 100 or the transistor 300. The conductor 120 and the insulator 130 function as a plug or wiring. On top, an insulator 150 is provided.

[0341] Here, similar to the insulator 241 shown in the above embodiment, the conductor 21 functioning as a plug An insulator 217 is provided in contact with the side surface of the insulator 210. 12, insulator 214, and insulator 216 are provided in contact with the inner walls of the openings formed therein. That is, the insulator 217 is made up of the conductor 218, the insulator 210, the insulator 212, and the insulator 213. 14 and the insulator 216. 8, the insulator 217 is formed in contact with the side surface of the conductor 205. In some cases, this can be achieved.

[0342] The insulator 217 may be, for example, silicon nitride, aluminum oxide, silicon nitride oxide, or the like. The insulator 217 is made of the insulator 210, the insulator 212, and the insulator 211. 4, insulator 216, and insulator 222, so that insulator 210, insulator Impurities such as water and hydrogen contained in 216 are mixed into oxide 230 through conductor 218. In particular, silicon nitride has a blocking property against hydrogen. In addition, the oxygen contained in the insulator 210 or the insulator 216 is preferably contained in the conductor 2. It can prevent it from being absorbed by 18.

[0343] Insulator 217 can be formed in a similar manner to insulator 241. For example, PEAL Using the D method, a silicon nitride film is formed and anisotropic etching is used to reach the conductor 356. An opening may be formed.

[0344] Insulators that can be used as the interlayer film include oxides, nitrides, and oxides having insulating properties. These include nitrides, nitride oxides, metal oxides, metal oxide nitrides, and metal nitride oxides.

[0345] For example, by using a material with a low relative dielectric constant for the insulator that functions as an interlayer film, Therefore, depending on the function of the insulator, the material can be It's good to choose.

[0346] For example, the insulators 150, 210, 352, and 354 have a relative dielectric constant of It is preferable to have a low insulating material. For example, the insulating material may be silicon nitride oxide, silicon nitride, or the like. Silicon, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon and nitrogen It is preferable to use silicon oxide doped with silicon dioxide, silicon oxide having pores, resin, etc. Alternatively, the insulator may be silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or the like. Silicon, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon and nitrogen The laminated structure is made of silicon oxide to which the compound is added or silicon oxide having pores, and a resin. Silicon oxide and silicon oxynitride are thermally stable, so they are preferable for use in resins. By combining with a resin, it is possible to obtain a thermally stable laminated structure with a low relative dielectric constant. Examples of the fat include polyester, polyolefin, polyamide (nylon, aramid) etc.), polyimide, polycarbonate, acrylic, etc.

[0347] In addition, a transistor using an oxide semiconductor suppresses the permeation of impurities such as hydrogen and oxygen. By surrounding the transistor with an insulator that has the function of stabilizing the electrical characteristics of the transistor, Therefore, impurities such as hydrogen are present in the insulators 214, 212, and 350. An insulator having a function of suppressing the permeation of substances and oxygen may be used.

[0348] Examples of insulators that have the function of suppressing the permeation of impurities such as hydrogen and oxygen include porosity. Uron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine , argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium Insulators containing titanium, hafnium or tantalum may be used in a single layer or in a multilayer configuration. Specifically, it is an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. Aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide aluminum, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide or tantalum oxide Metal oxides such as silicon dioxide, silicon nitride oxide, silicon nitride, etc. can be used.

[0349] Conductors that can be used for wiring and plugs include aluminum, chromium, copper, silver, and gold. , platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium Smoke, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium Materials containing one or more metal elements selected from the group consisting of ammonium, phosphate, and phosphates can be used. Semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements, Silicides such as nickel silicide may also be used.

[0350] For example, conductor 328, conductor 330, conductor 356, conductor 218, conductor 112, etc. Examples of the materials include metal materials, alloy materials, metal nitride materials, and metal oxide materials formed from the above materials. Conductive materials such as these can be used in a single layer or in a laminated form. It is preferable to use a high melting point material such as tungsten or molybdenum. Alternatively, it may be formed of a low-resistance conductive material such as aluminum or copper. By using a low-resistance conductive material, the wiring resistance can be reduced.

[0351] <Wiring or plug in layer provided with oxide semiconductor> When an oxide semiconductor is used for the transistor 200, excess oxide is present near the oxide semiconductor. In this case, the insulator having the excess oxygen region and the An insulator having a barrier property is provided between the insulator having the excess oxygen region and the conductor provided thereon. It is preferable to do so.

[0352] For example, in FIG. 14, insulator 224 and insulator 280 have excess oxygen, and conductor 24 0, an insulator 241 is preferably provided between the insulator 241 and the insulator 222. The insulator 224 and the transistor 200 are in contact with each other. The insulator 241 can be used to seal the circuit board. It is preferable that the insulator 241 also contacts a part of the insulator 274. By extending the insulating layer, the diffusion of oxygen and impurities can be further suppressed.

[0353] In other words, by providing the insulator 241, the excess acid contained in the insulators 224 and 280 can be reduced. It is possible to prevent the absorption of the element by the conductor 240. By this, hydrogen, which is an impurity, diffuses into the transistor 200 through the conductor 240. This can prevent this from happening.

[0354] The insulator 241 has a function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. For example, silicon nitride, silicon oxide nitride, silicon oxide, It is preferable to use aluminum oxide, hafnium oxide, etc. In particular, silicon nitride is a In addition, for example, magnesium oxide, Gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide Metal oxides such as neodymium oxide and tantalum oxide can be used.

[0355] The above is a description of the configuration example. By using this configuration, In semiconductor devices using transistors, fluctuations in electrical characteristics are suppressed and reliability is improved. In addition, a transistor including an oxide semiconductor with high on-state current can be provided. In addition, a transistor including an oxide semiconductor and having a low off-state current can be provided. Furthermore, a semiconductor device with reduced power consumption can be provided.

[0356] [Storage device 2] An example of a memory device using a semiconductor device according to one embodiment of the present invention is shown in FIG. The memory device shown includes the transistor 200, the transistor 300, and the capacitor shown in FIG. In addition to the semiconductor device having the element 100, a transistor 400 is also included.

[0357] The transistor 400 can control the second gate voltage of the transistor 200. For example, the first gate and the second gate of the transistor 400 are connected to the source and the diode. and connect the source of transistor 400 to the second gate of transistor 200. In this configuration, when the second gate of the transistor 200 is held at a negative potential, The first gate-source voltage and the second gate-source voltage of the transistor 400 are In the transistor 400, the second gate voltage and the first gate voltage are The drain current at 0V is very small, so the transistor 200 and the transistor Even if the power supply to the transistor 400 is not provided, the negative potential of the second gate of the transistor 200 can be maintained for a long time. This allows transistor 200 and transistor 40 A storage device with 0 can retain its contents for a long period of time.

[0358] Therefore, in FIG. 15, the wiring 1001 is electrically connected to the source of the transistor 300. The wiring 1002 is electrically connected to the drain of the transistor 300. The line 1003 is electrically connected to one of the source and drain of the transistor 200. The line 1004 is electrically connected to the first gate of the transistor 200, and the wiring 1006 is electrically connected to the first gate of the transistor 200. The second gate of the transistor 200 is electrically connected to the second gate of the transistor 30. The gate of the transistor 200 and the other of the source and drain of the transistor 200 are connected to the capacitance element 10 The wiring 1005 is electrically connected to one of the electrodes of the capacitor 100. The wiring 1007 is electrically connected to the source of the transistor 400. The wiring 1008 is electrically connected to the first gate of the transistor 400, and the wiring 1009 is The wiring 1010 is electrically connected to the second gate of the transistor 400. 00. Here, the wiring 1006, the wiring 1007, the wiring 1008 and wiring 1009 are electrically connected.

[0359] 15 is arranged in a matrix, similar to the storage device shown in FIG. By doing so, a memory cell array can be configured. can control the second gate voltages of the plurality of transistors 200. The number of transistors 400 may be smaller than the number of transistors 200 .

[0360] <Transistor 400> The transistor 400 is formed in the same layer as the transistor 200 and is fabricated in parallel. The transistor 400 functions as a first gate. The conductor 460 (conductor 460a and conductor 460b) functions as a second gate. The conductor 405 functions as a gate insulating layer, the insulator 222 functions as a gate insulating layer, the insulator 224 functions as a gate insulating layer, and the and an insulator 450, an oxide 430c having a channel forming region, and a gate electrode 430b acting as a source. The conductor 442a, the oxide 431a, and the oxide 431b, and the conductor functioning as a drain The conductor 442b, the oxide 432a, and the oxide 432b, and the conductor acting as a plug 440 (conductor 440a and conductor 440b) and the barrier insulation of conductor 440 and an insulator 441 (insulator 441a and insulator 441b) that functions as a membrane. .

[0361] The conductor 405 and the conductor 205 are formed in the same layer. The oxide 432a and the oxide 230a are formed in the same layer, and the oxide 431b and the oxide The conductor 432b and the oxide 230b are formed in the same layer. The oxide 430c and the conductor 242 are formed in the same layer. Insulator 450 and insulator 250 are formed in the same layer. The conductor 460 and the conductor 260 are formed in the same layer. The insulator 441 and the insulator 241 are formed in the same layer. do.

[0362] It should be noted that structures formed in the same layer can be formed simultaneously. For example, oxide 43 Oc can be formed by processing an oxide film that will become oxide 230c.

[0363] The oxide 430c that functions as the active layer of the transistor 400 is similar to the oxide 230. In addition, oxygen vacancies are reduced, and impurities such as hydrogen and water are reduced. The threshold voltage of the transistor 400 is set to be greater than 0V, the off-current is reduced, and the second gate voltage Furthermore, the drain current when the first gate voltage is 0V can be made very small.

[0364] <Dicing line> In the following, a large-area substrate is divided into individual semiconductor elements, thereby forming a plurality of semiconductor devices into chips. Dicing lines (scribe lines, dividing lines, The cutting method is as follows: After forming grooves (dicing lines) on the substrate to separate the semiconductor elements, dicing is performed. In some cases, the semiconductor device is cut on the production line and divided (divided) into a plurality of semiconductor devices.

[0365] Here, for example, as shown in FIG. 15, the area where the insulator 254 and the insulator 222 contact each other is It is preferable to design it so that it becomes a dicing line. 00, and dicing lines provided on the outer edges of transistor 400. An opening is provided in the insulator 224 near the region where the insulator 224 is to be formed. An insulator 254 is provided to cover it.

[0366] That is, the insulator 222 and the insulator 254 are in contact with each other through the opening provided in the insulator 224. For example, the insulators 222 and 254 are made of the same material and by the same method. The insulator 222 and the insulator 254 may be formed using the same material and method. For example, it is preferable to use aluminum oxide. stomach.

[0367] With this structure, the insulator 222 and the insulator 254 are insulated from the insulator 224 and the transistor 2 00 and the transistor 400. The insulator 222 and the insulator 254 has the function of suppressing the diffusion of oxygen, hydrogen, and water, and therefore is used in this embodiment. The substrate is divided into individual circuit regions each having a semiconductor element formed thereon, thereby forming a plurality of chips. Even if the substrate is processed properly, impurities such as hydrogen and water can enter from the side of the divided substrate, causing damage to the transistors. Diffusion to the gate 200 and the transistor 400 can be prevented.

[0368] In addition, this structure allows excess oxygen in the insulator 224 to penetrate the insulator 254 and the insulator 222. Therefore, the excess oxygen in the insulator 224 can be prevented from diffusing to the outside through the insulator 224. The oxide that efficiently forms the channel in transistor 200 or transistor 400 The oxygen is supplied to the transistor 200 or the transistor 400. This reduces the oxygen vacancies in the oxide in which the channel is formed. The oxide on which the channel in transistor 200 or transistor 400 is formed is missing. An oxide semiconductor having a low density of recessed states and stable characteristics can be obtained. The fluctuation of the electrical characteristics of the transistor 200 or 400 is suppressed, and reliability is improved. can be improved.

[0369] The configurations, methods, etc. shown in this embodiment may be used in combination with the configurations, structures, It can be used in combination with other methods as appropriate.

[0370] (Embodiment 3) In this embodiment, a semiconductor device using an oxide according to one embodiment of the present invention will be described with reference to FIGS. 16 and 17. Transistors used in the semiconductor device (hereinafter sometimes referred to as OS transistors) and capacitors This section explains the storage device to which the OS is applied (hereinafter, sometimes referred to as the OS memory device). The OS memory device includes at least a capacitance element and an OS transistor that controls the charging and discharging of the capacitance element. The off-state current of an OS transistor is extremely small. S memory devices have excellent retention characteristics and can function as non-volatile memories.

[0371] <Storage device configuration example> FIG. 16A shows an example of the configuration of an OS memory device. The memory device 1400 includes a peripheral circuit 1411. , and a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, and a circuit 1430, output circuit 1440, and control logic circuit 1460.

[0372] The column circuitry 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, and The precharge circuit has the function of precharging the wiring. The amplifier has the function of amplifying the data signal read from the memory cell. are wirings connected to memory cells in the memory cell array 1470. The amplified data signal is output via an output circuit 1440 as a data signal RDAT A is output to the outside of the memory device 1400. The memory cell has a decoder, a word line driver circuit, etc., and can select a row to be accessed.

[0373] The storage device 1400 is supplied with a low power supply voltage (VSS) from the outside as a power supply voltage, and a peripheral circuit 141 1, and a high power supply voltage (VIL) for the memory cell array 1470. The memory device 1400 also receives control signals (CE, WE, RE), address signals, and The address signal ADDR and the data signal WDATA are input from the outside. The data signal WDATA is input to the write circuit. .

[0374] The control logic circuit 1460 receives externally input control signals (CE, WE, RE ) to generate control signals for the row decoder and column decoder. The control signal WE is a write enable signal, and the control signal RE is a read enable signal. Signals processed by the control logic circuit 1460 However, the present invention is not limited to this, and other control signals may be input as required.

[0375] The memory cell array 1470 includes a plurality of memory cells MC arranged in a matrix and a plurality of The wiring connecting the memory cell array 1470 and the row circuit 1420 is The number of memory cells MC is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, and the like. The number of wirings connecting the memory cell array 1470 and the column circuit 1430 is It is determined by the configuration of the cells MC, the number of memory cells MC in one row, and so on.

[0376] In FIG. 16A, the peripheral circuit 1411 and the memory cell array 1470 are arranged on the same plane. However, the present embodiment is not limited to this. As shown in FIG. 16B, a memory cell array 1470 overlaps a part of the peripheral circuit 1411. For example, the memory cell array 1470 may be provided so as to overlap the memory cell array 1470. A configuration may be adopted in which a sense amplifier is provided.

[0377] FIG. 17 illustrates an example of the configuration of a memory cell that can be applied to the above-described memory cell MC.

[0378] [DOSRAM] 17A to 17C show examples of circuit configurations of memory cells in a DRAM. Therefore, DRAM using one OS transistor and one capacitor type memory cell is called DOSRAM ( Dynamic Oxide Semiconductor Random Acces The memory cell 1471 shown in FIG. 17A is a The transistor M1 has a gate (top It has a gate (sometimes called a gate) and a back gate.

[0379] The first terminal of the transistor M1 is connected to the first terminal of the capacitance element CA. The second terminal of the transistor M1 is connected to the wiring BIL, and the gate of the transistor M1 is connected to the wiring WOL. The back gate of the transistor M1 is connected to the wiring BGL. The second terminal of the resistor 11 is connected to the wiring CAL.

[0380] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. AL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CA. When writing and reading data, a low level potential is applied to the wiring CAL. The wiring BGL is preferably a wiring for applying a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, the transistor M The threshold voltage of 1 can be increased or decreased.

[0381] Here, the memory cell 1471 shown in FIG. 17A corresponds to the memory device shown in FIG. That is, the transistor M1 is connected to the transistor 200, the capacitance element CA is connected to the capacitance element 100, The wiring BIL is connected to the wiring 1003, the wiring WOL is connected to the wiring 1004, and the wiring BGL is connected to the wiring 1006. The wiring CAL corresponds to the wiring 1005. 0 is a transistor provided in the peripheral circuit 1411 of the memory device 1400 shown in FIG. 16B. handle.

[0382] Furthermore, the memory cells MC are not limited to the memory cells 1471, and the circuit configuration may be changed. For example, the memory cell MC can be a memory cell 1472 shown in FIG. The back gate of transistor M1 is configured to be connected to wiring WOL instead of wiring BGL. Also, for example, the memory cell MC may be a memory cell 1473 shown in FIG. A transistor M having a single gate structure, i.e., a transistor without a back gate, The memory cell may be configured as 1.

[0383] When the semiconductor device described in the above embodiment is used for the memory cell 1471 or the like, the transistor M A transistor 200 can be used as the capacitor element 1, and a capacitor element 100 can be used as the capacitor element CA. By using an OS transistor as the transistor M1, The leakage current of M1 can be made very small. The frequency of memory cell refresh can be reduced by using register M1 for long-term retention. In addition, the refresh operation of the memory cells can be eliminated. In addition, since the leakage current is very small, the memory cells 1471 and 1472 , multi-value data or analog data can be stored in the memory cell 1473. .

[0384] In addition, in the DOSRAM, as described above, the memory cell array 1470 is overlapped below the memory cell array 1470. By providing a sense amplifier as shown above, the bit line can be shortened. This reduces the bit line capacitance and the storage capacitance of the memory cell.

[0385] [NOSRAM] 17D to 17G show the circuit of a gain cell type memory cell having two transistors and one capacitor. A configuration example is shown in FIG. 17D. The memory cell 1474 shown in FIG. 17D includes a transistor M2 and a transistor The transistor M2 has a top gate (single gate) and a capacitance element CB. In this specification, the term "transistor" refers to a transistor that has a gate. A memory device having a gain cell type memory cell using an OS transistor as the transistor M2 is provided. ,NOSRAM(Nonvolatile Oxide Semiconductor It is sometimes called RAM.

[0386] The first terminal of the transistor M2 is connected to the first terminal of the capacitance element CB. The second terminal of the transistor M1 is connected to the wiring WBL, and the gate of the transistor M2 is connected to the wiring WOL. The back gate of the transistor M2 is connected to the wiring BGL. The second terminal of the transistor M1 is connected to the line CAL. The first terminal of the transistor M2 is connected to the line RB. The second terminal of the transistor M3 is connected to the line SL, and the second terminal of the transistor M3 is connected to the line SL. The gate of the capacitor CB is connected to the first terminal of the capacitor CB.

[0387] The wiring WBL functions as a write bit line, and the wiring RBL functions as a read bit line. The wiring WOL functions as a word line. The wiring CAL is connected to the second terminal of the capacitance element CB. It functions as a wiring for applying a predetermined potential to the element. When writing data, data is retained. During this process, when reading data, it is preferable to apply a low level potential to the wiring CAL. The wiring BGL is a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the transistor M2 The threshold voltage can be increased or decreased.

[0388] Here, the memory cell 1474 shown in FIG. 17D corresponds to the memory device shown in FIG. That is, the transistor M2 is connected to the transistor 200, the capacitance element CB is connected to the capacitance element 100, The transistor M3 is connected to the transistor 300, the wiring WBL is connected to the wiring 1003, and the wiring WOL is To the wiring 1004, the wiring BGL to the wiring 1006, the wiring CAL to the wiring 1005, the wiring RB L corresponds to the wiring 1001, and the wiring SL corresponds to the wiring 1002.

[0389] Furthermore, the memory cell MC is not limited to the memory cell 1474, and the circuit configuration may be changed as appropriate. For example, the memory cell MC can be a memory cell 1475 shown in FIG. , the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL. For example, the memory cell MC may be the memory cell 1476 shown in FIG. As such, a transistor with a single gate structure, i.e., a transistor without a back gate, For example, the memory cell MC may be configured as shown in FIG. As shown in FIG. 14G, the wiring WBL and the wiring RBL are connected to one wiring BIL. It may also be configured as a single unit.

[0390] When the semiconductor device described in the above embodiment is used for the memory cell 1474 or the like, the transistor M Transistor 200 is used as transistor M2, and transistor 300 is used as transistor M3. The capacitance element CB can be a capacitance element 100. By using an S transistor, the leakage current of transistor M2 is made very small. This allows the written data to be held for a long time by the transistor M2. This reduces the frequency of refreshing the memory cells. In addition, the memory cell refresh operation can be eliminated. Since the memory cell 1474 is so small, it is possible to store multi-value data or analog data. The same applies to memory cells 1475 to 1477.

[0391] The transistor M3 is a transistor having silicon in the channel forming region (hereinafter, The conductivity type of the Si transistor is n The Si transistor may be either a n-channel type or a p-channel type. Therefore, the field effect mobility of the read transistor may be higher than that of the read transistor. A Si transistor may be used as the transistor M3 that functions as a transistor. By using a Si transistor for transistor M3, the transistor Since the memory cell M2 can be provided, the area occupied by the memory cell can be reduced, and the memory device can be highly integrated. It is possible to achieve accumulation.

[0392] The transistor M3 may be an OS transistor. When an OS transistor is used for the transistor M3, the memory cell array 1470 is The circuit can be constructed using only transistors.

[0393] FIG. 17H shows an example of a gain cell type memory cell having three transistors and one capacitor. The memory cell 1478 shown in FIG. 17H includes transistors M4 through M6, and The memory cell 1478 has a capacitor CC. The capacitor CC is provided as appropriate. IL, wiring RWL, wiring WWL, wiring BGL, and wiring GNDL. The wiring GNDL is a wiring that applies a low-level potential. Instead of the wiring BIL, the wiring RBL and the wiring WBL may be electrically connected.

[0394] The transistor M4 is an OS transistor having a back gate. The back gate and gate of the transistor M4 are electrically connected to the line BGL. Alternatively, the transistor M4 may have no back gate. It's okay.

[0395] The transistors M5 and M6 are n-channel Si transistors. Alternatively, a p-channel Si transistor may be used. In this case, the memory cell array 1470 is configured as an n-type transistor. The circuit can be constructed using only transistors.

[0396] When the semiconductor device described in the above embodiment is used for the memory cell 1478, the transistor M4 The transistor 200 is used as the transistor M1, and the transistors M2 and M3 are used as the transistors M4 and M5. The transistor 300 can be used as the capacitance element CC, and the capacitance element 100 can be used as the capacitance element CC. By using an OS transistor as the transistor M4, the leakage current of the transistor M4 can be made very small.

[0397] Note that the configurations of the peripheral circuit 1411, the memory cell array 1470, and the like shown in this embodiment are as follows: These circuits, wiring connected to the circuits, and circuits The arrangement or function of elements etc. may be changed, deleted or added as required.

[0398] The transistors described in this specification may be double-gate transistors. FIG. 18A shows an example of a circuit symbol for a double-gate transistor 1500A.

[0399] The transistor 1500A is a transistor Tr1 and a transistor Tr2 connected in series. In FIG. 18A, either the source or the drain of the transistor Tr1 is connected to a terminal S, and the other of the source or drain of the transistor Tr1 is The source or drain of transistor Tr2 is electrically connected to the The other of the source and drain is electrically connected to terminal D. In 18A, the gates of transistors Tr1 and Tr2 are electrically connected, 10 shows a state in which the terminal G is electrically connected to the terminal G.

[0400] The transistor 1500A shown in FIG. 18A changes the potential of the terminal G to It has the function of switching between the conductive and non-conductive states between the electrodes D. The transistor 1500A is a transistor Tr1 and a transistor T The transistor with r2 inside functions as one transistor. , one of the source and drain of the transistor 1500A is electrically connected to the terminal S; The other of the source and drain is electrically connected to terminal D, and the gate is electrically connected to terminal G. It can be said that it is continuing.

[0401] The transistors described in this specification may be triple-gate transistors. FIG. 18B shows an example of a circuit symbol for a triple-gate transistor 1500B.

[0402] The transistor 1500B includes transistor Tr1, transistor Tr2, and transistor In FIG. 18B, the source of transistor Tr1 is connected in series with transistor Tr3. or drain is electrically connected to the terminal S, and the source or drain of the transistor Tr1 is The other of the drains is electrically connected to either the source or the drain of the transistor Tr2. The other of the source or drain of the transistor Tr2 is connected to the source or drain of the transistor Tr3. is electrically connected to one of the drains of the transistor Tr3 and the other of the source or drain of the transistor Tr4. 18B shows a state in which the transistor is electrically connected to terminal D. The gates of transistors Tr1, Tr2, and Tr3 are electrically connected. 10B, and is electrically connected to terminal G.

[0403] The transistor 1500B shown in FIG. 18B changes the potential of the terminal G. It has the function of switching between the conductive and non-conductive states between the children D. The transistor 1500B, which is a transistor of the same type, is a transistor Tr1, a transistor Tr2 and transistor Tr3 function as a single transistor. That is, in FIG. 18B, one of the source and drain of transistor 1500B is electrically connected to terminal S, and the other of the source or drain is electrically connected to terminal D. , the gate can be said to be electrically connected to terminal G.

[0404] Like transistor 1500A and transistor 1500B, it has multiple gates, A transistor with multiple gates electrically connected is called a "multi-gate transistor." These transistors are sometimes called "multi-gate transistors" or "multi-gate transistors."

[0405] In addition, the transistors described in this specification and the like may be transistors having a back gate. FIG. 18C shows an example circuit symbol for a transistor 1500C with a back gate. FIG. 18D shows an example of a circuit symbol for a transistor 1500D having a back gate.

[0406] The transistor 1500C has a structure in which the gate and the back gate are electrically connected. The transistor 1500D has a configuration in which the back gate is electrically connected to the terminal BG. The back gate is arranged so that the channel forming region of the semiconductor layer is sandwiched between the gate and the back gate. The back gate can function similarly to a gate.

[0407] By electrically connecting the gate and back gate, the on-current of the transistor can be increased. In addition, by independently changing the back gate potential, the threshold voltage of the transistor can be adjusted. The voltage can be varied to any desired value.

[0408] The structure described in this embodiment mode may be appropriately combined with structures described in other embodiment modes, examples, etc. It can be used.

[0409] (Fourth embodiment) In this embodiment, a chip 1200 on which the semiconductor device of the present invention is mounted will be described with reference to FIG. An example is shown below. A chip 1200 is implemented with multiple circuits (systems). The technology of integrating multiple circuits (systems) on a single chip is called System-on-Chip (S-Chip). It is sometimes called System on Chip (SoC).

[0410] As shown in FIG. 19A, the chip 1200 includes a CPU 1211, a GPU 1212, and one or more A plurality of analog arithmetic units 1213, one or more memory controllers 1214, one or more It has a plurality of interfaces 1215, one or more network circuits 1216, etc. .

[0411] The chip 1200 is provided with bumps (not shown), and as shown in FIG. 19B, The first surface of the printed circuit board (PCB) 1201 and In addition, a plurality of bumps 1202 are provided on the back surface of the first surface of the PCB 1201. and connects to the motherboard 1203.

[0412] The motherboard 1203 includes storage devices such as a DRAM 1221 and a flash memory 1222. For example, the DRAM 1221 may be provided with the DOSRA shown in the previous embodiment. M can be used. For example, the flash memory 1222 can be The NOSRAM shown can be used.

[0413] The CPU 1211 preferably has multiple CPU cores. It is preferable to have multiple GPU cores. Each of the CPUs 12 may have a memory for temporarily storing data. Even if a memory common to the GPU 1211 and the GPU 1212 is provided on the chip 1200, The memory can be the aforementioned NOSRAM or DOSRAM. The GPU1212 is suitable for parallel calculation of large amounts of data, and is used for image processing and multiply-and-accumulate operations. The GPU1212 can be used for image processing circuits that use oxide semiconductors, By providing a multiply-and-accumulate circuit using conductors, image processing and multiply-and-accumulate operations can be performed with low power consumption. It becomes possible to carry out

[0414] In addition, the CPU 1211 and GPU 1212 are mounted on the same chip, The wiring between PU1211 and GPU1212 can be shortened, and Data transfer to the GPU 1212, the memory of the CPU 1211 and the GPU 1212 After the data transfer between GPU1212 and the calculation in GPU1212, The calculation results can be transferred to 1 at high speed.

[0415] The analog calculation unit 1213 includes an A / D (analog / digital) conversion circuit and a D / A (digital The analog calculation unit 1213 has one or both of a digital / analog conversion circuit. The product-sum calculation circuit may be provided in the

[0416] The memory controller 1214 is a circuit that functions as a controller for the DRAM 1221. and a circuit that functions as an interface with the flash memory 1222.

[0417] The interface 1215 includes a display device, a speaker, a microphone, a camera, a controller, and The controller has an interface circuit with external devices such as a mouse. Such interfaces include devices such as keyboards, game controllers, etc. , USB (Universal Serial Bus), HDMI (registered trademark) gh-Definition Multimedia Interface) It is possible.

[0418] The network circuit 1216 is a network circuit such as a LAN (Local Area Network). It has a network circuit and may also have a circuit for network security. .

[0419] The above circuits (systems) can be formed on the chip 1200 in the same manufacturing process. Therefore, even if the number of circuits required for chip 1200 increases, the manufacturing process can be increased. This eliminates the need for a ferroelectric capacitor, allowing chip 1200 to be manufactured at low cost.

[0420] A PCB 1201 on which a chip 1200 having a GPU 1212 is mounted, a DRAM 1221 The motherboard 1203 provided with the GPU module 1222 and the flash memory 1222 It can be called Rule 1204.

[0421] The GPU module 1204 includes a chip 1200 that uses SoC technology. In addition, because it has excellent image processing capabilities, it can be used on smartphones. Mobile devices such as smartphones, tablets, laptops, and portable (portable) game consoles It is suitable for use in mobile electronic devices. Deep neural networks (DNNs) and convolutional neural networks ( CNN), recurrent neural network (RNN), autoencoder, deep Boltzmann It can implement techniques such as deep belief networks (DBM) and deep belief networks (DBN). Therefore, the chip 1200 is an AI chip, or the GPU module 1204 is an AI system module. It can be used as a tool.

[0422] The structure described in this embodiment mode may be appropriately combined with structures described in other embodiment modes, examples, etc. It can be used.

[0423] (Embodiment 5) In this embodiment, an application example of a memory device using the semiconductor device described in the above embodiment will be described. The semiconductor device described in the above embodiment is applicable to, for example, various electronic devices (for example, information terminals, terminals, computers, smartphones, e-book readers, digital cameras (including video cameras) This can be applied to storage devices such as video recorders, video recorders, and navigation systems. Here, computers include tablet computers, laptop computers, desktop computers, etc. This includes not only desktop computers but also large computers such as server systems. Alternatively, the semiconductor device described in the above embodiment may be used in a memory card (for example, an SD card). Various removable drives such as USB flash drives and SSDs (Solid State Drives) This is applied to storage devices. Figure 20 shows some configuration examples of removable storage devices. For example, the semiconductor device described in the above embodiment is added to a packaged memory chip. It is engineered and used in various storage devices and removable memory.

[0424] FIG. 20A is a schematic diagram of a USB memory. The USB memory 1100 includes a housing 1101, a carrier The board 1104 includes a chip 1102, a USB connector 1103, and a circuit board 1104. It is housed in a housing 1101. For example, the substrate 1104 includes a memory chip 1105, The controller chip 1106 is attached to the memory chip 1105. The semiconductor device shown in the above embodiment can be incorporated.

[0425] FIG. 20B is a schematic diagram of the external appearance of an SD card, and FIG. 20C is a schematic diagram of the internal structure of an SD card. The SD card 1110 includes a housing 1111, a connector 1112, and a board 1113. The substrate 1113 is housed in a housing 1111. For example, the substrate 1113 has: A memory chip 1114 and a controller chip 1115 are attached to the board 111. By providing a memory chip 1114 on the back side of the SD card 1110, the capacity of the SD card 1110 can be increased. In addition, a wireless chip having a wireless communication function may be provided on the substrate 1113. This allows the memory chip to communicate wirelessly between the host device and the SD card 1110. The data in the memory chip 1114 can be read and written. The semiconductor device described in the embodiment can be incorporated.

[0426] FIG. 20D is a schematic diagram of the external appearance of an SSD, and FIG. 20E is a schematic diagram of the internal structure of an SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153. The board 1153 is housed in the housing 1151. For example, the board 1153 may include a memory chip. 1154, memory chip 1155, and controller chip 1156 are attached. The memory chip 1155 is a working memory for the controller chip 1156, and A memory chip 1154 is also provided on the back side of the substrate 1153. By doing so, the capacity of the SSD 1150 can be increased. The semiconductor device shown in the embodiment can be incorporated.

[0427] This embodiment may be implemented in appropriate combination with the configurations described in other embodiments, examples, etc. It is possible to do this.

[0428] (Embodiment 6) A semiconductor device according to one aspect of the present invention is a processor such as a CPU or a GPU, or a chip. FIG. 21 shows a processor such as a CPU or a GPU according to one embodiment of the present invention. Specific examples of electronic devices equipped with the chip are shown below.

[0429] <Electronic devices and systems> A GPU or chip according to one embodiment of the present invention can be mounted in various electronic devices. Examples of electronic devices include television sets, desktop or notebook computers, etc. Monitors for information terminals, digital signage (electronic signage) In addition to electronic devices with relatively large screens, such as large game machines like pachinko machines, Digital cameras, digital video cameras, digital photo frames, e-book readers , mobile phones, portable game machines, personal digital assistants, sound reproducing devices, etc. By providing an electronic device with a GPU or chip according to one aspect of the present invention, It can be equipped with artificial intelligence.

[0430] The electronic device according to one embodiment of the present invention may include an antenna. This allows the display of images and information on the display unit. In the case where the device has a secondary battery, the antenna may be used for contactless power transmission.

[0431] The electronic device according to one embodiment of the present invention includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, etc.). , distance, light, liquid, magnetic, temperature, chemical, sound, time, hardness, electric field, current, voltage, power, (including the ability to measure radiation, flow rate, humidity, gradient, vibration, odor or infrared radiation) It may be possible.

[0432] The electronic device according to one embodiment of the present invention can have various functions. Still images, videos, text images, etc.) on the display, touch panel function, calendar It has the functions of displaying the date, time, etc., and running various software (programs). functions, wireless communication functions, and functions to read programs or data recorded on recording media. The electronic device may have the following functions: Fig. 21 shows an example of the electronic device.

[0433] [Information terminal] FIG. 21A shows a mobile phone (smartphone), which is a type of information terminal. The information terminal 5100 has a housing 5101 and a display unit 5102, and an input interface. As a face, a touch panel is provided on the display unit 5102, and buttons are provided on the housing 5101. It is assumed.

[0434] By applying the chip of one embodiment of the present invention to the information terminal 5100, it is possible to perform applications using artificial intelligence. Applications that use artificial intelligence include: For example, an application that recognizes a conversation and displays the conversation content on the display unit 5102; The display unit 5102 recognizes characters, figures, etc. input by the user on the touch panel. The application to be displayed on the display unit 5102 and the application to perform biometric authentication such as fingerprint or voiceprint are displayed. Examples include recreation.

[0435] 21B shows a notebook type information terminal 5200. The information terminal includes a main body 5201 of the information terminal, a display unit 5202, and a keyboard 5203.

[0436] The notebook type information terminal 5200 is similar to the information terminal 5100 described above, and is a chip according to one embodiment of the present invention. By applying the app, it is possible to run applications that utilize artificial intelligence. Examples of applications that use artificial intelligence include design support software, text annotation software, and Examples include software for cutting food and software for automatically generating menus. By using the 5200, new artificial intelligence can be developed.

[0437] In the above, a smartphone and a notebook type information terminal are used as examples of electronic devices. As shown in Figures 21A and 21B, the devices are not limited to smartphones and notebook computers. Other information terminals can be applied. Examples of information terminals include PDAs (Personal Digital Assistants) ant), desktop information terminals, and workstations.

[0438] [Game consoles] FIG. 21C shows a portable game machine 5300, which is an example of a game machine. 300 includes a housing 5301, a housing 5302, a housing 5303, a display unit 5304, a connection unit 530 5, operation keys 5306, etc. The housing 5302 and the housing 5303 are The connection part 5305 provided on the housing 5301 can be removed from another housing. By attaching it to the body (not shown), the image output on the display unit 5304 can be displayed on another video device. (not shown). At this time, the housings 5302 and 5303 Each of these can function as an operation unit. This allows multiple players to play at the same time. The boards of the housings 5301, 5302, and 5303 are The chip shown in the above embodiment can be incorporated into the provided chip.

[0439] FIG. 21D shows a stationary game machine 5400, which is an example of a game machine. A controller 5402 is connected to the stationary game machine 5400 wirelessly or by wire. do.

[0440] The present invention can be applied to a game machine such as a portable game machine 5300 or a stationary game machine 5400. By applying a GPU or chip, it is possible to realize a low-power gaming machine. In addition, low power consumption reduces heat generated by the circuit, This reduces the impact on the circuit itself, peripheral circuits, and modules.

[0441] Furthermore, by applying the GPU or chip of one embodiment of the present invention to the portable game console 5300, This makes it possible to realize a portable game machine 5300 with artificial intelligence.

[0442] Originally, it was a representation of the game's progress, the behavior of the creatures that appear in the game, and the phenomena that occur in the game. Currently, the game is determined by the program that the game has, but the portable game console 5300 By applying artificial intelligence to the game, it becomes possible to express things that are not limited to game programs. For example, the content of the player's questions, the game progress, the time, and the characters that appear in the game. It becomes possible to express things such as a character's words and actions changing.

[0443] Also, when playing games that require multiple players on the handheld game console 5300, the AI Therefore, it is possible to create anthropomorphic game players, and opponents can be controlled by artificial intelligence. By having multiple game players, the game can be played by one person.

[0444] 21C and 21D show examples of game machines, such as a portable game machine and a stationary game machine. Although the figure shows a game machine, a game machine to which the GPU or chip of one embodiment of the present invention is applied is not shown. The GPU or chip of one embodiment of the present invention can be applied to a game machine such as For example, arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.), sports Examples include pitching machines for batting practice that will be installed at the facility.

[0445] [Mainframe Computer] The GPU or chip according to one embodiment of the present invention can be applied to a mainframe computer.

[0446] FIG. 21E is a diagram showing a supercomputer 5500, which is an example of a large computer. FIG. 21F shows a rack-mounted computer 5500 included in the supercomputer 5500. 502.

[0447] The Supercomputer 5500 consists of a rack 5501 and multiple rack-mounted computers. The computers 5502 are stored in a rack 5501. The computer 5502 is provided with a plurality of substrates 5504, on which the above-mentioned implementations are The GPU or chip described in the form of

[0448] The Supercomputer 5500 is a large computer primarily used for scientific and technological calculations. Scientific and technical calculations require high speed processing of huge amounts of calculations, which consumes a lot of power. The chip generates a lot of heat. By applying this chip, it is possible to realize a low-power supercomputer. In addition, low power consumption reduces heat generated by the circuit, This reduces the impact on the circuit itself, peripheral circuits, and modules.

[0449] 21E and 21F show a supercomputer as an example of a large computer. However, the GPU or chip of one embodiment of the present invention may be applied to a large computer only. The GPU or chip of one embodiment of the present invention can be applied to a large computer. For example, computers that provide services (servers), large general-purpose computers (mainframes), Examples include the use of a frame.

[0450] [Moving object] The GPU or chip of one embodiment of the present invention is used in automobiles, which are moving objects, and in the area around the driver's seat of the automobile. Can be applied to edges.

[0451] FIG. 21G is a diagram showing the area around the windshield in the interior of an automobile, which is an example of a moving body. In FIG. 21G, a display panel 5701 attached to the dashboard, a display panel 5702 attached to the dashboard, and a display panel 5703 attached to the dashboard are shown. 702, a display panel 5703, and a display panel 5704 attached to the pillar are also shown. are.

[0452] The display panels 5701 to 5703 display a speedometer, a tachometer, a driving It provides a variety of other information by displaying distance, fuel gauge, gear status, air conditioning settings, etc. In addition, the display items and layout displayed on the display panel can be customized by the user. It can be changed as needed to suit the user's preferences, enhancing the design. The display panels 5701 to 5703 can also be used as lighting devices.

[0453] The display panel 5704 displays an image from an imaging device (not shown) installed in the car. By doing so, it is possible to compensate for the blind spot obstructed by the pillar. , by displaying images from an imaging device installed outside the vehicle, blind spots are compensated for, This can increase safety. Also, by projecting images that complement the invisible parts, The display panel 5704 is a lighting device and It can also be used as such.

[0454] The GPU or chip of one embodiment of the present invention can be applied as a component of artificial intelligence, e.g. For example, the chip can be used in an autonomous driving system for automobiles. The display panels 5701 to 5705 can be used in systems that provide road guidance, risk prediction, etc. The display panel 5704 may be configured to display information such as road guidance and risk prediction.

[0455] In the above description, an automobile is used as an example of a moving body. For example, the moving object may be a train, a monorail, a ship, or an aircraft (helicopter). , unmanned aerial vehicles (drones), airplanes, rockets, etc., and these movements By applying the chip of one aspect of the present invention to the body, a system using artificial intelligence can be provided. can.

[0456] [electric appliances] FIG. 21H shows an electric refrigerator-freezer 5800, which is an example of an electric appliance. The cabinet 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0457] By applying the chip of one embodiment of the present invention to the electric refrigerator-freezer 5800, artificial intelligence can be realized. By utilizing artificial intelligence, The Electric Refrigerator-Freezer 5800 is a refrigerator-freezer that can It also has a function to automatically generate menus based on the expiration date of food, and a function to automatically generate menus based on the expiration date of food stored in the electric refrigerator-freezer 5800. It can have a function to automatically adjust the temperature to suit the ingredients being cooked.

[0458] We have explained the electric refrigerator-freezer as an example of an electrical appliance, but other electrical appliances include: For example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water heaters, etc. Servers, heating and cooling appliances including air conditioners, washing machines, dryers, audiovisual equipment Examples include personal equipment.

[0459] The electronic devices described in the present embodiment, the functions of the electronic devices, application examples of artificial intelligence, and their effects, etc. These may be combined with descriptions of other electronic devices as appropriate.

[0460] This embodiment may be implemented in appropriate combination with the configurations described in other embodiments, examples, etc. It is possible to do this. [Example]

[0461] A transistor 800 having a structure equivalent to that of the transistor 200 disclosed in the above embodiment. The transistor 800 had a channel length and a channel width of 60 nm, The thickness of the gate insulating layer (TGI) is defined as EOT (Equivalent Oxide Thickness The thickness was 6 nm in terms of the thickness of the semiconductor layer where the channel is formed. The transistor 800 is a field-effect transistor using CAAC-IGZO as a semiconductor layer. It is a photonic crystal transistor (also called "CAAC-IGZO FET").

[0462] 22A and 22B show cross-sectional TEM images of transistor 800. 22A is a cross-sectional TEM photograph of the transistor 800 in the gate length direction, and FIG. 22B is a cross-sectional TEM photograph of the transistor 800 in the gate length direction. 22A and 22B are cross-sectional TEM photographs of the transistor in the gate width direction. 800 gate electrode (TGE), gate insulating layer (TGI), source electrode and drain electrode pole (SDE), semiconductor layer (CAAC-IGZO), back gate insulating layer (BGI), and The back gate electrode (BGE) is shown in FIG. 22B. The SDE is not visible because this is a cross-sectional TEM photograph taken in the gate width direction through the gate electrode.

[0463] Next, the Id-Vg characteristics of the transistor 800 were measured. 0, the voltage between the source and drain (also called "drain voltage" or "Vds") is 1. The voltage supplied to the back gate (also called "Vbg") is set to 0V, and the gate voltage is set to 3V. Between the source and drain when the voltage (also called "Vg") is changed from -3V to 3V The current flowing through the gate (also called "drain current" or "Id") was measured. The properties were measured at four temperatures: -40°C, room temperature (27°C), 85°C, and 125°C.

[0464] 23 shows the measurement results of the Id-Vg characteristics of the transistor 800. The horizontal axis of FIG. The vertical axis shows Id on a logarithmic scale. The lower limit of measurement (ML) of the measuring instrument is 1×10 -13 A. In Figure 23, ML is indicated by a dashed line.

[0465] From Figure 23, it can be seen that Id increases as the measurement temperature increases. This is the opposite trend to that of silicon-based FETs (also called "Si transistors"). From the Id-Vg characteristics at room temperature, it was found that the S value at room temperature was 90 mV / dec.

[0466] FIG. 24A shows the gate breakdown voltage of transistor 800 when Vds=1.2V and Vbg=0V. 24B shows the current of the transistor 800 when Vgs=2.5V and Vbg=0V. The drain breakdown voltage is shown. Although the gate length of the transistor 800 is as small as 60 nm, However, the gate voltage is 3V or more and the drain voltage is 6V or more. Therefore, the transistor 800 can be used as an interface between a CMOS circuit and an external circuit. can be expected. [Example]

[0467] An inverter circuit 810 was fabricated using the transistor 800. 8 shows a circuit diagram of a circuit 810. The inverter circuit 810 includes transistors 800. The source of transistor M1 is Alternatively, one of the drains is electrically connected to the terminal 801, and the other is electrically connected to the output terminal out. The gate of transistor M1 is connected to the source or drain of transistor M1. The back gate of the transistor M1 is electrically connected to the terminal bg1. Either the source or the drain of the transistor M2 is electrically connected to the output terminal out. The other end is electrically connected to the terminal 802. The gate of the transistor M2 is connected to the input The back gate is electrically connected to the terminal bg2. Terminal 801 is supplied with Vdd, and terminal 802 is supplied with Vss.

[0468] The threshold voltage of the transistor M1 is changed by the voltage (Vbg1) supplied to the terminal bg1. The voltage (Vbg2) supplied to the terminal bg2 turns on the transistor M2. The threshold voltage of the transistor can be changed.

[0469] The channel width of transistor M2 is preferably larger than the channel width of transistor M1. In this embodiment, one transistor 800 is used as the transistor M1 (M =1). Also, as transistor M2, 100 transistors 800 are connected in parallel. Therefore, the channel width of the transistor M2 is substantially It can be considered to be 100 times the channel width of transistor M1.

[0470] FIG. 25B shows the DC voltage of the inverter circuit 810 when Vss is set to 0 V and Vdd is set to 3.3 V. The horizontal axis of FIG. 25B represents the voltage Vin supplied to the input terminal in, and The vertical axis represents the voltage Vout supplied to the output terminal out. The measurement results are shown for bg2 of 2V, 0V, -2V, -4V, and -6V. Vbg1 was set to 0V.

[0471] As can be seen from FIG. 25B, by changing the voltage supplied to the back gate, the inverter circuit 810 It can be seen that the logic threshold of [Example]

[0472] A ring oscillator 820 was fabricated using the inverter circuit 810 described in Example 2. FIG. 26A shows a circuit diagram of the ring oscillator 820. The core 811 is composed of an odd number of stages connected in a ring. 26A, the first-stage inverter circuit 810 is an inverter circuit The inverter circuit 810 in the second stage is designated as an inverter circuit 810_1, and the inverter circuit 810 in the second stage is designated as an inverter circuit 810_2. and the n-th inverter circuit 810 is represented as an inverter circuit 810_n (n is an odd number equal to or greater than 3). .) is shown.

[0473] The output of the inverter circuit 810 in the i-th stage (i is a natural number between 2 and n-1) is the i+1th stage. The input of the (i-1)th inverter circuit 810 is electrically connected to the input of the (i-1)th inverter circuit 810. The output of the circuit 810 is electrically connected to the input of the inverter circuit 810 in the i-th stage. The output of the n-th inverter circuit 810 is electrically connected to the input of the first inverter circuit 810. In the core 811, the inverter circuits 810 are connected in a ring shape.

[0474] The input of the output buffer 812 is connected to an odd number of inverter circuits 810 included in the core 811. That is, it is electrically connected to the output of any inverter circuit 810. In other words, The output of the inverter circuit 810 is electrically connected to the input of the output buffer 812. The output of the buffer 812 is electrically connected to the terminal Rout. A ring oscillator 820 having an inverter circuit 810 with 151 stages was fabricated. 26B shows a die photograph of the manufactured ring oscillator 820. The size of the core 811 is , 100 μm × 350 μm.

[0475] The ring oscillator 820 was supplied with a power supply voltage of 3.3 V (Vss = 0 V, Vdd The output waveform when a voltage of 3.3V is supplied is shown in Figure 27. The horizontal axis of Figure 27 represents time, and the vertical axis indicates the output voltage (voltage at terminal Rout) in arbitrary units (au). From Figure 27, It was found that the delay time of the ring oscillator 820 was 43 μs. The delay time of the two inverter circuits 810 is 142 ns.

[0476] The delay time varies depending on the operating temperature. However, by adjusting Vbg2, it is possible to Even in this case, the delay time can be adjusted to the same time as when operating at room temperature.

[0477] Figure 28 shows the temperature dependence of delay time normalized by the delay time at room temperature. Delay time when operating at room temperature (RT: 27°C), 85°C, 125°C, and 150°C The horizontal axis of Figure 28 indicates the temperature, and the vertical axis on the left indicates the standard delay time at room temperature. The vertical axis on the right side shows the Vbg2 value. The delay time was measured at room temperature with Vbg1 at 0V and Vbg2 at 2V.

[0478] The "x" in Figure 28 indicates that the delay time was measured with Vbg2 at 2 V at all operating temperatures. It is clear that the delay time becomes shorter as the operating temperature increases. At an operating temperature of 150°C, the delay time is about 35% shorter than when operating at room temperature. This is because temperature causes a decrease in threshold voltage and an increase in field effect mobility.

[0479] The "□" in Figure 28 indicates that the delay time was measured after adjusting Vbg2 to match the operating temperature. The "△" in Figure 28 indicates the Vbg2 value set for each operating temperature. By adjusting Vbg2 according to the operating temperature, the delay time can be maintained even if the operating temperature changes. In this embodiment, the operating temperature is increased by 150°C from room temperature. The delay time fluctuation was reduced to less than 1% within the range of °C.

[0480] The "○" in Figure 28 indicates the delay of the CMOS inverter using SPICE simulation. The time calculation results are shown. The transistors that make up the CMOS inverter have a channel length A typical 60nm bulk Si transistor is assumed. It can be seen that the delay time increases as the operating temperature rises. At ℃, the delay time is about 14% longer than when operating at room temperature. This is because the threshold voltage increases and the field-effect mobility decreases. It is difficult to provide a back gate in a transistor. Therefore, it is necessary to adjust the delay time for each operating temperature. is difficult.

[0481] By using CAAC-IGZO FET, it is possible to increase the operating speed by increasing the temperature. It is possible to keep the speed constant by using a simple correction circuit. [Explanation of symbols]

[0482] 200: transistor, 800: transistor, 801: terminal, 802: terminal, 810: Inverter circuit, 811: core, 812: output buffer, 820: ring oscillator

Claims

[Claim 1] A semiconductor device including n-stage (n is an odd number equal to or greater than 3) inverter circuits, Among the n-stage inverter circuits, The output of the i-th inverter circuit (i is a natural number between 1 and n) is electrically connected to the input of the i+1-th inverter circuit, an output of the (i-1)th inverter circuit is electrically connected to an input of the i-th inverter circuit; each of the n-stage inverter circuits includes a first transistor and a second transistor; a gate of the first transistor electrically connected to one of a source and a drain of the first transistor; one of the source and the drain of the first transistor is electrically connected to a first terminal; the other of the source and the drain of the first transistor is electrically connected to an output terminal; the gate of the second transistor is electrically connected to an input terminal; one of the source and the drain of the second transistor is electrically connected to the output terminal; the other of the source and the drain of the second transistor is electrically connected to a second terminal; the first transistor has a first back gate; the second transistor has a second back gate; The first transistor and the second transistor each include an oxide semiconductor in a semiconductor layer.

Images