Pattern-based cache block compression

Abstract

To provide a method for performing pattern-based cache block compression.SOLUTION: A process 300 for compressing pattern-based uncompressed cache blocks using byte-selective compression (BSC) includes inputting an uncompressed cache block to a compressor, identifying byte values in the uncompressed cache block, searching a set of cache block patterns for a cache block pattern based on the byte values, and outputting a compressed cache block based on the byte values and the cache block pattern.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims the benefit of U.S. Provisional Application No. 62 / 939,990, filed November 25, 2019, entitled "PATTERN-BASED CACHE BLOCK COMPRESSION," and U.S. Non-Provisional Application No. 17 / 029,158, filed September 23, 2020, entitled "PATTERN-BASED CACHE BLOCK COMPRESSION," the contents of which are incorporated herein by reference.

[0002] (Government Rights) This invention was made with government support under the PathForward Project at Lawrence Livermore National Security (Prime Contract No. DE-AC52-07NA27344, Subcontract No. B620717, awarded by the U.S. Department of Energy (DOE)). The U.S. Government has certain rights in this invention. [Background technology]

[0003] A cache memory or cache is a hardware memory, typically implemented on the same die as the processor that accesses the cache, that is configured to reduce the time and / or energy required to access frequently used information by the processor compared to retrieving that information from a storage location that is slower and / or remote from the processor, such as main memory, a backing store, a lower level cache memory, etc.

[0004] Information is typically stored in a cache in fixed-size units, commonly referred to as cache blocks or cache lines. Compressing the information in a fixed-size cache block into a smaller representation (e.g., compressing a 64-byte block into a 32-byte block) can increase the cache's capacity, link bandwidth, and / or memory. Compressing cache blocks in this manner is commonly referred to as cache block compression.

[0005] Various techniques for compressing cache blocks are generally applicable to other types of data and / or storage devices, and in this context, such techniques are typically referred to as data block compression.

[0006] A more detailed understanding may be had from the following description, given by way of example in conjunction with the accompanying drawings, in which: [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a block diagram of an example device capable of implementing one or more functions of the present disclosure. [Figure 2] FIG. 2 is a block diagram of the device of FIG. 1 showing additional details. [Figure 3] 10 is a flowchart illustrating an exemplary process for compressing an uncompressed cache block. [Figure 4] FIG. 2 is a schematic diagram illustrating an example of a compression circuit. [Figure 5] 1 is a flowchart illustrating an exemplary process for decompressing a compressed cache block. [Figure 6] FIG. 1 is a schematic diagram illustrating an example of a decompression circuit. [Figure 7] FIG. 2 is a block diagram illustrating an example set of cache block patterns. [Figure 8] FIG. 2 is a block diagram illustrating an example of cache block values ​​represented by a particular cache block pattern. [Figure 9]1 is a flowchart illustrating an exemplary process for generating a compressor and / or decompressor. [Figure 10] 10 is a flowchart illustrating an exemplary process for determining a pattern trace from a training trace. [Figure 11] FIG. 1 is a grid diagram illustrating exemplary relationships between cache block patterns in an example set of cache block patterns. [Figure 12] 10 is a flowchart illustrating an exemplary process for reducing a set of cache block patterns. [Figure 13] 1 is a bar chart showing example performance of various compression algorithms; DETAILED DESCRIPTION OF THE INVENTION

[0008] In some embodiments, a compressor and / or a method implemented in the compressor is provided for pattern-based cache block compression. An uncompressed cache block is input to the compressor. A byte value is identified within the uncompressed cache block. A cache block pattern is searched for in a set of cache block patterns based on the byte value. A compressed cache block is output based on the byte value and the cache block pattern.

[0009] In some embodiments, byte values ​​are converted to symbols, and uncompressed cache blocks are represented by symbols, with each symbol representing a particular cache block. In some embodiments, a cache block pattern is looked up in the set of cache block patterns based on the byte value by looking up the set of cache block patterns based on the symbol. In some embodiments, a compressed cache block includes a byte value and an index to the set of cache block patterns. In some embodiments, a compressed cache block includes a byte dictionary and metadata. In some embodiments, the metadata includes an index to the set of cache block patterns. In some embodiments, the byte dictionary includes each of the byte values, and for each byte value, the byte dictionary includes only one copy.

[0010] Some embodiments provide a decompressor and / or a method implemented in a decompressor for pattern-based cache block decompression. A compressed cache block is input to the decompressor. A cache block pattern is identified based on metadata of the cache block. The cache block pattern is applied to a byte dictionary of the cache block. An uncompressed cache block is output based on the cache block pattern and the byte dictionary.

[0011] In some embodiments, the compressed block includes byte values ​​and an index to a set of cache block patterns. In some embodiments, the byte dictionary includes byte values ​​of the uncompressed cache block. In some embodiments, the byte dictionary includes each of the byte values, and for each byte value, the byte dictionary includes only one copy. In some embodiments, the metadata includes an index to the set of cache block patterns. In some embodiments, identifying a cache block pattern based on the metadata of the cache block includes searching for the cache block pattern in the set of cache block patterns based on the metadata. In some embodiments, the cache block pattern includes at least one symbol corresponding to at least one byte of the byte dictionary. In some embodiments, the compressed cache block includes byte values. In some embodiments, the byte dictionary of the cache block includes specific byte values ​​of the uncompressed cache block.

[0012] In some embodiments, methods, systems, and devices are provided for generating hardware configured for pattern-based cache block compression. A cache trace is input, and a set of cache block patterns is determined based on the cache trace. A subset of cache block patterns is determined from the set of cache block patterns based on a set of compressed sizes and a target number of patterns for each size. A hardware description is output based on the determined subset of cache block patterns.

[0013] In some embodiments, the set of cache block patterns is ranked based on frequency of occurrence in cache traces to generate a ranked set of cache block patterns. In some embodiments, the ranked cache block patterns are reduced by removing patterns that occur in cache traces less than a threshold frequency to generate a thresholded set of cache block patterns. In some embodiments, cache block patterns that are not maximally inclusive are removed from the thresholded cache block patterns to generate a set of locally largest cache block patterns. In some embodiments, the largest patterns in the set of locally largest cache block patterns are combined to generate a set of absolutely largest cache block patterns. In some embodiments, subsets of the set of absolutely largest cache block patterns are iteratively sorted based on which of the set of absolutely largest cache block patterns describes more cache blocks to determine the subset of cache block patterns.

[0014] 1 is a block diagram of an example device 100 capable of implementing one or more features of the present disclosure. Device 100 may include, for example, a computer, a gaming device, a handheld device, a set-top box, a television, a mobile phone, or a tablet computer. Device 100 includes a processor 102, memory 104, storage 106, one or more input devices 108, and one or more output devices 110. Device 100 may also optionally include an input driver 112 and an output driver 114. It should be understood that device 100 may include additional components not shown in FIG. 1 .

[0015] In various alternatives, processor 102 includes a central processing unit (CPU), a graphics processing unit (GPU), a CPU and a GPU located on the same die, or one or more processor cores, each of which may be a CPU or a GPU. In various alternatives, memory 104 is located on the same die as processor 102 or is located remotely from processor 102. Memory 104 includes volatile or non-volatile memory (e.g., random access memory (RAM), dynamic RAM, cache). In some embodiments, processor 102 includes a GPU implemented as an accelerator and a CPU configured to manage input / output tasks for the GPU.

[0016] Storage 106 includes fixed or removable storage (e.g., hard disk drive, solid state drive, optical disk, flash drive). Input devices 108 include, but are not limited to, a keyboard, keypad, touch screen, touchpad, detector, microphone, accelerometer, gyroscope, biometric scanner, or network connection (e.g., wireless local area network card for transmitting and / or receiving wireless IEEE 802 signals). Output devices 110 include, but are not limited to, a display, speaker, printer, haptic feedback device, one or more lights, antenna, or network connection (e.g., wireless local area network card for transmitting and / or receiving wireless IEEE 802 signals).

[0017] The input driver 112 communicates with the processor 102 and the input device 108, allowing the processor 102 to receive input from the input device 108. The output driver 114 communicates with the processor 102 and the output device 110, allowing the processor 102 to send output to the output device 110. Note that the input driver 112 and the output driver 114 are optional components, and that the device 100 operates identically without the input driver 112 and the output driver 114. The output driver 114 includes an accelerated processing device (APD) 116 coupled to a display device 118. The APD receives computational and graphics rendering commands from the processor 102, processes the computational and graphics rendering commands, and provides pixel output to the display device 118 for display. As described in further detail below, the APD 116 includes one or more parallel processing units that perform computations according to the single instruction, multiple data (SIMD) paradigm. Thus, although various functions are described herein as being performed by or in conjunction with APD 116, in various alternatives, the functions described as being performed by APD 116 are additionally or alternatively performed by other computing devices that are not driven by a host processor (e.g., processor 102) but have similar functionality for providing graphical output to display device 118. For example, it is contemplated that any processing system that performs processing tasks according to the SIMD paradigm may perform the functions described herein. Alternatively, it is contemplated that computing systems that do not perform processing tasks according to the SIMD paradigm may perform the functions described herein.

[0018] FIG. 2 is a block diagram of device 100 illustrating additional details related to the execution of processing tasks on APD 116. Processor 102 maintains one or more control logic modules in system memory 104 for execution by processor 102. The control logic modules include operating system 120, kernel-mode driver 122, and applications 126. These control logic modules control various aspects of the operation of processor 102 and APD 116. For example, operating system 120 communicates directly with hardware and provides an interface to the hardware for other software executing on processor 102. Kernel-mode driver 122 controls the operation of APD 116 and accesses various features of APD 116, for example, by providing an application programming interface (API) for software (e.g., applications 126) executing on processor 102. Kernel-mode driver 122 also includes a just-in-time compiler that compiles programs for execution by processing components of APD 116 (such as SIMD unit 138, described in more detail below).

[0019] APD 116 executes commands and programs for selected functions, such as graphics and non-graphics operations that may be suitable for parallel processing. APD 116 can be used to perform graphics pipeline operations, such as pixel operations, geometric calculations, and to render images to display device 118 based on commands received from processor 102. APD 116 also performs computational operations not directly related to graphics operations, such as video-related operations, physics simulations, computational fluid dynamics, or other tasks based on commands received from processor 102.

[0020] The APD 116 includes a compute unit 132 that includes one or more SIMD units 138 that perform operations at the request of the processor 102 in parallel according to the SIMD paradigm. The SIMD paradigm allows multiple processing elements to share a single program control flow unit and program counter, thus executing the same program but with different data. In one example, each of the SIMD units 138 includes 16 lanes, each of which can execute the same instruction simultaneously with the other lanes of the SIMD unit 138 but execute the instruction with different data. Predication can be used to turn off lanes when not all lanes need to execute a given instruction. Predication can also be used to execute programs with branching control flows. More specifically, for programs with conditional branches or other instructions whose control flow is based on calculations performed by individual lanes, prediction of lanes corresponding to currently unexecuted control flow paths and serial execution of different control flow paths allows arbitrary control flow.

[0021] The basic unit of execution on the compute unit 132 is the work-item. Each work-item represents a single instantiation of a program executing in parallel on a particular lane. Work-items can execute simultaneously on a single SIMD processing unit 138 as a "wavefront." One or more wavefronts are included in a "workgroup," which includes a collection of work-items designated to execute the same program. A workgroup can be executed by executing each of the wavefronts that make up the workgroup. Alternatively, wavefronts execute serially on a single SIMD unit 138, or partially or fully in parallel on different SIMD units 138. A wavefront can be thought of as the largest collection of work-items that can execute simultaneously on a single SIMD unit 138. Thus, if commands received from processor 102 indicate that a particular program is to be parallelized to such an extent that the program cannot run simultaneously on a single SIMD unit 138, then the program is divided into wavefronts that are processed in parallel on two or more SIMD units 138, or that are processed serially (or both in parallel and serially, as appropriate) on the same SIMD unit 138. Scheduler 136 performs the operations related to scheduling the various wavefronts on the different compute units 132 and SIMD units 138.

[0022] The parallelism allowed by the compute units 132 is suitable for graphics-related operations such as pixel value calculations, vertex transformations, and other graphics operations. Thus, in some cases, the graphics pipeline 134, which receives graphics processing commands from the processor 102, provides computational tasks to the compute units 132 for execution in parallel.

[0023] The computation unit 132 is also used to perform computational tasks that are not related to graphics or that are not performed as part of the "normal" operation of the graphics pipeline 134 (e.g., custom operations performed to supplement processing performed on the operation of the graphics pipeline 134). Applications 126 or other software running on the processor 102 send programs defining such computational tasks to the APD 116 for execution.

[0024] Cache block compression (or, more generally, data block compression) is the basis of cache, memory, and link compression schemes. By compressing fixed-size cache blocks of information into smaller representations (e.g., compressing 64-byte blocks into 32 bytes), cache block compression effectively increases cache and memory link bandwidth and capacity, depending on the embodiment. In some embodiments, cache block compression can significantly improve system performance and energy efficiency. Cache block compression techniques are generally applicable to compressing other, non-cache blocks of data. Therefore, cache block compression applied to non-caching use cases is referred to as data block compression. While techniques and examples related to cache blocks and cache block compression are described herein, it should be noted that these techniques and examples are also applicable to data block compression in general.

[0025] Cache block compression techniques that include byte selection are referred to herein as “byte selection compression” (BSC). An example of a BSC technique is described in U.S. Patent Application US2020 / 0133866A1 (Das et al.), the contents of which are incorporated by reference in their entirety as if fully set forth herein. Byte selection during compression refers to selecting which bytes of a cache block to store and selecting where to store the selected bytes. In this context, compression can be described as byte deduplication. Byte selection during decompression refers to moving stored bytes from a compressed cache block back to their original order in the uncompressed (i.e., decompressed) cache block.

[0026] As examples herein, techniques are presented for compressing and decompressing cache blocks based on a set of patterns, and techniques for generating a set of patterns for use in compressing and decompressing cache blocks, and hardware for performing compression and decompression according to these techniques can be derived based on the set of patterns.

[0027] While cache block compression algorithms have been proposed, previous designs are typically based on the application of an ad-hoc selection of common patterns that designers have observed in data. Accordingly, some embodiments provide a search strategy that identifies cache block patterns that yield compression algorithms that exhibit closer-to-ideal performance than current compression approaches (e.g., closer performance to an algorithm that discovers and compresses all patterns that can be described within the compressed output size), while also incurring lower hardware overhead than current compression approaches.

[0028] Techniques for compressing and decompressing cache blocks based on patterns are described primarily with respect to Figures 3, 4, 5, and 6, and techniques for generating sets of patterns and corresponding hardware for performing the compression and decompression are described primarily with respect to Figures 7, 8, 9, 10, 11, and 12. The relative performance of BSC compression is described primarily with reference to Figure 13.

[0029] FIG. 3 is a flowchart illustrating an example process 300 for compressing uncompressed cache blocks based on a pattern using a BSC.

[0030] In step 310, the uncompressed cache block is input to a suitable compressor. The compressor may be implemented in any suitable manner, such as entirely in hardware using any suitable compression circuitry, or a combination of hardware and software or firmware. In some embodiments, the uncompressed cache block is input to the compressor's input buffer. An example 12-byte uncompressed cache block contains 12 bytes of information represented in hexadecimal format in Table 1. [Table 1]

[0031] In step 320, specific byte values ​​within the uncompressed cache block are identified, e.g., using appropriate comparison logic in the compression circuitry. For example, in some embodiments, a comparator is used to detect duplicate bytes within the uncompressed cache block. Specific byte values ​​within the exemplary uncompressed cache block of Table 1 are shown in Table 2. [Table 2]

[0032] The term "particular byte value" in this context refers to a byte value that appears at least once in an uncompressed cache block. For example, the particular byte value "FF" appears nine times in the example 12-byte cache block shown in Table 1, while the particular byte value "1C" appears once. The byte value "00" does not appear in the example 12-byte uncompressed cache block shown in Table 1, and thus is not a particular byte value for the uncompressed cache block and is not included in Table 2. Because the uncompressed cache block of Table 1 can be expressed in terms of the particular byte values ​​of Table 2, these particular byte values ​​are referred to in this context as a "byte dictionary."

[0033] In step 330, a pattern of a particular byte value in the uncompressed cache block is searched for in a set of cache block patterns. The set of cache block patterns can be stored in any suitable manner, such as a table, matrix, or vector in memory, such as a register file. In some embodiments, the pattern is "searched for" or indexed, for example, based on the output of a comparator. For example, to search for a pattern, a particular byte value can be represented and referenced using a symbol rather than a full byte. Example symbols for each particular byte value in the byte dictionary are shown in decimal in Table 3. Because there are four particular byte values ​​in this example byte dictionary, each symbol can be represented using a minimum of two bits. It should be noted that these particular symbols are exemplary, and any suitable symbol can be used in other embodiments. The process for representing particular byte values ​​in the byte dictionary using symbols is described further herein. [Table 3]

[0034] Based on the symbols in Table 3, the byte pattern for the example cache block shown in Table 1 can be expressed as shown in Table 4. [Table 4]

[0035] Generating a cache block pattern in this manner for a symbol is, in some embodiments, an intermediate step in searching for a cache block pattern. Note that the particular pattern of byte values ​​present in the exemplary uncompressed cache block shown in Table 1 can be expressed in other ways. The determination of such pattern representations and the determination of sets of cache block patterns are described further herein.

[0036] On condition 340, if a cache block pattern shown in Table 4 is not found in the set of cache block patterns, process 300 ends and the exemplary uncompressed cache block shown in Table 1 is not compressed or is compressed using other techniques. On condition 340, if a pattern shown in Table 4 is found in the set of cache block patterns, a compressed cache block is output in step 350 based on the indexes to the cache block patterns in the set of cache block patterns and the byte dictionary. In some embodiments, the compressed cache block includes a byte dictionary (e.g., one shown in Table 2) and metadata including the indexes to the cache block patterns in the set. The compressed cache block can be stored in a cache or transmitted over a link, for example. Table 5 shows an example of a compressed cache block. [Table 5]

[0037] In some embodiments, the metadata also includes a bit that indicates whether the cache line is compressed.

[0038] Figure 4 is a schematic diagram illustrating an exemplary compression circuit 400 for compressing pattern-based uncompressed cache blocks using a BSC. The exemplary compression circuit 400 can be used to implement, for example, the process shown and described with respect to Figure 3. It should be noted that the exemplary compression circuit 400 is merely exemplary, and any suitable configuration of hardware and / or software capable of generating pattern-based compressed cache blocks using a BSC can be used in other embodiments.

[0039] Compression circuit 400 includes logic 450 including comparison circuit 410 and stored cache block pattern 460, multiplexer circuit 420, memory cells 430 for holding uncompressed cache blocks, and memory cells 440 for holding compressed cache blocks including a byte dictionary and metadata.

[0040] During operation, the uncompressed cache block is stored in memory cells 430 of compression circuit 400. This corresponds to step 310 shown and described with respect to FIG. 3. Memory cells 430 may include cache block storage within a cache or any other suitable buffer or other storage circuit. In this example, the uncompressed cache block corresponds to the example 12-byte cache block shown and described with respect to Table 1.

[0041] Bytes of the uncompressed cache block are compared to one another by comparison circuit 410 to identify patterns of particular byte values ​​within the cache block. This corresponds to step 320 shown and described with respect to FIG. 3. Comparator circuit 410, in some embodiments, is part of or in communication with logic circuit 450. In this example, the particular byte values ​​within the exemplary cache block correspond to the example bytes shown and described with respect to Table 2. Patterns may be identified with symbols, for example, as shown and described with respect to Table 4.

[0042] A pattern of particular byte values ​​within the uncompressed cache block is searched for in cache block pattern set 460. This corresponds to step 330 shown and described with respect to Figure 3. For example, any suitable logic within logic circuit 450 and / or comparator circuit 410 is used to compare the cache block pattern to cache block pattern set 460. In some embodiments, cache pattern set 460 is represented by symbols, and the cache block patterns are converted to symbols as an intermediate step, for example, as described with respect to step 330 with respect to Figure 3.

[0043] If the cache block pattern does not match a corresponding pattern in cache block pattern set 460, the uncompressed cache block is not compressed or is compressed using other techniques. If the cache block pattern matches a corresponding pattern in cache block pattern set 460, logic circuit 450 configures multiplexer circuit 420 (e.g., by setting a select line) to store a particular byte value in memory cell 440 as a byte dictionary of the compressed cache block corresponding to the uncompressed cache block, and encodes and stores an index to the cache block pattern in cache block pattern set 460 as metadata for the compressed cache block in memory cell 440. This corresponds to condition 340 and step 350 shown and described with respect to FIG. 3. In this example, the compressed cache block includes a byte dictionary and metadata, and the metadata includes an index to cache block pattern set 460. In some embodiments, the metadata includes other information, as described further herein.

[0044] FIG. 5 is a flowchart illustrating an example process 500 for compressing uncompressed cache blocks based on a pattern using BSC.

[0045] In step 510, the uncompressed cache blocks are input to an appropriate decompressor. The decompressor may be implemented in any suitable manner, such as entirely in hardware using any suitable decompression circuitry, or a combination of hardware and software or firmware. In some embodiments, the compressed cache blocks are input to a buffer of the decompressor. Examples of compressed cache blocks are shown in Table 5 above. In some embodiments, each of the compressed cache blocks is generated according to the process and / or circuitry shown and described with respect to Figures 3 and / or 4.

[0046] In condition 520, if the metadata of the compressed cache block does not contain an index to a set of cache block patterns, the cache block is not decompressed using process 500 and the process ends. If the metadata does contain an index to a set of cache block patterns, the cache block pattern is searched for in the set based on the index in step 530. The cache block patterns correspond to Table 4 in this example. In this example, if an index is present in the metadata, it is assumed that the cache block pattern is included in the cache block pattern set.

[0047] In step 540, the byte dictionary from the compressed block, which in this example corresponds to Table 2, is applied to the cache block pattern (e.g., based on the symbol mapping of Table 3) to generate an uncompressed cache block (shown in this example in Table 1), and the uncompressed cache block is output in step 550. The uncompressed cache block can be stored in a register of the CPU or any other suitable storage location.

[0048] Figure 6 is a schematic diagram illustrating an example decompression circuit 600 for compressing pattern-based compressed cache blocks using a BSC. The example decompression circuit 600 can be used to implement, for example, the process shown and described with respect to Figure 5. It should be noted that the example decompression circuit 600 is merely exemplary, and any suitable configuration of hardware and / or software capable of generating pattern-based decompressed cache blocks using a BSC can be used in other embodiments.

[0049] Decompression circuit 600 includes memory cell 610 configured to input a particular byte value from a byte dictionary of a compressed cache block. This corresponds to step 510 shown and described with respect to FIG. 5. Memory cell 610 may include cache block storage within a cache or any other suitable buffer or other storage circuit. In this example, the compressed cache block corresponding to the example compressed cache block is shown in Table 5 above.

[0050] Decompression circuit 600 also includes logic circuit 620 configured to input metadata from the compressed cache block in memory cell 610 and identify a cache block pattern within the set of stored cache block patterns based on an index included in the metadata. This corresponds to condition 520 and step 530 shown and described with respect to Figure 5. If the metadata does not include an index for the set of cache block patterns, decompression circuit 600 is not used to decompress the compressed cache block.

[0051] Alternatively, if the metadata includes an index to a set of cache block patterns, the cache block pattern is identified within the cache block patterns set by logic circuit 620. Logic circuit 620 sets a select line of multiplexer 630 based on the identified cache block pattern, causing multiplexer 630 to map the byte dictionary of the compressed cache block to memory cells 640 corresponding to the uncompressed cache block. This corresponds to steps 540 and 550 shown and described with respect to FIG. 5. The uncompressed cache block may be stored in a register of the CPU or any other suitable storage location.

[0052] In some embodiments, such as that shown and described with respect to Figure 5, the BSC compressor (including the cache block pattern set) is implemented with a comparator (e.g., to detect duplicate bytes), a multiplexer (e.g., to route bytes to and from a byte dictionary), and logic (e.g., to encode and decode metadata). In some embodiments, such as that shown and described with respect to Figure 6, the BSC decompressor (including the cache block pattern set) is implemented with a multiplexer, where the byte dictionary of the compressed cache block is input to the multiplexer input, and the value of the multiplexer selector is derived from the metadata of the compressed cache block. In some embodiments, limiting the implementation of the compressor and / or decompressor primarily to comparators and multiplexers has the advantage of limiting the complexity of the algorithms and the area and / or latency of the corresponding hardware.

[0053] In some embodiments, the area complexity of the BSC compression and decompression hardware is determined by the number of inputs to the byte multiplexer and the complexity of the logic for generating and processing the metadata. In some embodiments, the latency is determined by the maximum number of inputs to any multiplexer and the depth of the metadata logic. In some embodiments, the size and contents of the cache block pattern set affect the performance of compression and / or decompression by the BSC in terms of speed and die area.

[0054] Thus, in some embodiments, techniques are provided for generating a set of patterns and corresponding hardware for performing compression and decompression. As shown in the example processes and circuits described with respect to Figures 3, 4, 5, and 6, a cache block pattern can be represented as a string of symbols, one for each byte of a cache block, which represent the byte values ​​of the cache block. A cache block can be described by a particular cache block pattern if bytes of the cache block having the same value are represented by the same symbol in the cache block pattern. For example, the example cache block listed in Table 1 can be described by the cache block patterns listed in Table 4, because each byte in Table 1 having the same value is represented by the same symbol in Table 4.

[0055] A cache block pattern acts as a string of indices into a byte dictionary. If it is possible to generate a byte dictionary from an uncompressed cache block, the uncompressed cache block can be described by a particular cache block pattern, and the index of the particular cache block pattern can be used to decompress the byte dictionary into an uncompressed cache block.

[0056] As shown with respect to Figures 3, 4, 5, and 6, the cache block patterns are used to deduplicate bytes of an uncompressed cache block to generate a compressed cache block that includes a byte dictionary and metadata, where the metadata includes an index to a set of cache block patterns that can reconstruct the uncompressed cache block.

[0057] 7 is a block diagram illustrating a set of example cache block patterns for a four-byte cache block. As shown in FIG. 7, a four-byte cache block in which one particular byte value is repeated in each of the four bytes of the cache block can be represented using one symbol (0 in this example set of cache block patterns). Note that the illustrated set is not exhaustive. For example, in other examples, any available symbol can be used to represent a particular one-byte value.

[0058] As also shown in Figure 7, a four-byte cache block containing two specific byte values ​​can be represented using two symbols in an order dependent on their position within the cache block. Several cache block patterns for cache blocks containing two specific cache byte values ​​are shown in Figure 7. Note that the illustrated set is not exhaustive. As will be further explained with respect to Figure 8, a cache block pattern with two symbols can represent a cache block containing one specific byte value.

[0059] As further shown in Figure 7, a four-byte cache block containing three specific byte values ​​can be represented using three symbols in an order according to their position within the cache block. Several cache block patterns for cache blocks containing three specific cache byte values ​​are shown in Figure 7. Note that the illustrated set is not exhaustive. As further explained with respect to Figure 8, a cache block pattern with three symbols can represent a cache block containing one specific byte value or two specific byte values.

[0060] As further shown in FIG. 7, a four-byte cache block containing four specific byte values ​​can be represented using four symbols. In this example, the order of the symbols is not important because each byte of the cache block contains a different specific byte value. Appropriately, an example cache block pattern for a cache block containing four specific cache byte values ​​is shown in FIG. 7. Note that the example cache block pattern shown is not exhaustive. However, other cache block patterns that can be used to represent such cache blocks are equivalent and therefore redundant. Alternative permutations of symbols representing each byte of a cache block containing a different specific byte value are provided in FIG. 7 merely as examples. As further described with respect to FIG. 8, a cache block pattern having four symbols can represent a cache block containing one specific byte value, two specific byte values, or three specific byte values.

[0061] The example cache block patterns included in the example cache block pattern set shown in Figure 7 are not exhaustive. For example, if a 4-byte cache block contains four specific byte values, the symbols 0, 1, 2, and 3 can be used in any order to represent the bytes, or different symbols can be used. This is also true for the 1, 2, and 3 specific byte values ​​shown in Figure 7.

[0062] Figure 8 is a block diagram showing example cache block patterns for an example 4-byte cache block, along with example cache block values ​​that can be described using these example cache block patterns. The example in Figure 8 shows how many cache blocks can be described using a few patterns.

[0063] As shown in FIG. 8, if the symbol "0" is mapped to the value "FF" and the symbol "1" is mapped to the value "01," then the cache block pattern 0101 describes a cache block having a byte value of FF01FF01. Similarly, if the symbol "0" is mapped to the value "00" and the symbol "1" is mapped to the value "01," then this cache block pattern can be used to describe a cache block having a byte value of 00010001. If the symbol "0" is mapped to the value "00" and the symbol "1" is mapped to the value "00," then this cache block pattern describes a cache block having a byte value of 00000000. In each of these cases, an example cache block is described by the cache block pattern 0101. This is because each of the particular byte values ​​of an example cache block having the same value is represented by the same symbol in the cache block pattern.

[0064] 8, if the symbol "0" is mapped to the value "00," the symbol "1" is mapped to the value "01," and the symbol "2" is mapped to the value "02," then cache block pattern 0102 describes a cache block having a byte value of 00010002. This example shows cache block pattern 0102 representing a cache block having three specific byte values. Similarly, if the symbol "0" is mapped to the value "00," the symbol "1" is mapped to the value "01," and the symbol "2" is mapped to the value "01," then cache block pattern 0102 describes a cache block having a byte value of 00010001. This example shows cache block pattern 0102 representing a cache block having two specific byte values. If the symbol "0" is mapped to the value "00", the symbol "1" is mapped to the value "00", and the symbol "2" is mapped to the value "02", then cache block pattern 0102 describes a cache block with a byte value of 00000002. This example shows a second example of cache block pattern 0102 that represents a cache block with two specific byte values, with the specific cache block being arranged differently.

[0065] If the symbol "0" is mapped to the value "00," the symbol "1" is also mapped to the value "00," and the symbol "2" is also mapped to the value "00," then cache block pattern 0102 describes a cache block having a byte value of 00000000. This example shows cache block pattern 0102 representing a cache block with one particular byte value. In each of these cases, the example cache block is described by cache block pattern 0102. This is because the cache block pattern indicates a particular byte value at each position where a symbol occurs, and in some cases, different symbols can be used to represent the same particular byte value.

[0066] As demonstrated by the example in Figure 8, many cache blocks can be described using a few patterns. For example, any cache block that has all of the matching bytes can be described by any pattern, including an "all zero" cache block.

[0067] Since each pattern can be used to describe several different cache block values, a subset of all possible patterns can be used to describe all possible cache blocks. If patterns are removed from the subset, the number of cache blocks can be further reduced.

[0068] An ideal BSC compression and / or decompression algorithm would include all possible non-equivalent patterns in the set of cache block patterns (i.e., the complete list of possible symbolic representations of the bytes of the uncompressed cache block). However, the metadata to index the cache block pattern set containing all possible patterns would potentially be too large to result in compressed blocks that are smaller (or sufficiently smaller) than the uncompressed cache block.

[0069] Accordingly, some embodiments include methods, devices, and systems for selecting a subset of all possible cache block patterns (e.g., to limit the metadata and / or hardware complexity required for compression and decompression by the BSC) that still yield a desired level of performance.

[0070] In some embodiments, a subset of all possible cache block patterns is developed to best achieve the selected constraints for compressing cache blocks to a set of desired target sizes (i.e., quantized compression ratios) below a desired threshold cost (e.g., a threshold cost in terms of latency and / or energy consumption).

[0071] Note that the set of all cache block patterns is not the same as the set of all n-byte strings consisting of digits from 0 to n-1. This is because many patterns are equivalent in terms of the set of cache blocks they can describe. Any patterns that differ only in the names of the symbols they use are all equivalent.

[0072] Consider four-byte patterns (e.g., 0101, 1010, and 1313). The patterns (and many others) all describe the same set of cache blocks where the first and third bytes match and the second and fourth bytes match. Thus, rather than selecting a subset of strings of all possible pattern lengths, in some embodiments, the subsets are selected from a subset of all unique sets of cache blocks that can be described, one pattern per set.

[0073] In some embodiments, the number of patterns considered is constrained to keep the implemented hardware area and delay costs below a threshold (i.e., to constrain area and / or delay), e.g., when using a relatively large byte dictionary size. For example, in some embodiments, limiting the number of patterns considered limits the number of comparators in the compressor and the complexity of the computation logic of the selectors in both the compressor and decompressor.

[0074] Thus, the pattern search constraints are a set of compressed sizes d and a target number of patterns of each size n. In some embodiments, the only metadata required to decompress a compressed cache block is the pattern index. In such a case, [log2(n)] bits of metadata are required, where n is the target number of patterns. In some embodiments, the metadata required for each target compressed size is subtracted to generate a set of byte dictionary size constraints. In some embodiments, the target sizes are independent of interactions between patterns of different target sizes. In some embodiments, the pattern search constraints constrain the selection of a set of patterns to an optimal n from the set of all possible patterns when the byte dictionary size is less than or equal to p.

[0075] Considering the pattern-based compression and decompression techniques described above, in some embodiments it is desirable to select a set of patterns that meets certain, possibly conflicting, goals. This task is referred to as the pattern search problem. One example goal is to develop a set of patterns large enough to achieve a desired (i.e., suitably high) quantized compression ratio. Stated differently, in some embodiments, a set of patterns is developed that describes, for example, a portion of desired blocks for a set of desired workloads (e.g., in a set of general workloads, for a training set of workloads, for most workloads, etc.). Another example goal is to develop a set of patterns small enough to achieve a desired (i.e., suitably bounded and / or suitably small) metadata size.

[0076] In some embodiments, the compressed representation requires [log2(n)] bits of metadata to fully describe p patterns. Thus, in some embodiments, a larger number of patterns tends to reduce the number of bytes available for the byte dictionary, as the metadata takes up more space in the compressed representation. Furthermore, a larger number of patterns increases the area and delay overhead of the compression and decompression logic. On the other hand, in some embodiments, fewer patterns require fewer comparators, smaller priority encoders in the compressor, and fewer inputs to the multiplexers in the compressor and decompressor.

[0077] Another example goal is to select patterns based on available compressed output sizes. As noted above, compressing to fewer bytes than the quantized output size provides no benefit unless it is compressed to an output size that is an even smaller quantized size. Thus, in some embodiments, a set of compressed output sizes is input, and a set of patterns is identified for each size.

[0078] In some embodiments, the development of the cache block pattern set does not consider interactions between patterns of different target sizes. In some embodiments (e.g., for simplicity), the multi-target size problem is decomposed into a separate search problem for each quantized output size. In some embodiments, encoding techniques are used to distinguish between different sizes of metadata, for example, by encoding each target output size with a unique symbol. Thus, in some embodiments, the core search problem is posed as follows: From the set of all possible patterns, choose the best p patterns with byte dictionary size less than or equal to n.

[0079] FIG. 9 is a flowchart illustrating an exemplary process 900 for generating a BSC compressor and / or decompressor. Process 900 includes a process for selecting a subset of all possible cache block patterns. The process for selecting an appropriate subset of all possible cache block patterns addresses the pattern search problem described above. Process 900 also generates a hardware description of an appropriate compressor and / or decompressor based on the subset. Generally, after determining a ranked set of cache block patterns, e.g., using associated counters, the ranked set of cache block patterns is reduced to generate a subset of these patterns. For example, in some embodiments, the best p patterns (e.g., p is a target number of patterns derived from the target compressed cache block size, as described above) require n bytes or less to decompress.

[0080] More specifically, in step 910, a training program is executed using a cache or a model of a cache (e.g., either hardware or simulation), and a trace (e.g., a log) of cache blocks occurring during the execution of the training program is captured. In some embodiments, the training program is representative of a program that will be executed after training. In some embodiments, a training program is representative of a program that will be executed after training if a pattern appears in the training program and the target future program at the same or similar rates (e.g., within a threshold degree or percentage similarity). Cache block patterns that appear in the trace are identified and ranked based on the training trace, and a ranked list of all cache block patterns is generated. In some embodiments, the cache block patterns are ranked based on a count of the number of cache blocks represented by each pattern that appear in the training trace.

[0081] In step 920, the ranked set of cache block patterns is reduced based on different characteristics, for example, in four phases as described below, to generate a reduced set of cache block patterns. In step 930, a register transfer language (RTL) or other suitable representation of compression and decompression hardware is generated based on the reduced set of cache block patterns.

[0082] Examples of steps 910, 920, and 930 are described in more detail as follows: In step 910, pattern counts used to generate a ranked set of cache block patterns are derived from the training trace. This process is called trace processing. In some embodiments, to derive pattern counts, patterns occurring in the trace are identified. A simple approach to deriving pattern counts is to determine, for each cache block pattern in a list of all possible cache block patterns for a given cache block size, the number of cache blocks that occurred in the trace (i.e., passed through the cache during execution of the training program) that can be described by that pattern. However, in some embodiments, the number of all possible patterns is very large, and a cache block can be described by multiple patterns. Thus, in some embodiments, directly counting patterns in this manner is both computationally expensive and loses useful information about which patterns share which blocks. For example, if two patterns are capable of describing some (but not all) of the same cache blocks in the training trace, counting both patterns makes it impossible to know the number of cache blocks counted by both patterns versus the number of blocks counted by only one pattern. This can be disadvantageous in embodiments where it is desirable to determine which of two patterns represents more of the pattern (eg, to the detriment of eliminating the other for efficiency).

[0083] Thus, in some embodiments, for each pattern that appears in the trace, the number of cache blocks for which that pattern is the simplest pattern that can describe the cache block (i.e., the pattern that contains the fewest number of symbols) is determined. In some embodiments, the simplest pattern for each cache block that appears in the trace is determined, and the number of times each of these patterns appears is counted. In some embodiments, to determine the simplest pattern for a cache block, certain byte values ​​of the cache block are placed (or otherwise indexed) into an array in the order that they appear in the cache block. Each byte value of the original cache block is then swapped with its index in the array.

[0084] As an illustrative example of an aspect of step 910, Figure 10 is a flow chart showing an exemplary process 1000 for determining a pattern trace from a training trace. A pattern trace is a list of patterns that describe cache blocks that appear in the training trace. This pattern trace can be used to derive a pattern count for the training trace.

[0085] In step 1010, an exemplary cache trace including five 4-byte uncompressed cache blocks is captured based on an exemplary training run. In step 1020, the specific byte values ​​of each of the five 4-byte uncompressed cache blocks are arranged (or equivalently indexed) into an array in the order in which they appear in the uncompressed cache block. In step 1030, a pattern is recorded for each of the five 4-byte uncompressed cache blocks by swapping each specific byte value with its index in the array.

[0086] For example, the four-byte block FFFF0000 appears in the original trace captured in step 1010 and contains the specific byte values ​​FF and 00. In step 1020, these specific byte values ​​are arranged (or equivalently indexed) into an array in the order they appear in the cache block as FF00, where FF is at index 0 and 00 is at index 1. In step 1030, in the recorded pattern trace, each occurrence of the byte value FF in the original trace is swapped with index 0, and each occurrence of the byte value 00 in the original trace is swapped with index 1. As shown in FIG. 10 , the example process 1000 is performed for each of several four-byte blocks in the original trace to generate a corresponding recorded pattern trace.

[0087] After a pattern trace is determined from the training trace, a pattern count is determined, e.g., using a process consistent with exemplary process 1000. For example, while each of the four-byte cache block examples in the original trace has a different value, one of the patterns in the recorded pattern trace (in this example, pattern 0011) is the simplest byte pattern representation of three cache blocks. Thus, the count for this pattern is 3, while the counts for the other two sample patterns in the recorded pattern trace are each 1.

[0088] After the pattern count is determined, returning to FIG. 9 , the cache block pattern set is reduced in step 920. In some embodiments, the cache block pattern set is reduced in a multi-phase process, with each phase cutting successively more patterns. In the exemplary process 900, step 920 is a four-phase process. In some embodiments, the algorithmic complexity of each phase is equal to or greater than the previous phase. The first phase takes as input the patterns and counters (e.g., a set of ranked cache block patterns) generated in step 910. The final (e.g., fourth) phase outputs a set of sorted patterns, and the best p can be used to generate RTL in step 930.

[0089] In Phase 1, infrequent patterns are removed. In some embodiments, any pattern that is the simplest descriptive pattern for less than a threshold number of cache blocks is removed in Phase 1. In some embodiments, the threshold is set so that later phases finish in an acceptable amount of time. The higher the threshold generated, the fewer patterns are generated for later, more complex phases to process. In some embodiments, the threshold is set to provide regularization to the process. For example, a higher threshold may improve the compaction results of later phases or may prevent or avoid scenarios where input from this phase negatively impacts later phases. In some embodiments, patterns are cut in this phase solely based on the heuristic that infrequently occurring patterns are less useful (i.e., less likely to describe cache blocks seen after training in the target application, etc.). In some embodiments, the output from Phase 1 is in the same format as the input to Phase 1. For example, the list of cache block patterns not cut in Phase 1 includes a corresponding count of the number of cache blocks in the trace for which that pattern is the simplest descriptive pattern.

[0090] If the number of patterns input to Phase 1 is n1, then Phase 1 can be described as having O(n1) complexity, where complexity represents the number of operations performed in this phase. Subsequent phases are described relative to this phase in terms of their functionality.

[0091] In phase 2, cache block patterns that are not maximally inclusive with respect to the training trace (ie, are "non-maximal" cache block patterns) are removed from the list of patterns output from phase 1.

[0092] A cache block pattern is maximally inclusive (i.e., "maximal") with respect to a training trace if the cache blocks of the recorded pattern trace that it describes are not a subset of the cache blocks that can be described by any other cache block pattern in the recorded pattern trace. In other words, a cache block pattern is maximal if no other cache block pattern in the recorded pattern trace describes the same cache block or any subsequent cache blocks. A cache block pattern is not maximal with respect to a training trace if the cache blocks that can be described by the cache block pattern are a subset of the cache blocks that can be described by another cache block pattern in the recorded pattern trace. In other words, a cache block pattern is not maximal with respect to a training trace if no other cache block pattern in the recorded pattern trace describes the same cache block or any subsequent cache blocks in the trace.

[0093] A pattern is said to be less than another pattern if the set of cache blocks it describes is a subset of the cache blocks described by another pattern in the recorded pattern trace. Therefore, a partial ordering of cache block patterns in a recorded pattern trace can be generated based on the set of cache blocks in the trace that the cache block pattern describes. This partial ordering of cache block patterns can be expressed using a lattice of all possible cache block patterns of cache block size. In this context, a partial ordering of cache block patterns in a recorded pattern trace means a partially ordered set. That is, for all patterns, the subset operation is recursive, antisymmetric, and transitive. In a partial ordering, for some pairs of cache block patterns, neither is a subset of the other, but in a total ordering, for any pair of cache block patterns, one compresses a subset of the blocks compressed by the other.

[0094] FIG. 11 is a lattice diagram illustrating exemplary relationships between cache block patterns in an example set of cache block patterns for 4-byte cache blocks.

[0095] In the grid in Figure 11, arrows connecting different patterns indicate that the source pattern (at the base of the arrow) is smaller than the destination pattern (at the head of the arrow). The "bottom" layer of the grid contains patterns that describe cache blocks containing only one specific byte value. In this example, the bottom layer of the grid describes a cache block containing only one specific byte value using the symbol "0000". The "top" layer of the grid contains patterns that represent the maximum number of specific byte values ​​for the cache block size (i.e., four specific byte values ​​for a four-byte cache block in this example). In this example, the top layer of the grid describes a cache block containing four specific byte values ​​using the symbol "0123". Patterns closer to the top of the grid describe a larger number (i.e., the largest number) of cache blocks than patterns closer to the bottom. The cache block pattern at the head of the arrow denotes all cache blocks that can be described by the pattern at the base of the arrow, and also denotes other cache blocks.

[0096] As noted above, the byte dictionary size constraint n is, in some embodiments, derived from the target compressed size. Thus, in some embodiments, for quantized compression, there is no advantage to compressing to a size smaller than the size used to derive n.

[0097] Therefore, returning to Figure 9 for Phase 2, that pattern in the set of cache block patterns output from Phase 1 that is as close as possible to the highest layer of the lattice describing this set while still satisfying the byte dictionary size constraint n is retained and considered maximal with respect to the output of Phase 1.

[0098] To illustrate this point, consider the example lattice of FIG. 11, which includes all cache block patterns in dictionaries of 1, 2, 3, and 4 bytes (i.e., all cache blocks that are 4 bytes long). For example, assuming a constraint of n=3, the largest pattern for the entire lattice, conforming to the constraint, is the pattern requiring a 3-byte dictionary. An example of a recorded pattern trace in the lattice input from phase 1 is shown in the legend of FIG. 11 (i.e., cache block patterns 0000, 0010, and 0011 are shown). Based on this input, no patterns in the lattice requiring 3 bytes appear in the input from phase 1. Therefore, the patterns input from phase 1 are largest for the training trace, in this example, 0010 and 0011. This is because no further largest patterns appeared in the training trace. Pattern 0000 is not largest because it is at the base of an arrow pointing to one of these patterns (i.e., the largest pattern appeared in the training trace).

[0099] Thus, the output of Phase 2 includes the maximum patterns, and non-maximum patterns are filtered out. In addition to eliminating non-maximum patterns from the search, a count of the number of cache blocks described by each maximum pattern is kept. For each maximum pattern, the count includes counts of all patterns that are less maximum than itself or equally maximum. However, because a non-maximum pattern may be less maximum than some maximum patterns, a set of non-maximum patterns and counts is maintained to avoid double-counting patterns in later stages. In some embodiments, this ensures that the same set of cache blocks is described in later stages. However, non-maximum patterns are filtered out from the search itself. In other words, in some embodiments, none of the non-maximum patterns identified in Phase 2 are used in the output of the final compression algorithm, but the non-maximum patterns may be used in later phases to choose among the maximum patterns that may be included in the final compression algorithm.

[0100] The set of patterns that is maximal with respect to the output of phase 1 (i.e., maximal with respect to the output of phase 2) can represent n or fewer specific byte values ​​in the cache block (i.e., usable in an n or fewer byte dictionary). However, to represent n specific byte values ​​in the cache block, a pattern that is maximal with respect to the lattice (i.e., usable in an n-byte dictionary) is needed. A pattern that is maximal with respect to the entire lattice is called absolutely maximal or near maximal because it is maximally inclusive regardless of the training trace.

[0101] If the number of patterns input to Phase 2 is n2, Phase 2 is O(n2 2 ) can be explained as a complexity of

[0102] In phase 3, the relatively largest patterns (ie, patterns that are largest with respect to the training set but not generally largest with respect to the lattice) are combined to reduce the number of patterns in the set.

[0103] As described with respect to Phase 2, some patterns are maximal for the set of patterns under consideration (e.g., patterns present in the training trace) but not maximal for the set of all possible patterns. In other words, the pattern is relatively maximal (e.g., maximal for the training trace) but not absolutely maximal (i.e., not maximal for the lattice). Patterns that are merely relatively maximal do not fully utilize the available byte dictionary space. Further reducing the size of the compressed block beyond n bytes does not provide any benefit because it is not useful for the target hardware application. Therefore, in some embodiments, patterns from the set that are merely relatively maximal are more maximal (i.e., maximal for the lattice), and if such a pattern exists, it is replaced with a pattern in a lattice that is larger than the replaced pattern while still satisfying the constraint. Because larger cache block patterns describe all cache blocks described by smaller cache block patterns, larger patterns identified in Phase 3 that did not appear in the training trace are guaranteed to describe at least the same cache blocks (i.e., not reduced by cache blocks described after Phase 3).

[0104] Returning to Figure 11, the trace patterns were maximal in absolute terms. The two relatively maximal patterns, 0010 and 0011, are less maximal than pattern 0012, which both satisfy the n=3 constraint. Therefore, pattern 0012 can be used in place of both 0010 and 0011 in the cache block pattern set, so that the same cache block can be described using (at least) fewer patterns.

[0105] Returning to FIG. 9 , some embodiments of Phase 3 attempt to combine all pairs of patterns under consideration. For example, to combine pairs, the simplest pattern that can describe the union of the sets of cache blocks described by the two patterns of the pair is determined. If the new pattern satisfies a predetermined byte dictionary size constraint, the two patterns of the pair are replaced with the new pattern. Any other relatively maximal patterns that are not maximal compared to the new pattern are also removed. The counters of the disjoint cache block sets from the first phase are used to calculate the counter values ​​of the new pattern. In some embodiments, Phase 3 continues to combine pairs of cache block patterns from sets that are not absolutely maximal until no more pairs of cache block patterns can be combined.

[0106] If the number of patterns input to Phase 3 is n3, Phase 3 is O(n3 3 ) can be explained as a complexity of

[0107] In Phase 4, a subset of the cache block patterns output from Phase 3 is chosen, which represents the largest number of cache blocks. In some embodiments, this subset is chosen by first iteratively sorting the remaining cache block patterns. In the iterative sorting, two sets of patterns are maintained: the first set is empty in the first iteration, and the second set contains all patterns remaining after Phase 3. In each iteration, patterns from the second set that increase the number of cache blocks (from the training traces) compressed by the first set are moved from the second set to the first set. The best p patterns are then selected from the sorted list.

[0108] FIG. 12 is a flowchart illustrating an exemplary process 1200 for reducing the set of cache block patterns output from phase 3 of FIG. 9. In step 1210, the process begins with no patterns, with iteration number i=0. Note that this example iteration counter is used merely for convenience and to briefly explain the flowchart of FIG. 12, and iterations can be tracked in any suitable manner. In step 1220, a pattern is selected from the list of patterns output from phase 3 that describes the largest number of cache blocks. In some embodiments, this is determined based on a counter associated with the ranked set of cache block patterns (i.e., a count of the number of cache blocks represented by each pattern) described above with respect to step 1010.

[0109] On condition 1230 that the target number of patterns has not yet been added to the set, the iteration counter is incremented in step 1240 (or the iteration is otherwise tracked), and step 1220 is repeated. The target number of patterns is based on p. After at least one pattern has been added to the set, a next pattern is selected in the iteration after step 1220 that describes the largest additional number of cache blocks beyond those already described by the patterns in the set. In some embodiments, repeatedly generating a sorted list of the selected patterns in this manner guarantees that the best pattern is selected at each iteration given the current sorted list. In some embodiments, this guarantee requires updating, with respect to descriptive lines, the benefit of adding each remaining pattern to the current set of patterns at every iteration. To make this search practical, an A* search can be used. In some embodiments, the "guarantee" that the best pattern is selected given the current sorted list is weaker than the guarantee that the best set of patterns overall is selected. In some embodiments, the "best" pattern is the pattern that, when added to the current set, increases the number of cache blocks most compressed by the current set from the training traces. A* search is an example of a search algorithm known in the field of artificial intelligence.

[0110] Upon condition 1230 that the target number of patterns have been added to the set, the list of cache block patterns is complete, and phase 4 may, for example, output the list of patterns to HDL or any other suitable format for later implementation in hardware and / or software.

[0111] In some embodiments, the iterative sorting of phase 4 produces a single sorted list of patterns that can be reused for different values ​​of p. Once a large enough sorted list is produced, the best p can be selected for any value of p that is less than or equal to the size of the list.

[0112] The output from phase 4 is a set of p patterns that respect the byte dictionary size constraint n, and a sorted list of the best cache block patterns for p input from phase 3.

[0113] Returning to Figure 9, after the set of ranked cache block patterns is reduced in step 920, circuitry and / or software can be generated to implement a BSC compressor and / or decompressor based on these patterns. In step 930, RTL or other suitable hardware description code or other description of an implementation circuit is generated for the compression and decompression processes based on the patterns output from phase 4. Figures 3, 4, 5, and 6 are each examples of a compression process, compression circuit, decompression process, and decompression circuit that can be generated in step 930 based on the output of phase 4.

[0114] For example, in some embodiments, the cache block pattern sets shown and described with respect to step 330 of FIG. 3, logic circuitry 450 of FIG. 4, step 530 of FIG. 5, and logic circuitry 620 of FIG. 6 are generated based on the output of phase 4.

[0115] In some embodiments, the RTL or other representation "hard-codes" the cache block patterns from Phase 4, i.e., explicitly defines the values ​​of the cache block patterns in hardware. In some embodiments, this hard-coding has the advantage of facilitating logic synthesis of the input RTL or other representation, significantly improving the performance and area characteristics of the resulting hardware compared to a non-hard-coded approach.

[0116] FIG. 13 is a bar graph comparing the performance of existing algorithms (Base-Delta-Immediate (BDI), Bitplane Compression (BPC), Cache Packer (CPack), Frequent Pattern Compression (FPC), and Zero Content Extension (ZCA)) with the performance of byte selection compression using one byte of metadata (UB-M1). The bar graph shows that the existing algorithms perform half the performance of the byte selection algorithm examples and perform ideally. As can be seen, for example, the compression ratio of the ideal byte selection performance, UB-M1, is at least twice that of the existing algorithm with 1-bit quantization.

[0117] Table 6 shows examples of performance and overhead characteristics of various compression algorithms. [Table 6]

[0118] In some embodiments, data compression with BSC outperforms other algorithms, but single-cycle compression and decompression incurs significant latency. In some embodiments, even greater data reduction can be achieved by trading die area for compression latency (e.g., one-cycle latency).

[0119] The teachings disclosed herein may be useful in any hardware where data storage capacity and / or data transmission bandwidth are an issue. This includes all CPUs, GPUs, and SoCs. The teachings disclosed herein automate the design of cache block compression algorithms to provide the algorithm with the maximum number of compressed blocks. It should be understood that many variations are possible based on the disclosure herein. Although features and elements are described above in specific combinations, each feature or element can be used alone without other features and elements, or in various combinations with or without other features and elements.

[0120] The various functional units illustrated and / or described herein (including, but not limited to, processor 102, input driver 112, input device 108, output driver 114, output device 110, accelerated processing device 116, scheduler 136, graphics processing pipeline 134, computation unit 132, SIMD unit 138) may be implemented as a general-purpose computer, processor, or processor core, or as a program, software, or firmware stored on a non-transitory computer-readable medium or another medium and executable by the general-purpose computer, processor, or processor core. The provided methods may be performed in a general-purpose computer, processor, or processor core. Suitable processors include, by way of example, a general-purpose processor, a special-purpose processor, a conventional processor, a digital signal processor (DSP), multiple microprocessors, one or more microprocessors in association with a DSP core, a controller, a microcontroller, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) circuit, any other type of integrated circuit (IC), and / or a state machine. Such a processor can be manufactured by configuring a manufacturing process using the results of the processed hardware description language (HDL) instructions and other intermediate data, including a netlist (such instructions, which can be stored on a computer-readable medium). The result of such processing can be a maskwork used in a semiconductor manufacturing process to produce a processor that implements the functions of the present disclosure.

[0121] The methods or flowcharts provided herein may be implemented in a computer program, software, or firmware embodied in a non-transitory computer-readable storage medium for execution by a general-purpose computer or processor. Examples of non-transitory computer-readable storage media include read-only memory (ROM), random access memory (RAM), registers, cache memory, semiconductor memory devices, magnetic media such as internal hard disks and removable disks, magneto-optical media, and optical media such as CD-ROM disks and digital versatile disks (DVDs).

Claims

[Claim 1] 1. A method implemented in a compressor for pattern-based cache block compression, comprising: inputting an uncompressed cache block; identifying a byte value within the uncompressed cache block; searching for a cache block pattern in a set of cache block patterns based on the byte value; outputting a compressed cache block based on the byte value and the cache block pattern. method.

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