Semiconductor device and method of manufacturing the same

Abstract

Embodiments described herein relate generally to a semiconductor device and a method of manufacturing a semiconductor device.SOLUTION: According to one embodiment, a semiconductor device having a first device structure, a second device structure, and an insulating member is provided. The first device structure has a first planar surface. The second device structure has a second planar surface. The second flat surface is joined to the first flat surface. The insulating member is disposed between an outer end of the first device structure and an outer end of the second device structure. The insulating member has a flat portion. The flat portion includes therein extension surfaces of the first flat surface and the second flat surface. The flat portion extends flat along the first flat surface and the second flat surface.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present embodiment relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] A semiconductor device is manufactured by bonding two substrate device structures, each of which includes a device structure and a substrate portion, to form a bonded assembly, and then processing the bonded assembly. When manufacturing a semiconductor device, it is desirable that the bonded assembly be processed appropriately. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2022 / 0028833 [Patent Document 2] US Patent Application Publication No. 2023 / 0352438 [Patent Document 3] US Patent Application Publication No. 2020 / 0066507 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of one embodiment is to provide a semiconductor device suitable for appropriately processing a bonded body during manufacturing, and a method for manufacturing the semiconductor device. [Means for solving the problem]

[0005] According to one embodiment, there is provided a semiconductor device having a first device structure, a second device structure, and an insulating member. The first device structure has a first flat surface. The second device structure has a second flat surface. The second flat surface is bonded to the first flat surface. The insulating member is disposed between an outer edge of the first device structure and an outer edge of the second device structure. The insulating member has a flat portion. The flat portion includes the first flat surface and an extension surface of the second flat surface therein. The flat portion extends flatly along the first flat surface and the second flat surface. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a cross-sectional view showing a configuration of a semiconductor device according to an embodiment. [Figure 2] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 3] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 4] 1A to 1C are plan views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 5] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 6] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 7] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 8] 10A and 10B are plan views showing a method for manufacturing a semiconductor device according to a first modified example of the embodiment. [Figure 9] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor device according to a second modified example of the embodiment. [Figure 10] 10A to 10C are cross-sectional views showing a method for manufacturing a semiconductor device according to a second modified example of the embodiment. [Figure 11] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor device according to a third modified example of the embodiment. [Figure 12] 10A to 10C are cross-sectional views showing a method for manufacturing a semiconductor device according to a third modified example of the embodiment. [Figure 13] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor device according to a fourth modified example of the embodiment. [Figure 14] 10A to 10C are cross-sectional views showing a method for manufacturing a semiconductor device according to a fourth modified example of the embodiment. [Figure 15] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor device according to a fifth modified example of the embodiment. [Figure 16] 10A to 10C are cross-sectional views showing a method for manufacturing a semiconductor device according to a fifth modified example of the embodiment. [Figure 17] 10A to 10C are cross-sectional views showing a method for manufacturing a semiconductor device according to a fifth modified example of the embodiment. [Figure 18] FIG. 10 is a cross-sectional view showing the configuration of a semiconductor device according to a sixth modified example of the embodiment. [Figure 19] 10A to 10C are cross-sectional views showing a method for manufacturing a semiconductor device according to a sixth modified example of the embodiment. [Figure 20] 10A to 10C are cross-sectional views showing a method for manufacturing a semiconductor device according to a sixth modified example of the embodiment. [Figure 21] FIG. 13 is a cross-sectional view showing the configuration of a semiconductor device according to a seventh modification of the embodiment. [Figure 22] 13A to 13C are cross-sectional views showing a method for manufacturing a semiconductor device according to a seventh modified example of the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, a semiconductor device according to an embodiment will be described in detail with reference to the accompanying drawings, but the present invention is not limited to the embodiment.

[0008] (Embodiment) The semiconductor device according to the embodiment is manufactured by processing a bonded assembly of two substrates, and has a configuration suitable for appropriately processing the bonded assembly during manufacturing. The semiconductor device 1 may have a configuration as shown in Fig. 1. Fig. 1 is a cross-sectional view showing the configuration of the semiconductor device 1.

[0009] The semiconductor device 1 has a substrate 2, a device structure 3, a device structure 4, and an insulating member 5. In the following, the direction perpendicular to the surface 2a of the substrate 2 is defined as the Z direction, and two directions perpendicular to each other in a plane perpendicular to the Z direction are defined as the X direction and the Y direction.

[0010] The substrate 2 has a substantially disk-like shape, and is substantially circular in the XY plane. The substrate 2 may be made of a material whose main component is a semiconductor (e.g., silicon). The substrate 2 has a front surface 2a on the +Z side, a back surface 2b on the -Z side, and curved end surfaces 2c on the outer sides of the front surface 2a and back surface 2b in the XY direction.

[0011] The surface 2a extends flatly in the XY directions. The surface 2a has a main region 2a1 and a peripheral region 2a2. The peripheral region 2a2 is an annular region disposed outward in the XY directions from the main region 2a1, and surrounds the main region 2a1 in the XY plane view.

[0012] The rear surface 2b extends flat in the X and Y directions. The rear surface 2b may be subjected to a flattening treatment, and may form an obtuse angle with the curved end surface 2c near its end in a cross section including the Z axis (for example, in a YZ cross section).

[0013] The curved end surface 2c includes the outer end 2c1 of the substrate portion 2. In the YZ cross-sectional view, the curved end surface 2c extends while curving from the end of the front surface 2a (the end of the peripheral region 2a2) in the -Z direction and outward in the XY directions to reach the outer end 2c1 of the substrate portion 2, and then extends while curving inward in the -Z direction and in the XY directions to the end of the back surface 2b.

[0014] The device structure 3 is arranged on the surface 2a. The device structure 3 may be arranged up to the curved end surface 2c. The outer end 3c of the device structure 3 may be located near the outer end 2c1 of the substrate portion 2. The main portion of the device structure 3 is arranged in the main region 2a1. The device structure 3 may function as a control circuit for controlling the device structure 4. The device structure 3 may include a structure of multiple CMOS devices that function as a control circuit.

[0015] The device structure 3 has flat surfaces 3a and 3d on the +Z side, and flat surface 3b on the -Z side. Flat surface 3a covers flat surface 4a of device structure 4 in the XY directions. Flat surface 3d is arranged outside flat surface 3a in the XY directions, extends annularly in the XY plane view, and surrounds flat surface 3a. The Z height of flat surface 3d from surface 2a is lower than the Z height of flat surface 3a from surface 2a. A step surface 3e corresponding to the difference in Z height is arranged at the boundary between flat surfaces 3a and 3d. Flat surface 3b covers surface 2a of the substrate portion 2 in the XY directions.

[0016] The device structure 3 includes a plurality of electrodes 31_1 to 31_6, an interlayer insulating film 32, a plurality of conductive patterns, etc. The electrodes 31_1 to 31_6 are arranged near the flat surface 3a. The +Z side surfaces of the electrodes 31_1 to 31_6 are exposed to the flat surface 3a. The +Z side surfaces of the electrodes 31_1 to 31_6 and the flat surface 3a form a continuous surface. Although the plurality of conductive patterns are not shown for simplification, they may function as lines extending between the interlayer insulating film 32, cover the surface 2a of the substrate portion 2, or be arranged near the surface 2a within the substrate portion 2 to function as electrodes of the CMOS device.

[0017] The device structure 4 is arranged on the flat surface 3a. The XY position of the outer end 4c of the device structure 4 may be near the XY position of the outer end 2c1 of the substrate portion 2. The main portion of the device structure 4 is arranged on the flat surface 3a. The device structure 4 may function as a memory cell array. The device structure 4 may include a structure in which a plurality of memory cells are arranged three-dimensionally.

[0018] The device structure 4 has a flat surface 4a, a flat surface 4d, and an inclined side surface 4e on the -Z side, and a flat surface 4b on the +Z side. The flat surface 4a covers the flat surface 3a of the device structure 3 in the XY direction. The flat surface 4d is arranged outside the flat surface 4a in the XY direction, extends in an annular shape in the XY plane view, and surrounds the flat surface 4a. The Z height of the flat surface 4d from the surface 2a is higher than the Z height of the flat surface 4a from the surface 2a. A step surface 4f corresponding to the difference in Z height is arranged at the boundary between the flat surfaces 4a and 4d. The flat surface 4b is exposed on the +Z side.

[0019] The device structure 4 includes a plurality of electrodes 41_1 to 41_6, an interlayer insulating film 42, a stacked body 43, a plurality of pillars (not shown), etc. The electrodes 41_1 to 41_6 are arranged near the flat surface 4a. The -Z side surfaces of the electrodes 41_1 to 41_6 are exposed to the flat surface 4a. The -Z side surfaces of the electrodes 41_1 to 41_6 and the flat surface 4a form a continuous surface.

[0020] The electrodes 41_1 to 41_6 correspond to the electrodes 31_1 to 31_6. Each electrode 41 is joined to the corresponding electrode 31 and electrically connected thereto.

[0021] The stack 43 is formed by alternately stacking conductive films and insulating films multiple times in the Z direction. Although not shown for simplicity, the multiple pillars may be arranged two-dimensionally in the X and Y directions and each may penetrate the stack 43 in the Z direction. Each pillar may be formed of a material containing a semiconductor as a main component. Multiple locations where the multiple pillars and multiple conductive films intersect can function as multiple memory cells.

[0022] The insulating member 5 is disposed between the outer end 3c of the device structure 3 and the outer end 4c of the device structure 4 in the Z direction. The insulating member 5 is disposed outside the flat surfaces 3a and 4a in the XY directions. The insulating member 5 is formed of an insulator. The insulator may contain at least one of a semiconductor oxide, a semiconductor nitride, and a semiconductor oxynitride. The insulating member 5 may be formed of an insulator having a different composition from the interlayer insulating films 32 and 42, or may be formed of an insulator having the same composition as the interlayer insulating films 32 and 42 but a different film density.

[0023] The insulating member 5 includes a flat portion 51 and an outer peripheral portion 52. The flat portion 51 is disposed between the flat surfaces 3a and 4a and the outer peripheral portion 52. The flat portion 51 includes an extension surface EX of the flat surfaces 3a and 4a therein. The flat portion 51 extends flatly along the extension surface EX.

[0024] The flat surfaces 3a and 4a may be substantially circular in the XY plane view. The flat portion 51 may extend annularly outside the flat surfaces 3a and 4a in the XY direction in the XY plane view, and may surround the flat surfaces 3a and 4a in a substantially circular shape. The Z thickness of the flat portion 51 is uniform in the radial direction (for example, the Y direction in the YZ cross section of FIG. 1). The Z height of the flat portion 51 from the main surface 2a of the substrate portion 2 is uniform in the radial direction.

[0025] The outer peripheral portion 52 is disposed on the outer side in the X and Y directions of the flat portion 51. The Z thickness of the outer peripheral portion 52 may gradually increase as it moves outward in the X and Y directions from the flat portion 51. The outer peripheral portion 52 may have a substantially triangular shape in a cross section including the Z axis.

[0026] The outer surface 5a of the peripheral portion 52 may extend in the Z direction from the outer end 4c of the device structure 4 to reach the outer end 3c of the device structure 3. In FIG. 1 , for simplicity, the outer surface 5a is shown as a surface that extends flat in the Z direction. The outer surface 5a may also have a curved surface that bulges outward in the X and Y directions. The outer surface 5a may extend from the outer end 4c of the device structure 4 while curving outward in the -Z direction and the X and Y directions to a predetermined Z position, and then extend from the predetermined Z position to the outer end 3c of the device structure 3 while curving inward in the -Z direction and the X and Y directions.

[0027] The insulating member 5 is in contact with the flat surface 3d of the device structure 3 and the flat surface 4d and inclined side surface 4e of the device structure 4, and supports both the device structure 3 and the device structure 4.

[0028] Next, a method for manufacturing the semiconductor device 1 will be described with reference to Fig. 1 and Fig. 2 to Fig. 7. Fig. 2(a) to Fig. 2(c), Fig. 3(a), Fig. 3(b), Fig. 5(a), Fig. 5(b), Fig. 6(a), Fig. 6(b), Fig. 7(a), and Fig. 7(b) are YZ cross-sectional views showing the method for manufacturing the semiconductor device 1. Fig. 4 is an XY plan view showing the method for manufacturing the semiconductor device 1. Fig. 1 is a diagram showing the configuration of the semiconductor device 1, but will be used as a diagram showing the method for manufacturing the semiconductor device 1.

[0029] In the method for manufacturing the semiconductor device 1, the steps of Figures 2(a) and 2(b) and the steps of Figures 2(c) and 2(d) are performed in parallel. After the steps of Figures 2(a) and 2(b) and the steps of Figures 2(c) and 2(d) are both completed, the steps of Figures 2(e) to 6(b) are performed. In practice, each step is performed using a substrate on which multiple chip areas are mounted, but for simplicity, each cross-sectional view illustrates a cross section of a substrate on which one chip area is mounted.

[0030] 2(a), a substrate unit 6 is prepared. The substrate unit 6 has a substantially disk shape, and is substantially circular in the XY plane view. The substrate unit 6 has a main surface 6a on the -Z side and a main surface 6b on the +Z side. The substrate unit 6 can be formed from a material containing a semiconductor (e.g., silicon) as its main component.

[0031] 2(b), the device structure 4 is formed on the main surface 6a of the substrate portion 6. The device structure 4 may include a memory cell array structure in which a plurality of memory cells are arranged three-dimensionally.

[0032] After depositing an insulating film and a conductive film on the surface 6a of the substrate portion 6, insulating layers and sacrificial layers are alternately deposited multiple times to form the stacked body 43a. The insulating layer may be made of an insulator such as silicon oxide. The sacrificial layer may be made of an insulator (e.g., silicon nitride) that can ensure an etching selectivity with respect to the insulating layer. Each insulating layer and each sacrificial layer may be deposited to approximately the same film thickness.

[0033] A resist pattern with linear openings extending in the Y direction where the dividing films are to be formed is formed on the insulating layer on the -Z side. Anisotropic etching such as RIE (Reactive Ion Etching) is performed using the resist pattern as a mask to form grooves penetrating the stacked body 43a in the YZ direction. The dividing films are then embedded in the grooves. The dividing films may be made of a material primarily composed of an insulator (e.g., silicon oxide). The dividing films divide the stacked body 43a into multiple stacked bodies 43b extending in the YZ direction and aligned in the X direction. In each stacked body 43b, insulating layers and sacrificial layers are alternately stacked multiple times.

[0034] A resist pattern with an opening corresponding to the position where the memory hole is to be formed is formed on the -Z side of the insulating layer on the +Z side of each stacked body 43b and on the -Z side of the dividing film. Anisotropic etching such as RIE is performed using the resist pattern as a mask to form a memory hole that penetrates the stacked body 43b and reaches the conductive film.

[0035] A block insulating film, a charge storage film, and a tunnel insulating film are deposited in this order on the side and bottom surfaces of the memory hole. The block insulating film may be made of an insulator such as silicon oxide. The charge storage film may be made of an insulator such as silicon nitride. The tunnel insulating film may be made of an insulator such as silicon oxide. Portions of the block insulating film, the charge storage film, and the tunnel insulating film on the bottom surface of the memory hole are selectively removed.

[0036] A semiconductor film is deposited on the side and bottom surfaces of the memory hole. The semiconductor film may be formed of a material whose main component is a semiconductor (e.g., polysilicon) that is substantially free of impurities. Then, a core member is buried in the memory hole. The core member may be formed of an insulator such as silicon oxide. This forms a columnar body that penetrates the stack 43b in the Z direction.

[0037] The sacrificial layer of the laminate 43b is removed. An insulating film is formed on the exposed surface of the void formed by the removal. The insulating film may be made of an insulating material such as aluminum oxide. A conductive layer is further embedded in the void. The conductive layer may be made of a material whose main component is a conductor (for example, a metal such as tungsten). This forms the laminate 43 in which conductive layers and insulating layers are alternately stacked.

[0038] This forms a memory cell array structure in which multiple memory cells are arranged three-dimensionally. In the memory cell array structure, multiple memory cells are formed at multiple positions where multiple conductive layers in the stacked body 43 intersect with the semiconductor film of multiple pillars. The conductive film arranged on the +Z side of the stacked body 43 functions as a source region in the memory cell array structure. The conductive layer closest to the +Z side of the multiple conductive layers functions as a source-side select gate line. The conductive layer closest to the -Z side of the multiple conductive layers functions as a drain-side select gate line. The remaining conductive layers of the multiple conductive layers each function as a word line.

[0039] Furthermore, an interlayer insulating film 42 is further deposited, a predetermined wiring structure (not shown) is formed, and the surface on the -Z side of the interlayer insulating film 42 is planarized to form a flat surface 4a. Holes and / or grooves are formed in the flat surface 4a at positions corresponding to the predetermined wiring structure. A conductive material (e.g., a material mainly composed of copper) is embedded in the holes and / or grooves to form electrodes 41.

[0040] This forms a device structure 4 having a memory cell array structure including the electrodes 41, the interlayer insulating film 42, and the stacked body 43. The configuration including the substrate portion 6 and the device structure 4 is referred to as a substrate SB2. The device structure 4 may have inclined side surfaces 4e on the outer sides in the X and Y directions.

[0041] 2(c), the substrate unit 2 is prepared. The substrate unit 2 has a substantially disk shape, and is substantially circular in the XY plane view. The substrate unit 2 has a main surface 2a on the +Z side and a main surface 2ba on the -Z side. The substrate unit 2 can be formed from a material containing a semiconductor (e.g., silicon) as its main component.

[0042] In the step of FIG. 2(d), impurities are introduced into a portion of the main surface 2a of the substrate portion 2, and a conductive film is deposited and patterned on the main surface 2a to form transistor electrodes. The conductive film may be made of a semiconductor (e.g., polysilicon) that is made conductive. An interlayer insulating film 32 is deposited to cover the transistor. The interlayer insulating film 32 may be made of silicon oxide. Thereafter, holes that expose the transistor electrodes are formed in the interlayer insulating film 32, and a conductive material (e.g., tungsten) is buried in the holes to form a wiring structure. This results in the formation of a device structure 3 that includes a circuit structure including the transistor. For simplicity, the circuit structure is not shown in the step of FIG. 2(d).

[0043] Furthermore, an interlayer insulating film 32 is deposited, a predetermined wiring structure (not shown) is formed, and the surface on the -Z side of the interlayer insulating film 32 is planarized to form a flat surface 3a. Holes and / or grooves are formed in the flat surface 3a at positions corresponding to the predetermined wiring structure. A conductive material (e.g., a material mainly composed of copper) is embedded in the holes and / or grooves to form electrodes 31. This results in a substrate part 2 including multiple chip regions. Each chip region includes a circuit structure and is also called a circuit chip. In each chip region, the flat surface 3a on the +Z side of the interlayer insulating film 32 is exposed, and multiple electrodes 31 are arranged on the flat surface 3a.

[0044] This forms the device structure 3, which includes the electrodes 31, the interlayer insulating film 32, and the circuit structure. The configuration including the substrate portion 2 and the device structure 3 is called the substrate SB1.

[0045] 2(e), the flat surface 3a of the substrate SB1 and the flat surface 4a of the substrate SB2 may each be activated by plasma irradiation or the like. The substrates SB1 and SB2 are arranged so that the flat surfaces 3a and 4a face each other. The XY positions of the substrates SB1 and SB2 are aligned so that the XY positions of the electrode 31 on the flat surface 3a correspond to the XY positions of the electrode 41 on the flat surface 4a.

[0046] 3(a), the substrates SB1 and SB2 are brought close to each other in the Z direction to bond the flat surfaces 3a and 4a together. At this time, the substrates SB1 and SB2 may be heated and pressurized.

[0047] This allows easy alignment of electrode 31 and electrode 41, allowing substrate SB1 and substrate SB2 to be bonded together, forming a bonded body BB1 in which substrate SB1 and substrate SB2 are bonded together at bonding surface BF1. At bonding surface BF1, flat surface 3a and flat surface 4a are bonded together by direct bonding, and electrode 31 and electrode 41 can be bonded together by direct bonding. At this time, an unbonded region can be formed in the region indicated by the thick black line on the outer periphery of bonding surface BF1.

[0048] The unbonded region is an area where bonding is not performed properly. It includes mechanical damage such as cracks near the +Z side surface of substrate SB1 or the -Z side surface of substrate SB2, or where the +Z side surface of substrate SB1 and the -Z side surface of substrate SB2 are separated in the Z direction, forming a void. If the unbonded region is left unattended, the area near the unbonded region is weak in strength and can easily chip during subsequent polishing, resulting in scraps scattered in the polishing machine and mechanical damage to the polished surface. Because the area near the unbonded region is weak in strength, subsequent heat treatment or other processes can cause the voids to expand and erode the properly bonded area. This can make it difficult to perform subsequent processes properly.

[0049] Therefore, the unbonded region of the bonded body BB1 is measured. The unbonded region may be measured using an ultrasonic flaw detector (SAT) (FS100II, manufactured by Hitachi Construction Machinery Finetechs Co., Ltd.). In measuring the unbonded region, an SAT image of the bonded body BB1 is acquired, and the depth of the unbonded region in the XY direction is measured by analyzing the SAT image. The depth of the unbonded region in the XY direction is calculated by the distance D in the XY direction from the outer end 2c1 of the substrate portion 2 to the inner end of the unbonded region. UB The depth D of the unbonded region in the X and Y directions may be measured as UB In the example of FIG. 3(a), the depth D in the XY direction of the unbonded region UB on the +Y side is UBis measured, and the depth D in the XY direction of the unbonded area UB on the -Y side UB The depth D of the unbonded area in the X and Y directions is measured. UB may be obtained by selecting the maximum value of the measured values ​​at multiple locations.

[0050] The thickness of the unbonded area is Z, W UB may be experimentally determined in advance as the Z-thickness of the unbonded region that is formed on average when a plurality of substrates are bonded.

[0051] 3(b), grooves 7 are formed from the outside to the inside along the bonding surface BF1 of the bonded body BB1 in accordance with the measurement results of the unbonded region, thereby removing the unbonded region. The grooves 7 may be formed by cutting using a blade BL, as shown in FIGS. 3(b) and 4.

[0052] The depth of the groove 7 is the distance D in the XY direction from the outer end 2c1 of the substrate portion 2 to the inner end of the unbonded region. BL The formation depth D of the groove 7 may be determined as follows. BL is the depth D of the unbonded area in the XY direction measured in the process of Figure 3(a). UB The depth D of the groove 7 in the X and Y directions can be determined depending on the BL is the depth D of the unbonded area in the XY direction, as shown in Figure 3(b). UB The depth D of the unbonded region in the X and Y directions may be larger than UB The value D is obtained by adding the machining margin ΔD of the blade BL in the X and Y directions to the above. BL (=D UB +ΔD).

[0053] The thickness of the groove 7 is the Z thickness W of the blade BL. BL The thickness W of the groove 7 is approximately uniform. BL is the thickness W of the unbonded area Z, as shown in Figure 3(b). UB The thickness of the unbonded area, Z, may be larger than W. UB The value W is calculated by adding the machining margin ΔW in the Z direction of the blade BL to BL (=W UB +ΔW).

[0054] The cutting device (not shown) rotates the bonded body BB1 in a direction RT1 around the Z axis shown by a solid arrow in FIG. 4, and rotates the blade BL in the opposite direction RT2 around the Z axis shown by a dashed arrow in FIG. 4. In FIG. 4, the unbonded region UB is shown by diagonal hatching. The depth of the unbonded region UB in the XY direction is D. UB In this state, the blade BL is gradually moved from the outside of the joining surface BF1 in the XY direction toward the center CP of the joined body BB1, cutting the area near the joining surface BF1 including the unjoined area UB. The cutting is performed until the tip of the blade BL reaches a depth D in the XY direction as shown in FIG. BL 4 and 5(a), the unbonded region UB is removed, and a groove 7 is formed that includes the extension EX of the bonding surface BF1 on the inside. In addition, an opening 8 that is approximately triangular in cross section including the Z axis is formed on the outer side of the groove 7 in the XY direction, between the inclined side surface 4e of the device structure 4 and the device structure 3.

[0055] In the step of FIG. 5(b), an insulating material is filled into the groove 7 and the opening 8 to form the insulating member 5. The filling of the insulating material may be performed by a CVD method or the like using a process gas appropriate for the insulating material, or by a coating method or the like using a solution containing the insulating material. The insulating material may be a relatively viscous material. The insulating material may be an organic adhesive containing a filler or a silica-based inorganic adhesive containing a filler. The insulating material may be a urethane resin, an epoxy resin, or the like. The filler is an aggregate intended to reduce the thermal shrinkage of the filling material to be filled, such as silica particles used as an abrasive.

[0056] An insulating material is filled into the groove 7 to form a flat portion 51 that is flat in the XY directions. An insulating material is filled into the opening 8 to form a peripheral portion 52 that is substantially triangular in a cross section including the Z axis. The insulating member 5, including the flat portion 51 and the peripheral portion 52, is formed so as to be in contact with the flat surface 3d of the device structure 3 and the flat surface 4d and the inclined side surface 4e of the device structure 4. This forms a bonded body BB1a that can support both the device structures 3 and 4 with the insulating member 5 outside the bonding surface BF1 in the XY directions.

[0057] 6(a), the grinder GL of the polishing device is pressed against the back surface 6b of the substrate portion 6, and the grinder GL rotates around an axis perpendicular to the contact surface. This thins the substrate portion 6. At this time, in the bonded body BB1a', the insulating member 5 supports both the device structure 3 and the device structure 4. This prevents chipping of the portion near the outer end 3c of the device structure 3 and / or the portion near the outer end 4c of the device structure 4, thereby suppressing the generation of scrap material.

[0058] In the step shown in FIG. 6(b), the grinder GL of the polishing device continues to be pressed against the back surface 6b1 of the substrate portion 6, and the grinder GL rotates around an axis perpendicular to the contact surface. This polishes the substrate portion 6 until the flat surface 4b of the device structure 4 is exposed. As a result, the substrate portion 6 is peeled off. At this time, in the bonded body BB1b, the insulating member 5 continues to support both the device structure 3 and the device structure 4. This continues to prevent chipping of the portion near the outer end 3c of the device structure 3 and / or the portion near the outer end 4c of the device structure 4, and suppresses the generation of scrap material. Furthermore, the presence of the insulating member 5 makes it easy to maintain the flatness of the flat surface 4b.

[0059] In the step shown in FIG. 7(a), a protective member 9 is attached to the flat surface 4b on the +Z side of the device structure 4. The protective member 9 may be a protective tape having an adhesive applied to the -Z side surface 9a of a substrate. That is, the protective member 9 is attached to the +Z side of the bonded body BB1b. At this time, the presence of the insulating member 5 in the bonded body BB1b makes it easy to maintain the flatness of the flat surface 4b, so that an inexpensive member (e.g., a protective member 9 with a relatively thin thickness) can be used as the protective member 9, thereby reducing manufacturing costs. Furthermore, the presence of the insulating member 5 makes it easy to maintain the flatness of the flat surface 4b, so that the flatness of the +Z side surface 9a of the protective member 9 can be easily ensured.

[0060] In the step shown in FIG. 7(b), the bonded body BB1b with the protective member 9 attached thereto is placed on a table TB having a chuck mechanism CK, with the +Z side surface 9a of the protective member 9 facing the table TB. The chuck mechanism CK may be a vacuum chuck mechanism having a plurality of holes penetrating the table TB in the Z direction and communicating with an exhaust device (not shown). The chuck mechanism CK adsorbs the protective member 9 and the bonded body BB1b to the table TB. At this time, the insulating member 5 of the bonded body BB1b easily maintains the flatness of the flat surface 4b, and the flatness of the +Z side surface 9a of the protective member 9 can be easily ensured. Therefore, the chuck mechanism CK can easily adsorb the protective member 9 and the bonded body BB1b to the table TB.

[0061] In this state, the grinder GL of the polishing device is pressed against the back surface 2ba of the substrate portion 2, and the grinder GL rotates around an axis perpendicular to the contact surface. This thins the substrate portion 2 and polishes the back surface 2b of the substrate portion 2. At this time, in the bonded body BB1c, the insulating member 5 supports both the device structure 3 and the device structure 4. This prevents chipping of the portion near the outer end 3c of the device structure 3 and / or the portion near the outer end 4c of the device structure 4, thereby suppressing the generation of scrap material.

[0062] Thereafter, the chucking by the chuck mechanism CK is released, the protective member 9 and the bonded body BB1b are removed from the table TB, and the protective member 9 is peeled off. In this way, the semiconductor device 1 as shown in FIG.

[0063] As described above, in the embodiment, in the semiconductor device 1 manufactured by processing a bonded assembly of two substrates, the insulating member 5 is disposed outside the bonding surface BF1 (the flat surfaces 3a and 4a of the device structures 3 and 4) in the XY direction and has a flat portion 51 that includes the extension surface EX of the bonding surface BF1 and extends flat along the extension surface EX. The flat portion 51 is formed by filling an insulating material into a groove formed by removing the unbonded region resulting from the bonding of the two substrates, and is a structure suitable for avoiding defects caused by leaving the unbonded region. The flat portion 51 can support the device structures 3 and 4 on the bonded assembly BB during manufacturing and can help ensure that the bonded assembly BB is properly polished and heat-treated thereafter. In other words, this structure makes it possible to provide a semiconductor device 1 suitable for properly processing the bonded assembly BB during manufacturing.

[0064] As a first modification of the embodiment, the cutting of the unbonded region in the step shown in Fig. 3(b) may be performed using a wire saw SW shown in Fig. 8 instead of the blade BL (see Fig. 4). Fig. 8 is a plan view showing a method for manufacturing a semiconductor device according to the first modification of the embodiment.

[0065] The cutting device (not shown) rotates the bonded body BB1 in a direction RT1 around the Z axis shown by a solid arrow in FIG. 8, and vibrates the wire saw SW in a direction BI1 shown by a dashed arrow in FIG. 8. In FIG. 8, the unbonded region UB is shown by diagonal hatching. The depth of the unbonded region UB in the XY direction is D UB In this state, the wire saw SW is gradually moved from the outside of the bonding surface BF1 in the XY direction toward the center CP of the bonded body BB1, cutting the area near the bonding surface BF1 including the unbonded area UB. The cutting is performed by moving the tip of the wire saw SW to a depth D in the XY direction as shown in FIG. BL This is done until it reaches

[0066] The depth of the groove 7 is the distance D in the XY direction from the outer end 2c1 of the substrate portion 2 to the inner end of the unbonded region. BL The formation thickness of the groove 7 is approximately equal to the Z thickness of the wire saw SW, as in the embodiment.

[0067] By such cutting, the unbonded region UB is removed, and the groove 7 including the extension surface EX of the bonding surface BF1 on the inside can be formed, as shown in FIG. 8 and FIG. 5(a).

[0068] Alternatively, as a second modified example of the embodiment, in a semiconductor device 1i, an insulating member 5i may be configured to have a thickness corresponding to the device structure 3, as shown in Fig. 9. Fig. 9 is a cross-sectional view showing the configuration of a semiconductor device 1i according to the second modified example of the embodiment.

[0069] The insulating member 5i has a flat portion 51i instead of the flat portion 51 (see FIG. 1), and does not have an outer peripheral portion 52 (see FIG. 1). The flat portion 51i extends from the end of the bonding surface BF1 (i.e., the flat surfaces 3a, 4a) along its extension surface EX to the outer surface 5a of the insulating member 5i. The Z thickness of the flat portion 51i corresponds to the Z thickness of the device structure 3. The Z thickness of the flat portion 51i may be thicker than the Z thickness of the device structure 3. The flat portion 51i may be in contact with the surface 2a of the substrate portion 2. As in the embodiment, the Z thickness of the flat portion 51i is uniform in the radial direction.

[0070] The device structure 4 may have a flat side surface 4e1 in the Z direction instead of the inclined side surface 4e (see FIG. 1).

[0071] In the method for manufacturing the semiconductor device 1i, the step of FIG. 10(a) may be performed instead of the step of FIG. 3(b).

[0072] 10(a), grooves 7i are formed from the outside to the inside along the bonding surface BF1 of the bonded body BB1 in accordance with the measurement results of the unbonded region (see FIG. 3(a)), thereby removing the unbonded region. The formation of the grooves 7i may be performed by cutting using a blade BLi, as shown in FIG. 3(b).

[0073] The depth of the groove 7i is the distance D in the XY direction from the outer end 2c1 of the substrate portion 2 to the inner end of the unbonded region. BLi The formation depth D of the groove 7i may be determined as follows. BLi is the depth D of the unbonded area in the XY direction measured in the process of Figure 3(a).UB The depth D of the groove 7i in the X and Y directions can be determined depending on the BLi is the depth D of the unbonded region in the XY direction, as shown in Figure 10(a). UB The depth D of the unbonded region in the X and Y directions may be larger than UB The value D is obtained by adding the machining margin ΔD of the blade BLi in the X and Y directions to the above. BLi (=D UB +ΔD).

[0074] The thickness of the groove 7i is the Z thickness W of the blade BLi. BLi The thickness W of the groove 7i is approximately uniform. BLi is the thickness W of the unbonded area Z, as shown in Figure 10(a). UB The thickness of the unbonded area, Z, may be larger than W. UB The value W is calculated by adding the Z-thickness W3 of the device structure 3 and the Z-direction processing margin ΔW of the blade BL to the above. BLi (=W UB +W3+ΔW).

[0075] The cutting device (not shown) rotates the bonded body BB1 in a direction RT1 around the Z axis (see FIG. 4) and rotates the blade BLi in the opposite direction RT2 around the Z axis (see FIG. 4). In this state, the blade BL is gradually moved from the outside of the bonded surface BF1 in the XY direction toward the center CP of the bonded body BB1, cutting the area near the bonded surface BF1 including the unbonded area UB. The cutting is performed when the tip of the blade BLi reaches a depth D in the XY direction. BLi 10(b), the unbonded region UB is removed, and a groove 7i is formed which includes the extension EX of the bonding surface BF1 on the inside.

[0076] In this semiconductor device 1i, the flat portion 51i of the insulating member 5i is formed by filling an insulating material into a groove 7i formed by removing the unbonded region resulting from bonding two substrates, and is a structure suitable for avoiding defects caused by leaving the unbonded region. The flat portion 51i can support the device structures 3 and 4 in the bonded body BB during manufacturing and can help ensure that subsequent polishing and heat treatment of the bonded body BB are performed appropriately. In other words, this structure also makes it possible to provide a semiconductor device 1i suitable for appropriately processing the bonded body BB during manufacturing.

[0077] Alternatively, as a third modification of the embodiment, in a semiconductor device 1j, insulating members 5j may extend outward in the XY directions from positions corresponding to some of the electrodes, as shown in Fig. 11. Fig. 11 is a cross-sectional view showing the configuration of a semiconductor device 1j according to the third modification of the embodiment.

[0078] The insulating member 5j has a flat portion 51j instead of the flat portion 51 (see FIG. 1), and does not have an outer peripheral portion 52 (see FIG. 1). The flat portion 51j extends from the end of the bonding surface BF1 (i.e., the flat surfaces 3a and 4a) along its extension surface EX to the outer surface 5a of the insulating member 5j. The end of the bonding surface BF1 corresponds to a position between the electrodes 41_1 and 41_6 (see FIG. 1) on the outer side in the XY direction and the electrodes 41_2 and 41_5 on the inner side in the XY direction. In other words, the flat portion 51j may extend outward from a position corresponding to some of the electrodes 41_1 and 41_6.

[0079] The Z thickness of the flat portion 51j is greater than the Z thickness of the device structure 3. The flat portion 51j may be in contact with the surface 2a of the substrate portion 2. The Z thickness of the flat portion 51j is uniform in the radial direction, as in the embodiment.

[0080] The device structure 4 may have a flat side surface 4e1 in the Z direction instead of the inclined side surface 4e (see FIG. 1).

[0081] In the method for manufacturing the semiconductor device 1j, the steps of FIGS. 3(a) and 3(b) may be replaced by the steps of FIGS. 12(a) and 12(b).

[0082] 12(a), the substrates SB1 and SB2 are brought close to each other in the Z direction, and the flat surfaces 3a and 4a are bonded together, thereby forming a bonded body BB1 in which the substrates SB1 and SB2 are bonded together at the bonding surface BF1.

[0083] The unbonded region of the bonded body BB1 is measured. The unbonded region may be measured by SAT. In measuring the unbonded region, an SAT image of the bonded body BB1 is acquired, and the SAT image is analyzed to measure the depth of the unbonded region in the X and Y directions. The depth of the unbonded region in the X and Y directions is calculated by the distance D from the outer edge 2c1 of the substrate portion 2 to the inner edge of the unbonded region. UB The depth D of the unbonded region in the X and Y directions may be measured as UB is measured at multiple points in the circumferential direction.

[0084] 12(a) shows the measurement result when the unbonded region reaches some of the electrodes 41_1 and 41_6. The depth D in the XY direction of the unbonded region UB that reaches the electrode 41_1 on the +Y side is UB is measured, and the depth D in the XY direction of the unbonded region UB that reaches the electrode 41_6 on the -Y side is UB The depth D of the unbonded area in the X and Y directions is measured. UB may be obtained by selecting the maximum value of the measured values ​​at multiple locations.

[0085] The thickness of the unbonded area is Z, W UB may be experimentally determined in advance as the Z-thickness of the unbonded region that is formed on average when a plurality of substrates are bonded.

[0086] 12(b), a groove 7j is formed from the outside to the inside along the bonding surface BF1 of the bonded body BB1 in accordance with the measurement result of the unbonded region, thereby removing the unbonded region. The groove 7j may be formed by cutting using a blade BLj, as shown in FIG.

[0087] The depth of the groove 7j is the distance D in the XY direction from the outer end 2c1 of the substrate portion 2 to the inner end of the unbonded region. BLjThe formation depth D of the groove 7j may be determined as follows. BLj is the depth D of the unbonded area in the XY direction measured in the process of Figure 12(a). UBj The depth D of the groove 7j in the X and Y directions can be determined depending on the BLj is the depth D of the unbonded region in the XY direction, as shown in Figure 12(b). UBj The distance D in the XY direction from the outer end 2c1 of the substrate portion 2 to the position between the electrode to which the unbonded region reaches and the electrode inside the electrode may be larger than the distance D BLj may be.

[0088] The thickness of the groove 7j is the Z thickness W of the blade BLj. BLj The thickness W of the groove 7j is approximately uniform. BLj is the thickness W of the unbonded area Z, as shown in Figure 12(b). UBj The thickness W of the groove 7j may be larger than the thickness W of the blade BLj, and may be such that the +Z surface of the blade BLj comes into contact with the surface 2a of the substrate portion 2. BLj is the sum of the Z-thickness W31 of the electrode 31 and the Z-thickness W41 of the electrode 41 plus the machining margin ΔW in the Z direction of the blade BL. BL (=W31+W41+ΔW) may also be used.

[0089] The cutting device (not shown) rotates the bonded body BB1 in a direction RT1 (see FIG. 4) around the Z axis, and rotates the blade BLj in the opposite direction RT2 (see FIG. 4) around the Z axis. In this state, the blade BL is gradually moved from the outside of the bonded surface BF1 in the XY direction toward the center CP of the bonded body BB1, cutting the area near the bonded surface BF1 including the unbonded area UBj. The cutting is performed when the tip of the blade BLj reaches a depth D in the XY direction. BLj 12(c), the unbonded region UBj is removed, and a groove 7j is formed which includes the extension EX of the bonding surface BF1 on the inside.

[0090] In this semiconductor device 1j, the flat portion 51j of the insulating member 5j is formed by filling a groove formed by removing the unbonded region between the two substrates with an insulating material, and is a structure suitable for avoiding defects caused by leaving the unbonded region. The flat portion 51j can support the device structures 3 and 4 in the bonded body BB during manufacturing and can help ensure that subsequent polishing and heat treatment of the bonded body BB are performed appropriately. In other words, this structure also makes it possible to provide a semiconductor device 1j suitable for appropriately processing the bonded body BB during manufacturing.

[0091] Alternatively, as a fourth modification of the embodiment, as shown in Fig. 13, in a semiconductor device 1k, an insulating member 5k may be configured to have a thickness corresponding to the device structure 4. Fig. 13 is a cross-sectional view showing the configuration of a semiconductor device 1k according to the fourth modification of the embodiment.

[0092] The insulating member 5k has a flat portion 51k instead of the flat portion 51 (see FIG. 1), and does not have an outer peripheral portion 52 (see FIG. 1). The flat portion 51k extends from the end of the bonding surface BF1 (i.e., the flat surfaces 3a and 4a) along its extension surface EX to the outer surface 5a of the insulating member 5k. The Z-thickness of the flat portion 51k corresponds to the Z-thickness of the device structure 4. The Z-thickness of the flat portion 51k may be thicker than the Z-thickness of the device structure 4. The flat surface 5b on the +Z side of the flat portion 51k may form a continuous surface with the +Z-side surface 4b of the device structure 4. The height of the flat surface 5b on the +Z side of the flat portion 51k from the surface 2a may be equal to the height of the +Z-side surface 4b of the device structure 4 from the surface 2a. As in the embodiment, the Z-thickness of the flat portion 51k is uniform in the radial direction. The flat portion 51k may have rounded corners on the inner side in the XY directions and on the +Z side in a cross-sectional view.

[0093] In the method for manufacturing the semiconductor device 1k, the step of FIG. 14(a) may be performed instead of the step of FIG. 3(b).

[0094] 14(a), grooves 7k are formed from the outside to the inside along the bonding surface BF1 of the bonded body BB1 in accordance with the measurement results of the unbonded region (see FIG. 3(a)), thereby removing the unbonded region. The formation of the grooves 7k may be performed by cutting using a blade BLk, as shown in FIG.

[0095] The depth of the groove 7k is the distance D in the XY direction from the outer end 2c1 of the substrate portion 2 to the inner end of the unbonded region. BLk The formation depth D of the groove 7k may be determined as follows. BLk is the depth D of the unbonded area in the XY direction measured in the process of Figure 3(a). UB The depth D of the groove 7k in the XY direction can be determined depending on the BLk is the depth D of the unbonded region in the XY direction, as shown in FIG. 14(a). UB The depth D of the unbonded region in the X and Y directions may be larger than UB The value D is obtained by adding the machining margin ΔD of the blade BLk in the X and Y directions to BLk (=D UB +ΔD).

[0096] The thickness of the groove 7k is the Z thickness W of the blade BLk. BLk The thickness W of the groove 7k is approximately equal to the thickness W of the groove 7k. BLk is the thickness W of the unbonded area Z, as shown in Figure 14(a). UB The thickness W of the groove 7k may be larger than the thickness W of the blade BLk, and may be such that the +Z surface of the blade BLk contacts the surface 6a of the substrate portion 6. BLk is the thickness Z of the unbonded area, W UB The value W is calculated by adding the Z thickness W4 of the device structure 4 and the Z direction processing margin ΔW of the blade BLk to the above. BLk (=W UB +W4+ΔW).

[0097] The cutting device (not shown) rotates the bonded body BB1 in a direction RT1 around the Z axis (see FIG. 4) and rotates the blade BLk in the opposite direction RT2 around the Z axis (see FIG. 4). In this state, the blade BL is gradually moved from the outside of the bonded surface BF1 in the XY direction toward the center CP of the bonded body BB1, cutting the area near the bonded surface BF1 including the unbonded area UB. The cutting is performed when the tip of the blade BLk reaches a depth D in the XY direction. BLk 14(b), the unbonded region UB is removed, and a groove 7k is formed that includes the extension EX of the bonding surface BF1 on the inside.

[0098] In this semiconductor device 1k, the flat portion 51k of the insulating member 5k is formed by filling an insulating material into a groove 7k formed by removing the unbonded region resulting from bonding two substrates, and is a structure suitable for avoiding defects caused by leaving the unbonded region. The flat portion 51k can support the device structures 3 and 4 in the bonded body BB during manufacturing and can help ensure that subsequent polishing and heat treatment of the bonded body BB are performed appropriately. In other words, this structure also makes it possible to provide a semiconductor device 1k suitable for appropriately processing the bonded body BB during manufacturing.

[0099] Alternatively, as a fifth modification of the embodiment, in a semiconductor device 1n, an insulating member 5n may be configured to have a thickness corresponding to the device structure 4, as shown in Fig. 15. Fig. 15 is a cross-sectional view showing the configuration of a semiconductor device 1n according to the fifth modification of the embodiment.

[0100] The insulating member 5n has a flat portion 51n instead of the flat portion 51 (see FIG. 1) and does not have an outer peripheral portion 52 (see FIG. 1). The flat portion 51n extends from the end of the bonding surface BF1 (i.e., the flat surfaces 3a and 4a) along its extension surface EX to the outer surface 5a of the insulating member 5n. The Z-thickness of the flat portion 51n corresponds to the Z-thickness of the device structure 4. The Z-thickness of the flat portion 51n may be thicker than the Z-thickness of the device structure 4. The flat surface 5b on the +Z side of the flat portion 51n may form a continuous surface with the +Z-side surface 4b of the device structure 4. The height of the flat surface 5b on the +Z side of the flat portion 51n from the surface 2a may be equal to the height of the +Z-side surface 4b of the device structure 4 from the surface 2a. The Z-thickness of the flat portion 51n is uniform in the radial direction, as in the embodiment. The corner of the flat portion 51n on the inside in the XY directions and on the +Z side may be approximately right angles in a cross-sectional view.

[0101] In addition, in the manufacturing method of semiconductor device 1n, the steps of Figures 3(b), 5(b), 6(a), and 6(b) may be replaced by the steps of Figures 16(a), 17(a), and 17(b).

[0102] 16(a), grooves 7n are formed from the outside to the inside along the bonding surface BF1 of the bonded body BB1 in accordance with the measurement results of the unbonded region (see FIG. 3(a)), thereby removing the unbonded region. The formation of the grooves 7n may be performed by cutting using a blade BLn, as shown in FIG.

[0103] The depth of the groove 7n is the distance D in the XY direction from the outer end 2c1 of the substrate portion 2 to the inner end of the unbonded region. BLn The formation depth D of the groove 7n may be determined as follows. BLn is the depth D of the unbonded area in the XY direction measured in the process of Figure 3(a). UB The depth D of the groove 7n in the X and Y directions can be determined depending on the BLn is the depth D of the unbonded region in the XY direction, as shown in FIG. UB The depth D of the unbonded region in the X and Y directions may be larger than UB The value D is obtained by adding the machining margin ΔD of the blade BLn in the X and Y directions to the above. BLn (=D UB+ΔD).

[0104] The thickness of the groove 7n is the Z thickness W of the blade BLn. BLn The thickness W of the groove 7n is approximately uniform. BLn is the thickness W of the unbonded area Z, as shown in Figure 16(a). UB The thickness W of the groove 7n may be larger than the thickness W of the blade BLn, and may be such that the +Z surface of the blade BLn is located inside the base plate portion 6. BLn is approximately twice the Z thickness W4 of the device structure 4. BLn (=2×W4) is also acceptable.

[0105] The cutting device (not shown) rotates the bonded body BB1 in a direction RT1 around the Z axis (see FIG. 4) and rotates the blade BLn in the opposite direction RT2 around the Z axis (see FIG. 4). In this state, the blade BL is gradually moved from the outside of the bonded surface BF1 in the XY direction toward the center CP of the bonded body BB1, cutting the area near the bonded surface BF1 including the unbonded area UB. The cutting is performed when the tip of the blade BLn reaches a depth D in the XY direction. BLn 16(b), the unbonded region UB is removed, and a groove 7n is formed which includes the extension EX of the bonding surface BF1 on the inside.

[0106] In the step of FIG. 17(a), an insulating material is filled into the trench 7n to form an insulating member 5n1.

[0107] An insulating material is filled in the groove 7n to form a flat portion 51n1 that is flat in the XY directions. The insulating member 5n1 including the flat portion 51n1 is formed so as to be in contact with the flat surface 3d of the device structure 3 and the side surface 4en of the device structure 4. This forms a bonded body BB1a that can support both the device structures 3 and 4 with the insulating member 5n1 outside the bonding surface BF1 in the XY directions.

[0108] In the step shown in FIG. 17(b), the grinder GL of the polishing device is pressed against the back surface 6b of the substrate portion 6, and the grinder GL rotates around an axis perpendicular to the contact surface. This polishes the substrate portion 6 until the flat surface 4b of the device structure 4 is exposed, and the +Z side portion of the insulating member 5n1 is also polished. As a result, the substrate portion 6 is peeled off, and the +Z side flat surface 5b of the flat portion 51n is formed as a surface continuous with the +Z side surface 4b of the device structure 4. At this time, in the bonded body BB1b, the insulating member 5n supports both the device structure 3 and the device structure 4. This prevents chipping of the portion near the outer end 3c of the device structure 3 and / or the portion near the outer end 4c of the device structure 4, thereby suppressing the generation of scrap. Furthermore, the insulating member 5n facilitates maintaining the flatness of the flat surface 4b.

[0109] In this semiconductor device 1n, the flat portion 51n of the insulating member 5n is formed by filling an insulating material into a groove 7n formed by removing the unbonded region resulting from bonding two substrates, and is a structure suitable for avoiding defects caused by leaving the unbonded region. The flat portion 51n can support the device structures 3 and 4 in the bonded body BB during manufacturing and can help ensure that subsequent polishing and heat treatment of the bonded body BB are performed appropriately. In other words, this structure also makes it possible to provide a semiconductor device 1n suitable for appropriately processing the bonded body BB during manufacturing.

[0110] Alternatively, as a sixth modified example of the embodiment, in a semiconductor device 1p, an insulating member 5p may be configured to have a thickness corresponding to the device structures 3 and 4, as shown in Fig. 18. Fig. 18 is a cross-sectional view showing the configuration of a semiconductor device 1p according to the sixth modified example of the embodiment.

[0111] The insulating member 5p has a flat portion 51p instead of the flat portion 51 (see FIG. 1) and does not have an outer peripheral portion 52 (see FIG. 1). The flat portion 51p extends from the end of the bonding surface BF1 (i.e., the flat surfaces 3a and 4a) along its extension surface EX to the outer surface 5a of the insulating member 5p. The Z-thickness of the flat portion 51p corresponds to the Z-thickness of the device structure 3 and the device structure 4. The Z-thickness of the flat portion 51p may be thicker than the sum of the Z-thickness of the device structure 3 and the Z-thickness of the device structure 4. The flat surface 5b on the +Z side of the flat portion 51p may form a continuous surface with the +Z-side surface 4b of the device structure 4. The height of the flat surface 5b on the +Z side of the flat portion 51p from the surface 2a may be equal to the height of the +Z-side surface 4b of the device structure 4 from the surface 2a. As in the embodiment, the Z-thickness of the flat portion 51p is uniform in the radial direction. The height of the flat surface 5c on the -Z side of the flat portion 51p from the back surface 2b may be smaller than the height of the surface 3b on the -Z side of the device structure 3 from the back surface 2b.

[0112] In addition, in the manufacturing method of semiconductor device 1p, the steps of Figures 19(a), 20(a), and 20(b) may be performed instead of the steps of Figures 3(b), 5(b), 6(a), and 6(b).

[0113] 19(a), grooves 7p are formed from the outside to the inside along the bonding surface BF1 of the bonded body BB1 in accordance with the measurement results of the unbonded region (see FIG. 3(a)), thereby removing the unbonded region. The formation of the grooves 7p may be performed by cutting using a blade BLp, as shown in FIG.

[0114] The depth of the groove 7p is the distance D in the XY direction from the outer end 2c1 of the substrate portion 2 to the inner end of the unbonded region. BLp The formation depth D of the groove 7p may be determined as follows. BLp is the depth D of the unbonded area in the XY direction measured in the process of Figure 3(a). UB The depth D of the groove 7p in the XY direction can be determined depending on the BLp is the depth D of the unbonded region in the XY direction, as shown in FIG. UB The depth D of the unbonded region in the X and Y directions may be larger than UBThe value D is obtained by adding the machining margin ΔD of the blade BLp in the X and Y directions to the above. BLp (=D UB +ΔD).

[0115] The thickness of the groove 7p is the Z thickness W of the blade BLp. BLp The thickness W of the groove 7p is approximately equal to the thickness W of the groove 7p. BLp is the thickness W of the unbonded area Z, as shown in Figure 19(a). UB The thickness W of the groove 7p may be larger than the thickness W of the groove 7p, and may be such that the +Z surface of the blade BLp is located within the substrate portion 6 and the -Z surface of the blade BLp is located within the substrate portion 2. BLp is approximately twice the sum of the Z-thickness W3 of the device structure 3 and the Z-thickness W4 of the device structure 4. BLp (=2×(W3+W4)) may also be used.

[0116] The cutting device (not shown) rotates the bonded body BB1 in a direction RT1 around the Z axis (see FIG. 4) and rotates the blade BLp in the opposite direction RT2 around the Z axis (see FIG. 4). In this state, the blade BL is gradually moved from the outside of the bonded surface BF1 in the XY direction toward the center CP of the bonded body BB1, cutting the area near the bonded surface BF1 including the unbonded area UB. The cutting is performed when the tip of the blade BLp reaches a depth D in the XY direction. BLp 19(b), the unbonded region UB is removed, and a groove 7p is formed which includes the extension EX of the bonding surface BF1 on the inside.

[0117] In the step of FIG. 20(a), an insulating material is filled into the trench 7p to form an insulating member 5p1.

[0118] An insulating material is filled in the groove 7p to form a flat portion 51p1 that is flat in the XY directions. The insulating member 5p1 including the flat portion 51p1 is formed so as to be in contact with the side surface 3ep of the device structure 3 and the side surface 4ep of the device structure 4. This forms a bonded body BB1a that can support both the device structures 3 and 4 with the insulating member 5p1 outside the bonding surface BF1 in the XY directions.

[0119] In the step shown in FIG. 20(b), the grinder GL of the polishing device is pressed against the back surface 6b of the substrate portion 6, and the grinder GL rotates around an axis perpendicular to the contact surface. This polishes the substrate portion 6 until the flat surface 4b of the device structure 4 is exposed, and the +Z side portion of the insulating member 5p1 is also polished. As a result, the substrate portion 6 is peeled off, and the +Z side flat surface 5b of the flat portion 51p is formed as a surface continuous with the +Z side surface 4b of the device structure 4. At this time, in the bonded body BB1b, the insulating member 5p supports both the device structure 3 and the device structure 4. This prevents chipping of the portion near the outer end 3c of the device structure 3 and / or the portion near the outer end 4c of the device structure 4, thereby suppressing the generation of scrap. Furthermore, the presence of the insulating member 5p facilitates maintaining the flatness of the flat surface 4b.

[0120] In this semiconductor device 1p, the flat portion 51p of the insulating member 5p is formed by filling an insulating material into a groove 7p formed by removing the unbonded region resulting from bonding two substrates, and is a structure suitable for avoiding defects caused by leaving the unbonded region. The flat portion 51p can support the device structures 3 and 4 in the bonded body BB during manufacturing and can help ensure that subsequent polishing and heat treatment of the bonded body BB are performed appropriately. In other words, this structure also makes it possible to provide a semiconductor device 1p suitable for appropriately processing the bonded body BB during manufacturing.

[0121] Alternatively, as a seventh modification of the embodiment, in a semiconductor device 1r, an insulating member 5r may be made of a plurality of materials as shown in Fig. 21. Fig. 21 is a cross-sectional view showing the configuration of a semiconductor device 1r according to the seventh modification of the embodiment.

[0122] The insulating member 5r may include two or more materials. The flat portion 51r may be formed of a first material, and the outer peripheral portion 52r may be formed of a second material. The first material and the second material may have different compositions, or may have the same composition but different film densities.

[0123] For example, the first material may have a lower viscosity than the second material. The second material may have a higher Young's modulus than the first material. The second material may have a higher tensile strength than the first material. This ensures that the insulating material can be embedded in the grooves 7 during manufacturing while also ensuring the strength of the insulating member 5r as a whole.

[0124] In addition, in the method for manufacturing the semiconductor device 1r, the steps of FIGS. 22(a) and 22(b) may be performed between the step of FIG. 5(b) and the step of FIG. 6(a).

[0125] 5(b), a first material is filled as an insulating material into the grooves 7 and the openings 8. A material with relatively low viscosity may be used as the first material. This ensures that the insulating material can be embedded in the grooves 7, and allows the flat portions 51r to be properly formed.

[0126] The first material is embedded in the groove 7 to form a flat portion 51r that is flat in the XY directions. The first material is embedded in the opening 8 to form an outer peripheral portion 52r1 (not shown) that is substantially triangular in a cross section including the Z axis.

[0127] 22(a), the first material filled in the trench 7 and the opening 8 is etched back, the outer periphery 52r1 filled in the opening 8 is removed, and the flat portion 51r filled in the trench 7 is selectively left. As a result, the opening 8 is again formed outside the flat portion 51r in the XY directions, as shown in FIG.

[0128] In the step of FIG. 22(b), a second material is filled in the opening 8 as an insulating material. The second material may have a lower viscosity than the first material. The second material may have a higher Young's modulus than the first material. The second material may have a higher tensile strength than the first material. This ensures the strength of the outer periphery 52r due to the insulating material filled in the opening 8.

[0129] The second material is embedded in the opening 8 to form an outer circumferential portion 52r that is substantially triangular in a cross section including the Z axis. This forms the insulating member 5r that includes the flat portion 51r and the outer circumferential portion 52r. Since the strength of the outer circumferential portion 52r can be ensured, the strength of the insulating member 5r as a whole can be ensured.

[0130] 6(a), the grinder GL of the polishing device is pressed against the back surface 6b of the substrate portion 6, and the grinder GL rotates around an axis perpendicular to the contact surface. This thins the substrate portion 6. At this time, in the bonded body BB1a', the strength of the insulating member 5r as a whole can be ensured, so that the insulating member 5r can reliably support both the device structure 3 and the device structure 4. This further prevents chipping in the portion near the outer end 3c of the device structure 3 and / or the portion near the outer end 4c of the device structure 4, and further suppresses the generation of scrap material.

[0131] In this semiconductor device 1r, the flat portion 51r of the insulating member 5r is formed by filling an insulating material into the groove 7 formed by removing the unbonded region resulting from bonding two substrates, and is a structure suitable for avoiding defects caused by leaving the unbonded region. The flat portion 51r can support the device structures 3 and 4 in the bonded body BB during manufacturing and can help ensure that subsequent polishing and heat treatment of the bonded body BB are performed appropriately. In other words, this structure also makes it possible to provide a semiconductor device 1r suitable for appropriately processing the bonded body BB during manufacturing.

[0132] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0133] 1, 1i, 1j, 1k, 1n, 1p, 1r semiconductor device, 2, 6 substrate portion, 3, 4 device structure, 5, 5i, 5j, 5k, 5n, 5p, 5r insulating member

Claims

1. a first device structure having a first planar surface; a second device structure having a second planar surface bonded to the first planar surface; an insulating member disposed between an outer end of the first device structure and an outer end of the second device structure, the insulating member having a flat portion that includes extensions of the first flat surface and the second flat surface therein and extends flat along the extensions; A semiconductor device comprising:

2. The flat portion has a uniform thickness in the radial direction. The semiconductor device according to claim 1 .

3. further comprising a substrate portion having a first main surface; the first device structure is disposed on the first major surface; The flat portion has a uniform height from the first main surface in the radial direction. The semiconductor device according to claim 1 .

4. The insulating member has a first portion including a first material and a second portion including a second material. The semiconductor device according to claim 1 .

5. The first portion includes the flat portion. The semiconductor device according to claim 4 .

6. The flat portion extends flatly along the first flat surface and the second flat surface to the outer surface of the insulating member. The semiconductor device according to claim 1 .

7. further comprising a substrate portion having a first main surface; the first device structure is disposed on the first major surface; The flat portion is disposed on the first main surface outside the first device structure. The semiconductor device according to claim 6.

8. the first device structure has a third planar surface opposite the first planar surface; The flat portion has a fourth flat surface that is continuous with the third flat surface. The semiconductor device according to claim 6.

9. forming a bonded body by bonding a first flat surface of a first device structure of a first substrate including a first device structure having a first flat surface and a substrate portion to a second flat surface of a second substrate including a second device structure having a second flat surface and a substrate portion; forming a groove from the outside to the inside along the joining surface of the joined body; Filling the groove with an insulating material; A method for manufacturing a semiconductor device comprising:

10. measuring the depth of the unbonded region from the edge of the first substrate in a planar direction; determining a depth of the groove from an end of the first substrate in a planar direction according to the measured depth of the unbonded region in a planar direction; Furthermore, The formation of the grooves is forming the groove from the outside to the inside along the joining surface of the joint body to the determined width. The method for manufacturing a semiconductor device according to claim 9 .

11. After the embedding, the substrate portion of the second substrate is peeled off. The method for manufacturing a semiconductor device according to claim 9 .

12. The embedding may be Filling a first portion of the trench with a first insulating material; filling a second portion of the groove outside the first portion with a second insulating material; Contains The method for manufacturing a semiconductor device according to claim 9 .

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