Semiconductor device

Abstract

To improve the electrical characteristics of a semiconductor device.SOLUTION: A semiconductor device includes a plurality of p-type body regions 25 provided separately in an X direction, a gate insulating film, a gate electrode, a source insulating film 32 provided separately from the gate insulating film in the X direction, a source electrode 34, a plurality of p-type column layers provided at intervals in the X direction and extending in a Z direction, and a source wiring 13. The semiconductor layer 20 includes a p-type source contact region 29. A part of the source wiring 13 is disposed so as to overlap the source contact region 29 in plan view. The source interconnect 13 includes a first source contact portion 13D that is in contact with both the source contact region 29 and the source electrodes 34.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a metal-insulator-semiconductor field-effect transistor (MISFET) having a superjunction structure. + a drain layer and an n - a p-type drift layer, a p-type channel region, a p-type pillar layer, and an n + type source region and p + The p-type pillar layer includes a p-type channel contact region, a gate electrode, a gate insulating film, and an interlayer insulating film. + The gate electrode extends toward the drain layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-161712

[0004] [overview] There is a demand for improvements in the electrical characteristics of semiconductor devices.

[0005] A semiconductor device according to one aspect of the present disclosure includes a semiconductor layer of a first conductivity type including a first surface and a second surface opposite to the first surface, a plurality of body regions of a second conductivity type provided on the first surface and spaced apart in a first direction in a plan view seen from a thickness direction of the semiconductor layer, a source region of the first conductivity type provided on the first surface of each of the plurality of body regions, a body contact region of the second conductivity type provided to penetrate the source region in the thickness direction, a gate insulating film provided on the first surface and arranged to straddle two of the body regions adjacent to each other in the first direction, a gate electrode disposed on the gate insulating film, and a gate electrode provided on the gate insulating film and spaced apart from the gate insulating film in the first direction on the first surface, the body contact region of the second conductivity type provided on the first surface and spaced apart from each other in the first direction. a source insulating film arranged across a body region, a source electrode arranged on the source insulating film, a plurality of column layers of a second conductivity type spaced apart in the first direction within the semiconductor layer and extending in the thickness direction, and a source wiring provided on the first surface, wherein a body region pitch, which is an arrangement interval between the plurality of body regions in the first direction, is shorter than a column layer pitch, which is an arrangement interval between the plurality of column layers in the first direction, the semiconductor layer includes a source contact region of the second conductivity type, a portion of the source electrode is arranged to overlap the source contact region in the planar view, and the source wiring includes a first source contact portion in contact with both the source contact region and the source wiring. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic plan view of an exemplary semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a schematic plan view showing an enlarged portion of the cell region of the semiconductor device of FIG. [Figure 3] FIG. 3 is a schematic cross-sectional view of the semiconductor device taken along line F3-F3 in FIG. [Figure 4] FIG. 4 is a schematic plan view showing an enlarged view of a part of the cell region and a part of the outer peripheral region of the semiconductor device of FIG. [Figure 5]FIG. 5 is a schematic cross-sectional view of the semiconductor device taken along line F5-F5 in FIG. [Figure 6] FIG. 6 is a schematic cross-sectional view for explaining the manufacturing process of the cell region of the semiconductor device of the first embodiment. [Figure 7] FIG. 7 is a schematic cross-sectional view showing the manufacturing process of the cell region subsequent to FIG. [Figure 8] FIG. 8 is a schematic cross-sectional view showing the manufacturing process of the cell region subsequent to FIG. [Figure 9] FIG. 9 is a schematic cross-sectional view showing the manufacturing process of the cell region subsequent to FIG. [Figure 10] FIG. 10 is a schematic cross-sectional view showing the manufacturing process of the cell region subsequent to FIG. [Figure 11] FIG. 11 is a schematic cross-sectional view showing the manufacturing process of the outer periphery region following FIG. [Figure 12] FIG. 12 is a schematic cross-sectional view showing the manufacturing process of the cell region subsequent to FIG. [Figure 13] FIG. 13 is a schematic cross-sectional view showing the manufacturing process of the outer periphery region subsequent to FIG. [Figure 14] FIG. 14 is a schematic cross-sectional view showing the manufacturing process of the cell region subsequent to FIG. [Figure 15] FIG. 15 is a schematic cross-sectional view showing the manufacturing process of the outer periphery region subsequent to FIG. [Figure 16] FIG. 16 is a schematic cross-sectional view showing the manufacturing process of the cell region subsequent to FIG. [Figure 17] FIG. 17 is a schematic cross-sectional view showing the manufacturing process of the outer periphery region subsequent to FIG. [Figure 18] FIG. 18 is a schematic cross-sectional view showing the manufacturing process of the cell region subsequent to FIG. [Figure 19] FIG. 19 is a schematic cross-sectional view showing the manufacturing process of the outer periphery region subsequent to FIG. [Figure 20] FIG. 20 is a schematic cross-sectional view showing the manufacturing process of the cell region subsequent to FIG. [Figure 21] FIG. 21 is a schematic cross-sectional view showing the manufacturing process of the outer periphery region subsequent to FIG. [Figure 22]FIG. 22 is a schematic cross-sectional view of an exemplary semiconductor device according to the second embodiment. [Figure 23] FIG. 23 is a schematic cross-sectional view of an exemplary semiconductor device according to the third embodiment. [Figure 24] FIG. 24 is a schematic plan view showing an enlarged view of a part of the cell region and a part of the outer peripheral region of the semiconductor device of FIG. [Figure 25] FIG. 25 is a schematic plan view showing an enlarged view of a part of the cell region and a part of the outer periphery region in a semiconductor device according to a modified example. [Figure 26] FIG. 26 is a schematic plan view showing an enlarged view of a part of the cell region and a part of the outer peripheral region in a semiconductor device according to a modified example. [Figure 27] FIG. 27 is a schematic plan view showing an enlarged view of a part of the cell region and a part of the outer periphery region in a semiconductor device according to a modified example. [Figure 28] FIG. 28 is a schematic plan view showing an enlarged view of a part of the cell region and a part of the outer periphery region in a semiconductor device according to a modified example. [Figure 29] FIG. 29 is a schematic plan view showing an enlarged view of a part of the cell region and a part of the outer periphery region in a semiconductor device according to a modified example. [Figure 30] FIG. 30 is a schematic plan view showing an enlarged view of a part of the cell region and a part of the outer peripheral region in a semiconductor device according to a modified example. [Figure 31] FIG. 31 is a schematic plan view showing an enlarged view of a part of the cell region and a part of the outer periphery region in a semiconductor device according to a modified example. [Figure 32] FIG. 32 is a schematic plan view showing an enlarged view of a part of the cell region and a part of the outer periphery region in a semiconductor device according to a modified example. [Figure 33] FIG. 33 is a schematic plan view showing an enlarged view of a part of the cell region and a part of the outer periphery region in a semiconductor device according to a modified example. [Figure 34] FIG. 34 is a schematic plan view showing an enlarged view of a part of the cell region and a part of the outer periphery region in a semiconductor device according to a modified example. [Figure 35] FIG. 35 is a schematic cross-sectional view showing an enlarged portion of the cell region in a semiconductor device according to a modified example. [Figure 36] FIG. 36 is a schematic cross-sectional view showing an enlarged view of a part of the cell region and a part of the outer peripheral region in a semiconductor device according to a modified example. [Figure 37] FIG. 37 is a schematic plan view showing an enlarged view of a part of the cell region and a part of the outer periphery region in a semiconductor device according to a modified example. [Figure 38] FIG. 38 is a schematic plan view showing an enlarged view of a part of the cell region and a part of the outer periphery region in a semiconductor device according to a modified example.

[0007] [Detailed explanation] Hereinafter, several embodiments of the semiconductor device of the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of explanation, the components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered to limit the present disclosure.

[0008] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0009] Terms such as "first," "second," and "third" are used in this disclosure merely to label and are not necessarily intended to dictate any ordering of their objects. The phrase "at least one" used in this disclosure means "one or more" of the desired options. As an example, the phrase "at least one" used in this disclosure means "only one option" or "both of two options" when the number of options is two. As another example, the phrase "at least one" used in this disclosure means "only one option" or "any combination of two or more options" when the number of options is three or more.

[0010] As used in this disclosure, "the dimensions (width, length, depth) of A are equal to the dimensions (width, length, depth) of B" or "the dimensions (width, length, depth) of A and the dimensions (width, length, depth) of B are equal to each other" also includes a relationship in which the difference between the dimensions (width, length, depth) of A and the dimensions (width, length, depth) of B is, for example, within 10% of the dimensions (width, length, depth) of A.

[0011] First Embodiment [Overall configuration of semiconductor device] The overall configuration of a semiconductor device 10 according to the first embodiment will be described with reference to Fig. 1. Fig. 1 schematically shows the planar structure of the semiconductor device 10 according to the first embodiment.

[0012] 1, the semiconductor device 10 is flat and has a thickness in the Z direction. Hereinafter, two mutually orthogonal directions perpendicular to the Z direction will be referred to as the "X direction" and the "Y direction." Also, viewing the semiconductor device 10 from the Z direction will be referred to as a "planar view."

[0013] The semiconductor device 10 has a rectangular shape in a plan view. The semiconductor device 10 includes a cell region 11 and a peripheral region 12 surrounding the cell region 11. The cell region 11 is a region in which an element structure including, for example, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) is provided. The peripheral region 12 includes a termination structure that relieves electric field concentration in the peripheral region 12. An example of the termination structure is a guard ring structure.

[0014] The semiconductor device 10 includes a source wiring 13 and a gate wiring 14. The source wiring 13 and the gate wiring 14 are provided on the surface of the semiconductor device 10. The source wiring 13 and the gate wiring 14 are covered with a passivation layer 15. The passivation layer 15 is provided, for example, over the entire surface of the semiconductor device 10. The passivation layer 15 includes a first opening 15A and a second opening 15B. The first opening 15A exposes a portion of the source wiring 13. The second opening 15B exposes a portion of the gate wiring 14. The region of the source wiring 13 exposed by the first opening 15A constitutes a source pad 13A. The region of the gate wiring 14 exposed by the second opening 15B constitutes a gate pad 14A.

[0015] The source wiring 13 is provided so as to cover the cell region 11. The source wiring 13 includes a recess 13B that is recessed inward of the source wiring 13 in a plan view. In the first embodiment, the recess 13B is provided in a portion of the source wiring 13 that corresponds to a corner portion of the surface of the semiconductor device 10 in a plan view.

[0016] The gate wiring 14 is provided in the outer peripheral region 12. The gate wiring 14 includes a pad portion 14B disposed in the recess 13B in a plan view, and finger portions 14C extending from the pad portion 14B along the sides of the surface of the semiconductor device 10. The pad portion 14B and the finger portions 14C are integrated. The finger portions 14C are annular in a plan view, surrounding the source wiring 13. Note that the shape of the finger portions 14C is not limited to annular and can be changed as desired.

[0017] Although not shown in FIG. 1, the semiconductor device 10 includes a drain wiring 16 (see FIG. 3). The drain wiring 16 is provided on the back surface opposite to the front surface of the semiconductor device 10. In one example, the drain wiring 16 is provided over the entire back surface of the semiconductor device 10.

[0018] [Cell Area Structure] The planar structure of the cell region 11 will be described with reference to Figures 2 and 3. Figure 2 schematically shows an enlarged planar structure of a portion of the cell region 11 in Figure 1. In Figure 2, to make the drawing easier to understand, gate electrodes 33 and source electrodes 34, which will be described later, are each marked with a dot. Figure 3 schematically shows a cross-sectional structure of the cell region 11 taken along line F3-F3 in Figure 2.

[0019] 3, the semiconductor device 10 includes a semiconductor layer 20 of a first conductivity type (n-type in the first embodiment) with its thickness direction aligned in the Z direction. The semiconductor layer 20 includes a first surface 20S and a second surface 20R opposite to the first surface 20S. The first surface 20S forms the front surface of the semiconductor device 10, and the second surface 20R forms the back surface of the semiconductor device 10. Here, the term "planar view" can also be interpreted as viewing the semiconductor layer 20 from the thickness direction.

[0020] The semiconductor layer 20 includes a semiconductor substrate 21 and an epitaxial layer 22 provided on the semiconductor substrate 21. The semiconductor substrate 21 forms a second surface 20R. The epitaxial layer 22 forms a first surface 20S.

[0021] The semiconductor substrate 21 is + The semiconductor substrate 21 is configured as a semiconductor substrate of the type. For example, a Si (silicon) substrate may be used as the semiconductor substrate 21. Note that a semiconductor substrate generally used for transistors, such as a SiC (silicon carbide) substrate or a GaN (gallium nitride) substrate, may also be used as the semiconductor substrate 21. + The n-type semiconductor substrate 21 may be a semiconductor substrate that has been grown as a crystal while being doped with n-type impurities.

[0022] Examples of n-type impurities that can be used include P (phosphorus), As (arsenic), and Sb (antimony). + The impurity concentration of the semiconductor substrate 21 is, for example, 1×10 18 cm -3 5x10 or more 20 cm -3 It can be as follows:

[0023] The epitaxial layer 22 is formed by epitaxially growing an n-type impurity on the semiconductor substrate 21. - The epitaxial layer 22 may be a layer of the same type. The impurity concentration of the epitaxial layer 22 is lower than the impurity concentration of the semiconductor substrate 21. In one example, the impurity concentration of the epitaxial layer 22 is 1×10 15 cm -3 More than 1×10 17 cm -3 The epitaxial layer 22 includes a drift region 23.

[0024] The semiconductor device 10 includes a plurality of second conductivity type column layers 24 provided in the semiconductor layer 20. The plurality of column layers 24 are provided in the epitaxial layer 22. It can also be said that the plurality of column layers 24 are provided in the drift region 23. Each column layer 24 may be a p-type semiconductor layer provided by ion-implanting p-type impurities into the epitaxial layer 22. Examples of p-type impurities that can be used include B (boron), Al (aluminum), and Ga (gallium). The impurity concentration of the column layer 24 is, for example, 1×10 15 cm -3 More than 1×10 18 cm -3 It can be as follows:

[0025] The column layers 24 are spaced apart in the X direction. Here, the X direction corresponds to the "first direction." Furthermore, the Y direction, which is orthogonal to the X direction in a plan view, corresponds to the "second direction."

[0026] As shown in FIG. 2, each column layer 24 extends in the Y direction in plan view. Each column layer 24 is strip-shaped with a predetermined width (dimension in the X direction) in plan view. Therefore, the multiple column layers 24 are striped in plan view. In one example, as shown in FIG. 3, the multiple column layers 24 are arranged at equal intervals in the X direction. Hereinafter, the pitch between the multiple column layers 24 will be referred to as the "column layer pitch P1." The column layer pitch P1 is the arrangement interval between the multiple column layers 24 in the X direction. Therefore, the column layer pitch P1 can be defined as the center-to-center distance in the width direction (X direction in the first embodiment) of two column layers 24 adjacent to each other in the X direction. In one example, the column layer pitch P1 is 7 μm.

[0027] Each column layer 24 extends in the Z direction. In other words, each column layer 24 extends in the thickness direction of the semiconductor layer 20 (epitaxial layer 22). Each column layer 24 extends from a portion of the epitaxial layer 22 closer to the first surface 20S to a portion of the epitaxial layer 22 closer to the second surface 20R, beyond the center of the epitaxial layer 22 in the Z direction.

[0028] The side surface 24A of each column layer 24 is provided as a periodically undulating uneven surface. More specifically, a plurality of convex portions 24AA and a plurality of concave portions 24AB are provided alternately in the Z direction on the side surface 24A of each column layer 24. The number of these convex portions 24AA and concave portions 24AB usually roughly matches the number of steps in the n-type semiconductor layer 63 (see Figures 7 and 8), which will be described later. The width W1 of the column layer 24 (the dimension of the convex portion 24AA in the X direction) can be, for example, 2 μm or more and 3 μm or less. Here, the width W1 of the column layer 24 can be defined by the maximum dimension of the convex portion 24AA of the column layer 24 in the X direction.

[0029] In this way, a plurality of column layers 24 are provided in the semiconductor layer 20 (epitaxial layer 22), thereby providing a superjunction structure 20A in the semiconductor layer 20 (epitaxial layer 22). That is, the superjunction structure 20A is formed by the p-type column layers 24 and the n-type column layers 24. -The semiconductor device 10 is configured by alternately and repeatedly arranging the thin-film epitaxial layer 22 and the thin-film epitaxial layer 22 in a direction (X direction in the first embodiment) perpendicular to the thickness direction (Z direction) of the epitaxial layer 22. Therefore, it can be said that the semiconductor device 10 includes a superjunction structure 20A.

[0030] The semiconductor device 10 includes a plurality of second conductivity type body regions 25 spaced apart in the X direction relative to the first surface 20S. Each body region 25 is provided in a surface layer portion of the semiconductor layer 20 closer to the first surface 20S. Each body region 25 may be a p-type semiconductor layer provided by ion implanting p-type impurities into the epitaxial layer 22. The impurity concentration of the body region 25 is, for example, 1×10 15 cm -3 More than 1×10 19 cm -3 In one example, the impurity concentration of the body region 25 may be equal to the impurity concentration of the column layer 24.

[0031] Each body region 25 has a strip shape extending in the Y direction in a plan view. In the first embodiment, the multiple body regions 25 are arranged in stripes at intervals in the X direction. Hereinafter, the pitch in the X direction of the body regions 25 is referred to as the "body region pitch P2." The body region pitch P2 is the arrangement interval in the X direction of the multiple body regions 25. Therefore, the body region pitch P2 can be defined as the center-to-center distance in the width direction (X direction in the first embodiment) of two body regions 25 adjacent in the X direction.

[0032] The inter-body region pitch P2 is shorter than the inter-column layer pitch P1. In the first embodiment, the inter-body region pitch P2 is equal to 1 / 2 of the inter-column layer pitch P1. In other words, the ratio P2 / P1 of the inter-body region pitch P2 to the inter-column layer pitch P1 is 1 / 2. In one example, the inter-column layer pitch P1 is 7 μm, and the inter-body region pitch P2 is 3.5 μm. Note that, as long as the inter-body region pitch P2 is shorter than the inter-column layer pitch P1, the ratio P2 / P1 of the inter-body region pitch P2 to the inter-column layer pitch P1 may be a value other than 1 / 2.

[0033] In the first embodiment, the width W2 of the body region 25 is smaller than the width W1 of the column layer 24. Here, the width W2 of the body region 25 can be defined by the maximum dimension of the body region 25 in the X direction. The relationship between the width W1 of the column layer 24 and the width W2 of the body region 25 can be changed as desired. In one example, the width W2 of the body region 25 may be equal to the width W1 of the column layer 24. In another example, the width W2 of the body region 25 may be larger than the width W1 of the column layer 24.

[0034] In the first embodiment, the width W2 of the body region 25 is slightly larger than the first column-layer distance D1, which is the distance between the convex portions 24AA of the column layers 24 adjacent to each other in the X direction. On the other hand, the width W2 of the body region 25 is slightly smaller than the second column-layer distance D2, which is the distance between the concave portions 24AB of the column layers 24 adjacent to each other in the X direction. In addition, the width W2 of the body region 25 is larger than the body-region distance D3, which is the distance between the body regions 25 adjacent to each other in the X direction.

[0035] The width W1 of the column layer 24 and the width W2 of the body region 25 can be changed arbitrarily. The width W2 of the body region 25 may be equal to or smaller than the first column-layer distance D1. The width W2 of the body region 25 may be equal to or smaller than the second column-layer distance D2. The width W2 of the body region 25 may be equal to or smaller than the body region distance D3.

[0036] In the first embodiment, the plurality of column layers 24 are disposed at positions overlapping the corresponding body regions 25 in a plan view. Each column layer 24 is connected to the corresponding body region 25 in the Z direction. In one example, the portion of the side surface 24A of each column layer 24 that is connected to the body region 25 is a recess 24AB. As shown in FIG. 3 , the interface between each body region 25 and the drift region 23 forms a pn junction surface. Therefore, a parasitic diode 25A is formed in each body region 25 at the interface with the drift region 23.

[0037] The semiconductor device 10 includes a first conductivity type source region 26 provided in the first surface 20S of each of the plurality of body regions 25. Each source region 26 is provided in the corresponding body region 25. Each source region 26 is provided in a surface layer portion of the corresponding body region 25.

[0038] Each source region 26 has a strip shape extending in the Y direction in plan view. In plan view, each source region 26 is provided at a predetermined distance inward from the periphery of the corresponding body region 25 (the boundary between the body region 25 and the drift region 23). In the first embodiment, each source region 26 is a region slightly smaller than the corresponding body region 25 in plan view. In this way, in plan view, the body region 25 is interposed between the source region 26 and the drift region 23. This interposed body region 25 becomes a channel region 27 in which a channel is formed when a gate voltage is applied to a gate electrode 33, which will be described later.

[0039] Each source region 26 is provided by selectively ion-implanting n-type impurities into the body region 25. The impurity concentration of each source region 26 is higher than the impurity concentration of the drift region 23. The impurity concentration of each source region 26 is, for example, 1×10 18 cm -3 5x10 or more 20 cm -3 It can be as follows:

[0040] The semiconductor device 10 includes a second conductivity type body contact region 28 provided to penetrate the source region 26 in the Z direction. The body contact region 28 passes through the source region 26 and reaches the body region 25. On the other hand, the body contact region 28 is provided within the body region 25 and does not reach the drift region 23.

[0041] As shown in FIG. 2, the body contact region 28 has a strip shape extending in the Y direction in a plan view. The body contact region 28 is selectively provided in the surface layer portion of the body region 25. The body contact region 28 is provided by selectively ion-implanting p-type impurities into the body region 25. The impurity concentration of the body contact region 28 is higher than the impurity concentration of the body region 25. The impurity concentration of the body contact region 28 is, for example, 1×10 17 cm -3 More than 1×10 19 cm -3 It can be as follows:

[0042] A MISFET element structure 20B (unit cell) is configured by the body region 25, the source region 26, and the body contact region 28. That is, the element structures 20B are arranged in the cell region 11 in a striped pattern.

[0043] 3, the semiconductor device 10 includes a gate insulating film 31 and a source insulating film 32 provided on the first surface 20S. The semiconductor device 10 includes a gate electrode 33 disposed on the gate insulating film 31 and a source electrode 34 disposed on the source insulating film 32.

[0044] The gate insulating film 31 is on and in contact with the first surface 20S. The gate insulating film 31 is arranged to straddle two body regions 25 adjacent in the X direction. More specifically, the gate insulating film 31 covers part of the surface of the source region 26, the surface of the channel region 27, and part of the surface of the drift region 23. It can be said that the gate insulating film 31 covers at least the surface of the corresponding body region 25. The gate insulating film 31 extends in the Y direction. A plurality of gate insulating films 31 are provided spaced apart in the X direction.

[0045] The source insulating film 32 is in contact with the first surface 20S on the first surface 20S. The source insulating film 32 is provided on the first surface 20S at a distance from the gate insulating film 31 in the X direction. The source insulating film 32 is arranged to straddle two body regions 25 adjacent to each other in the X direction. More specifically, the source insulating film 32 covers a part of the surface of the source region 26, the surface of the channel region 27, and a part of the surface of the drift region 23. It can be said that the source insulating film 32 covers at least the surface of the corresponding body region 25. A plurality of source insulating films 32 are provided at a distance in the X direction. The source insulating film 32 extends in the Y direction. The source insulating film 32 is arranged between gate insulating films 31 adjacent to each other in the X direction. In other words, the plurality of gate insulating films 31 and the plurality of source insulating films 32 are arranged alternately one by one in the X direction.

[0046] Both the gate insulating film 31 and the source insulating film 32 may be made of, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a hafnium oxide film, an alumina film, or a tantalum oxide film. The gate insulating film 31 and the source insulating film 32 may be made of, for example, the same material. For example, the gate insulating film 31 and the source insulating film 32 are made of a silicon oxide film. In this case, the MISFET may be referred to as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The gate insulating film 31 and the source insulating film 32 may have the same thickness. For example, the thickness of both the gate insulating film 31 and the source insulating film 32 may be 300 Å or more and 700 Å or less. The thicknesses of the gate insulating film 31 and the source insulating film 32 may be set independently. That is, the thicknesses of the gate insulating film 31 and the source insulating film 32 may be different from each other.

[0047] The gate electrode 33 is on the gate insulating film 31 and is in contact with the gate insulating film 31. The gate electrode 33 includes a plurality of first gate portions 33A provided corresponding to the gate insulating film 31. The plurality of first gate portions 33A are provided spaced apart in the X direction. In one example, each first gate portion 33A is provided over the entire corresponding gate insulating film 31 in a plan view. Therefore, each first gate portion 33A extends in the Y direction. The gate electrode 33 has a predetermined width. Here, the width of the gate electrode 33 is the dimension in a direction perpendicular to the direction in which the gate electrode 33 extends in a plan view. Therefore, the width of the first gate portion 33A is the dimension in the X direction of the first gate portion 33A. The gate electrode 33 is electrically connected to the gate wiring 14 shown in FIG. 1.

[0048] The source electrode 34 is on the source insulating film 32 and is in contact with the source insulating film 32. A plurality of source electrodes 34 are provided corresponding to the source insulating films 32. Therefore, the plurality of source electrodes 34 are provided spaced apart in the X direction. The plurality of source electrodes 34 and the plurality of gate electrodes 33 are alternately arranged one by one in the X direction. The distance Dsg between the source electrodes 34 and the gate electrodes 33 adjacent to each other in the X direction can be set to 0.5 μm or more and 3 μm or less. In one example, the distance Dsg can be set to 1.7 μm. The distance Dsg can be changed as desired depending on the performance required of the semiconductor device 10.

[0049] In one example, each source electrode 34 is provided over the entire corresponding source insulating film 32 in a plan view. Therefore, each source electrode 34 extends in the Y direction. The source electrode 34 has a predetermined width. Here, the width WS of the source electrode 34 is the dimension in a direction perpendicular to the direction in which the source electrode 34 extends in a plan view. In the first embodiment, the width WS of the source electrode 34 is the dimension of the source electrode 34 in the X direction. In one example, the width WS of the source electrode 34 is equal to the width WG of the gate electrode 33. In one example, the width WS of the source electrode 34 is equal to the width WG1 of the first gate portion 33A.

[0050] The gate electrode 33 may be made of, for example, polysilicon into which an impurity has been implanted. The materials constituting the gate electrode 33 can be changed as desired. For example, the gate electrode 33 may be made of Al, Cu (copper), Ti (titanium), or the like. The source electrode 34 may be made of, for example, polysilicon into which an impurity has been implanted. When both the gate electrode 33 and the source electrode 34 are made of polysilicon into which an impurity has been implanted, the impurity concentration of the gate electrode 33 and the impurity concentration of the source electrode 34 may be equal to each other. Furthermore, the impurity concentration of the source electrode 34 may be different from the impurity concentration of the gate electrode 33.

[0051] The semiconductor device 10 includes an interlayer insulating film 35 provided on the first surface 20S. The interlayer insulating film 35 covers the gate electrode 33 and the source electrode 34. The interlayer insulating film 35 is made of an insulating material such as a silicon oxide film, a silicon nitride film, or TEOS (tetraethoxysilane).

[0052] The interlayer insulating film 35 includes a contact hole 35A that exposes the body contact region 28 and the source region 26 of the cell region 11 (MISFET). The contact hole 35A penetrates the interlayer insulating film 35 in the Z direction.

[0053] The source wiring 13 is provided on the interlayer insulating film 35. Therefore, it can be said that the source wiring 13 is provided on the first surface 20S. The source wiring 13 includes a wiring main body 13C provided on the interlayer insulating film 35. The wiring main body 13C includes a portion that constitutes the source pad 13A shown in FIG. 1. The wiring main body 13C is in contact with the surface of the interlayer insulating film 35. The wiring main body 13C is made of a material containing, for example, Al, Cu, etc. In one example, the wiring main body 13C is made of a material containing Al.

[0054] The source wiring 13 includes a first source contact portion 13D (see FIG. 5) and a second source contact portion 13E, which will be described later. Both the first source contact portion 13D and the second source contact portion 13E are in contact with the wiring main body 13C. The first source contact portion 13D is made of, for example, W, Cu, Al, or polysilicon. The second source contact portion 13E is made of, for example, W, Cu, Al, or polysilicon. The first source contact portion 13D and the second source contact portion 13E may be made of, for example, the same material. In the first embodiment, the second source contact portion 13E is made of W.

[0055] The source wiring 13 is electrically connected to the body contact region 28 and the source region 26. Specifically, the second source contact portion 13E is embedded in the contact hole 35A. The second source contact portion 13E is in contact with the body contact region 28 through the contact hole 35A. In the first embodiment, the second source contact portion 13E is in contact with both the body contact region 28 and the source region 26. In other words, the second source contact portion 13E connects the wiring main body 13C to the body contact region 28 and the source region 26.

[0056] The second source contact portion 13E extends in the Y direction in plan view. The second source contact portion 13E is strip-shaped with a predetermined width in plan view. In the example shown in FIG. 3, the second source contact portion 13E includes a portion whose width is constant in the Z direction. Note that the second source contact portion 13E may have a tapered shape whose width narrows from the surface of the interlayer insulating film 35 toward the first surface 20S.

[0057] In one example, the ratio (LZ / LX) of the length LZ in the Z direction of the second source contact portion 13E to the maximum length LX in the X direction of the second source contact portion 13E is, for example, 1 or more and 5 or less. In the first embodiment, the maximum length LX in the X direction of the second source contact portion 13E is the length in the X direction of the end face of the second source contact portion 13E that contacts the wire main body 13C. The maximum length LX in the X direction of the second source contact portion 13E can also be said to be the maximum width of the second source contact portion 13E. The length LZ in the Z direction of the second source contact portion 13E can be defined as the distance in the Z direction between the end face of the second source contact portion 13E that contacts the wire main body 13C and the end face of the second source contact portion 13E that contacts the body contact region 28.

[0058] The maximum length LX of the second source contact portion 13E in the X direction is equal to the maximum length of the contact hole 35A in the X direction. In other words, the maximum length LX can be said to be the maximum width of the contact hole 35A. In the first embodiment, the maximum length LX can be set to 0.7 μm. Furthermore, the distance Dc between adjacent second source contact portions 13E in the X direction is greater than the maximum length LX. The distance Dc can be set to, for example, 2.8 μm.

[0059] Furthermore, the width WG1 of the first gate portion 33A as the width WG of the gate electrode 33 is equal to the width WS1 of the source electrode 34 in the cell region 11 as the width WS of the source electrode 34. In one example, the width WG1 of the first gate portion 33A and the width WS of the source electrode 34 can be 1.8 μm.

[0060] A drain wiring 16 is provided on the second surface 20R of the semiconductor layer 20. The drain wiring 16 is made of a material including Al, Cu, Au (gold), Ni (nickel), etc. In one example, the drain wiring 16 is provided over the entire surface of the second surface 20R. The drain wiring 16 is in contact with, for example, the second surface 20R. The drain wiring 16 is electrically connected to the drift region 23 through the semiconductor substrate 21.

[0061] [Structure of the outer region] The connection structure of the source electrode 34 and the source wiring 13 in the peripheral region 12 will be described with reference to Figures 4 and 5. Figure 4 schematically shows an enlarged planar structure of a portion of the peripheral region 12. Figure 5 schematically shows a cross-sectional structure of the peripheral region 12 taken along line F5-F5 in Figure 4. Note that the interlayer insulating film 35 is omitted in Figure 4 to make the drawing easier to understand.

[0062] As shown in FIGS. 4 and 5 , the semiconductor layer 20 includes a p-type source contact region 29. The source contact region 29 is provided in a surface layer portion of the semiconductor layer 20. The source contact region 29 is provided in the peripheral region 12. In one example, the source contact region 29 is provided in the peripheral region 12 at a distance from the cell region 11. In one example, the source contact region 29 has an annular shape surrounding the cell region 11 in a planar view. Therefore, the source contact region 29 is provided closer to the periphery of the semiconductor layer 20 than the body region 25 and at a distance from the body region 25 in a planar view. In one example, the source contact region 29 has an annular shape surrounding the body region 25 in a planar view. Note that the source contact region 29 may also be a region integrated with the body region 25.

[0063] The semiconductor device 10 includes a peripheral insulating film 37 provided in the peripheral region 12. The peripheral insulating film 37 covers a portion of the first surface 20S of the semiconductor layer 20 that corresponds to the peripheral region 12. The peripheral insulating film 37 is in contact with the first surface 20S. In the first embodiment, the thickness of the peripheral insulating film 37 is equal to the thickness of the gate insulating film 31 and the thickness of the source insulating film 32. The thickness of the peripheral insulating film 37 can be changed as desired.

[0064] The peripheral insulating film 37 has a ring shape surrounding the cell region 11 in a plan view. The peripheral insulating film 37 is connected to a plurality of gate insulating films 31 and a plurality of source insulating films 32. In one example, the peripheral insulating film 37, the plurality of gate insulating films 31, and the plurality of source insulating films 32 are integrated.

[0065] Both the first gate portion 33A of the gate electrode 33 and the source electrode 34 extend in the Y direction from the cell region 11 to the peripheral region 12. That is, the first gate portion 33A of the gate electrode 33 extends in the Y direction over the gate insulating film 31 and the peripheral insulating film 37. The source electrode 34 extends in the Y direction over the source insulating film 32 and the peripheral insulating film 37. The first gate portion 33A extends closer to the outer edge of the semiconductor layer 20 in the Y direction than the source electrode 34. The source electrode 34 extends closer to the outer edge of the semiconductor layer 20 in the Y direction than the second source contact portion 13E.

[0066] The gate electrode 33 includes a second gate portion 33B connecting the multiple first gate portions 33A. The second gate portion 33B extends in the X direction. The second gate portion 33B is provided on the peripheral insulating film 37. The second gate portion 33B is on the peripheral insulating film 37 and in contact with the peripheral insulating film 37. The second gate portion 33B is arranged closer to the outer edge of the semiconductor layer 20 in the Y direction than the source electrode 34. In one example, the multiple first gate portions 33A and the second gate portion 33B are integrated. In one example, the thickness of the second gate portion 33B is equal to the thickness of the first gate portion 33A. The thicknesses of the first gate portion 33A and the second gate portion 33B can each be changed as desired.

[0067] Each first gate portion 33A includes a wide portion 33AA and a narrow portion 33AB. The narrow portion 33AB is located closer to the second gate portion 33B in the Y direction than the wide portion 33AA. The narrow portion 33AB is a portion of the first gate portion 33A that is narrower than the wide portion 33AA. The width WGB of the narrow portion 33AB can also be said to be smaller than the width WGA of the wide portion 33AA. In one example, the wide portion 33AA is located closer to the cell region 11 in the Y direction than the Y-direction edge of the source electrode 34. The wide portion 33AA is located on both the peripheral insulating film 37 and the gate insulating film 31. The narrow portion 33AB is located on the peripheral insulating film 37. The narrow portion 33AB is connected to the second gate portion 33B. The narrow portion 33AB is located at a position in the Y direction corresponding to a source opening 38, which will be described later. That is, the narrow width portion 33AB is disposed between source openings 38 adjacent to each other in the X direction. The narrow width portion 33AB is provided at a position adjacent to the source opening 38 in the X direction.

[0068] 5, the interlayer insulating film 35 covers the peripheral region 12. That is, the interlayer insulating film 35 covers the peripheral insulating film 37. Therefore, the interlayer insulating film 35 covers both the gate electrode 33 (see FIG. 4) and the source electrode 34 provided on the peripheral insulating film 37.

[0069] Both the interlayer insulating film 35 and the peripheral insulating film 37 include source openings 38 that expose the first surface 20S of the semiconductor layer 20. The source openings 38 expose both the source electrode 34 and the source contact region 29 in the peripheral region 12. A plurality of source openings 38 are provided and spaced apart in the X direction. As shown in FIG. 4 , each source opening 38 is provided between adjacent first gate portions 33A in the X direction. Each source opening 38 is located closer to the cell region 11 in the Y direction than the second gate portion 33B. Each source opening 38 is located away from the cell region 11 in the Y direction. Each source opening 38 is located adjacent to the second gate portion 33B in the Y direction. Each source opening 38 has a rectangular shape in a plan view. In one example, each source opening 38 has a rectangular shape with longer sides in the Y direction and shorter sides in the X direction in a plan view.

[0070] A portion of the source electrode 34 is disposed so as to overlap the source contact region 29 in a plan view. More specifically, an electrode end 34A, which is the Y-direction end of the source electrode 34, is exposed from the source opening 38 in a plan view. Therefore, it can be said that the source electrode 34 extends to a position overlapping with the source opening 38. The electrode end 34A of the source electrode 34 is disposed at an end of the source opening 38 closer to the cell region 11 in the Y direction. The electrode end 34A is disposed spaced apart in the Z direction from the first surface 20S of the semiconductor layer 20. A peripheral insulating film 37 is interposed between the electrode end 34A and the first surface 20S of the semiconductor layer 20. Therefore, the electrode end 34A is disposed spaced apart in the Z direction from the source contact region 29. The source electrode 34 is located at the Y-direction end of the source contact region 29 in a plan view. More specifically, the electrode end 34A of the source electrode 34 is located at an end of the source contact region 29 closer to the cell region 11 in the Y direction.

[0071] The first source contact portion 13D is in contact with both the source contact region 29 and the source electrode 34. More specifically, the first source contact portion 13D is embedded in the source opening 38. That is, a plurality of first source contact portions 13D are provided corresponding to the corresponding source openings 38. Therefore, the plurality of first source contact portions 13D are arranged spaced apart from each other in the X direction. The first source contact portion 13D embedded in the source opening 38 is in contact with the electrode end portion 34A of the source electrode 34 exposed from the source opening 38 and the source contact region 29 exposed from the source opening 38. Therefore, the source electrode 34 is electrically connected to the source contact region 29 through the first source contact portion 13D.

[0072] As shown in FIG. 4, the multiple source openings 38 have, for example, the same size and shape. Each source opening 38 has a predetermined width WA. The width WA of each source opening 38 is larger than the width WB of the second source contact portion 13E. Therefore, the width of the first source contact portion 13D (see FIG. 5) embedded in the source opening 38 is larger than the width WB of the second source contact portion 13E. Furthermore, the width WA of each source opening 38 is larger than the width WG1 of the first gate portion 33A. It can be said that the width WA of each source opening 38 is larger than the width WG of the gate electrode 33. Therefore, the width of the first source contact portion 13D embedded in the source opening 38 is larger than the width WG1 of the first gate portion 33A. Furthermore, the width WA of each source opening 38 is larger than the width WS1 of the source electrode 34 in the cell region 11. Therefore, the width of the first source contact portion 13D embedded in the source opening 38 is larger than the width WS1 of the source electrode 34 in the cell region 11.

[0073] In this manner, the source electrode 34 and the source wiring 13 are electrically connected by the first source contact portion 13D in the source opening 38. The source electrode 34 is disposed on the semiconductor layer 20, sandwiching the source insulating film 32 and the peripheral insulating film 37 therebetween. Therefore, the semiconductor device 10 includes a capacitor between the source electrode 34 and the semiconductor layer 20, the capacitance of which corresponds to the area of ​​the source electrode 34 overlapping with the source insulating film 32 and the peripheral insulating film 37 and the thicknesses of the insulating films 32 and 37. The resistance component of the source electrode 34, made of polysilicon, essentially functions as a resistor connected to the source wiring 13 by the first source contact portion 13D. Therefore, it can be said that the semiconductor device 10 includes a capacitor and a resistor between the capacitor and the source wiring 13. As shown in FIG. 3 , a drain wiring 16 is provided on the second surface 20R of the semiconductor layer 20. That is, the semiconductor device 10 includes a resistor and a capacitor between the source wiring 13 and the drain wiring 16. The resistor and capacitor form a snubber circuit 40 connected between the source wiring 13 and the drain wiring 16. In other words, the semiconductor device 10 includes a snubber circuit 40 that includes a resistance component of the source electrode 34 and a capacitance component between the source electrode 34 and the semiconductor layer 20 .

[0074] As shown in FIG. 4 , the semiconductor device 10 includes a plurality of gate electrodes 33 and a plurality of source electrodes 34 provided on a semiconductor layer 20 and arranged alternately in the X direction. Each of the plurality of source electrodes 34 provided on the semiconductor layer 20 is one electrode of a resistor and a capacitor of a snubber circuit 40. The plurality of source electrodes 34 also straddles the cell region 11 and the peripheral region 12. In this manner, the snubber circuit 40 is provided in the cell region 11. A portion of the snubber circuit 40 is also provided in the peripheral region 12. In this manner, it can be said that the snubber circuit 40 is provided across the cell region 11 and the peripheral region 12.

[0075] [Method of manufacturing a semiconductor device] An example of a method for manufacturing the semiconductor device 10 will be described with reference to Figures 6 to 21. Figures 6 to 10, 12, 14, 16, 18, and 20 show the cross-sectional structure of the semiconductor device 10 corresponding to Figure 3. Figures 11, 13, 15, 17, 19, and 21 show the cross-sectional structure of the semiconductor device 10 corresponding to Figure 5.

[0076] As shown in FIGS. 6 to 8, the method for manufacturing the semiconductor device 10 includes forming a semiconductor layer 20. 6, a semiconductor substrate 21 is first prepared. Then, an initial base layer 61 is formed by epitaxial growth on the semiconductor substrate 21. Next, p-type impurities 62 are selectively implanted into the surface of the initial base layer 61 at positions where the column layers 24 (see FIG. 3) are to be formed.

[0077] Next, as shown in FIG. 7, multiple n-type semiconductor layers 63 are stacked on the initial base layer 61 by multi-epitaxial growth, which repeats the process of selectively injecting p-type impurities 62 into positions where the column layers 24 are to be formed while forming n-type semiconductor layers 63.

[0078] 8, an uppermost n-type semiconductor layer 64 is deposited without implanting p-type impurities 62. As a result, the plurality of n-type semiconductor layers 63, 64 and the initial base layer 61 are integrated to form the epitaxial layer 22 (drift region 23). Through the above steps, the semiconductor layer 20 is formed.

[0079] 9, the manufacturing method of the semiconductor device 10 includes forming a column layer 24. In this step, for example, an annealing treatment is performed at a temperature of 1000° C. or higher and 1200° C. or lower to diffuse the p-type impurities 62 (see FIG. 8) in the initial base layer 61 and the multiple n-type semiconductor layers 63, 64. As a result, the column layer 24 is formed in the epitaxial layer 22.

[0080] As shown in FIG. 10, the method for manufacturing the semiconductor device 10 includes forming a body region 25, forming a source region 26, and forming a body contact region .

[0081] To form the body regions 25, p-type impurities are selectively implanted into the surface layer portion of the epitaxial layer 22. This forms a plurality of body regions 25. In the first embodiment, the body region 25 disposed directly above the column layer 24 is connected to the column layer 24.

[0082] To form the source regions 26, n-type impurities are selectively implanted into the surface layer of each body region 25. As a result, the source regions 26 are formed in each body region 25. To form the body contact regions 28, p-type impurities are selectively implanted into the surface layer portion of each body region 25. This forms the body contact regions 28 in each body region 25. The body contact regions 28 are formed so as to penetrate the source regions 26 in the Z direction.

[0083] As shown in FIG. 11, the method for manufacturing the semiconductor device 10 includes forming a source contact region 29. To form the source contact region 29, p-type impurities are selectively implanted into the surface layer portion of the epitaxial layer 22. This results in the formation of the source contact region 29. The step of forming the source contact region 29 may be performed in a common step with the step of forming the body region 25. That is, the source contact region 29 and the plurality of body regions 25 may be formed simultaneously. Alternatively, the source contact region 29 and the plurality of body regions 25 may be integrated.

[0084] As shown in FIG. 12, the method for manufacturing the semiconductor device 10 includes forming a gate insulating film 31 and a source insulating film 32. In this step, the epitaxial layer 22 is thermally oxidized to grow an oxide film, and then the oxide film is patterned to form the gate insulating film 31 and the source insulating film 32 .

[0085] As shown in FIG. 13, the method for manufacturing the semiconductor device 10 includes forming a peripheral insulating film 37 and forming a first source opening 38A. In this step, epitaxial layer 22 is thermally oxidized to grow an oxide film, and then the oxide film is patterned to form peripheral insulating film 37 and first source opening 38A. First source opening 38A exposes source contact region 29. The step of forming peripheral insulating film 37 and first source opening 38A may be performed in a common step with the step of forming gate insulating film 31 and source insulating film 32. In other words, gate insulating film 31, source insulating film 32, peripheral insulating film 37, and first source opening 38A may be formed simultaneously.

[0086] As shown in FIGS. 14 and 15, the method for manufacturing the semiconductor device 10 includes forming a gate electrode 33 and a source electrode 34. In this step, for example, an impurity-doped polysilicon film is formed so as to cover the epitaxial layer 22, the gate insulating film 31, the source insulating film 32, and the peripheral insulating film 37. Subsequently, the polysilicon film is selectively etched by, for example, photolithography to form the gate electrode 33 and the source electrode 34.

[0087] As shown in FIGS. 16 and 17, the method for manufacturing the semiconductor device 10 includes forming an interlayer insulating film 35, forming a contact hole 35A, and forming a second source opening 38B.

[0088] 16, in the step of forming the interlayer insulating film 35, the interlayer insulating film 35 is formed by, for example, chemical vapor deposition (CVD) so as to cover the gate electrode 33 and the source electrode 34. In this step, the interlayer insulating film 35 is formed so as to cover the peripheral insulating film 37.

[0089] In the step of forming the contact holes 35A, the interlayer insulating film 35 is etched by photolithography, for example, to form the contact holes 35A in the interlayer insulating film 35. 17, in the step of forming the second source opening 38B, the interlayer insulating film 35 is etched by, for example, photolithography to form the second source opening 38B in the interlayer insulating film 35. The second source opening 38B communicates with the first source opening 38A. This forms the source opening 38. The source opening 38 is formed so as to expose the electrode end 34A of the source electrode 34.

[0090] The step of forming the second source opening 38B may be performed in the same step as the step of forming the contact hole 35A. That is, the contact hole 35A and the second source opening 38B may be formed at the same time.

[0091] As shown in FIGS. 18 and 19, the manufacturing method of the semiconductor device 10 includes thinning the semiconductor substrate 21. In this step, the semiconductor substrate 21 is ground from the back surface side that forms the second surface 20R of the semiconductor layer 20. This flattens the back surface of the semiconductor substrate 21. The thickness of the semiconductor substrate 21 after grinding is 90 μm or more and 310 μm or less. The thickness of the semiconductor substrate 21 after grinding can be changed as desired.

[0092] The manufacturing method of the semiconductor device 10 then includes forming the first source contact portion 13D and the second source contact portion 13E. In this step, a first metal layer is formed on the interlayer insulating film 35 while filling the contact hole 35A and the source opening 38. The first metal layer is then patterned to remove the first metal layer on the interlayer insulating film 35. This results in the second source contact portion 13E embedded in the contact hole 35A and the first source contact portion 13D embedded in the source opening 38.

[0093] 20 and 21, the method for manufacturing the semiconductor device 10 includes forming the source wiring 13 and the gate wiring 14 (see FIG. 1). In this step, a second metal layer that constitutes the source wiring 13 and the gate wiring 14 is formed on the interlayer insulating film 35 by, for example, sputtering. Subsequently, the second metal layer is patterned to form the source wiring 13 and the gate wiring 14.

[0094] Although not shown, the manufacturing method of the semiconductor device 10 includes forming a passivation layer 15. In this step, the passivation layer 15 (see FIG. 1) is formed so as to cover the source wiring 13 and the gate wiring 14. Subsequently, a first opening 15A and a second opening 15B (both see FIG. 1) are formed in the passivation layer 15 by, for example, photolithography.

[0095] Although not shown, the method for manufacturing the semiconductor device 10 includes forming the drain wiring 16. In this step, the drain wiring 16 is formed on the second surface 20R of the semiconductor layer 20 by, for example, electrolytic plating. Through the above steps, the semiconductor device 10 is manufactured.

[0096] [Operation of the first embodiment] The operation of the semiconductor device 10 of the first embodiment will be described. Comparative examples of the semiconductor device 10 include a semiconductor device of a first comparative example and a semiconductor device of a second comparative example.

[0097] The semiconductor device of the first comparative example has a configuration in which the pitch P2 between body regions is equal to the pitch P1 between column layers, and the gate electrodes 33 and source electrodes 34 are arranged alternately in the X direction. In the semiconductor device of the second comparative example, the pitch P2 between the body regions is half the pitch P1 between the column layers, and the source electrode 34 is omitted. That is, in the semiconductor device of the second comparative example, the gate electrodes 33 are arranged at the pitch P2 between the body regions in the cell region 11.

[0098] In the semiconductor device of the first comparative example, the number of gate electrodes 33 is small. Therefore, the gate-drain capacitance is low, and the switching speed of the semiconductor device can be improved. On the other hand, in the semiconductor device of the first comparative example, the gate electrodes 33 and the source electrodes 34 are alternately arranged in the X direction, which reduces the channel path. As a result, the on-resistance of the semiconductor device of the first comparative example is large.

[0099] In the semiconductor device of the second comparative example, the pitch P2 between the body regions is half the pitch P1 between the column layers, resulting in a larger number of channel paths. As a result, the on-resistance can be reduced in the semiconductor device of the second comparative example. On the other hand, the number of gate electrodes 33 is increased, resulting in an increase in gate-drain capacitance. This makes it difficult to improve the switching speed of the semiconductor device. As such, it is difficult to achieve both an improvement in switching speed and a reduction in on-resistance in the semiconductor devices of the first and second comparative examples.

[0100] In this regard, in the semiconductor device 10 of the first embodiment, the pitch P2 between the body regions is half the pitch P1 between the column layers, and the gate electrodes 33 and the source electrodes 34 are alternately arranged in the X direction. This allows the channel path to be increased compared to the semiconductor device of the first comparative example, and the gate-drain capacitance to be reduced compared to the semiconductor device of the second comparative example. Therefore, it is possible to achieve both improved switching speed and reduced on-resistance.

[0101] Additionally, a source electrode 34 electrically connected to the source wiring 13 and a source insulating film 32 interposed between the source electrode 34 and the semiconductor layer 20 are provided in the cell region 11. The resistance component of the source electrode 34 and the capacitance component of the source insulating film 32 form a snubber circuit 40. In other words, the semiconductor device 10 can incorporate the snubber circuit 40. This snubber circuit 40 can reduce noise in the semiconductor device 10.

[0102] [Effects of the first embodiment] According to the semiconductor device 10 of the first embodiment, the following effects can be obtained. (1-1) The semiconductor device 10 includes an n-type semiconductor layer 20 including a first surface 20S and a second surface 20R opposite to the first surface 20S, a plurality of p-type body regions 25 spaced apart in the X direction from the first surface 20S in a plan view, an n-type source region 26 provided in the first surface 20S of each of the plurality of body regions 25, a p-type body contact region 28 provided so as to penetrate the source region 26 in the Z direction, and a p-type body contact region 28 provided on the first surface 20S and spanning two body regions 25 adjacent in the X direction. The semiconductor layer 20 includes a gate insulating film 31 arranged so as to overlap two adjacent body regions 25 in the X direction, a gate electrode 33 arranged on the gate insulating film 31, a source insulating film 32 arranged on the first surface 20S at a distance from the gate insulating film 31 in the X direction and arranged so as to straddle two adjacent body regions 25 in the X direction, a source electrode 34 arranged on the source insulating film 32, a plurality of p-type column layers 24 arranged at intervals in the X direction in the semiconductor layer 20 and extending in the Z direction, and a source wiring 13 arranged on the first surface 20S. A body region pitch P2, which is the arrangement interval between the plurality of body regions 25 in the X direction, is shorter than a column layer pitch P1, which is the arrangement interval between the plurality of column layers 24 in the X direction. The semiconductor layer 20 includes a p-type source contact region 29. A portion of the source wiring 13 is arranged so as to overlap the source contact region 29 in a plan view. The source wiring 13 includes a first source contact portion 13D in contact with both the source contact region 29 and the source electrode 34.

[0103] This configuration can improve the switching speed while reducing the on-resistance. In addition, since the snubber circuit 40 including the source insulating film 32 and the source electrode 34 is provided within the semiconductor device 10, the semiconductor device 10 can reduce noise.

[0104] (1-2) The semiconductor layer 20 includes a cell region 11 in which a transistor is provided in a plan view, and a peripheral region 12 surrounding the cell region 11. Both the source insulating film 32 and the source electrode 34 are provided in the cell region 11.

[0105] According to this configuration, the snubber circuit 40, which includes the resistance components of the semiconductor layer 20, the source insulating film 32, and the source electrode 34 and the capacitance component of the capacitor, is provided in the cell region 11. Therefore, the resistance components and capacitance components of the snubber circuit 40 can be increased according to the size of the semiconductor device 10. As a result, the noise of the semiconductor device 10 can be reduced.

[0106] (1-3) The source electrode 34 extends from the cell region 11 to the peripheral region 12. The source contact region 29 is provided in the peripheral region 12. According to this configuration, the connection structure between the source electrode 34 and the source wiring 13 is provided in the peripheral region 12. Therefore, compared to when the connection structure is provided in the cell region 11, the number of transistors in the cell region 11 can be increased, and the on-resistance of the semiconductor device 10 can be reduced.

[0107] (1-4) The semiconductor device 10 includes a peripheral insulating film 37 provided in the peripheral region 12, and an interlayer insulating film 35 that covers the peripheral insulating film 37, the gate electrode 33, and the source electrode 34. The peripheral insulating film 37 is connected to the gate insulating film 31 and the source insulating film 32. Both the peripheral insulating film 37 and the interlayer insulating film 35 include a source opening 38 that exposes both the source electrode 34 and the source contact region 29 in the peripheral region 12. The first source contact portion 13D is buried in the source opening 38.

[0108] According to this configuration, the source electrode 34 extends onto the peripheral insulating film 37. Therefore, the snubber circuit 40 includes a resistance component of the source electrode 34 on the peripheral insulating film 37 and a capacitance component of a capacitor formed by the peripheral insulating film 37 and the semiconductor layer 20 directly below the source electrode 34. This makes it possible to increase the resistance component and capacitance component of the snubber circuit 40. As a result, the noise of the semiconductor device 10 can be reduced.

[0109] (1-5) The source electrode 34 extends in the Y direction. An electrode end 34A, which is the end of the source electrode 34 in the Y direction, extends into the source opening 38 and is exposed from the source opening 38. The first source contact portion 13D is in contact with the electrode end 34A.

[0110] This configuration increases the contact area between the source electrode 34 and the first source contact portion 13D compared to when only the Y-direction end face of the source electrode 34 is exposed, thereby facilitating electrical connection between the source electrode 34 and the first source contact portion 13D.

[0111] (1-6) The number of source electrodes 34 is equal to the number of gate electrodes 33. The source electrodes 34 and the gate electrodes 33 are arranged alternately one by one in the X direction. This configuration makes it possible to achieve a good balance between an improvement in switching speed and a reduction in on-resistance.

[0112] (1-7) The width WA of the source opening 38 is larger than the width WS of the source electrode 34 . This configuration makes it possible to increase the contact area between the source contact region 29 exposed in the source opening 38 and the first source contact portion 13D. This allows the current in the semiconductor layer 20 to flow smoothly to the source wiring 13 via the source contact region 29 and the first source contact portion 13D, for example, when the semiconductor device 10 breaks down.

[0113] (1-8) The width WA of the source opening 38 is larger than the width WG of the gate electrode 33. This configuration makes it possible to increase the contact area between the source contact region 29 exposed in the source opening 38 and the first source contact portion 13D. This allows the current in the semiconductor layer 20 to flow smoothly to the source wiring 13 via the source contact region 29 and the first source contact portion 13D, for example, when the semiconductor device 10 breaks down.

[0114] (1-9) The gate electrode 33 includes a wide portion 33AA provided in the cell region 11 and a narrow portion 33AB provided in the peripheral region 12 and narrower than the wide portion 33AA. The narrow portion 33AB is provided adjacent to the source opening 38 in the X direction.

[0115] This configuration allows the width WA of the source opening 38 to be increased, thereby increasing the contact area between the source contact region 29 exposed in the source opening 38 and the first source contact portion 13D. This allows the current in the semiconductor layer 20 to flow smoothly to the source wiring 13 via the source contact region 29 and the first source contact portion 13D, for example, when the semiconductor device 10 breaks down.

[0116] (1-10) Both the source insulating film 32 and the gate insulating film 31 are made of silicon oxide films. According to this configuration, both the source insulating film 32 and the gate insulating film 31 can be formed simultaneously and easily.

[0117] (1-11) The source wiring 13 includes a second source contact portion 13E that penetrates the interlayer insulating film 35 and contacts the body contact region 28. The ratio (LZ / LX) of the length LZ of the second source contact portion 13E in the Z direction to the maximum length LX of the second source contact portion 13E in the X direction is 1 or more and 5 or less.

[0118] According to this configuration, the second source contact portion 13E can be easily embedded in the interlayer insulating film 35. In particular, when tungsten (W) is used for the second source contact portion 13E, the embedding property of the second source contact portion 13E in the interlayer insulating film 35 is further improved, so that the source wiring 13 and the body contact region 28 can be reliably electrically connected through the second source contact portion 13E.

[0119] (1-12) The distance Dsg between the source electrode 34 and the gate electrode 33 adjacent to each other in the X direction is not less than 0.5 μm and not more than 3 μm. This configuration can prevent the occurrence of defective formation of the second source contact portion 13E. Therefore, the source wiring 13 and the body contact region 28 can be reliably electrically connected through the second source contact portion 13E. In particular, when tungsten (W) is used for the second source contact portion 13E, the second source contact portion 13E is more easily embedded in the interlayer insulating film 35, thereby reliably electrically connecting the source wiring 13 and the body contact region 28 through the second source contact portion 13E.

[0120] (1-13) The width W2 of the body region 25 is smaller than the width W1 of the column layer 24. According to this configuration, even if the inter-column layer pitch P1 is reduced, the body regions 25 can be arranged at the inter-body region pitch P2. This allows the number of transistors in the cell region 11 to be increased, thereby reducing the on-resistance.

[0121] Second Embodiment A semiconductor device 10 according to the second embodiment will be described with reference to Fig. 22. The semiconductor device 10 according to the second embodiment differs from the semiconductor device 10 according to the first embodiment mainly in the relationship between the column layer 24 and the body region 25. In the following, components common to the first embodiment are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0122] FIG. 22 schematically shows a cross-sectional structure of a part of the cell region 11 of the semiconductor device 10. As shown in FIG. As shown in FIG. 22, the column layer 24 is disposed apart from the body region 25 in the Z direction.

[0123] The upper end of the column layer 24 has a curved shape that is convex toward the body region 25. In other words, the upper end of the column layer 24 has a curved convex shape that approaches the body region 25 as it moves toward the center in the X direction. The body region 25 directly above the column layer 24 has the same size and shape as the body region 25 provided between adjacent column layers 24 in the X direction.

[0124] In the second embodiment, the distance between the body region 25 and the column layer 24 in the Z direction becomes smaller toward the center in the X direction of the body region 25 and the center in the X direction of the column layer 24. Therefore, the distance between the body region 25 and the column layer 24 in the Z direction is shortest at the center in the X direction of the body region 25 (the center in the X direction of the column layer 24).

[0125] In one example, the shortest distance D4 between the body region 25 and the column layer 24 in the Z direction is greater than the shortest distance between adjacent body regions 25 in the X direction (body region distance D3). In one example, the shortest distance D4 is equal to or less than half the shortest distance between adjacent column layers 24 in the X direction (first column layer distance D1). In one example, the shortest distance D4 is equal to or less than half the second column layer distance D2. In one example, the shortest distance D4 is smaller than the depth dimension HA of the body region 25.

[0126] The shortest distance D4 can be arbitrarily changed depending on the required electrical characteristics of the semiconductor device 10. In one example, the shortest distance D4 may be equal to or less than the body region distance D3. In one example, the shortest distance D4 may be greater than half the first column-layer distance D1. In one example, the shortest distance D4 may be greater than half the second column-layer distance D2. In one example, the shortest distance D4 may be equal to or greater than the depth dimension HA of the body region 25.

[0127] [Effects of the second embodiment] According to the semiconductor device 10 of the second embodiment, the following effects can be obtained. (2-1) The semiconductor device 10 includes an n-type semiconductor layer 20 including a first surface 20S and a second surface 20R opposite to the first surface 20S, a plurality of p-type body regions 25 spaced apart in the X direction from the first surface 20S in a plan view, an n-type source region 26 provided in the first surface 20S of each of the plurality of body regions 25, a p-type body contact region 28 provided so as to penetrate the source region 26 in the Z direction, and a p-type body contact region 28 provided on the first surface 20S and spanning two body regions 25 adjacent in the X direction. The semiconductor layer 20 includes a gate insulating film 31 arranged such that the body regions 25 overlap each other, a gate electrode 33 arranged on the gate insulating film 31, a source insulating film 32 arranged on the first surface 20S at a distance from the gate insulating film 31 in the X direction and arranged to straddle two body regions 25 adjacent to each other in the X direction, a source electrode 34 arranged on the source insulating film 32, a plurality of p-type column layers 24 arranged at intervals in the X direction in the semiconductor layer 20 and extending in the Z direction, and a source wiring 13 provided on the first surface 20S. A body region pitch P2, which is the arrangement interval between the plurality of body regions 25 in the X direction, is shorter than a column layer pitch P1, which is the arrangement interval between the plurality of column layers 24 in the X direction. In a plan view, the column layers 24 are arranged at positions overlapping the body regions 25. In the Z direction, the column layers 24 are arranged at a distance from the body regions 25.

[0128] This configuration can improve switching speed and reduce on-resistance at the same time. Additionally, since the snubber circuit 40 including the source insulating film 32 and the source electrode 34 is provided within the semiconductor device 10, noise from the semiconductor device 10 can be reduced. Furthermore, since the body region 25 and the column layer 24 are spaced apart in the Z direction, a current path is formed between the body region 25 and the column layer 24 in the Z direction. In other words, the number of current paths within the semiconductor layer 20 increases. Therefore, the on-resistance can be reduced.

[0129] (2-2) The shortest distance D4 between the body region 25 and the column layer 24 in the Z direction is greater than the body region-to-body region distance D3, which is the shortest distance between the body regions 25 adjacent to each other in the X direction. According to this configuration, the current path formed between the body region 25 and the column layer 24 in the Z direction is large, and therefore, the on-resistance can be reduced.

[0130] (2-3) The shortest distance D4 between the body region 25 and the column layer 24 in the Z direction is equal to or less than half the first inter-column layer distance D1, which is the shortest distance between the column layers 24 adjacent to each other in the X direction.

[0131] This configuration prevents a depletion layer from spreading in the Z direction between the body region 25 and the column layer 24, thereby preventing breakdown of the body region 25. This prevents a decrease in the breakdown voltage of the semiconductor device 10.

[0132] Third Embodiment 23 and 24, a semiconductor device 10 of the third embodiment will be described. The semiconductor device 10 of the third embodiment differs from the semiconductor device 10 of the first embodiment mainly in the relationship between the numbers of gate electrodes 33 and source electrodes 34. In the following, components common to the first embodiment are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0133] 23 is a schematic cross-sectional view of a portion of the cell region 11 of the semiconductor device 10. FIG. 24 is a schematic plan view of a portion of the outer periphery region 12 of the semiconductor device 10. As shown in FIG. 23 , in the third embodiment, the number of source electrodes 34 is different from the number of gate electrodes 33. In one example, the number of source electrodes 34 is greater than the number of gate electrodes 33. In the third embodiment, the gate electrodes 33 and the source electrodes 34 are not alternately arranged one by one in the X direction, but a plurality of source electrodes 34 (three in the third embodiment) arranged side by side in the X direction and the gate electrodes 33 are arranged side by side in the X direction. In other words, a plurality of source electrodes 34 are arranged between gate electrodes 33 adjacent to each other in the X direction. Therefore, a plurality of source insulating films 32 (three in the third embodiment) are also arranged side by side in the X direction corresponding to the plurality of source electrodes 34 arranged side by side in the X direction. In the third embodiment, it can be said that a group of three source electrodes 34 and one gate electrode 33 are arranged alternately in the X direction.

[0134] In one example, the pitch between the three source electrodes 34 is equal to the pitch between the source electrodes 34 and the gate electrodes 33 adjacent to the source electrodes 34. The size of the three source electrodes 34 is the same as, for example, the source electrodes 34 in the first embodiment.

[0135] 24, in the third embodiment, the configuration of the source opening 38 is different in accordance with the fact that three source electrodes 34 are arranged side by side in the X direction. That is, the source opening 38 is provided so as to be wide in the X direction in correspondence with the three source electrodes 34. In other words, the source opening 38 is configured as a common source opening for the plurality of source electrodes 34 arranged side by side in the X direction.

[0136] Although not shown, the first source contact portion 13D (see FIG. 5) of the source wiring 13 is buried in the source opening 38. Therefore, the first source contact portion 13D is in contact with the electrode ends 34A of the three source electrodes 34.

[0137] [Effects of the third embodiment] According to the semiconductor device 10 of the third embodiment, the following effects can be obtained. (3-1) A plurality of source electrodes 34 and a plurality of gate electrodes 33 are provided. The number of source electrodes 34 is different from the number of gate electrodes 33.

[0138] According to this configuration, the capacitance component of the snubber circuit 40 can be adjusted according to the number of source electrodes 34. In particular, if the number of source electrodes 34 is greater than the number of gate electrodes 33, the capacitance component of the snubber circuit 40 can be increased, thereby reducing noise in the semiconductor device 10.

[0139] (3-2) A plurality of source electrodes 34 are disposed between the gate electrodes 33 adjacent to each other in the X direction. The source opening 38 is provided in common to the plurality of source electrodes 34 between the gate electrodes 33 adjacent to each other in the X direction.

[0140] This configuration allows the width WA of the source opening 38 to be increased, thereby increasing the contact area between the source contact region 29 exposed in the source opening 38 and the first source contact portion 13D. This allows the current in the semiconductor layer 20 to flow smoothly to the source wiring 13 via the source contact region 29 and the first source contact portion 13D, for example, when the semiconductor device 10 breaks down.

[0141] <Example of change> The above-described embodiments can be modified, for example, as follows: The above-described embodiments and the following modified examples can be combined with each other as long as no technical contradiction occurs. In the following modified examples, parts common to the above-described embodiments are designated by the same reference numerals as the above-described embodiments, and their description will be omitted.

[0142] [Adjusting the resistance and capacitance of the snubber circuit] In the first and second embodiments, the configurations of the source electrode 34 and the source opening 38 in the peripheral region 12 can be modified as desired. Examples of such modifications include first to third modifications shown in Figures 25 to 27. The first to third modifications can be combined with each other.

[0143] (First modified example) 25, in the first modified example, the dimension in the Y direction of the source opening 38 is smaller than the dimension in the Y direction of the source opening 38 in the first and second embodiments. The source opening 38 is arranged closer to the second gate portion 33B of the gate electrode 33 than the cell region 11 in a plan view. In one example, the source opening 38 is provided at a position adjacent to the second gate portion 33B of the gate electrode 33 in the Y direction. In other words, the distance in the Y direction between the source opening 38 and the cell region 11 in the first modified example is larger than the distance in the Y direction between the source opening 38 and the cell region 11 in the first and second embodiments.

[0144] The source electrode 34 extends from the cell region 11 to a position overlapping with the source opening 38 in plan view. Due to the change in the Y-direction length of the source opening 38, the Y-direction length of the source electrode 34 is longer than the Y-direction lengths of the source electrodes 34 of the first and second embodiments. The electrode end 34A of the source electrode 34 is disposed closer to the second gate portion 33B than in the first and second embodiments. In addition, in the source electrode 34 of the first modified example, the Y-direction length of the portion disposed on the peripheral insulating film 37 is longer than that of the source electrode 34 of the first and second embodiments.

[0145] According to the configuration of the first modified example, the source electrode 34 is elongated in the Y direction, thereby increasing the resistance component of the snubber circuit 40. In addition, the portion of the source electrode 34 that is disposed on the peripheral insulating film 37 is elongated in the Y direction, thereby increasing the capacitance component of the snubber circuit 40. In this way, by changing the length of the source electrode 34 in the Y direction, the resistance component and capacitance component of the snubber circuit 40 can be adjusted.

[0146] (Second modified example) 26, in the second modified example, the dimension in the Y direction of the source opening 38 is smaller than the dimension in the Y direction of the source opening 38 in the first and second embodiments. The source opening 38 is provided at a position adjacent to the second gate portion 33B of the gate electrode 33 in the Y direction. In other words, the distance in the Y direction between the source opening 38 and the cell region 11 is larger than the distance in the Y direction between the source opening 38 and the cell region 11 in the first and second embodiments. In one example, the dimension in the Y direction of the source opening 38 in the second modified example is larger than the dimension in the Y direction of the source opening 38 in the first modified example.

[0147] The source electrode 34 extends from the cell region 11 to a position overlapping with the source opening 38 in a plan view. Due to the change in the Y-direction length of the source opening 38, the Y-direction length of the source electrode 34 is longer than that of the source electrode 34 of the first and second embodiments. Meanwhile, the Y-direction length of the source electrode 34 of the second modified example is shorter than that of the source electrode 34 of the first modified example. In the second modified example, the source electrode 34 includes a wide portion 34B provided in the cell region 11 and a narrow portion 34C provided in the peripheral region 12. The narrow portion 34C has a width (dimension in the X-direction) narrower than that of the wide portion 34B. In one example, the wide portion 34B and the narrow portion 34C are integrated. In one example, the width of the narrow portion 34C is half the width of the wide portion 34B. In one example, the narrow portion 34C includes an electrode end portion 34A.

[0148] A part of the wide width portion 34B is provided in the outer peripheral region 12. The length LA in the Y direction of the part of the wide width portion 34B provided in the outer peripheral region 12 is shorter than the length LB in the Y direction of the narrow width portion 34C.

[0149] According to the configuration of the second modified example, the source electrode 34 is elongated in the Y direction, thereby increasing the resistance component of the snubber circuit 40. In addition, the narrow portion 34C of the source electrode 34 increases the electrical resistance of the source electrode 34. Furthermore, the portion of the source electrode 34 that is disposed on the peripheral insulating film 37 is elongated in the Y direction, thereby increasing the capacitance component of the snubber circuit 40. In addition, the narrow portion 34C of the source electrode 34 disposed on the peripheral insulating film 37 allows the area of ​​the source electrode 34 on the peripheral insulating film 37 to be adjusted. This allows the capacitance component of the snubber circuit 40 to be adjusted. In this way, the resistance component and capacitance component of the snubber circuit 40 can be adjusted by changing the length of the source electrode 34 in the Y direction and the width of the source electrode 34.

[0150] The length in the Y direction of the source opening 38 in the second modified example can be changed arbitrarily. The length in the Y direction of the source opening 38 may be equal to the length in the Y direction of the source opening 38 in the first modified example. Furthermore, the length in the Y direction of the narrow portion 34C of the source electrode 34 in the second modified example can be changed arbitrarily. For example, the entire portion of the source electrode 34 that is provided in the outer circumferential region 12 in the Y direction may be the narrow portion 34C. The lengths in the Y direction of each of the source opening 38 and the narrow portion 34C can be adjusted according to the performance required of the snubber circuit 40. Furthermore, the width (dimension in the X direction) of the narrow portion 34C can be adjusted according to the performance required of the snubber circuit 40.

[0151] (Third modified example) 27, in the third modified example, the shape of the source opening 38 in plan view differs from the shapes of the source openings 38 in the first and second embodiments. More specifically, the source opening 38 in the third modified example includes a main opening 38C and an opening extension 38D extending from the main opening 38C in the Y direction. In one example, the main opening 38C and the opening extension 38D communicate with each other.

[0152] The main opening 38C is provided at a position adjacent to the second gate portion 33B of the gate electrode 33 in the Y direction. The main opening 38C has a rectangular shape in plan view. The dimension in the X direction of the main opening 38C is larger than the width WS of the source electrode 34. The dimension in the Y direction of the main opening 38C is smaller than the dimension in the Y direction of the source opening 38 of the second modified example. The source electrode 34 extends from the cell region 11 to a position overlapping with the main opening 38C of the source opening 38 in plan view.

[0153] The opening extensions 38D are provided at a distance from the source electrode 34 in at least one direction in the X direction. In the third modified example shown in Fig. 27, the opening extensions 38D are provided on both sides of the source electrode 34 in the X direction. These opening extensions 38D extend in the Y direction from the main opening 38C toward the cell region 11.

[0154] As shown in FIG. 27, a first source contact portion 13D is buried in the source opening 38. The first source contact portion 13D includes a contact main portion 13DA buried in the main opening 38C and a contact extension portion 13DB buried in the opening extension portion 38D. In one example, the contact main portion 13DA and the contact extension portion 13DB are integrated. Both the contact main portion 13DA and the contact extension portion 13DB are in contact with the source contact region 29 (see FIG. 5). The contact main portion 13DA is in contact with an electrode end portion 34A of the source electrode 34. The contact extension portions 13DB are provided on both sides of the source electrode 34 in the X direction and spaced apart from the source electrode 34. An interlayer insulating film 35 (see FIG. 5) is interposed between the contact extension portion 13DB and the source electrode 34.

[0155] According to the configuration of the third modified example, the source electrode 34 is elongated in the Y direction, thereby increasing the resistance component of the snubber circuit 40. In addition, the portion of the source electrode 34 that is disposed on the peripheral insulating film 37 is elongated in the Y direction, thereby increasing the capacitance component of the snubber circuit 40. In this way, by changing the length of the source electrode 34 in the Y direction, the resistance component and capacitance component of the snubber circuit 40 can be adjusted.

[0156] In addition, the contact extension portion 13DB can increase the contact area between the first source contact portion 13D and the source contact region 29. This allows the current in the semiconductor layer 20 to flow smoothly to the source wiring 13 via the source contact region 29 and the first source contact portion 13D, for example, when the semiconductor device 10 breaks down.

[0157] Note that the configuration of the source opening 38 in the third modified example can be modified as desired. In one example, at least one of the two opening extensions 38D can be provided spaced apart from the main opening 38C. In one example, one of the two opening extensions 38D of the source opening 38 can be omitted. The Y-direction dimensions of the main opening 38C and the Y-direction dimensions of the opening extension 38D can be modified as desired. The Y-direction dimensions of each of the main opening 38C and the opening extension 38D can be adjusted depending on the required contact area between the first source contact portion 13D and the source contact region 29. In one example, the Y-direction dimensions of the two opening extensions 38D can be different from each other.

[0158] In the third embodiment, the configurations of the source electrode 34 and the source opening 38 in the peripheral region 12 can be changed arbitrarily. Examples of such changes include first to seventh changes shown in Figs. 28 to 34.

[0159] (Examples 1 to 3 of the changes) As shown in FIG. 28 , in the first modified example, the dimension in the Y direction of the source opening 38 is smaller than the dimension in the Y direction of the source opening 38 in the first and second embodiments. The source opening 38 is disposed closer to the second gate portion 33B of the gate electrode 33 than the cell region 11 in a plan view. In one example, the source opening 38 is provided at a position adjacent to the second gate portion 33B of the gate electrode 33 in the Y direction. That is, the distance in the Y direction between the source opening 38 and the cell region 11 in the first modified example is larger than the distance in the Y direction between the source opening 38 and the cell region 11 in the third embodiment. Therefore, the source opening 38 has a rectangular shape with its long sides in the X direction and its short sides in the Y direction in a plan view.

[0160] Each of the three source electrodes 34 extends from the cell region 11 to a position overlapping with the source opening 38 in plan view. Due to the change in the Y-direction length of the source opening 38, the Y-direction length of each of the three source electrodes 34 is longer than the Y-direction length of the source electrode 34 of the third embodiment. The electrode end 34A of the source electrode 34 is disposed closer to the second gate portion 33B than in the third embodiment.

[0161] According to the first modification, the length of each of the three source electrodes 34 in the Y direction increases, thereby increasing the resistance component of the snubber circuit 40. In addition, the length of the portion of each source electrode 34 that is disposed on the peripheral insulating film 37 increases in the Y direction, thereby increasing the capacitance component of the snubber circuit 40. In this way, by changing the length of each of the three source electrodes 34 in the Y direction, the resistance component and capacitance component of the snubber circuit 40 can be adjusted.

[0162] 29 , the Y-direction length of one of the three source electrodes 34 may be shorter than the Y-direction lengths of the other two source electrodes 34. In this case, the Y-direction dimension of the portion of the source opening 38 corresponding to the shorter source electrode 34 in the Y-direction is larger than the Y-direction dimension of the portion corresponding to the other two source electrodes 34.

[0163] As in a third modified example shown in FIG. 30 , the Y-direction lengths of two of the three source electrodes 34 may be shorter than the Y-direction length of the remaining source electrode 34. In other words, the Y-direction length of one of the three source electrodes 34 is longer than the Y-direction lengths of the other two source electrodes 34. In the example shown in FIG. 30 , the Y-direction length of the central source electrode 34 in the X-direction is longer than the Y-direction lengths of the other two source electrodes 34. As in the second and third modified examples, the resistance component and capacitance component of the snubber circuit 40 may be adjusted by changing the number of source openings 38 and source electrodes 34 that change their Y-direction lengths.

[0164] (Examples 4 to 6 of the changes) As shown in FIG. 31 , in the fourth modified example, the Y-direction dimension of the source opening 38 is smaller than those of the source opening 38 in the first and second embodiments. The source opening 38 is disposed closer to the second gate portion 33B of the gate electrode 33 than the cell region 11 in a plan view. In one example, the source opening 38 is provided at a position adjacent to the second gate portion 33B of the gate electrode 33 in the Y direction. That is, the distance between the source opening 38 and the cell region 11 in the Y direction in the first modified example is larger than the distance between the source opening 38 and the cell region 11 in the Y direction in the third embodiment. Therefore, the source opening 38 has a rectangular shape with its longer side in the X direction and its shorter side in the Y direction in a plan view. The Y-direction dimension of the source opening 38 in the fourth modified example is larger than the Y-direction dimension of the source opening 38 in the first modified example shown in FIG.

[0165] Each of the three source electrodes 34 extends from the cell region 11 to a position overlapping the source opening 38 in a plan view. Due to the change in the Y-direction length of the source opening 38, the Y-direction length of each source electrode 34 is longer than that of the source electrode 34 of the third embodiment. Meanwhile, the Y-direction length of the source electrode 34 of the fourth modified example is shorter than that of the source electrode 34 of the first modified example shown in FIG. 30 . In the fourth modified example, each source electrode 34 includes a wide portion 34B provided in the cell region 11 and a narrow portion 34C provided in the peripheral region 12. The narrow portion 34C has a width (dimension in the X-direction) narrower than that of the wide portion 34B. In one example, the wide portion 34B and the narrow portion 34C are integrated. In one example, the width of the narrow portion 34C is half the width of the wide portion 34B.

[0166] A part of the wide width portion 34B is provided in the outer peripheral region 12. The length LA in the Y direction of the part of the wide width portion 34B provided in the outer peripheral region 12 is shorter than the length LB in the Y direction of the narrow width portion 34C.

[0167] According to the configuration of the fourth modified example, the length of each of the three source electrodes 34 in the Y direction increases, thereby increasing the resistance of the snubber circuit 40. Additionally, the narrow width portion 34C of each of the three source electrodes 34 increases the electrical resistance of each source electrode 34. Furthermore, the length of the portion of each source electrode 34 located on the peripheral insulating film 37 increases in the Y direction, thereby increasing the capacitance of the snubber circuit 40. Additionally, the narrow width portion 34C of each source electrode 34 located on the peripheral insulating film 37 allows the area of ​​each source electrode 34 on the peripheral insulating film 37 to be adjusted. This allows the capacitance of the snubber circuit 40 to be adjusted. In this way, the resistance and capacitance of the snubber circuit 40 can be adjusted by changing the length of each of the three source electrodes 34 in the Y direction and the width of the source electrode 34.

[0168] The lengths LB in the Y direction of the narrow portions 34C of the three source electrodes 34 may be adjusted individually. That is, the lengths LB in the Y direction of the narrow portions 34C of the three source electrodes 34 may be different from one another. Furthermore, the length LA in the Y direction of the portion of the wide portion 34B provided in the outer circumferential region 12 may be equal to or greater than the length LB in the Y direction of the narrow portion 34C.

[0169] 32, the narrow portion 34C may be omitted from one of the three source electrodes 34. In this case, the one source electrode 34 is constituted by the wide portion 34B.

[0170] 33, the narrow portions 34C may be omitted from two of the three source electrodes 34. In this case, the two source electrodes 34 are configured with the wide portions 34B. As in the fifth and sixth modifications, the resistance and capacitance of the snubber circuit 40 may be adjusted by changing the number of source electrodes 34 whose widths WS are changed.

[0171] (Seventh Change) 34, in the seventh modified example, the shape of the source opening 38 in plan view differs from the shape of the source opening 38 of the third embodiment. More specifically, the source opening 38 of the seventh modified example includes a main opening 38C and an opening extension 38D extending from the main opening 38C in the Y direction. In one example, the main opening 38C and the opening extension 38D are in communication with each other.

[0172] The main opening 38C is provided at a position adjacent to the second gate portion 33B of the gate electrode 33 in the Y direction. The main opening 38C has a rectangular shape in plan view. The dimension in the X direction of the main opening 38C is larger than the width WS of the source electrode 34. The dimension in the Y direction of the main opening 38C is smaller than the dimension in the Y direction of the source openings 38 of the first to third modified examples. Each source electrode 34 extends from the cell region 11 to a position overlapping with the main opening 38C of the source opening 38 in plan view.

[0173] A plurality of aperture extensions 38D are provided spaced apart in the X direction. In the seventh modified example shown in Fig. 34, aperture extensions 38D are provided on both sides in the X direction of each of the three source electrodes 34. These aperture extensions 38D extend in the Y direction from the main opening 38C toward the cell region 11. In one example, the widths of the aperture extensions 38D located at both ends in the X direction among the plurality of aperture extensions 38D are narrower than the widths of the other aperture extensions 38D.

[0174] As shown in FIG. 34, a first source contact portion 13D is embedded in the source opening 38. The first source contact portion 13D includes a contact main portion 13DA embedded in the main opening 38C and contact extension portions 13DB embedded in each of the multiple opening extension portions 38D. In one example, the contact main portion 13DA and the multiple contact extension portions 13DB are integrated. The contact main portion 13DA and the multiple contact extension portions 13DB are both in contact with the source contact region 29 (see FIG. 5). The contact main portion 13DA is in contact with an electrode end portion 34A of the source electrode 34. The multiple contact extension portions 13DB are provided spaced apart from the corresponding source electrodes 34 in the X direction. An interlayer insulating film 35 (see FIG. 5) is interposed between the contact extension portion 13DB and the source electrode 34.

[0175] According to the configuration of the seventh modified example, each of the three source electrodes 34 is elongated in the Y direction, thereby increasing the resistance component of the snubber circuit 40. In addition, the Y direction length of the portion of each source electrode 34 that is disposed on the peripheral insulating film 37 is increased, thereby increasing the capacitance component of the snubber circuit 40. In this way, by changing the Y direction length of each of the three source electrodes 34, the resistance component and capacitance component of the snubber circuit 40 can be adjusted.

[0176] In addition, the contact extension portion 13DB can increase the contact area between the first source contact portion 13D and the source contact region 29. This allows the current in the semiconductor layer 20 to flow smoothly to the source wiring 13 via the source contact region 29 and the first source contact portion 13D, for example, when the semiconductor device 10 breaks down.

[0177] In each embodiment and each modified example, when the source electrode 34 is made of polysilicon, the resistance component of the source electrode 34 may be adjusted by adjusting the impurity concentration of the source electrode 34. In other words, the resistance component of the snubber circuit 40 may be adjusted by adjusting the impurity concentration of the source electrode 34.

[0178] [Adjusting the capacitance of the snubber circuit] In each embodiment, the relationship between the thickness of the gate insulating film 31 and the thickness of the source insulating film 32 can be changed as desired. For example, as shown in FIG. 35, the thickness TS of the source insulating film 32 may be thinner than the thickness TG of the gate insulating film 31. By reducing the thickness TS of the source insulating film 32, the capacitance component of the snubber circuit 40 can be increased. In this way, by changing the thickness TS of the source insulating film 32, the capacitance component of the snubber circuit 40 can be adjusted.

[0179] In each embodiment, as shown in FIG. 36 , the source electrode 34 may be in contact with the source contact region 29. The source electrode 34 is sandwiched in the Z direction between the source contact region 29 and the first source contact portion 13D. With this configuration, the area of ​​the source electrode 34 that overlaps with the peripheral insulating film 37 in plan view is reduced, thereby reducing the capacitance component of the snubber circuit 40. In this way, the capacitance component of the snubber circuit 40 can be adjusted by changing the area of ​​the source electrode 34 that overlaps with the insulating film (at least one of the source insulating film 32 and the peripheral insulating film 37) in plan view.

[0180] In each embodiment, the width WG of the gate electrode 33 and the width WS of the source electrode 34 can each be changed arbitrarily. The width of the gate insulating film 31 is changed according to the width WGA of the gate electrode 33, and the width of the source insulating film 32 is changed according to the width WS1 of the source electrode 34. In other words, the width of the gate insulating film 31 is equal to the width WGA of the gate electrode 33, and the width of the source insulating film 32 is equal to the width WS1 of the source electrode 34.

[0181] 37, the width WS1 of the source electrode 34 may be smaller than the width WGA of the gate electrode 33. With this configuration, the area of ​​the source electrode 34 that overlaps with the source insulating film 32 in a plan view is reduced, and therefore the capacitance component of the snubber circuit 40 can be reduced.

[0182] 38, the width WS1 of the source electrode 34 may be larger than the width WGA of the gate electrode 33. With this configuration, the area of ​​the source electrode 34 that overlaps with the source insulating film 32 in a plan view is increased, thereby increasing the capacitance of the snubber circuit 40. In this way, the capacitance of the snubber circuit 40 can be adjusted by changing the area of ​​the source insulating film 32.

[0183] In each embodiment, the material constituting the source insulating film 32 can be changed as desired. For example, the material constituting the source insulating film 32 may be different from the material constituting the gate insulating film 31. For example, the source insulating film 32 may be made of a material having a higher dielectric constant than that of the gate insulating film 31. That is, the dielectric constant of the source insulating film 32 may be higher than that of the gate insulating film 31. Examples of such a material with a higher dielectric constant include a high-k insulator. A high-k insulator is an insulating material with a higher dielectric constant than SiO2. Examples of high-k insulators include SiN (silicon nitride), SiON (nitrogen-doped silicon oxide), HfSiO (hafnium silicate), and HfAlON (nitrogen-doped hafnium aluminate). By using a material with a high dielectric constant for the source insulating film 32, the capacitance of the snubber circuit 40 can be increased. Note that a high-k insulator may also be used for the gate insulating film 31. A high-k insulator may also be used for the peripheral insulating film 37.

[0184] In the third embodiment, the number of source electrodes 34 arranged side by side in the X direction can be changed arbitrarily. For example, the number of source electrodes 34 arranged side by side in the X direction may be two, or may be four or more.

[0185] [Other change examples] In each embodiment, the ratio (LZ / LX) of the length LZ of the second source contact portion 13E in the Z direction to the maximum length LX of the second source contact portion 13E in the X direction can be changed as desired. For example, the ratio (LZ / LX) may be less than 1 or may be 5 or greater.

[0186] In each embodiment, the location of the source contact region 29 can be changed as desired. In one example, the source contact region 29 may be provided in the cell region 11. In each embodiment, the position of the source opening 38 in the Y direction can be changed as desired. For example, the source opening 38 may be disposed closer to the cell region 11 in the Y direction than the second gate portion 33B of the gate electrode 33. In other words, the distance between the source opening 38 and the cell region 11 in the Y direction may be smaller than the distance between the source opening 38 and the second gate portion 33B in the Y direction.

[0187] In each embodiment, the configuration of the first gate portion 33A of the gate electrode 33 can be changed as desired. For example, the wide portion 33AA may be omitted from the first gate portion 33A. That is, the first gate portion 33A may be composed of the narrow portion 33AB. For another example, the narrow portion 33AB may be omitted from the first gate portion 33A. That is, the first gate portion 33A may be composed of the wide portion 33AA.

[0188] In each embodiment, the distance between the source electrode 34 and the gate electrode 33 adjacent to each other in the X direction is not limited to the range of 0.5 μm to 3 μm, and can be changed arbitrarily. In the first and second embodiments, the width WA of the source opening 38 can be changed as desired. For example, the width WA of the source opening 38 may be equal to or smaller than the width WS1 of the source electrode 34. For another example, the width WA of the source opening 38 may be equal to or smaller than the width WGA of the gate electrode 33.

[0189] In the third embodiment, it is possible to arbitrarily change the configuration of the source opening 38. In one example, a plurality of source openings 38 may be provided corresponding to a plurality of source electrodes 34 adjacent to each other in the X direction.

[0190] One or more of the various examples described herein may be combined to the extent that they are not technically inconsistent. The term "on" as used in this disclosure includes the meanings of "on" and "above" unless the context clearly indicates otherwise. Thus, for example, the expression "a first element is disposed on a second element" means that in some embodiments, the first element may be disposed directly on the second element in contact with the second element, while in other embodiments, the first element may be disposed above the second element without contacting the second element. In other words, the term "on" does not exclude a structure in which another element is formed between the first element and the second element.

[0191] The Z direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" in the Z axis direction described in this specification being "up" and "down" in the vertical direction. For example, the X direction may be the vertical direction, or the Y direction may be the vertical direction.

[0192] <Additional Notes> The technical ideas that can be understood from the above-described embodiments and modifications are described below. The reference numerals of the components of the embodiments corresponding to the components described in each appendix are shown in parentheses. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0193] [Appendix 1] a semiconductor layer (20) of a first conductivity type including a first surface (20S) and a second surface (20R) opposite to the first surface (20S); a plurality of body regions (25) of a second conductivity type provided on the first surface (20S) and arranged apart in a first direction (X) in a plan view seen from a thickness direction (Z) of the semiconductor layer (20); a first conductivity type source region (26) provided in the first surface (20S) of each of the plurality of body regions (25); a second conductivity type body contact region (28) provided so as to penetrate the source region (26) in the thickness direction (Z); a gate insulating film (31) provided on the first surface (20S) and arranged so as to straddle two of the body regions (25) adjacent to each other in the first direction (X); a gate electrode (33) disposed on the gate insulating film (31); a source insulating film (32) provided on the first surface (20S) at a distance from the gate insulating film (31) in the first direction (X) and arranged so as to straddle two of the body regions (25) adjacent to each other in the first direction (X); a source electrode (34) disposed on the source insulating film (32); a plurality of column layers (24) of a second conductivity type provided in the semiconductor layer (20) at intervals in the first direction (X) and extending in the thickness direction (Z); a source wiring (13) provided on the first surface (20S); Including, a body region pitch (P2) that is an arrangement interval of the plurality of body regions (25) in the first direction (X) is shorter than a column layer pitch (P1) that is an arrangement interval of the plurality of column layers (24) in the first direction (X); the semiconductor layer (20) includes a source contact region (29) of a second conductivity type; a portion of the source electrode (34) is arranged to overlap the source contact region (29) in the plan view; The source wiring (13) includes a first source contact portion (13D) that contacts both the source contact region (29) and the source wiring (13). A semiconductor device (10).

[0194] [Appendix 2] the semiconductor layer (20) includes a cell region (11) in which an element structure (20B) is provided in the plan view, and a peripheral region (12) surrounding the cell region (11); Both the source insulating film (32) and the source electrode (34) are provided in the cell region (11). 2. The semiconductor device according to claim 1.

[0195] [Appendix 3] The source electrode (34) extends from the cell region (11) to the outer peripheral region (12), The source contact region (29) is provided in the outer peripheral region (12). 3. The semiconductor device according to claim 2.

[0196] [Appendix 4] a peripheral insulating film (37) provided in the peripheral region (12) and connected to the gate insulating film (31) and the source insulating film (32); an interlayer insulating film (35) covering the gate electrode (33) and the source electrode (34); Including, both the peripheral insulating film (37) and the interlayer insulating film (35) include a source opening (38) that exposes both the source electrode (33) and the source contact region (29) in the peripheral region (12); The first source contact portion (13D) is embedded in the source opening (38). 4. The semiconductor device according to claim 3.

[0197] [Appendix 5] When the direction perpendicular to the first direction (X) in the plan view is defined as a second direction (Y), The source electrode (34) extends in the second direction (Y), an electrode end (34A) of the source electrode (34) in the second direction (Y) extends into the source opening (38) and is exposed from the source opening (38); The first source contact portion (13) is in contact with the electrode end portion (34A). 5. The semiconductor device according to claim 4.

[0198] [Appendix 6] The gate electrode (33) a plurality of first gate portions (33A) extending in the second direction (Y); a second gate portion (33B) extending in the first direction (X) and connecting the plurality of first gate portions (33A); Including, the source opening (38) is disposed closer to the second gate portion (33B) than the cell region (11) in the plan view, The source electrode (34) extends from the cell region (11) to a position overlapping the source opening (38) in the plan view. 6. The semiconductor device according to claim 5.

[0199] [Appendix 7] The source electrode (34) is a wide portion (34B) provided in the cell region (11); a narrow portion (34C) provided in the outer peripheral region (12) and having a width narrower than that of the wide portion (34B); Contains 7. The semiconductor device according to claim 6.

[0200] [Appendix 8] the source opening (38) includes an opening extension (38D) provided at a distance from the source electrode (34) in at least one of the first directions (X) relative to the source electrode (33); The first source contact portion (13D) includes a contact extension portion (13DB) embedded in the opening extension portion (38D). 8. The semiconductor device according to claim 6 or 7.

[0201] [Appendix 9] a plurality of the source electrodes (34) and a plurality of the gate electrodes (33) are provided; a plurality of the source electrodes (34) are disposed between the gate electrodes (33) adjacent to each other in the first direction (X); The source opening (38) is provided in common to the plurality of source electrodes (34) between the gate electrodes (33) adjacent to each other in the first direction (X). 9. The semiconductor device according to any one of claims 4 to 8.

[0202] [Appendix 10] The gate electrode (33) a wide portion (33AA) provided in the cell region (11); a narrow portion (33AB) provided in the outer peripheral region (12) and narrower than the wide portion (33AA); Including, The narrow width portion (33AB) is provided at a position adjacent to the source opening (38) in the first direction (X). 10. The semiconductor device according to any one of appendices 4 to 9.

[0203] [Appendix 11] The source opening (38) has a predetermined width (WA), The width (WA) of the source opening (38) is greater than the width (WS) of the source electrode (34). 11. The semiconductor device according to any one of claims 4 to 10.

[0204] [Appendix 12] The source opening (38) has a predetermined width (WA), The width (WA) of the source opening (38) is greater than the width (WGA) of the gate electrode (33). 12. The semiconductor device according to any one of claims 4 to 11.

[0205] [Appendix 13] the source wiring (13) includes a second source contact portion (13E) that penetrates the interlayer insulating film (35) and contacts the body contact region (28); a ratio (LZ / LX) of a length (LZ) in the thickness direction (Z) of the second source contact portion (13E) to a maximum length (LX) in the first direction (X) of the second source contact portion (13E) is 1 or more and 5 or less; 13. The semiconductor device according to any one of claims 4 to 12.

[0206] [Appendix 14] The distance between the source electrode (34) and the gate electrode (33) adjacent to each other in the first direction (X) is 0.5 μm or more and 3 μm or less. 14. The semiconductor device according to claim 13.

[0207] [Appendix 15] The second source contact portion (13E) is made of tungsten. 15. The semiconductor device according to claim 13 or 14.

[0208] [Appendix 16] The first source contact portion (13D) is made of tungsten or polysilicon. 16. The semiconductor device according to any one of claims 1 to 15.

[0209] [Appendix 17] Both the source electrode (34) and the gate electrode (33) have a predetermined width, The width (WS1 / WS) of the source electrode (34) is greater than the width (WGA) of the gate electrode (33). 17. The semiconductor device according to any one of claims 1 to 16.

[0210] [Appendix 18] Both the source electrode (34) and the gate electrode (33) have a predetermined width, The width (WS1 / WS) of the source electrode (34) is smaller than the width (WGA) of the gate electrode (33). 17. The semiconductor device according to any one of claims 1 to 16.

[0211] [Appendix 19] Both the source electrode (34) and the gate electrode (33) have a predetermined width, The width (WS1 / WS) of the source electrode (34) is equal to the width (WGA) of the gate electrode (33). 17. The semiconductor device according to any one of claims 1 to 16.

[0212] [Appendix 20] a plurality of the source electrodes (34) and a plurality of the gate electrodes (33) are provided; The number of the source electrodes (34) is different from the number of the gate electrodes (33). 20. The semiconductor device according to any one of appendices 1 to 19.

[0213] [Appendix 21] The number of the source electrodes (34) is equal to the number of the gate electrodes (33), The source electrodes (34) and the gate electrodes (33) are alternately arranged one by one in the first direction (X). 20. The semiconductor device according to any one of appendices 1 to 19.

[0214] [Appendix 22] The dielectric constant of the source insulating film (32) is higher than the dielectric constant of the gate insulating film (31). 22. The semiconductor device according to any one of claims 1 to 21.

[0215] [Appendix 23] The thickness (TS) of the source insulating film (32) is thinner than the thickness (TG) of the gate insulating film (31). 23. The semiconductor device according to any one of claims 1 to 22.

[0216] [Appendix 24] Both the source insulating film (32) and the gate insulating film (31) are made of silicon oxide films. 22. The semiconductor device according to any one of claims 1 to 21.

[0217] [Appendix 25] In the plan view, the column layer (24) is disposed at a position overlapping the body region (25), In the thickness direction (Z), the column layer (24) is disposed apart from the body region (25). 25. The semiconductor device according to any one of claims 1 to 24.

[0218] [Appendix 26] The shortest distance (D4) between the body region (25) and the column layer (24) in the thickness direction (Z) is greater than the shortest distance (D3) between the body regions (25) adjacent to each other in the first direction (X). 26. The semiconductor device according to claim 25.

[0219] [Appendix 27] The shortest distance (D4) between the body region (25) and the column layer (24) in the thickness direction (Z) is equal to or less than half the shortest distance (D1) between the column layers (24) adjacent to each other in the first direction (X). 27. The semiconductor device according to claim 25 or 26.

[0220] [Appendix 28] The width (W2) of the body region (25) is smaller than the width (W1) of the column layer (24). 28. The semiconductor device according to any one of claims 1 to 27.

[0221] [Appendix 29] a semiconductor layer (20) of a first conductivity type including a first surface (20S) and a second surface (20R) opposite to the first surface (20S); a plurality of second conductivity type body regions (25) provided on the first surface (20S) and arranged apart in a first direction (X) in a plan view seen from a thickness direction (Z) of the semiconductor layer (20); a first conductivity type source region (26) provided in the first surface (20S) of each of the plurality of body regions (25); a second conductivity type body contact region (28) provided so as to penetrate the source region (26) in the thickness direction (Z); a gate insulating film (31) provided on the first surface (20S) and arranged so as to straddle two of the body regions (25) adjacent to each other in the first direction (X); a gate electrode (33) disposed on the gate insulating film (31); a source insulating film (32) provided on the first surface (20S) at a distance from the gate insulating film (31) in the first direction (X) and arranged so as to straddle two of the body regions (25) adjacent to each other in the first direction (X); a source electrode (34) disposed on the source insulating film (32); a plurality of second conductivity type column layers (24) provided in the semiconductor layer (20) at intervals in the first direction (X) and extending in the thickness direction (Z); a source wiring (13) provided on the first surface (20S); Including, a body region pitch (P2) that is an arrangement interval of the plurality of body regions (25) in the first direction (X) is shorter than a column layer pitch (P1) that is an arrangement interval of the plurality of column layers (24) in the first direction (X); In the plan view, the column layer (24) is disposed at a position overlapping the body region (25), In the thickness direction (Z), the column layer (24) is disposed apart from the body region (25). A semiconductor device (10).

[0222] [Appendix 30] The pitch (P2) between the body regions is equal to 1 / 2 of the pitch (P1) between the column layers. 30. The semiconductor device according to any one of appendices 1 to 29.

[0223] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims. [Explanation of symbols]

[0224] 10...Semiconductor device 11...Cell area 12...Outer area 13...Source wiring 13A...Source pad 13B...recess 13C...Wiring main body 13D...First source contact 13DA...Main part of contact 13DB...Contact extension 13E...Second source contact 14...Gate wiring 14A...Gate pad 14B...Pad section 14C...Finger part 15...passivation layer 15A…1st opening 15B…Second opening 16...Drain wiring 20...Semiconductor layer 20S…Side 1 20R...2nd stage 20A...Super junction structure 20B...Element structure 21...Semiconductor substrate 22...Epitaxial layer 23...Drift region 24...Column layer 24A…Side 24AA...Convex part 24AB...recess 25...Body area 25A...Parasitic diode 26...Source region 27...Channel region 28...Body contact area 29...Source contact region 31...Gate insulating film 32...Source insulating film 33...Gate electrode 33A...First gate section 33AA...wide section 33AB…Narrow part 33B...Second Gate 34...Source electrode 34A...electrode end 34B...wide part 34C…Narrow part 35...Interlayer insulating film 35A...Contact hole 37...Peripheral insulating film 38...Source opening 38A...First source opening 38B...Second source opening 38C…Main opening 38D…Opening extension part 40...Snubber circuit 61...initial base layer 62...p-type impurity 63, 64...n-type semiconductor layer P1: Column layer pitch P2: Pitch between body regions D1: First column layer distance D2: Second column inter-layer distance D3: Distance between body regions D4: Shortest distance between the body region and the column layer Dsg: distance between source electrode and gate electrode Dc: Distance between adjacent second source contacts HA...Body area depth dimension LA: Length in the second direction (Y direction) of the wide portion of the source electrode provided in the peripheral region LB: Length of the narrow part of the source electrode in the second direction (Y direction) LX: Maximum length of the second source contact in the first direction (X direction) LZ: Length of the second source contact in the thickness direction (Z direction) TS: Source insulating film thickness TG: Gate insulating film thickness W1: Width of column layer W2: Width of body area WA: Source opening width WB: Width of second source contact WGA: Width of the wide part of the first gate WGB: Width of the narrow part of the first gate WG: gate electrode width WG1: Width of first gate WS: Source electrode width WS1: Width of source electrode in cell area

Claims

1. a semiconductor layer of a first conductivity type including a first surface and a second surface opposite to the first surface; a plurality of body regions of a second conductivity type provided on the first surface and arranged spaced apart in a first direction in a plan view seen from a thickness direction of the semiconductor layer; a source region of a first conductivity type provided in the first surface of each of the plurality of body regions; a body contact region of a second conductivity type provided so as to penetrate the source region in the thickness direction; a gate insulating film provided on the first surface and arranged to straddle two of the body regions adjacent to each other in the first direction; a gate electrode disposed on the gate insulating film; a source insulating film provided on the first surface and spaced apart from the gate insulating film in the first direction, the source insulating film being arranged across two of the body regions adjacent to each other in the first direction; a source electrode disposed on the source insulating film; a plurality of column layers of a second conductivity type provided in the semiconductor layer at intervals in the first direction and extending in the thickness direction; a source wiring provided on the first surface; Including, a body region pitch, which is an arrangement interval between the body regions in the first direction, is shorter than a column layer pitch, which is an arrangement interval between the column layers in the first direction; the semiconductor layer includes a source contact region of a second conductivity type; a portion of the source electrode is disposed so as to overlap with the source contact region in the plan view; The source wiring includes a first source contact portion that contacts both the source contact region and the source wiring. Semiconductor device.

2. the semiconductor layer includes a cell region in which an element structure is provided in the plan view, and a peripheral region surrounding the cell region; Both the source insulating film and the source electrode are provided in the cell region. The semiconductor device according to claim 1 .

3. the source electrode extends from the cell region to the outer periphery region; The source contact region is provided in the outer periphery region. The semiconductor device according to claim 2 .

4. a peripheral insulating film provided in the peripheral region and connected to the gate insulating film and the source insulating film; an interlayer insulating film covering the gate electrode and the source electrode; Including, each of the peripheral insulating film and the interlayer insulating film includes a source opening exposing both the source electrode and the source contact region in the peripheral region; The first source contact portion is embedded in the source opening. The semiconductor device according to claim 3 .

5. When a direction perpendicular to the first direction in the plan view is defined as a second direction, the source electrode extends in the second direction, an electrode end portion, which is an end portion of the source electrode in the second direction, extends into the source opening and is exposed from the source opening; The first source contact portion is in contact with the electrode end portion. The semiconductor device according to claim 4 .

6. The gate electrode is a plurality of first gate portions extending in the second direction; a second gate portion extending in the first direction and connecting the plurality of first gate portions; Including, the source opening is disposed closer to the second gate portion than the cell region in the plan view, The source electrode extends from the cell region to a position overlapping with the source opening in the plan view. The semiconductor device according to claim 5 .

7. The source electrode is a wide portion provided in the cell region; a narrow portion provided in the outer peripheral region and having a width narrower than that of the wide portion; Contains The semiconductor device according to claim 6.

8. the source opening includes an opening extension provided at a distance from the source electrode in at least one of the first directions with respect to the source electrode, The first source contact portion includes a contact extension portion embedded in the opening extension portion. The semiconductor device according to claim 6.

9. a plurality of the source electrodes and a plurality of the gate electrodes are provided; a plurality of the source electrodes are disposed between the gate electrodes adjacent to each other in the first direction; The source opening is provided in common to the plurality of source electrodes between the gate electrodes adjacent to each other in the first direction. The semiconductor device according to claim 4 .

10. The gate electrode is a wide portion provided in the cell region; a narrow portion provided in the outer peripheral region and having a width narrower than that of the wide portion; Including, The narrow width portion is provided at a position adjacent to the source opening in the first direction. The semiconductor device according to claim 4 .

11. the source wiring includes a second source contact portion that penetrates the interlayer insulating film and is in contact with the body contact region; a ratio of a length of the second source contact portion in the thickness direction to a maximum length of the second source contact portion in the first direction is 1 or more and 5 or less; The semiconductor device according to claim 4 .

12. The distance between the source electrode and the gate electrode adjacent to each other in the first direction is 0.5 μm or more and 3 μm or less. The semiconductor device according to claim 11.

13. The second source contact portion is made of tungsten. The semiconductor device according to claim 12.

14. a plurality of the source electrodes and a plurality of the gate electrodes are provided; The number of the source electrodes is different from the number of the gate electrodes. The semiconductor device according to claim 1 .

15. the number of the source electrodes is equal to the number of the gate electrodes; The source electrodes and the gate electrodes are alternately arranged one by one in the first direction. The semiconductor device according to claim 1 .

16. The dielectric constant of the source insulating film is higher than the dielectric constant of the gate insulating film. The semiconductor device according to claim 1 .

17. The thickness of the source insulating film is thinner than the thickness of the gate insulating film. The semiconductor device according to claim 1 .

18. In the plan view, the column layer is disposed at a position overlapping the body region, The column layer is disposed apart from the body region in the thickness direction. The semiconductor device according to any one of claims 1 to 17.

19. The shortest distance between the body region and the column layer in the thickness direction is greater than the shortest distance between the body regions adjacent to each other in the first direction.

19. The semiconductor device according to claim 18.

20. The shortest distance between the body region and the column layer in the thickness direction is equal to or less than half of the shortest distance between the column layers adjacent to each other in the first direction.

19. The semiconductor device according to claim 18.

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