Storage device

Abstract

To provide a storage device capable of operating at high speed.SOLUTION: A memory device according to an embodiment includes a memory cell, a word line, a bit line, a first transistor, a first latch circuit, a second transistor, and a third transistor. The word lines are connected to the memory cells. The bit lines are connected to the memory cells. The first transistor has a gate coupled to a first node coupled to a bit line, and is coupled to a second node. The first latch circuit is coupled to the second node and includes a third node. The second transistor is connected between the first node and the fourth node and has a gate connected to a node different from the third node. The third transistor is connected between the first node and the fourth node, and has a gate connected to the third node.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] FIELD Embodiments generally relate to storage devices. [Background technology]

[0002] Storage devices are required to be able to store more data and to be able to store and read data at high speeds. Storage devices are required to be able to store large amounts of data and operate at high speeds. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-095248 Summary of the Invention [Problem to be solved by the invention]

[0004] To provide a storage device capable of operating at high speed. [Means for solving the problem]

[0005] A memory device according to one embodiment includes a memory cell, a word line, a bit line, a first transistor, a first latch circuit, a second transistor, and a third transistor. The word line is connected to the memory cell. The bit line is connected to the memory cell. The first transistor has a gate connected to a first node connected to the bit line and is connected to a second node. The first latch circuit is connected to the second node and includes a third node. The second transistor is connected between the first node and a fourth node and has a gate connected to a node different from the third node. The third transistor is connected between the first node and the fourth node and has a gate connected to the third node. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 shows an example of components and connections of the components in a memory system including a storage device according to the first embodiment. [Figure 2] FIG. 2 shows an example of components of the storage device of the first embodiment and connections between the components. [Figure 3] FIG. 3 shows the components and connections of one block of the storage device of the first embodiment. [Figure 4] FIG. 4 shows an exploded view of the structure of the storage device of the first embodiment. [Figure 5] FIG. 5 shows an example of the cross-sectional structure of a part of the storage device of the first embodiment. [Figure 6] FIG. 6 shows an example of the cross-sectional structure of the memory pillar of the storage device of the first embodiment taken along the xy plane. [Figure 7] FIG. 7 shows an example of the distribution of threshold voltages of cell transistors storing 3-bit data in the memory device of the first embodiment and data mapping. [Figure 8] FIG. 8 shows the components and connections of the sense amplifier of the memory device of the first embodiment. [Figure 9] FIG. 9 is a circuit diagram of a sense amplifier circuit of the memory device of the first embodiment. [Figure 10] FIG. 10 shows an outline of a write operation in the storage device of the first embodiment along time. [Figure 11] FIG. 11 shows an example of setting a program loop in a write operation in the storage device of the first embodiment. [Figure 12] FIG. 12 shows a portion of the verify voltage and threshold voltage distribution used in the memory device of the first embodiment. [Figure 13] FIG. 13 shows the electrical characteristics of the cell transistor of the memory device of the first embodiment. [Figure 14] FIG. 14 shows the potential of a certain node over time based on the threshold voltage of a selected cell transistor during verification. [Figure 15] FIG. 15 shows the concept of verification in the storage device of the first embodiment. [Figure 16] FIG. 16 shows the potentials of several nodes and signals over time during verification of the memory device of the first embodiment. [Figure 17] FIG. 17 shows an example of data in the latch circuit during verification in the memory device of the first embodiment. [Figure 18] FIG. 18 shows one state of a part of the sense amplifier circuit of the memory device of the first embodiment. [Figure 19] FIG. 19 shows one state of a part of the sense amplifier circuit of the memory device of the first embodiment. [Figure 20] FIG. 20 shows an example of data in the latch circuit during verification in the memory device of the first embodiment. [Figure 21] FIG. 21 shows an example of data in the latch circuit during verification in the memory device of the first embodiment. [Figure 22] FIG. 22 shows an example of data in the latch circuit during verification in the memory device of the modified example of the first embodiment. [Figure 23] FIG. 23 is a circuit diagram of a sense amplifier circuit of a memory device according to the second embodiment. [Figure 24] FIG. 24 shows the potentials of several nodes and signals over time during verification of the memory device of the second embodiment. [Figure 25] FIG. 25 shows the potentials of some nodes and signals over time during verification in the modified second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. In order to distinguish between multiple components having substantially the same functions and configurations in a certain embodiment or different embodiments, additional numbers or letters may be added to the end of the reference numeral. Any description of one embodiment also applies to the description of another embodiment, unless explicitly or obviously excluded.

[0008] In this specification and claims, when a first element is "connected" to another second element, it includes the first element being connected to the second element directly or via a permanently or temporarily conductive element such as a switch.

[0009] Hereinafter, embodiments will be described using a three-dimensional Cartesian coordinate system. The direction of the x-axis is referred to as the X direction. The direction opposite to the X direction is referred to as the -X direction. The direction of the y-axis is referred to as the Y direction. The direction opposite to the Y direction is referred to as the -Y direction. The direction of the z-axis is referred to as the Z direction, with the Z direction representing the top. The direction opposite to the Z direction is referred to as the -Z direction, with the -Z direction representing the bottom.

[0010] 1. First embodiment 1.1.Configuration (Structure) FIG. 1 shows an example of components and connections of the components in a memory system including a storage device according to the first embodiment.

[0011] As shown in Figure 1, the memory system 2 includes a storage device 1 and a memory controller 3. The memory system 2 is a device that stores data. An example of the memory system 2 is an SD TM The memory system 2 includes a memory card such as a card, a Universal Flash Storage (UFS), and a Solid State Drive (SSD). The memory system 2 stores data, reads data, and erases data in response to a request from a host device 4. Examples of the host device 4 include a personal computer and a server in a data center.

[0012] The memory device 1 stores data using memory cells. The memory device 1 stores data to be written and outputs data stored in the memory device 1. In one example, the memory device 1 is realized as a single chip.

[0013] The memory controller 3 is a controller that controls the storage device 1. An example of the form of the memory controller 3 includes an integrated circuit such as an SoC (System-on-a-Chip). The memory controller 3 controls the storage device 1 to perform processing requested by the host device 4. Specifically, the memory controller 3 writes write data to the storage device 1 based on a write request from the host device 4. The memory controller 3 reads read data from the storage device 1 based on a read request from the host device 4, and transmits data based on the read data to the host device 4.

[0014] The memory controller 3 includes a CPU 301 , a read only memory (ROM) 302 , a random access memory (RAM) 303 , a host interface (host I / F) 304 , a memory interface (memory I / F) 305 , and an error correction circuit 307 .

[0015] The CPU 301 is a circuit that controls the overall operation of the memory controller 3. The CPU 301 executes a program that is stored in the ROM 302 and loaded onto the RAM 303, causing the memory controller 3 to perform various operations.

[0016] The ROM 302 is a non-volatile memory that stores programs including firmware.

[0017] The RAM 303 is a volatile memory that temporarily stores data and stores the programs stored in the ROM 302 while the memory system 2 is receiving power.

[0018] The host interface 304 is an interface through which the memory controller 3 communicates with the host device 4. The host interface 304 includes hardware or a combination of hardware and software. The host interface 304 is connected to the host device 4 via wiring to enable communication in a format that the memory controller 3 and the host device 4 comply with.

[0019] The memory interface 305 is an interface through which the memory controller 3 communicates with the storage device 1. The memory interface 305 includes hardware or a combination of hardware and software. The memory interface 305 is connected to the storage device 1 by wiring to enable communication in a manner based on the type of storage device 1. The memory interface 305 transmits commands, address information, and write data to the storage device 1 and receives read data from the storage device 1. The memory interface 305 transmits various control signals to the storage device 1 for controlling the storage device 1.

[0020] The error correction circuit 307 performs processing for detecting and correcting errors in data to be written to the storage device 1 and for detecting and correcting errors in data read from the storage device 1. The error correction circuit 307 may be realized as an independent dedicated semiconductor chip, may be a circuit formed on a semiconductor substrate, or may be realized by the CPU 301 executing firmware. The error correction circuit 307 generates an error correction code from data to be written to the storage device 1 (actual write data). Based on a method for generating the error correction code, the error correction code generated from this actual write data is added to the actual write data. The actual write data and the error correction code generated from this actual write data are written to the storage device 1. The error correction circuit 307 corrects errors in the read data using the error correction code.

[0021] FIG. 2 shows an example of components of the storage device of the first embodiment and connections between the components.

[0022] The memory device 1 includes components such as a memory cell array 11, an input / output circuit 12, a logic controller 13, a status register 14, an address register 15, a command register 16, a sequencer 17, a driver 18, a row decoder 19, and a sense amplifier 20.

[0023] The memory cell array 11 is a set of arranged memory cells. The memory cell array 11 includes a plurality of memory blocks (or blocks) BLK. Each block BLK includes a plurality of memory cells (cell transistors) MT (not shown). In the area where the memory cell array 11 is provided, wiring such as word lines WL (not shown) and bit lines BL (not shown) are also arranged.

[0024] The input / output circuit 12 transmits and receives various signals to and from the memory controller 3. The input / output circuit 12 transmits and receives input / output signals DQ (DQ_0, DQ_1, DQ_2, DQ_3, DQ_4, DQ_5, DQ_6, and DQ_7), as well as signals DQS and DQS. The symbol "" indicates the inverse logic of the signal without the symbol "" and indicates that the signal with the symbol "" is asserted when it is at a low ("L") level. The set of input / output signals DQ_0 to DQ_7 functions as signals such as a command (CMD), write data or read data (DAT), address information (ADD), and status information (STA). The signals DQS and DQS indicate the timing of capturing the input / output signals DQ_0 to DQ_7.

[0025] The logic controller 13 transmits and receives signals to and from the outside of the memory device 1, for example, a memory controller. The logic controller 13 receives signals CE, CLE, ALE, WE, RE, RE, and WP. The signal CE indicates that the memory device 1 should be enabled. The signal CLE indicates the transmission of a command by the input / output signal DQ. The signal ALE indicates the transmission of address information ADD by the input / output signal DQ. The signal WE indicates that the input / output signal DQ should be captured. The signal RE indicates the timing of the output of the input / output signal DQ.

[0026] The status register 14 temporarily stores status information STA, which indicates the state or result of one or more of various items of the storage device 1. The status information STA is sent from the sequencer 17 to the input / output circuit 12.

[0027] The address register 15 temporarily stores address information ADD received by the memory device 1. In one example, the address information ADD includes a plane address, a block address, a page address, and a column address. The plane address, block address, page address, and column address specify a plane PLN, a block BLK, a word line WL, and a bit line BL, respectively. The address information ADD is received by the input / output circuit 12 from outside the memory device 1, in one example, a memory controller, and transmitted to the address register 15.

[0028] The command register 16 temporarily stores commands CMD received by the memory device 1. The commands CMD instruct the memory device 1 to perform various operations including reading data, writing data, and erasing data.

[0029] The sequencer 17 is a circuit that controls the overall operation of the memory device 1. Based on the command CMD received from the command register 16, the sequencer 17 controls the driver 18, as well as the row decoder 19 and sense amplifier 20 of each plane PLN, to perform various operations including data read, data write, and data erase. The sequencer 17 transmits a ready / busy signal RY / BY. The ready / busy signal RY / BY indicates whether the memory device 1 is in a ready state or a busy state, and indicates a busy state by a low level. When the memory device 1 is in a ready state, it accepts the command CMD, and when it is in a busy state, it does not accept the command CMD.

[0030] The driver 18 is a circuit that applies various voltages required for the operation of the memory device 1 to several components. The driver 18 receives a power supply voltage from outside the memory device 1 and generates multiple voltages from the power supply voltage. The driver 18 supplies the generated voltages to the memory cell array 11, the sense amplifier 20, and the row decoder 19.

[0031] The row decoder 19 is a circuit for selecting a block BLK. The row decoder 19 transfers the voltage supplied from the driver 18 to one block BLK selected based on the block address received from the address register 15.

[0032] The sense amplifier 20 is a circuit that determines the data stored in the memory cell array 11. The sense amplifier 20 senses the state of the cell transistor MT and generates read data based on the sensed state. The generated read data DAT is sent to the input / output circuit 12. The sense amplifier 20 receives write data DAT and transfers the received write data DAT to the cell transistor MT.

[0033] 3 shows the components and connections of one block of the storage device of Embodiment 1. A plurality of blocks BLK, for example, all blocks BLK, include the components and connections shown in FIG.

[0034] One block BLK includes a plurality of string units SU. Figure 3 shows an example of five string units SU_0 to SU_4.

[0035] 3, m bit lines BL_0 to BL_m-1 are each connected to one NAND string NS from each of the string units SU_0 to SU_4 in each block BLK, where m is a positive integer.

[0036] Each NAND string NS includes one select gate transistor ST, n cell transistors MT (MT_0 to MT_n-1), and one select gate transistor DT (DT_0, DT_1, DT_2, DT_3, or DT_4), where n is a positive integer. The cell transistor MT functions as a memory cell and is an element that stores data in a nonvolatile manner. The cell transistor MT includes a control gate electrode or gate electrode (word line WL) and a charge storage film insulated from the surroundings, and stores data in a nonvolatile manner based on the charge in the charge storage film. Data is written to the cell transistor MT by injecting electrons into the charge storage film.

[0037] The select gate transistor ST, the cell transistors MT_0 to MT_n-1, and the select gate transistor DT are connected in series in this order between the source line SL and one bit line BL.

[0038] A plurality of NAND strings NS connected to different bit lines BL respectively constitute one string unit SU. In each string unit SU, the control gate electrodes of the cell transistors MT_0 to MT_n-1 are connected to word lines WL_0 to WL_n-1, respectively. A set of cell transistors MT sharing a word line WL in one string unit SU is called a cell unit CU.

[0039] The select gate transistors DT_0 to DT_4 belong to the string units SU_0 to SU_4, respectively. The select gate transistors DT_2, DT_3, and DT_4 are omitted from FIG. 3 . The gate of the select gate transistor DT0 of each of the multiple NAND strings NS in the string unit SU_0 is connected to a select gate line SGDL_0. Similarly, the gates of the select gate transistors DT_1, DT_2, DT_3, and DT_4 of each of the multiple NAND strings NS in the string units SU_1, SU_2, SU_3, and SU_4 are connected to select gate lines SGDL_1, SGDL_2, SGDL_3, and SGDL_4, respectively.

[0040] The gate of the select gate transistor ST is connected to a select gate line SGSL.

[0041] 4 shows an exploded view of the structure of the storage device of the first embodiment. As shown in FIG. 4, the storage device 1 includes a first structure 100 and a second structure 200 aligned along the z-axis. The first structure 100 and the second structure 200 extend along the xy plane and are aligned along the z-axis. The second structure 200 is located on the top surface of the first structure 100.

[0042] The first structure 100 and the second structure 200 each include a plurality of semiconductors, a plurality of conductors, and a plurality of insulators formed on a substrate using a substrate. The first structure 100 and the second structure 200 each include a plurality of elements and wiring realized by the semiconductors, conductors, and insulators. The first structure 100 and the second structure 200 each include an electric circuit including the elements and wiring. The elements and wiring in the first structure 100 and the elements and wiring in the second structure 200 are electrically connected to each other.

[0043] The set of the first structure 100 and the second structure 200 includes a memory cell array 11, an input / output circuit 12, a logic controller 13, a status register 14, an address register 15, a command register 16, a sequencer 17, a driver 18, a row decoder 19, and a sense amplifier 20.

[0044] The first structure 100 includes a plurality of conductive junction terminals BP1. The junction terminals BP1 are exposed on the top surface of the first structure 100. The junction terminals BP1 are connected to elements in the first structure 100.

[0045] The second structure 200 includes a plurality of conductive bond terminals BP2. The bond terminals BP2 are exposed on the bottom surface of the second structure 200. The bond terminals BP2 are connected to elements in the second structure 200. The bond terminals BP2 have the same layout as the bond terminals BP1 of the first structure 100. The bond terminals BP2 are arranged so that, when the first structure 100 and the second structure 200 are bonded together, each bond terminal BP2 contacts one of the bond terminals BP1 of the first structure 100 that corresponds to the particular bond terminal BP2. A particular bond terminal BP2 and one of the bond terminals BP1 of the first structure 100 that corresponds to the particular bond terminal BP2 are elements that function as the same node in a circuit.

[0046] FIG. 5 shows an example of a cross-sectional structure of a portion of the memory device of the first embodiment. As shown in FIG. 5, the first structure 100 further includes a substrate W1, a structure STIC, a transistor Tr1, contacts CS, C0, C1, C2, and C3, conductors L0, L1, and L2, and insulators 21 and 22. In the following description, a conductor also includes a semiconductor that is conductive due to containing impurities. In one example, the substrate W1 includes silicon. In one example, the contacts CS1, C0, C1, C2, and C3 and the conductors L0, L1, and L2 include copper or tungsten. In one example, the insulators 21 and 22 include silicon oxide.

[0047] The STIC structure has a shallow trench isolation (STI) structure. The STIC structure extends in the substrate W1 from the upper surface of the substrate W1 along the z-axis. In one example, the STIC structure includes silicon oxide.

[0048] Transistor Tr1 is located in a region above and near the top surface of substrate W1 and includes a gate insulator on the top surface of substrate W1, a gate electrode on the top surface of the gate insulator, and a pair of source / drain regions sandwiching a region below the gate electrode.

[0049] Each contact C0 has a lower surface that contacts the upper surface of the gate electrode of one transistor Tr1, and each contact CS has a lower surface that contacts one source / drain region.

[0050] Each conductor L0 is in contact with one contact C0 or CS at its bottom surface, and each contact C1 is in contact with the top surface of one conductor L0 at its bottom surface.

[0051] Each conductor L1 contacts the upper surface of one contact C1 at its lower surface, and each contact C2 contacts the upper surface of one conductor L1 at its lower surface.

[0052] The lower surface of each conductor L2 contacts the upper surface of one contact C2, and the lower surface of each contact C3 contacts the upper surface of one conductor L2.

[0053] The set of transistor Tr1, contacts CS, C0, C1, C2, and C3, and conductors L0, L1, and L2 implements a circuit included in the first structure 100. Thus, the first structure 100 has transistor Tr1, contacts CS, C0, C1, C2, and C3, and conductors L0, L1, and L2 in any shape and arrangement that implements the circuit included in the first structure 100.

[0054] The insulator 21 extends from the height of the upper surface of the substrate W1 to the height of the upper surface of the contact C3 and fills the region of the first structure 100 where the transistor Tr1, the contacts CS, C0, C1, C2, and C3, and the conductors L0, L1, and L2 are not provided.

[0055] The bottom surface of each bonding terminal BP1 is in contact with the top surface of one of the contacts C3. The insulator 22 fills in the region of the layer in which the bonding terminals BP1 are located, where the bonding terminals BP1 are not provided.

[0056] The second structure 200 further includes contacts C4, C5, and C6, conductors L3, L4, 31, 33, 36, 38, insulators 24, 32, 34, 35, 37, 40, 41, and memory pillar MP.

[0057] Each of the bonding terminals BP2 is located in the bottom layer of the second structure 200. The insulator 40 fills in the region of the layer in which the bonding terminals BP2 are located, where the bonding terminals BP2 are not provided.

[0058] The lower surface of each contact C4 contacts the upper surface of one of the bonding terminals BP2, and the lower surface of each conductor L3 contacts the upper surface of one of the contacts C4.

[0059] The bottom surface of each contact C5 contacts the top surface of one of the conductors L3, and the bottom surface of each conductor L4 contacts the top surface of one of the contacts C5.

[0060] The conductor 31 is located above the conductor L4. The conductor 31 has a plate-like shape along the xy plane. The conductor 31 functions as at least a part of the select gate line SGDL. The lower surface of the conductor 31 is exposed at the end and has a terrace.

[0061] The insulator 32 is located on the upper surface of the conductor 31. The insulator 32 has a plate shape along the xy plane.

[0062] The conductors 33 and insulators 34 are alternately stacked one by one on the upper surface of the insulator 32. The conductors 33 and insulators 34 have a plate-like shape along the xy plane. Each conductor 33 functions as at least a part of a word line WL. FIG. 5 shows an example where n, that is, the number of memory cell transistors MT, is 8. The conductors 33 function as at least a part of word lines WL0, WL1, WL2, WL3, WL4, WL5, WL6, and WL7, in order from the bottom up. The lower surface of each conductor 33 is exposed at the edge and has a terrace.

[0063] An insulator 35 is located on top of the top conductor 33 .

[0064] The conductor 36 is located on the upper surface of the insulator 35. The conductor 36 functions as at least a part of the select gate line SGSL.

[0065] Insulator 37 is located on the upper surface of conductor 36. Conductor 38 is located on the upper surface of insulator 37. The lower surface of conductor 38 is exposed at the end and has a terrace.

[0066] The memory pillar MP extends along the z-axis and penetrates a set of conductors 31, 33, and 36 and insulators 32, 34, 35, and 37. Each memory pillar MP includes an insulator CI, a semiconductor SM, and a stack SS. The semiconductor SM covers the side surface of the insulator CI. The stack SS covers the side surface of the semiconductor SM. The stack SS has an opening at the top end of the memory pillar MP. A portion of the semiconductor SM is located in the opening and contacts the conductor 38 on the top surface.

[0067] The upper portion of the memory pillar MP may be located in the conductor 38, the stacked body SS may have an opening at the portion facing the conductor 38, and a part of the semiconductor SM may be located in the opening.

[0068] 6 shows an example of a cross-sectional structure along the xy plane of a memory pillar of the memory device according to the first embodiment. As shown in FIG. 6, in one example, the stacked body SS includes a tunnel insulator TI, a charge storage film CA, and a block insulator BI.

[0069] A tunnel insulator TI surrounds the side of the semiconductor SM. A charge storage film CA surrounds the side of the tunnel insulator TI. A block insulator BI surrounds the side of the charge storage film CA. A conductor 31, 33, or 36 surrounds the side of the block insulator BI.

[0070] The semiconductor SM functions as a channel (current path) for the memory cell transistor MT and the select gate transistors DT and ST. The tunnel insulator TI and the block insulator BI each contain, for example, silicon oxide. The charge storage film CA stores charges. The charge storage film CA contains, for example, silicon nitride.

[0071] Returning to FIG. 5, the portion of each memory pillar MP that faces the conductor 31 functions as one select gate transistor DT. The portion of each memory pillar MP that faces the conductor 33 functions as one memory cell transistor MT. The portion of each memory pillar MP that faces the conductor 36 functions as one select gate transistor ST. The lower surface of the semiconductor SM is exposed at the lower surface of each memory pillar MP. The lower surface of the semiconductor SM is exposed at the upper surface of each memory pillar MP.

[0072] Each contact C6 contacts the upper surface of one of the conductors L4 at its lower surface. Each of several contacts C6 contacts the lower surface of the semiconductor SM of one of the memory pillars MP at its upper surface. Each of several contacts C6 contacts the lower surface of the terrace portion of one of the conductors 31, 33, and 37 at its upper surface.

[0073] The insulator 40 extends from the height of the upper surface of the insulator 24 to the height of the upper surface of the conductor 38. The insulator 40 embeds contacts C4, C5, and C6, conductors L3, L4, 31, 33, 36, and 38, insulators 40, 32, 34, 35, and 37, and regions of the second structure 200 where no memory pillar MP is provided.

[0074] Insulator 41 is located on the top surface of each of conductor 38 and insulator 40 .

[0075] The memory device 1 can store two or more bits of data in one cell transistor MT. FIG. 7 shows an example of the threshold voltage distribution and data mapping of cell transistors storing three bits of data in the memory device of the first embodiment. The threshold voltage of each cell transistor MT varies depending on the amount of electrons in its charge storage film CA and the stored data. In the case of three-bit storage, each cell transistor MT is in one of the states "S0", "S1", "S2", "S3", "S4", "S5", "S6", and "S7" depending on its threshold voltage. The cell transistors MT in the "S0", "S1", "S2", "S3", "S4", "S5", "S6", and "S7" states have higher threshold voltages in this order. When the threshold voltage of a cell transistor MT is lowered by data erasure, it is transitioned to the "S0" state.

[0076] When data is written, the cell transistor MT to be written is either maintained in the "S0" state or moved to one of the "S1", "S2", "S3", "S4", "S5", "S6", and "S7" states depending on the data to be written. Even multiple cell transistors MT that store the same 3-bit data may have different threshold voltages. A set of threshold voltages in a single state is called a threshold voltage lobe.

[0077] Three bits of data can be assigned to each state in any way. In one example, each state is treated as having the following three bits of data: In the following description, "ABC" means that A, B, and C represent the upper, middle, and lower bit values, respectively. “S0” state: “111” “S1” state: “110” “S2” state: “100” “S3” state: “000” “S4” state: “010” “S5” state: “011” “S6” state: “001” “S7” state: “101” Data reading is based on determining the state of the cell transistor MT to be read. To determine the state, multiple read voltages VCGR having different magnitudes are used. If the cell transistor MT has a threshold voltage equal to or greater than the read voltage VCGR, it is turned off even when the control gate electrode receives the read voltage VCGR. If the cell transistor MT has a threshold voltage less than the read voltage VCGR, it is turned on when the control gate electrode receives the read voltage VCGR. Based on this, it is determined whether the threshold voltage of the cell transistor MT to be read exceeds the read voltage VCGR.

[0078] The determination of whether the cell transistor MT to be read is in a state higher than the "S0", "S1", "S2", "S3", "S4", "S5", "S6", and "S7" states is performed using read voltages V1, V2, V3, V4, V5, V6, and V7, respectively. The read voltages V1, V2, V3, V4, V5, V6, and V7 are higher in this order. Obtaining a set of bits indicating whether the cell transistor MT is on or off by applying the read voltages V1, V2, V3, V4, V5, V6, and V7 (data read) is referred to as 1R, 2R, 3R, 4R, 5R, 6R, and 7R, respectively.

[0079] A set of data bits at the same position (digit) of the cell transistors MT of one cell unit CU constitutes one page. The set (or bit string) of the least significant (first digit from the bottom) bits (lower bits) of the cell transistors MT of each cell unit CU is called the lower page. The set (or bit string) of the second least significant bit (middle bits) of the cell transistors MT of each cell unit CU is called the middle page. The set (or bit string) of the third least significant bit (upper bits) of the cell transistors MT of each cell unit CU is called the upper page.

[0080] Reading the lower page uses 1R and 5R. The data of the lower page can be determined by 1R and 5R.

[0081] Reading the middle page uses 2R, 4R, and 6R, and the data of the middle page can be determined by 2R, 4R, and 6R.

[0082] Reading the upper page uses 3R and 7R, which allow the data on the upper page to be determined.

[0083] The voltage VREAD has a magnitude that turns on the cell transistor MT regardless of the state to which the cell transistor MT belongs.

[0084] 8 shows the components and connections of the sense amplifier of the memory device of the first embodiment. The sense amplifier 20 includes multiple latch circuits XDL and the same number of sense amplifier units SAU as the number of bit lines BL. Each sense amplifier unit SAU includes a sense amplifier circuit SAC and multiple, for example, five latch circuits SDL, ADL, BDL, CDL, and DDL.

[0085] The latch circuits SDL, ADL, BDL, CDL, and DDL are connected to the bus LBUS. Each of the latch circuits SDL, ADL, BDL, CDL, and DDL can store one bit of data.

[0086] The latch circuit XDL is connected to one sense amplifier unit SAU via a bus DBUS, which is connected to an input / output circuit 12.

[0087] The sense amplifier circuit SAC is connected to one bus LBUS and one bit line BL. During data read, the sense amplifier circuit SAC is connected to one selected cell transistor MT via one bit line BL connected to itself. The selected cell transistor MT is the cell transistor MT selected as the target for data read or data write. Each sense amplifier circuit SAC senses a voltage at a node (node ​​SEN described below) in the sense amplifier circuit SAC, the magnitude of which is determined based on the threshold voltage of the selected cell transistor MT. Based on the sensing result, the sense amplifier circuit SAC outputs data indicating which of two states the cell transistor MT belongs to. The two states of the cell transistor MT are represented as "0" data or "1" data. The data is stored in a latch circuit SDL connected to the sense amplifier circuit SAC.

[0088] 9 is a circuit diagram of a sense amplifier circuit of the memory device of Embodiment 1. Each sense amplifier circuit SAC further includes p-type metal oxide semiconductor field effect transistors (MOSFETs) T1 and T2, n-type MOSFETs T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, and T16, and a capacitor P1.

[0089] The transistors T3 and T4 are connected in series, in this order, between a bit line BL connected to the sense amplifier circuit SAC in Fig. 9 and a node N1. The transistor T3 receives a signal BLS at its gate. The transistor T4 receives a signal BLC at its gate.

[0090] The transistor T5 is connected between the node N1 and the node SEN and receives the signal XXL at its gate.

[0091] Transistors T1 and T6 are connected in series, in this order, between node VHSA and node N1. Node VHSA receives the power supply voltage for sense amplifier 20 from driver 18. Transistor T1 has its gate connected to node INVS. Transistor T6 has its gate receiving signal BLX.

[0092] The transistor T7 is connected between the node N1 and a node VSS, which receives the ground voltage VSS from the driver 18 or the memory controller 3. The transistor T7 receives a signal NLO at its gate.

[0093] The transistor T7 is connected between the node N1 and the node VSS and receives the signal NLO at its gate.

[0094] The transistor T8 is connected between the node VSS and the node to which the transistors T1 and T6 are connected, and the gate of the transistor T8 is connected to the node INVS.

[0095] Transistors T2 and T9 are connected in parallel between node VHLB and node N2. Node VHLB receives voltage VHLB from driver 18. Transistor T2 has its gate connected to node LATA. Transistor T9 receives signal SPC at its gate.

[0096] The transistor T10 is connected between the node N2 and the node SEN and receives the signal NPC at its gate.

[0097] Capacitor P1 is connected between node SEN and node CLKSA, which in one example receives a voltage from driver 18.

[0098] The transistors T11 and T12 are connected in series between the node SEN and the node VLOP in this order. The transistor T11 receives the signal LSL at its gate. The transistor T12 is connected to the bus LBUS at its gate.

[0099] The transistor T13 is connected between the node SEN and the LBUS and receives the signal BLQ at its gate.

[0100] The transistors T14 and T15 are connected in series in this order between the bus LBUS and the node VLOP. The transistor T14 receives a signal STB at its gate. The transistor T15 is connected to the node SEN at its gate.

[0101] The transistor T16 is connected between the bus LBUS and the bus DBUS and receives the signal DSW at its gate.

[0102] The latch circuit SDL includes n-type MOSFETs T21 and T22, and inverter circuits IV1 and IV2.

[0103] The transistor T21 is connected between the bus LBUS and the node INVS and receives the signal STI at its gate.

[0104] The transistor T22 is connected between the bus LBUS and the node LATS and receives the signal STL at its gate.

[0105] The inverter circuit IV1 has an input connected to the node LATS and an output connected to the node INVS.

[0106] The inverter circuit IV2 has an input connected to the node INVS and an output connected to the node LATS.

[0107] The latch circuit ADL includes n-type MOSFETs T23 and T24, and inverter circuits IV3 and IV4.

[0108] The transistor T23 is connected between the bus LBUS and the node INVA and receives the signal ATI at its gate.

[0109] The transistor T24 is connected between the bus LBUS and the node LATA and receives the signal ATL at its gate.

[0110] The inverter circuit IV3 has an input connected to the node LATA and an output connected to the node INVA.

[0111] The inverter circuit IV4 has an input connected to the node INVA and an output connected to the node LATA.

[0112] The latch circuit BDL includes n-type MOSFETs T25 and T26, and inverter circuits IV5 and IV6.

[0113] The transistor T25 is connected between the bus LBUS and the node INVB and receives the signal BTI at its gate.

[0114] The transistor T26 is connected between the bus LBUS and the node LATB and receives the signal BTL at its gate.

[0115] The inverter circuit IV5 has an input connected to the node LATB and an output connected to the node INVB.

[0116] The inverter circuit IV6 has an input connected to the node INVB and an output connected to the node LATB.

[0117] The latch circuit CDL includes n-type MOSFETs T27 and T28, and inverter circuits IV7 and IV8.

[0118] The transistor T27 is connected between the bus LBUS and the node INVC and receives the signal CTI at its gate.

[0119] The transistor T28 is connected between the bus LBUS and the node LATC and receives the signal CTL at its gate.

[0120] The inverter circuit IV7 has an input connected to the node LATC and an output connected to the node INVC.

[0121] The inverter circuit IV8 has an input connected to the node INVC and an output connected to the node LATC.

[0122] The latch circuit DDL has the same configuration as the latch circuits SDL, ADL, BDL, and CDL.

[0123] In one example, one, more, or all of the signals BLS, BLC, XXL, BLX, NLO, LSL, BLQ, and STB are provided by sequencer 17.

[0124] 1.2.Operation FIG. 10 shows an overview of the write operation in the memory device of the first embodiment over time. As shown in FIG. 10, the memory device 1 repeatedly executes program loops during the write operation. FIG. 10 shows the number of times the program loop has been executed (hereinafter referred to as the loop number) and the voltage of the selected word line WLsel (WLsel voltage). The selected word line WLsel is the word line WL connected to the cell unit CU to which data is written (write operation). Each program loop includes programming and verifying.

[0125] Programming is an operation for increasing the threshold voltage of a cell transistor MT. During programming, a selected cell transistor MTsel is set to a program state or a program-inhibited state. The selected cell transistor MTsel is a cell transistor MT connected to a selected word line WLsel. Whether the selected cell transistor MTsel is set to a program state or a program-inhibited state depends on the target state of each selected cell transistor MTsel. The target state is the state to which each selected cell transistor MTsel will be moved based on the data to be written. If the selected cell transistor MTsel has a threshold voltage below a voltage determined to be included in the target state, it is set to a program state. If the selected cell transistor MTsel has a threshold voltage equal to or greater than a voltage determined to be included in the target state, it is set to a program-inhibited state.

[0126] During programming, a program voltage VPGM of variable magnitude is applied to the selected word line WLsel, which is a high voltage capable of raising the threshold voltage of the selected cell transistor MTsel.

[0127] The program voltage VPGM is increased each time the number of loops increases. The increase width DVPGM of the program voltage VPGM can have any magnitude. When the program voltage VPGM is applied to the selected word line WLsel, the threshold voltage of the selected cell transistor MTsel in the programmed state increases. The increase in the threshold voltage of the selected cell transistor MTsel in the program inhibited state is suppressed.

[0128] Verify is an operation of checking whether the threshold voltage of the selected cell transistor MTsel is equal to or higher than a voltage determined to be included in the target state, and is a read operation. In the verify or read operation, the signal STB is asserted, and data based on the potential of the node SEN is stored in the latch circuit SDL, ADL, BDL, CDL, or DDL. Hereinafter, in the verify or read operation, the operation of storing data based on the potential of the node SEN in the latch circuit SDL, ADL, BDL, CDL, or DDL is referred to as a sense operation.

[0129] The sequencer 17 performs verification on the selected cell transistor MTsel having a specific target state in each program loop.

[0130] During the verify operation, it is determined whether the threshold voltage of the selected cell transistor MTsel is equal to or greater than a verify voltage Vp, which has a variable magnitude. Each sense amplifier unit SAU outputs data based on whether the threshold voltage of the selected cell transistor MTsel connected thereto is equal to or greater than the verify voltage Vp. If the threshold voltage of the selected cell transistor MTsel is equal to or greater than the verify voltage Vp, data indicating that the verify operation has passed is output. The verify voltage Vp has a magnitude that depends on the target state and is lower than the minimum threshold voltage that the selected cell transistor MTsel must have to be considered to have been transferred to the target state. In one example, the verify voltages Vp1, Vp2, Vp3, Vp4, Vp5, Vp6, and Vp7 for the “S0”, “S1”, “S2”, “S3”, “S4”, “S5”, “S6”, and “S7” states are the same as the read voltages V1, V2, V3, V4, V5, V6, and V7, respectively. In another example, the verify voltages Vp1, Vp2, Vp3, Vp4, Vp5, Vp6, and Vp7 are slightly lower than the read voltages V1, V2, V3, V4, V5, V6, and V7, respectively.

[0131] On the other hand, if the threshold voltage of the selected cell transistor MTsel is lower than the verify voltage Vp, data indicating a verify failure is output. Each sense amplifier unit SAU stores data indicating the verify result in an internal latch circuit ADL, BDL, CDL, or DDL. When verify in a certain program loop is completed, the sequencer 17 sets each selected cell transistor MTsel to a programmed state or a program-inhibited state based on the verify result, and starts the next program loop.

[0132] The memory device 1 may perform a detection operation after any program loop. In the detection operation, the number of selected cell transistors MTsel that have passed verification is counted for each target state. Then, the sequencer 17 determines whether the programming of each target state is complete based on the count value. In one example, when the count value exceeds a certain percentage of m (i.e., the number of cell transistors MT in one cell unit CU), the programming is determined to be complete.

[0133] 11 shows an example of setting a program loop in a write operation in the storage device of the first embodiment. Fig. 11 shows the relationship between the number of loops and the target states to be verified assigned to each loop. The target states to be verified are indicated by white circles.

[0134] 11, the type and number of target states to be verified vary depending on the progress of the program loop. In the example of FIG. 11, the sequencer 17 executes the program loop a maximum of 19 times. The maximum number of program loops is predetermined based on the characteristics of the memory device 1 as the number of times that the write operation is considered or expected to be completed (i.e., the increase in the threshold voltage of the selected cell transistor MTsel with the highest state as the target state is completed).

[0135] The sequencer 17 performs verification on at least one state in each program loop. Specifically, the "S1" state is set as the verification target in the first to sixth program loops. The "S2" state is set as the verification target in the second to eighth program loops. The "S3" state is set as the verification target in the fourth to tenth program loops. The "S4" state is set as the verification target in the sixth to twelfth program loops. The "S5" state is set as the verification target in the eighth to fourteenth program loops. The "S6" state is set as the verification target in the tenth to sixteenth program loops. The "S7" state is set as the verification target in the twelfth to nineteenth program loops. Verification may be omitted in the final program loop, as it is assumed that writing will be completed by the final program loop.

[0136] In verifying each target state, it is determined which of the four ranges the threshold voltage of the selected cell transistor MTsel belongs to. Below, we will describe the program verification for the selected cell transistor MTsel in the "S0" state as a representative. For the other states, the only difference is that the heights of the four threshold voltage ranges differ depending on the state, and they are the same as the "S0" state.

[0137] 12 shows a portion of the verify voltage and threshold voltage distribution used in the memory device of the first embodiment. Four voltage ranges include ranges A1, A2, A3, and A4. Range A1 is a range below voltage VL. Range A2 is a range equal to or greater than voltage VL and less than voltage VM. Range A3 is a range equal to or greater than voltage VM and less than voltage VH. Range A4 is a range equal to or greater than voltage VH. The voltages VL, VM, and VH are higher in this order. Voltage VH is the verify voltage Vp for the target state. That is, based on the example of programming the selected cell transistor MTsel in the "S0" state, voltage VH is voltage Vp1.

[0138] A sense operation that generates data indicating whether the selected cell transistor MTsel has a threshold voltage less than the voltage VL or greater than or equal to the voltage VL is called a VL sense operation. The VL sense operation corresponds to determining whether the selected cell transistor MTsel has a threshold voltage less than the voltage VL or greater than or equal to the voltage VL.

[0139] The sensing operation that generates data indicating whether the selected cell transistor MTsel has a threshold voltage less than the voltage VM or greater than the voltage VM is called a VM sensing operation. The VM sensing operation corresponds to determining whether the selected cell transistor MTsel has a threshold voltage less than the voltage VM or greater than the voltage VM.

[0140] The operation of indicating whether the selected cell transistor MTsel has a threshold voltage less than the voltage VH or greater than or equal to the voltage VH is called a VH sense operation. The VH sense operation corresponds to determining whether the selected cell transistor MTsel has a threshold voltage less than the voltage VH or greater than or equal to the voltage VM.

[0141] The range to which the threshold voltage of the selected cell transistor MTsel belongs can be determined by the VL sense operation, the VM sense operation, and the VH sense operation.

[0142] In a certain program loop, the selected cell transistor MTsel determined by the VL sense operation to have a threshold voltage less than the voltage VL is determined to have a threshold voltage less than the verify voltage VH (=Vp1) of the target state. Therefore, in the program of the next program loop, it is set to the programmed state. In programming the selected cell transistor MTsel determined to have a threshold voltage less than the voltage VL and set to the programmed state, first program conditions that significantly increase the threshold voltage of the selected cell transistor MTsel are used. The selected cell transistor MTsel to which the first program conditions are applied, i.e., determined to have a threshold voltage belonging to the range A1, may be referred to as the selected cell transistor MTsel1.

[0143] In a certain program loop, a selected cell transistor MTsel determined to have a threshold voltage equal to or greater than the voltage VL by the VL sense operation but lower than the voltage VM by the VM sense operation is determined to have a threshold voltage lower than the verify voltage VH of the target state. Therefore, the selected cell transistor MTsel is set to the programmed state in the next program loop. When programming the selected cell transistor MTsel determined to have a threshold voltage equal to or greater than the voltage VL and lower than the voltage VM and set to the programmed state, if the first program conditions are used, the threshold voltage of the selected cell transistor MTsel may rise excessively. Therefore, second program conditions are used that raise the threshold voltage of the selected cell transistor MTsel by a smaller amount than the first program condition. The selected cell transistor MTsel to which the second program conditions are applied, i.e., determined to have a threshold voltage belonging to range A2, may be referred to as the selected cell transistor MTsel2.

[0144] In a certain program loop, a selected cell transistor MTsel determined to have a threshold voltage equal to or greater than voltage VM by a VM sense operation but lower than voltage VH by a VH sense operation is determined to have a threshold voltage lower than the verify voltage VH of the target state. Therefore, the selected cell transistor MTsel is set to a programmed state in the next program loop. When programming the selected cell transistor MTsel determined to have a threshold voltage equal to or greater than voltage VM and lower than voltage VH and set to a programmed state, if the second program condition is used, the threshold voltage of the selected cell transistor MTsel may rise excessively. Therefore, a third condition is used, which raises the threshold voltage of the selected cell transistor MTsel by a smaller amount than the second program condition. The selected cell transistor MTsel to which the third program condition is applied, i.e., determined to have a threshold voltage belonging to range A3, may be referred to as a selected cell transistor MTsel3.

[0145] In a certain program loop, a selection cell transistor MTsel determined to have a threshold voltage equal to or higher than the voltage VH by VH sense operation is set to a program inhibition state in the program of the next program loop. A selection cell transistor MTsel determined to be set to the program inhibition state, that is, to have a threshold voltage belonging to range A4, may be referred to as selection cell transistor MTsel4.

[0146] In this way, by using different program conditions based on the four ranges of the threshold voltage of the selection cell transistor MTsel, the spread of the threshold voltage distribution after programming can be suppressed.

[0147] In the first embodiment, a difference in the degree of decrease in the potential of node SEN based on the threshold voltage of the selection cell transistor MTsel is utilized.

[0148] FIG. 13 shows the electrical characteristics of the cell transistors of the memory device of the first embodiment. In FIG. 13, the vertical axis represents the current flowing through the cell transistor MT (drain current Ids), and the horizontal axis represents the voltage Vgs between the gate and source of the cell transistor MT. When the voltage Vgs exceeds the threshold voltage Vth of the cell transistor, the drain current Ids increases rapidly.

[0149] On the other hand, even when a voltage of the same magnitude is applied to the selection cell transistor MTsel, the higher the threshold voltage of the selection cell transistor MTsel, the smaller the effective voltage Vgs. Therefore, even when a voltage of the same magnitude is applied to the selection cell transistor MTsel, the drain current Ids is different. Specifically, it is as follows. Assume that a drain current Ids1 flows through the selection cell transistor MTsel1, a drain current Ids2 flows through the selection cell transistor MTsel2, a drain current Ids3 flows through the selection cell transistor MTsel3, and a drain current Ids4 flows through the selection cell transistor MTsel4. Then, Ids4 < Ids3 < Ids2 < Ids1 holds.

[0150] FIG. 14 shows the potential of a node over time based on the threshold voltage of a selected cell transistor during verification. FIG. 14 shows the potential of node SEN when a constant voltage (e.g., the verify voltage Vp of the target state) is applied to the selected word line WLsel, and shows the potential of node SEN connected to selected cell transistors MTsel1, MTsel2, MTsel3, and MTsel4. FIG. 14 also shows a case in which the potential of node SEN drops from potential VSEN1 for all selected cell transistors MTsel1, MTsel2, MTsel3, and MTsel4. The threshold voltage Vt15U is the maximum possible threshold voltage of transistor T15 in the sense amplifier circuit SAC. The threshold voltage Vt15L is the minimum possible threshold voltage of transistor T15 in the sense amplifier circuit SAC. That is, the transistor T15 may have a different threshold voltage due to limitations in manufacturing technology, and may have a threshold voltage that is equal to or greater than the threshold voltage Vt15L and equal to or less than the threshold voltage Vt15U.

[0151] As described above with reference to Figure 13, the lower the threshold voltage of the selected cell transistor MTsel, the larger the drain current of the selected cell transistor MTsel. Therefore, as shown in Figure 14, the lower the threshold voltage of the selected cell transistor MTsel, the larger the amount of drop in the potential of the node SEN from the start of the drop in potential (time t0) until a certain period of time has elapsed. By utilizing this phenomenon, the VL sense operation, the VM sense operation, and the VH sense operation can be performed.

[0152] After time t1, the potential of the node SEN connected to the select cell transistor MTsel1 is equal to or lower than the threshold voltage Vt15L. Meanwhile, until time t2, the potential of the node SEN connected to the select cell transistor MTsel2, MTsel3, or MTsel4 is equal to or higher than the threshold voltage Vt15U. Therefore, by performing the sense operation from time t1 to time t2, it can be determined whether the select cell transistor MTsel is the select cell transistor MTsel1 or the select cell transistor MTsel2, MTsel3, or MTsel4. That is, the transistor T15 connected to the select cell transistor MTsel having a lower threshold voltage is turned on. Therefore, the select cell transistor MTsel connected to the transistor T15 that is turned on earlier from the start of the voltage drop at the node SEN can be determined to have a lower threshold voltage. The select cell transistor MTsel determined to be on from time t1 to time t2 has a threshold voltage within the range A1, i.e., it can be determined to be the select cell transistor MTsel1.

[0153] On the other hand, from time t1 to time t2, transistor T15 connected to a select cell transistor MTsel having a relatively low, relatively high, or high threshold voltage remains off. Therefore, the select cell transistor MTsel connected to transistor T15 that remains off from the early stage after the potential of node SEN starts to drop can be determined to have a relatively low, relatively high, or high threshold voltage. Such a select cell transistor MTsel that is off from time t1 to time t2 can be determined to have a threshold voltage that belongs to range A2, A3, or A4, i.e., to be select cell transistor MTsel2, MTsel3, or MTsel4.

[0154] Determining whether the threshold voltage of the selected cell transistor MTsel belongs to range A1 or range A2, A3, or A4 through the sense operation from time t1 to time t2 corresponds to the execution of a VL sense operation.

[0155] After time t3, the potential of the node SEN connected to the select cell transistor MTsel1 or MTsel2 is equal to or lower than the threshold voltage Vt15L. Meanwhile, until time t4, the potential of the node SEN connected to the select cell transistor MTsel3 or MTsel4 is equal to or higher than the threshold voltage Vt15U. Therefore, by the sense operation from time t3 to time t4, it can be determined whether the select cell transistor MTsel is the select cell transistor MTsel1 or MTsel2, or the select cell transistor MTsel3 or MTsel4. That is, the transistor T15 connected to the select cell transistor MTsel with a low or relatively low threshold voltage is on. Therefore, it can be determined that the select cell transistor MTsel connected to the transistor T15 that is on relatively early after the start of the drop in the potential of the node SEN has a threshold voltage belonging to range A2, i.e., is the select cell transistor MTsel1 or MTsel2.

[0156] On the other hand, from time t3 to time t4, the transistor T15 connected to the select cell transistor MTsel with a relatively high threshold voltage remains off. Therefore, the select cell transistor MTsel connected to the transistor T15 that remains off even after a relatively early stage from the start of the drop in the potential VSEN can be determined to have a relatively high threshold voltage. Such a select cell transistor MTsel that is off from time t3 to time t4 can be determined to have a threshold voltage that belongs to range A3 or A4, i.e., to be the select cell transistor MTsel2 or MTsel3.

[0157] Determining whether the threshold voltage of the selected cell transistor MTsel belongs to the range A1 or A2, or the range A3 or A4, through the sense operation from time t3 to time t4 corresponds to the execution of a VM sense operation.

[0158] After time t5, the potential of the node SEN connected to the select cell transistor MTsel1, MTsel2, or MTsel3 is equal to or lower than the threshold voltage Vt15L. Meanwhile, until time t6, the potential of the node SEN connected to the select cell transistor MTsel4 is equal to or higher than the threshold voltage Vt15U. Therefore, by the sense operation from time t5 to time t6, it can be determined whether the select cell transistor MTsel is the select cell transistor MTsel1, MTsel2, or MTsel3, or the select cell transistor MTsel4. That is, the transistor T15 connected to the select cell transistor MTsel with a low, relatively low, or relatively high threshold voltage is on. Therefore, it can be determined that the select cell transistor MTsel connected to the transistor T15 that is on relatively late after the start of the drop in the potential of the node SEN has a low, relatively low, or relatively high threshold voltage. The selected cell transistor MTsel that is determined to be on from time t5 to time t6 can be determined to have a threshold voltage that belongs to the range A1, A2, or A3, i.e., to be the selected cell transistor MTsel1, MTsel2, or MTsel3.

[0159] On the other hand, from time t5 to time t6, the transistor T15 connected to the select cell transistor MTsel with a high threshold voltage remains off. Therefore, the select cell transistor MTsel connected to the transistor T15 that remains off even after a relatively late stage from the start of the potential drop at the node SEN can be determined to have a high threshold voltage. The select cell transistor MTsel that remains off from time t5 to time t6 can be determined to have a threshold voltage that belongs to range A4, i.e., to be the select cell transistor MTsel4.

[0160] Determining whether the threshold voltage of the selected cell transistor MTsel belongs to the range A1, A2, or A3, or to the range A4, through the sense operation from time t5 to time t6 corresponds to the execution of a VH sense operation.

[0161] The method described with reference to FIG. 14 requires three sense operations. To reduce this number, the memory device 1 first performs a VM sense operation, and then performs a sense operation corresponding to one of a VL sense operation and a VH sense operation based on the result of the VM sense operation. An overview of the operation of the memory device 1 of the first embodiment will be described below with reference to FIG. 15. FIG. 15 shows the concept of verify in the memory device of the first embodiment. Specifically, FIG. 15 shows the potential of the node SEN over time during a certain sense operation in the memory device 1.

[0162] As shown in FIG. 15, the rate (or slope) of decrease in the potential of the node SEN connected to the select cell transistors MTsel1, MTsel2, MTsel3, and MTsel4 is the same as in the case of FIG. 14. The node SEN connected to the select cell transistor MTsel3 or MTsel4 has a potential VSEN1 at the start of the sense operation. On the other hand, the node SEN connected to the select cell transistor MTsel1 or MTsel2 has a potential VSEN2 at the start of the same sense operation. The potential VSEN2 is higher than the potential VSEN1. The potential VSEN2 is determined to satisfy the following condition. That is, the use of the potential VSEN2 changes the position of the line indicating the potential of the node SEN in the case of the select cell transistors MTsel1 and MTsel2. The potential VSEN2 is determined so that, based on the changed positions, a period occurs during which the potentials of the nodes SEN connected to the selected cell transistors MTsel1 and MTsel3 are less than the threshold voltage Vt15u and the potentials of the nodes SEN connected to the selected cell transistors MTsel2 and MTsel4 are equal to or greater than the threshold voltage Vt15u. In the example of Figure 15, such a period corresponds to the period from time t7 to time t8. Time t7 occurs after time t5, and time t8 occurs after time t7 and before time t6.

[0163] 15, after time t5, the potential of the node SEN connected to the selected cell transistor MTsel3 is less than the threshold voltage Vt15L. Until time t6, the potential of the node SEN connected to the selected cell transistor MTsel4 is equal to or greater than the threshold voltage Vt15U. Therefore, by the sense operation from time t5 to time t6, it can be determined whether the selected cell transistor MTsel is the selected cell transistor MTsel3 or the selected cell transistor MTsel4.

[0164] After time t7, the potential of the node SEN connected to the selected cell transistor MTsel1 is less than the threshold voltage Vt15L. Until time t8, the potential of the node SEN connected to the selected cell transistor MTsel2 is equal to or greater than the threshold voltage Vt15U. Therefore, by the sense operation from time t7 to time t8, it can be determined whether the selected cell transistor MTsel is the selected cell transistor MTsel1 or the selected cell transistor MTsel2.

[0165] In other words, the sense operation from time t7 to time t8 can concurrently determine whether the selected cell transistor MTsel with a threshold voltage less than VM is the selected cell transistor MTsel1 or MTsel2 (corresponding to a VL sense operation) and whether the selected cell transistor MTsel with a threshold voltage equal to or greater than VM is the selected cell transistor MTsel3 or MTsel4 (corresponding to a VH sense operation).

[0166] FIG. 16 shows the potentials of several nodes and signals over time during verification of the memory device of the first embodiment.

[0167] 16, the nodes and signals have the following potentials or levels: The selected word line WLsel, node VHLB, and node CLKSA have the potential VSS. The signals NPC, SPC, XXL, and STB have a low (“L”) level. The nodes INVA and INVB have a low level, i.e., the latch circuits ADL and BDL hold “0” data.

[0168] The low-level signal NPC turns off the transistor T10, and the node CLKSA has the potential VSS, so the node SEN has the potential VSS, which has the same magnitude as the ground voltage VSS.

[0169] At time t11, the potential of the selected word line WLsel is set to potential VH. The potential VH has the same magnitude as voltage VH and depends on the target state of the verify operation that generates the waveform of Figure 16. In one example, when the target state is the "S2" state, the potential VH has the magnitude of voltage Vp2.

[0170] At time t12, the potential of node VHLB is set to potential VSEN1. At time t12, signals NPC and SPC are set to high level. As a result, the potential of node VHLB is applied to node SEN via transistors T9 and T10, which are turned on, and node SEN has the potential VSEN1.

[0171] At time t13, the potential of the node VHLB is set to the potential VSS, and the signals NPC and SPC are set to the low level, thereby stopping the application of voltage from the node VHLB to the node SEN.

[0172] At time t13, the potential of the node CLKSA is set to the potential VCK1, so that the potential of the node SEN rises by the magnitude of the potential VCK1 due to coupling by the capacitor P1.

[0173] At time t14, signal XXL is set to high level, which turns on transistor T5. Also, although not shown, signals BLS and BLC are set to high level, which turns on transistors T3 and T4. Node SEN is connected to one bit line BL via transistors T3, T4, and T5, which are on. Therefore, the potential of node SEN decreases at a rate based on the threshold voltage of the selected cell transistor MTsel connected via the bit line BL.

[0174] When the node SEN is connected to the selected cell transistor MTsel that is turned off, the potential of the node SEN gradually decreases as shown by the dashed line. Hereinafter, the selected cell transistor MTsel that is turned off may be referred to as an off cell.

[0175] On the other hand, when the node SEN is connected to the selected cell transistor MTsel that is on, the potential of the node SEN drops rapidly as shown by the solid line. Hereinafter, the selected cell transistor MTsel that is on may be referred to as the on cell.

[0176] At time t15, the potential of the node CLKSA is set to the potential VSS, which causes the potential of the node SEN to drop by the magnitude of the potential VCK1.

[0177] At time t15, signal XXL is set to low level. This disconnects node SEN from bit line BL and causes it to electrically float. As a result, the decrease in the potential of node SEN that began at time t14 stops, and the potential of node SEN at time t15 is stored at node SEN. The period during which signal XXL is at high level determines the time during which the decrease in the potential of node SEN continues.

[0178] At time t16, signal STB is set to high level. This starts the first sensing operation. At time t17, signal ATI (not shown) is set to high level, and data based on the potential of node SEN is transferred to latch circuit ADL and stored in latch circuit ADL. That is, node INVA has a level based on the potential of node SEN. Specifically, when node SEN is connected to an off-cell, node INVA has a low level. When node SEN is connected to an on-cell, node INVA has a high level. The data in latch circuit ADL indicates the result of the VM sensing operation.

[0179] At time t18, signal STB is set to low level, thereby completing the first sensing operation. At time t18, signal ATI (not shown) is set to low level, thereby completing the transfer of data based on the potential of node SEN to latch circuit ADL. The first sensing operation from time t16 to time t18 corresponds to a VM sensing operation.

[0180] 17 shows an example of data stored in the latch circuit during verification in the memory device of the first embodiment. Specifically, FIG. 17 shows data stored in the latch circuit ADL at time t18 (the end of the VM sense operation). As shown in FIG. 17, the latch circuit ADL storing data based on the node SEN connected to the ON cell stores data "0" (low level). The selected cell transistor MTsel connected to the latch circuit ADL storing data "0" is determined to have a threshold voltage belonging to range A1 or A2.

[0181] On the other hand, the latch circuit ADL that stores data based on the node SEN connected to the off-cell stores data “1” (high level). The selected cell transistor MTsel connected to the latch circuit ADL that stores data “1” is determined to have a threshold voltage that belongs to the range A3 or A4.

[0182] Returning to Fig. 16, at time t19, the node SEN is set to the potential VSS.

[0183] At time t20, node VHLB is set to potential VSEN1, and signals NPC and SPC are set to high levels. The state of a portion of the sense amplifier circuit SAC at this time is shown in FIG. 18. FIG. 18 shows one state of a portion of the sense amplifier circuit of the memory device of the first embodiment. As shown in part (a) of FIG. 18, when node LATA of the sense amplifier circuit SAC has a low level based on the result of the VM sensing operation, transistor T2 is turned on. Therefore, a current path is formed between node VHLB and transistor T10 via transistor T2. On the other hand, as shown in part (b) of FIG. 18, when node LATA of the sense amplifier circuit SAC has a high level based on the result of the VM sensing operation, transistor T2 is turned off. Therefore, a current path is not formed between node VHLB and transistor T10 via transistor T2. However, transistor T9 is turned on by the high-level signal SPC. Therefore, a current path is formed between node VHLB and transistor T10 via transistor T9. Therefore, regardless of the result of the VM sensing operation, i.e., whether the transistor T2 is on or off, the node VHLB is connected to the node SEN, and the node SEN has the potential VSEN1.

[0184] Returning to FIG. 16, at time t21, the potential of node VHLB is set to potential VSEN2, and signal SPC is set to low level. The state of a portion of sense amplifier circuit SAC at this time is shown in FIG. 19. FIG. 19 shows one state of a portion of the sense amplifier circuit of the memory device of the first embodiment. As shown in FIG. 19, transistor T9 is turned off by the low-level signal SPC. Therefore, no current path is formed between node VHLB and transistor T10 via transistor T9.

[0185] 19A, when the node LATA of the sense amplifier circuit SAC has a low level based on the result of the VM sensing operation, the transistor T2 is on. Therefore, a current path is formed between the node VHLB and the transistor T10 through the transistor T2. Therefore, the node SEN has a potential VSEN2.

[0186] On the other hand, as shown in part (b) of Figure 19, when node LATA of sense amplifier circuit SAC has a high level based on the result of the VM sensing operation, transistor T2 is turned off. Therefore, no current path is formed between node VHLB and transistor T10, and the potential of node VHLB is not transferred to node SEN. Therefore, node SEN has a potential VSEN1.

[0187] 16, at time t22, the potential of the node VHLB is set to the potential VSS, and the signal NPC is set to low level, thereby stopping the application of voltage from the node VHLB to the node SEN.

[0188] At time t22, the potential of the node CLKSA is set to the potential VCK1, and therefore, due to coupling by the capacitor P1, the potential of the node SEN rises by the magnitude of the potential VCK1.

[0189] At time t23, signal XXL is set to high level. This turns on transistor T5. Although not shown, signals BLS and BLC are also set to high level. This turns on transistors T3 and T4. Node SEN is connected to one bit line BL via transistors T3, T4, and T5, which are on. Therefore, the potential of node SEN decreases at a rate based on the threshold voltage of the selected cell transistor MTsel connected via the bit line BL.

[0190] When node SEN has potential VSEN1 at time t23 and is connected to an ON cell, the change in potential of node SEN is the same as the change from time t14, as shown by the solid line. When node SEN has potential VSEN1 at time t23 and is connected to an OFF cell, the change in potential of node SEN is the same as the change from time t14, as shown by the dashed-dotted line.

[0191] When node SEN has potential VSEN2 at time t23 and is connected to an ON cell, the potential of node SEN decreases slowly as shown by the dashed line. When node SEN has potential VSEN2 at time t23 and is connected to an OFF cell, the potential of node SEN decreases rapidly as shown by the two-dot chain line.

[0192] 16, to avoid unnecessary complication, the potential of node SEN, which has potential VSEN1 at time t23 and is connected to the on cell, is drawn to be the same as the potential of node SEN, which has potential VSEN2 at time t23 and is connected to the on cell, at time t24. Similarly, the potential of node SEN, which has potential VSEN1 at time t23 and is connected to the off cell, is drawn to be the same as the potential of node SEN, which has potential VSEN2 at time t23 and is connected to the off cell, at time t24.

[0193] At time t24, the potential of the node CLKSA is set to the potential VSS, which causes the potential of the node SEN to drop by the magnitude of the potential VCK1.

[0194] At time t24, the signal XXL is set to low level. This disconnects the node SEN from the bit line BL and electrically floats. As a result, the decrease in the potential of the node SEN that began at time t23 stops, and the potential of the node SEN at time t24 is stored at the node SEN. The signal XXL maintains high level from time t22 to time t24. The high-level period of the signal XXL determines the time during which the decrease in the potential of the node SEN continues. Based on the example of FIG. 16, the high-level period of the signal XXL for the second sensing operation (from time t22 to time t24) is longer than the high-level period of the signal XXL for the first sensing operation (from time t13 to time t15).

[0195] At time t25, signal STB is set to high level, which starts the second sensing operation. At time t26, signal BTI (not shown) is set to high level, which causes data based on the potential of node SEN to be transferred to latch circuit BDL and stored in latch circuit BDL. That is, node INVB has a level based on the potential of node SEN. Specifically, when node SEN is connected to an off-cell, node INVB has a low level. When node SEN is connected to an on-cell, node INVB has a high level.

[0196] At time t27, signal STB is set to low level, thereby ending the second sensing operation. At time t27, signal BTI (not shown) is set to low level, thereby ending the transfer of data based on the potential of node SEN to latch circuit BDL. The second sensing operation from time t25 to time t27 corresponds to the VL sensing operation and VH sensing operation.

[0197] FIG. 20 shows an example of data in the latch circuit during verification in the memory device of the first embodiment. Specifically, FIG. 20 shows the data stored in the latch circuit BDL at time t27 (the end of the VL sense operation and the VH sense operation). FIG. 20 illustrates the case of an ON cell during the VM sense operation, i.e., the case where the latch circuit ADL stores data "0." As shown in FIG. 20, the latch circuit BDL, which stores data based on the node SEN connected to the ON cell, stores data "0." The selected cell transistor MTsel, which is connected to the node SEN that causes the latch circuit BDL to store data "0," is determined to have a threshold voltage belonging to the range A1.

[0198] On the other hand, the latch circuit BDL, which stores data based on the node SEN connected to the off-cell, stores data “1.” The selected cell transistor MTsel, which is connected to the node SEN that causes the latch circuit BDL to store data “1,” is determined to have a threshold voltage that belongs to range A2.

[0199] FIG. 21 shows an example of data in the latch circuit during verification in the memory device of the first embodiment. Specifically, FIG. 21 shows the data stored in the latch circuit BDL at time t27 (the end of the VL sense operation and the VH sense operation). FIG. 21 illustrates the case of an off cell during VM sense operation, i.e., the case where the latch circuit ADL stores data "1." As shown in FIG. 21, the latch circuit BDL, which stores data based on the node SEN connected to the on cell, stores data "0." The selected cell transistor MTsel, which is connected to the node SEN that causes the latch circuit BDL to store data "0," is determined to have a threshold voltage belonging to range A3.

[0200] On the other hand, the latch circuit BDL, which stores data based on the node SEN connected to the off-cell, stores data “1.” The selected cell transistor MTsel, which is connected to the node SEN that causes the latch circuit BDL to store data “1,” is determined to have a threshold voltage that belongs to range A4.

[0201] 16, at time t28, the node SEN is applied with the ground voltage VSS, and at time t29, the potential of the selected word line WLsel is set to the potential VSS.

[0202] 1.3.Advantages (Effects) According to the first embodiment, the storage device 1 can operate at high speed, as described below.

[0203] The memory device 1 performs a VM sense operation on each of a plurality of selected cell transistors MTsel while a verify voltage VH (Vp) based on a target state is applied to the selected word line WLsel. The VM sense operation provides information on whether the selected cell transistor MTsel has a threshold voltage lower than or higher than a certain voltage based on the target state, i.e., whether the selected cell transistor MTsel belongs to range A1, A2, or range A3, or A4. The memory device 1 applies a voltage to node SEN connected to selected cell transistors MTsel determined to belong to range A1 or A2 that is higher than the voltage applied to node SEN connected to selected cell transistors MTsel determined to belong to range A3 or A4. This creates a period during which the potential of node SEN of selected cell transistors MTsel determined to belong to range A1 or A2 overlaps with the potential of node SEN of selected cell transistors MTsel determined to belong to range A1 or A2. A sense operation is then performed during this overlap period. The sense operation performed on the selected cell transistor MTsel determined to belong to range A1 or A2 during the overlap period corresponds to the VL sense operation. The sense operation performed on the selected cell transistor MTsel determined to belong to range A3 or A4 during the overlap period corresponds to the VH sense operation. Therefore, the VL sense operation and the VH sense operation can be performed in parallel. Therefore, the VL sense operation, the VM sense operation, and the VH sense operation are completed in two sense periods. This allows the verify to be completed in a short time, i.e., high-speed operation is possible.

[0204] 1.4. Variations FIG. 22 shows the potentials of several nodes and signals over time during verification of the memory device of the modified example of the first embodiment.

[0205] 22, the potential of node CLKSA may be increased, thereby increasing the potential of node SEN to potential VSEN2. That is, from time t22 to time t24, the potential of node VHLB is set to potential VSEN3, while the potential of node CLKSA is set to potential VCK2. Potential VSEN3 is lower than potential VSEN2. Potential VCK2 is higher than potential VCK1. In this way, the lower potential of node VHLB is compensated for by the potential of node CLKSA.

[0206] 2. Second embodiment Fig. 23 is a circuit diagram of a sense amplifier circuit of a memory device according to Embodiment 2. As shown in Fig. 23, the sense amplifier circuit SAC does not include transistors T2 and T9, but includes transistors T31 and T32.

[0207] Transistor T10 is connected between node VHLB and node SEN. Transistors T31 and T32 are connected in parallel between node CLKSA and node N3. Capacitor P1 is connected between node SEN and node N3.

[0208] FIG. 24 shows the potentials of several nodes and signals over time during verification of the memory device of the second embodiment.

[0209] 24, the signal SPC is at a high level from time t13 to time t15. Therefore, a current path is formed between the node CLKSA and the capacitor P1, and the potential of the node CLKSA increases, causing the potential of the node SEN to increase.

[0210] After time t20, the operation at time t21 in the first embodiment does not occur. That is, from time t20 to time t22, the potential of the node VHLB is set to the potential VSEN1.

[0211] From time t22 to time t24, the signal SPC is at a low level, so the transistor T32 is off and no current path is formed between the node CLKSA and the node N3 via the transistor T32.

[0212] As in the first embodiment, at time t22, the potential of node CLKSA is set to potential VCK1. Between time t14 and time t15, node INVA of the sense amplifier circuit SAC connected to the off-cell is at low level. Therefore, node LATA is at high level, and therefore, at time t22, transistor T31 of the sense amplifier circuit SAC connected to the off-cell is off. Therefore, no current path is formed between node CLKSA and node N2. Therefore, the potential of node SEN connected to the off-cell during VM sensing operation does not rise at time t22.

[0213] Meanwhile, node INVA of the sense amplifier circuit SAC connected to the ON cell between time t14 and time t15 is at a high level. Therefore, node LATA is at a low level, and therefore, at time t22, transistor T31 of the sense amplifier circuit SAC connected to the ON cell is on. Therefore, a current path is formed between node CLKSA and node N2. Therefore, the potential of node SEN connected to the ON cell during VM sensing operation rises to potential VSEN4 at time t22.

[0214] In this way, at time t22, the potential of node SEN connected to the off-cell during VM sensing operation rises, while the potential of node SEN connected to the on-cell during VM sensing operation does not rise. Therefore, as in the first embodiment, VL sensing operation and VM sensing operation can be performed in parallel between time t23 and time t24.

[0215] The potential rise of node SEN due to the potential rise of node CLKSA at time t22 and the control of whether or not the potential of node SEN is raised may be used in combination. Fig. 25 shows the potentials of several nodes and signals over time during verification in the modified example of the second embodiment.

[0216] 25, the signal SPC is set to high level from time t21 to time t22, which turns on the transistor T32 and connects the node CLKSA to the capacitor P1 via the transistor T32 that is turned on.

[0217] At time t21, the potential of the node CLKSA is set to the potential VCK1, thereby causing the potential of the node SEN to rise to the potential VSEN1 regardless of the result of the VM sensing operation.

[0218] At time t22, the signal SPC is set to low level, which causes the current path between the node CLKSA and the capacitor P1 via the transistor T32 to disappear.

[0219] At time t22, the potential of node CLKSA is set to potential VCK3. Potential VCK3 is higher than potential VCK1. Node INVA of the sense amplifier circuit SAC connected to the off-cell during VM sensing operation is at low level. Therefore, node LATA is at high level, and therefore, at time t22, transistor T31 of the sense amplifier circuit SAC connected to the off-cell is off. Therefore, no current path is formed between node CLKSA and node N3. Therefore, the potential of node SEN connected to the off-cell during VM sensing operation does not rise at time t22.

[0220] Meanwhile, node INVA of the sense amplifier circuit SAC connected to the ON cell during VM sensing operation is at a high level. Therefore, node LATA is at a low level, and therefore, at time t22, transistor T31 of the sense amplifier circuit SAC connected to the ON cell is on. Therefore, a current path is formed between node CLKSA and node N3. Therefore, the potential of node SEN connected to the ON cell during VM sensing operation rises to potential VSEN5 at time t22. Potential VSEN5 is higher than potential VSEN1.

[0221] According to the second embodiment, as in the first embodiment, the potential of the node SEN connected to the selected cell transistor MTsel determined to belong to range A1 or A2 is increased based on the result of the VM sense operation. This allows the sensing period of the selected cell transistor MTsel determined to belong to range A1 or A2 to overlap with the sensing period of the selected cell transistor MTsel determined to belong to range A3 or A4. This provides the same advantages as the first embodiment.

[0222] 3. Variations In the first embodiment, the capacitor P1 may be omitted. In this case, the potential of the node SEN does not increase at time t13 and time t22, and the potential of the node SEN does not decrease at time t15 and time t24.

[0223] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0224] 1...Storage device, 2...Memory system, 4...host device, 11...Memory cell array, 12...input / output circuit, 13...Logic controller, 14...Status register, 15...Address register, 16...Command register, 17...Sequencer, 18...Driver, 19...row decoder, 20...Sense amplifier

Claims

1. A memory cell; a word line connected to the memory cell; a bit line connected to the memory cell; a first transistor having a gate connected to a first node connected to the bit line and connected to a second node; a first latch circuit connected to the second node and including a third node; a second transistor connected between the first node and a fourth node and having a gate connected to a node different from the third node; a third transistor connected between the first node and the fourth node and having a gate connected to the third node; A storage device comprising:

2. The first latch circuit a first inverter circuit having an input connected to the third node and an output connected to a fifth node; a second inverter circuit having an input connected to the fifth node and an output connected to the third node; Including, The storage device according to claim 1 .

3. the first node receives a dynamically selected one of a first voltage and a second voltage higher than the first voltage; The storage device according to claim 1 .

4. further comprising a fourth transistor connected between the first transistor and the second node; The storage device according to claim 1 .

5. further comprising a fifth transistor connected between the second transistor and the first node; The storage device according to claim 1 .

6. further comprising a capacitor connected between the first transistor and the first node; The storage device according to claim 1 .

7. A memory cell; a word line connected to the memory cell; a bit line connected to the memory cell; a sense amplifier circuit connected to the bit line, including a first node, for acquiring data based on the potential of the first node; Equipped with a first voltage is applied to the word line for a first period of time; the first period includes a second period, a third period after the second period, and a fourth period after the third period; The sense amplifier circuit during the second period, first data is acquired based on the potential of the first node; during the third period, applying one of a second voltage and a third voltage higher than the second voltage to the first node based on the first data; during the fourth period, second data is acquired based on the potential of the first node; storage device.

8. the sense amplifier circuit applies the second voltage to the first node and then applies the third voltage to the first node during the third period; The storage device according to claim 7.

9. The sense amplifier circuit If the memory cell is turned on during the second period, applying the second voltage to the first node during the third period; if the memory cell is not turned on during the second period, applying the third voltage to the first node during the third period; The storage device according to claim 8.

10. a first transistor connected between the bit line and the first node; the first transistor is turned on for a fifth period within the second period; the first transistor is turned on for a sixth period within the fourth period that is longer than the fifth period; The storage device according to claim 9.

11. a second transistor having a gate connected to the first node; a first latch circuit that stores the first data; a third transistor connected between the second transistor and the first latch circuit; Furthermore, the first period further includes a seventh period between the fifth period and the third period and an eighth period after the sixth period; the third transistor is turned on during each of the seventh period and the eighth period; The storage device of claim 10.

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