Variable capacitance circuit and oscillation circuit

Abstract

To provide a variable capacitance circuit capable of effectively changing capacitance.SOLUTION: The variable capacitance circuit (5) includes at least one capacitor (C1 to C5), at least one voltage-driven transistor (M1 to M5) whose first main electrodes are respectively connected to first ends of the capacitors, and a resistance voltage dividing circuit (3) configured to generate a gate voltage (G1 to G5) to be applied to a gate of the transistor by dividing a voltage between a variable first voltage (V1) and a variable or fixed second voltage (V2).SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to a variable capacitance circuit. [Background technology]

[0002] Conventionally, variable capacitors capable of changing capacitance have been known (for example, see patent document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2003-8032

[0004] [overview] An object of the present disclosure is to provide a variable capacitance circuit that makes it possible to effectively change the capacitance.

[0005] A variable capacitance circuit according to one aspect of the present disclosure includes: at least one capacitor; at least one voltage-driven transistor having a first main electrode connected to a first end of each of the capacitors; a resistive voltage divider circuit configured to generate a gate voltage to be applied to a gate of the transistor by dividing a first voltage that is variable and a second voltage that is variable or fixed; The configuration is provided with the following. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a diagram illustrating an example of the configuration of a crystal oscillation circuit. [Figure 2] FIG. 2 is a diagram showing a configuration of a variable capacitance circuit according to a comparative example. [Figure 3] FIG. 3 is a diagram schematically showing the relationship between the capacitance and the oscillation frequency due to switching of the switches in the variable capacitance circuit. [Figure 4]FIG. 4 is a diagram showing the configuration of the variable capacitance circuit according to the first embodiment. [Figure 5] FIG. 5 is a diagram schematically showing the relationship between the capacitance and the oscillation frequency in the variable capacitance circuit according to the first embodiment. [Figure 6] FIG. 6 is a diagram showing a specific example of a DAC in the variable capacitance circuit according to the first embodiment. [Figure 7] FIG. 7 is a diagram showing the configuration of a variable capacitance circuit according to the second embodiment. [Figure 8] FIG. 8 is a diagram showing the configuration of a variable capacitance circuit according to the third embodiment.

[0007] [Detailed explanation] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the drawings.

[0008] <Crystal oscillator circuit> FIG. 1 is a diagram illustrating an example of the configuration of a crystal oscillator circuit. The crystal oscillator circuit OSC shown in FIG. 1 includes a crystal oscillator X, an inverter IV, a feedback resistor Rf, a limiting resistor Rd, a variable capacitor Ca, and a capacitor Cb. The output terminal of the inverter IV is connected to one end of the limiting resistor Rd along with the output terminal Tout. The other end of the limiting resistor Rd is connected to one end of the crystal oscillator X along with one end of the capacitor Cb. The other end of the capacitor Cb is connected to a terminal to which ground potential is applied. The other end of the crystal oscillator X is connected to the input terminal of the inverter IV along with one end of the variable capacitor Ca. The other end of the variable capacitor Ca is connected to the ground terminal. A feedback resistor Rf is connected between the input and output of the inverter IV. With this configuration, an oscillation signal X_OSC is output from the output terminal Tout. The variable capacitor Ca is configured as a variable capacitance circuit (described later) and has a variable capacitance value. The capacitor Cb has a fixed capacitance value. By varying the capacitance value of the variable capacitor Ca, the frequency of the oscillation signal X_OSC becomes variable. Of the capacitors Ca and Cb, only Cb may be a variable capacitor, or both Ca and Cb may be variable capacitors.

[0009] Furthermore, the variable capacitance circuit described below is not limited to crystal oscillation circuits, but can also be applied to silicon oscillation circuits, LC oscillation circuits, and the like.

[0010] <Comparative Example> 2 is a diagram showing the configuration of a variable capacitance circuit 15 according to a comparative example for comparison with the present disclosure. The variable capacitance circuit 15 includes capacitors C1 to C5, switches SW1 to SW5, and a logic control unit 10.

[0011] One end of each of the capacitors C1 to C5 is commonly connected to the terminal T1. The other end of each of the capacitors C1 to C5 is connected to one end of each of the switches SW1 to SW5. The other end of each of the switches SW1 to SW5 is commonly connected to an end to which a ground potential is applied. That is, a configuration in which each of the capacitors C1 to C5 and each of the switches SW1 to SW5 are connected in series is connected in parallel between the terminal T1 and the end to which a ground potential is applied. The on / off state of each of the switches SW1 to SW5 is controlled by the logic control unit 10.

[0012] When the switches SW1 to SW5 are on, the capacitors C1 to C5 are active, and when the switches SW1 to SW5 are off, the capacitors C1 to C5 are inactive. Therefore, the capacitance can be changed by changing the number of switches SW1 to SW5 that are turned on by the logic control unit 10.

[0013] 3 is a diagram schematically showing the relationship between the capacitance C and the oscillation frequency Fosc due to switching of the switches SW1 to SW5 in the variable capacitance circuit 15 according to the comparative example. The oscillation frequency Fosc is the frequency of the oscillation signal output from the oscillation circuit. The illustration of "SW1 to SW5" in FIG. 3 indicates that the switches SW2 to SW5 are sequentially turned on from an ON state with the switches SW1 on and the switches SW2 to SW5 off. This switching causes the capacitance C to increase sequentially, and accordingly the oscillation frequency Fosc to decrease sequentially.

[0014] In this way, the oscillation frequency can be changed by changing the capacitance of variable capacitance circuit 15, making it possible to adjust the oscillation frequency according to the temperature in the oscillation circuit, for example. However, the configuration of variable capacitance circuit 15 has a problem in that a step occurs in the capacitance before and after switching of switches SW1 to SW5, and it takes time for the oscillation frequency to stabilize.

[0015] First Embodiment In view of the above problems, various embodiments described below are implemented. Fig. 4 is a diagram showing the configuration of a variable capacitance circuit 5 according to a first embodiment of the present disclosure. The variable capacitance circuit 5 includes capacitors C1 to C5, transistors M1 to M5, a first DAC (DA converter) 1, a second DAC 2, and a resistive voltage divider circuit 3.

[0016] One end of each of the capacitors C1 to C5 is commonly connected to the terminal T1. Each of the transistors M1 to M5 is configured by an N-channel MOSFET (metal-oxide-semiconductor field-effect transistor). That is, the transistors M1 to M5 are voltage-driven transistors. The other end of each of the capacitors C1 to C5 is connected to the drain of each of the transistors M1 to M5. The sources of the transistors M1 to M5 are commonly connected to a terminal to which a ground potential is applied.

[0017] The resistive voltage divider circuit 3 has resistors RA and RB and resistors R1 to R4. One end of the resistor RA is connected to an application terminal of a first voltage V1 output from the first DAC1. One end of the resistor RB is connected to an application terminal of a second voltage V2 output from the second DAC2. Resistors R1 to R4 are connected in series between the other end of the resistor RA and the other end of the resistor RB. Each of the resistors R1 to R4 is connected between the gates of each pair of transistors M1 to M5 (the pair of M1 and M2, the pair of M2 and M3, the pair of M3 and M4, and the pair of M4 and M5).

[0018] The resistive voltage divider circuit 3 divides the voltage between the first voltage V1 and the second voltage V2 using resistors RA, RB, and R1 to R4, and applies gate voltages G1 to G5 generated by the voltage division to the gates of the transistors M1 to M5, respectively. By changing the voltage difference between the voltages V1 and V2, the gate voltages G1 to G5 can be changed, and the on-state strength (i.e., on-resistance) of the transistors M1 to M5 can be changed. Therefore, the capacitance can be changed.

[0019] FIG. 5 is a diagram illustrating the relationship between the capacitance C and the oscillation frequency Fosc in the variable capacitance circuit 5 according to the first embodiment. In this embodiment, the capacitance can be smoothly changed by varying the voltage difference between voltages V1 and V2, and therefore the oscillation frequency Fosc can be smoothly changed. This shortens the time it takes for the oscillation frequency to stabilize after being changed. Furthermore, the adjustment accuracy of the oscillation frequency is improved.

[0020] 6 is a diagram showing a specific example of DACs 1 and 2 in the variable capacitance circuit 5 according to the first embodiment. The first DAC 1 shown in Fig. 6 has a constant current source 1A and a MOS transistor 1B. The second DAC 2 has a constant current source 2A and a MOS transistor 2B.

[0021] MOS transistor 1B is composed of an N-channel MOSFET. The drain of MOS transistor 1B is connected to constant current source 1A. The source of MOS transistor 1B is connected to a terminal to which ground potential is applied. The gate and drain of MOS transistor 1B are shorted. A constant current I1 is generated by constant current source 1A in accordance with the digital value, and the constant current I1 flows through MOS transistor 1B, generating a first voltage V1 at the gate of MOS transistor 1B.

[0022] The MOS transistor 2B is composed of an N-channel MOSFET. The drain of the MOS transistor 2B is connected to a constant current source 2A. The source of the MOS transistor 2B is connected to a terminal to which the ground potential is applied. The gate and drain of the MOS transistor 2B are shorted. A constant current I2 is generated by the constant current source 2A in accordance with the digital value, and the constant current I2 flows through the MOS transistor 2B, generating a second voltage V2 at the gate of the MOS transistor 2B.

[0023] To control the transistors M1 to M5 between a weakly on state and a strongly on state, precise voltage control is required near the threshold voltage Vth of the transistors M1 to M5. The threshold voltage Vth is the threshold voltage of the gate-source voltage Vgs, and is the same for all transistors M1 to M5. DAC1 and DAC2 configured as shown in Figure 6 enable precise control of the voltages V1 and V2.

[0024] The second DAC2 generates a constant current I2 that is, for example, a minute current (e.g., 0.1 μA) and generates a second voltage V2 that is just enough to turn on the MOS transistor 2B. On the other hand, the first DAC1 varies the constant current I1 from a minute current (e.g., 0.1 μA) to a large current (e.g., 150 μA), thereby varying the MOS transistor 1B from a weakly on state to a strongly on state and varying the first voltage V1.

[0025] As described above, when a minute constant current I2 flows in the second DAC2, the second voltage V2 is lower than the threshold voltage Vth. Similarly, when a minute constant current I1 flows in the first DAC1, the gate voltages G1 to G5 are all lower than the threshold voltage Vth, the transistors M1 to M5 are all in a weak on state, and the capacitance is small. When the transistors M1 to M5 are in a weak on state, the on resistance of the transistors M1 to M5 increases, which is similar to a state where the capacitance is small.

[0026] As the constant current I1 in the first DAC1 increases, the first voltage V1 rises, and the gate voltages G1 to G5 exceed the threshold voltage Vth in order from G1 to G5, increasing the capacitance. The on-state of the transistors M1 to M5 becomes stronger toward M1. In this way, by adjusting the constant current I1 in the first DAC1, it becomes possible to finely adjust the capacitance.

[0027] The constant current I2 in the second DAC 2 may be variable according to a first number of patterns, and the constant current I1 in the first DAC 1 may be adjusted while the constant current I2 is selected to a certain pattern. In this case, the second number of patterns, which is the number of patterns that the constant current I1 can take, is preferably at least twice the first number of patterns.

[0028] Second Embodiment FIG. 7 is a diagram showing the configuration of a variable capacitance circuit 50 according to a second embodiment of the present disclosure. The variable capacitance circuit 50 includes a resistive voltage divider circuit 30, but does not include a second DAC2. The resistive voltage divider circuit 30 differs from the resistive voltage divider circuit 3 in the first embodiment in that it includes a resistor RC. The resistor RC is connected between the resistor RB and the terminal to which the ground potential is applied. With this configuration, the second voltage V2 is equal to the ground potential, and the capacitance can be adjusted by adjusting the first voltage V1.

[0029] The second voltage V2 may be a fixed voltage lower than the threshold voltage Vth other than the ground potential.

[0030] <Third embodiment> FIG. 8 is a diagram showing the configuration of a variable capacitance circuit 51 according to a third embodiment of the present disclosure. The variable capacitance circuit 51 includes a resistive voltage divider circuit 31, but does not include a second DAC2. The resistive voltage divider circuit 31 differs from the resistive voltage divider circuit 3 in the first embodiment in that it includes a resistor RD. The resistor RD is connected between the resistor RB and the application terminal of the second voltage V2. The second voltage V2 is a fixed voltage higher than the threshold voltage Vth. With this configuration, the capacitance can be adjusted by adjusting the first voltage V1.

[0031] When the first voltage V1 is low, the transistor M1 of the transistors M1 to M5 is in a weaker on state, resulting in a smaller capacitance, whereas when the first voltage V1 is high, the transistors M1 to M5 are all in a stronger on state, resulting in a larger capacitance.

[0032] <Other> In addition to the above-described embodiments, various modifications can be made to the various technical features disclosed in this specification without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present disclosure should not be limited to the above-described embodiments, but should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0033] For example, the number of capacitors and transistors in the variable capacitance circuit is not limited to a plurality of capacitors and transistors, and may be one.

[0034] Furthermore, the transistor connected to the capacitor is not limited to an N-channel MOSFET, but may be configured as, for example, a P-channel MOSFET.

[0035] Furthermore, the MOS transistors in DAC1 and DAC2 are not limited to N-channel MOSFETs, but may be configured by P-channel MOSFETs, for example.

[0036] <Additional Notes> As described above, the variable capacitance circuit (5) according to one aspect of the present disclosure has: At least one capacitor (C1 to C5); at least one voltage-driven transistor (M1 to M5) having a first main electrode connected to each first end of the capacitor; The configuration includes a resistive voltage divider circuit (3) configured to generate gate voltages (G1 to G5) to be applied to the gates of the transistors by dividing the voltage between a variable first voltage (V1) and a variable or fixed second voltage (V2) (first configuration).

[0037] In the first configuration, the number of the capacitors and the number of the transistors are each plural, The resistive voltage divider circuit may be configured to have a first resistor (RA) having a first terminal connected to the application terminal of the first voltage, a second resistor (RB) having a first terminal connected to the application terminal of the second voltage, and at least one third resistor (R1 to R4) connected between the second terminal of the first resistor and the second terminal of the second resistor, and connecting the gates of the transistors (second configuration).

[0038] Furthermore, the first or second configuration may be configured to include a first DA converter (1) configured to output the first voltage (third configuration).

[0039] In addition, in the third configuration, the first DA converter may be configured to have a first constant current source (1A) configured to generate a variable first constant current (I1), and a first MOS transistor (1B) connected to the first constant current source (fourth configuration).

[0040] Furthermore, the fourth configuration may be configured to include a second DA converter (2) configured to output the second voltage (fifth configuration).

[0041] Furthermore, in the fifth configuration, the second DA converter may be configured to have a second constant current source (2A) configured to generate a variable second constant current (I2), and a second MOS transistor (2B) connected to the second constant current source (sixth configuration).

[0042] In the sixth configuration, the number of patterns in which the first constant current can be set may be at least twice the number of patterns in which the second constant current can be set (seventh configuration).

[0043] In any one of the first to seventh configurations, the second voltage may be a fixed voltage lower than a threshold voltage (Vth) of the transistor (eighth configuration).

[0044] In any one of the first to seventh configurations, the second voltage may be a fixed voltage higher than a threshold voltage (Vth) of the transistor (ninth configuration).

[0045] Moreover, an oscillator circuit (OSC) according to an aspect of the present disclosure includes a variable capacitance circuit having any one of the first to ninth configurations (tenth configuration).

[0046] The oscillator circuit of the tenth configuration may be configured as a crystal oscillator circuit (eleventh configuration). [Industrial Applicability]

[0047] The present disclosure can be used in, for example, an oscillator circuit. [Explanation of symbols]

[0048] 1 1st DAC 1A constant current source 1B MOS transistor 2 2nd DAC 2A constant current source 2B MOS transistor 3 Resistor voltage divider circuit 5 Variable capacitance circuit 10 Logic control section 15 Variable capacitance circuit 30 Resistor voltage divider circuit 31 Resistor voltage divider circuit 50 Variable capacitance circuit 51 Variable capacitance circuit Ca variable capacitor Cb capacitor C1~C5 capacitors IV Inverter M1~M5 transistors OSC Crystal oscillator circuit R1~R4 resistance RA,RB resistance Rd Limiting Resistor Rf feedback resistor SW1 to SW5 switches T1 terminal Tout output terminal X Crystal Oscillator

Claims

1. at least one capacitor; at least one voltage-driven transistor having a first main electrode connected to a first end of each of the capacitors; a resistive voltage divider circuit configured to generate a gate voltage to be applied to a gate of the transistor by dividing a voltage between a first voltage that is variable and a second voltage that is variable or fixed; A variable capacitance circuit comprising:

2. the capacitors and the transistors are each plural; The resistive voltage divider circuit is a first resistor having a first terminal connected to the first voltage application terminal; a second resistor having a first terminal connected to the second voltage application terminal; at least one third resistor connected between the second end of the first resistor and the second end of the second resistor and connecting the gates of the transistors; The variable capacitance circuit of claim 1 , wherein:

3. The variable capacitance circuit according to claim 1 , comprising a first DA converter configured to output the first voltage.

4. 4. The variable capacitance circuit according to claim 3, wherein the first DA converter comprises: a first constant current source configured to generate a variable first constant current; and a first MOS transistor connected to the first constant current source.

5. The variable capacitance circuit according to claim 4 , further comprising a second DA converter configured to output the second voltage.

6. 6. The variable capacitance circuit according to claim 5, wherein the second DA converter comprises: a second constant current source configured to generate a variable second constant current; and a second MOS transistor connected to the second constant current source.

7. 7. The variable capacitance circuit according to claim 6, wherein the number of patterns in which the first constant current can be set is at least twice the number of patterns in which the second constant current can be set.

8. The variable capacitance circuit according to claim 1 , wherein the second voltage is a fixed voltage lower than a threshold voltage of the transistor.

9. The variable capacitance circuit according to claim 1 , wherein the second voltage is a fixed voltage higher than a threshold voltage of the transistor.

10. An oscillation circuit comprising the variable capacitance circuit according to any one of claims 1 to 9.

11. 11. The oscillator circuit of claim 10 configured as a crystal oscillator circuit.

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