Semiconductor package, camera module, and camera

Abstract

To reduce transmission loss of an electric signal between components while reducing the number of connection components of a solid-state imaging element and a semiconductor element to a connection substrate, and to reduce a mounting area.SOLUTION: The semiconductor package 1 includes the solid-state imaging device 10 having the chip substrate 11 and the semiconductor device 60, the circuit substrate 20 is disposed in the outer peripheral portion of the first surface 11a which is the surface of the chip substrate 11 on the light incident side, the circuit substrate 20 has the first surface 20a which is the surface on the light incident side and the second surface 20a opposite to the first surface 20b of the circuit substrate 20, and the semiconductor device 60 is disposed on the second surface 20b of the circuit substrate 20.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor package, a camera module including the semiconductor package, and a camera including the camera module. [Background technology]

[0002] Patent Document 1 discloses a solid-state imaging device that is mounted on a camera module having a lens unit as an optical system including a plurality of lenses. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2023 / 032260 Summary of the Invention [Problem to be solved by the invention]

[0004] There is a strong demand for smaller and thinner camera modules to be installed in electronic devices such as smartphones and digital cameras.

[0005] In conventional camera modules including the device disclosed in Patent Document 1, a frame, electronic components, etc. are mounted on the upper surface (the surface on the light incident side) of a circuit board arranged around a CMOS (Complementary Metal Oxide Semiconductor) image sensor (CIS), which is a solid-state imaging element, so there is almost no area available for mounting semiconductor elements such as an ISP (Image Signal Processor) or semiconductor memory. Therefore, conventional camera modules have a structure in which the solid-state imaging element and the semiconductor element are separately mounted on a mounting board (motherboard).

[0006] However, the conventional structure requires a flexible board or connector to connect the mounting board and the solid-state imaging element, which increases the number of components in the camera and the mounting area, resulting in increased costs. Furthermore, the conventional structure also poses the problem of the long distance between the components, which can result in transmission loss of electrical signals.

[0007] The present invention has been made in consideration of the above-mentioned problems, and specifically aims to provide a semiconductor package, a camera module, and a camera that can reduce the number of connecting parts for solid-state imaging elements and semiconductor elements to a connecting board, while reducing transmission loss of electrical signals between parts and reducing the mounting area. [Means for solving the problem]

[0008] The above object can be achieved by any one of the following means (1) to (20).

[0009] (1) A semiconductor package including a solid-state imaging element having a chip substrate and a semiconductor element, wherein a circuit board is disposed on the outer periphery of a first surface of the chip substrate, which is the surface on which light is incident, and the circuit board has the first surface, which is the surface on which the light is incident, and a second surface opposite to the first surface of the circuit board, and the semiconductor element is disposed on the second surface of the circuit board.

[0010] (2) The semiconductor package according to (1), wherein a light-transmitting protective member is disposed on the first surface of the circuit board so as to cover at least the light-receiving region of the solid-state imaging element.

[0011] (3) A semiconductor package as described in (1) or (2) above, wherein the solid-state imaging element has a first connection terminal formed on the first surface of the chip substrate for electrically connecting to the circuit board, and an annular sealing portion is formed outside the first connection terminal on the first surface of the chip substrate so as to surround the first connection terminal and the light receiving area of ​​the solid-state imaging element.

[0012] (4) A semiconductor package according to any one of (1) to (3) above, wherein a second connection terminal for electrically connecting to the circuit board is formed on the first surface of the semiconductor element, and a sealing resin layer is formed to cover the side surface of the semiconductor element and the second connection terminal.

[0013] (5) A semiconductor package described in any one of (1) to (4) above, wherein a plurality of semiconductor elements having different chip heights are arranged on the second surface of the circuit board, and an encapsulating resin layer is formed on the second surface of at least one of the plurality of semiconductor elements.

[0014] (6) The semiconductor package according to (5) above, wherein the difference in chip height among the plurality of semiconductor elements is 200 μm or less.

[0015] (7) A semiconductor package according to any one of (1) to (4) above, wherein a plurality of semiconductor elements having approximately the same chip height are arranged on the second surface of the circuit board, and the second surface of at least one of the plurality of semiconductor elements has a ground surface.

[0016] (8) A semiconductor package according to any one of (1) to (7) above, wherein a third connection terminal electrically connected to the solid-state imaging element is formed on the first surface of the circuit board, and the solid-state imaging element is electrically connected to the third connection terminal by wire bonding.

[0017] (9) A semiconductor package according to any one of (1) to (7) above, wherein a first connection terminal for electrically connecting to the circuit board is formed on the first surface of the solid-state imaging element, and a second connection terminal for electrically connecting to the circuit board is formed on the first surface of the semiconductor element, the first connection terminal being connected to the inside of the second surface of the circuit board, and the second connection terminal being connected to the outside of the second surface of the circuit board.

[0018] (10) The semiconductor package according to any one of (1) to (9) above, wherein the semiconductor element is one or more elements selected from a semiconductor memory, an ISP, and a GPU.

[0019] (11) The semiconductor package described in (2) above, wherein the solid-state imaging element has an on-chip lens arranged in the light receiving region, and the distance between the surface of the on-chip lens and the second surface of the protective member is 0.6 mm or more.

[0020] (12) The semiconductor package according to any one of (1) to (11) above, wherein the circuit board has a linear expansion coefficient of 6 ppm / °C or less.

[0021] (13) The semiconductor package according to (2) above, wherein a fourth connection terminal for electrical connection to a mounting board is formed on the outer side of the protective member.

[0022] (14) The semiconductor package according to (13) above, wherein the difference in linear expansion coefficient between the circuit board and the mounting board is 4 ppm / °C or less.

[0023] (15) A camera module comprising: a semiconductor package according to any one of claims 1 to 14; and an optical unit including a lens unit, wherein the semiconductor package is disposed below the lens unit.

[0024] (16) The camera module according to (15) above, wherein the size of the optical unit is set appropriately according to the specifications of the protective member and / or the mounting board.

[0025] (17) The camera module according to (15) or (16), wherein the optical unit has a widthwise length that is shorter than the widthwise length of the circuit board.

[0026] (18) A camera comprising a camera module according to any one of (15) to (17) above and a heat sink, wherein the solid-state imaging element and the semiconductor element mounted in the semiconductor package of the camera module are thermally connected to the heat sink via a thermally conductive adhesive layer.

[0027] (19) The camera according to (18) above, wherein the heat sink is made of a heat sink material having a thermal conductivity of 150 W / mK or more.

[0028] (20) The camera according to (18) or (19) above, wherein the adhesive layer has a thermal conductivity of 3 W / mK or more. [Effects of the Invention]

[0029] According to the present invention, the number of connecting parts for connecting a solid-state imaging device or semiconductor device to a connecting board such as a mounting board can be reduced, while the transmission loss of electrical signals between the parts can be reduced and the mounting area can be reduced. [Brief explanation of the drawings]

[0030] [Figure 1] 1 is a partially enlarged cross-sectional view of a camera having a semiconductor package and a camera module according to an embodiment of the present invention. [Figure 2] 1 is a schematic perspective view of a solid-state imaging element viewed from a first surface side. [Figure 3A] FIG. 1 is a diagram showing step 1 of the method for manufacturing a semiconductor package. [Figure 3B] FIG. 10 is a diagram showing step 2 of the method for manufacturing a semiconductor package. [Figure 3C] FIG. 10 is a diagram showing step 3 of the method for manufacturing a semiconductor package. [Figure 3D] FIG. 10 is a diagram showing step 4 of the method for manufacturing a semiconductor package. [Figure 3E] FIG. 10 is a diagram showing step 5 of the method for manufacturing a semiconductor package. [Figure 3F] FIG. 10 is a diagram showing step 6 of the semiconductor package manufacturing method. [Figure 3G] FIG. 10 is a diagram showing step 7 of the semiconductor package manufacturing method. [Figure 3H] FIG. 10 is a diagram showing step 8 of the semiconductor package manufacturing method. [Figure 4] FIG. 10 is a partially enlarged cross-sectional view of a camera having a semiconductor package and a camera module according to a first modified example. [Figure 5]FIG. 11 is a partially enlarged cross-sectional view of a camera having a semiconductor package and a camera module according to a second modified example. DETAILED DESCRIPTION OF THE INVENTION

[0031] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following drawings, the same reference numerals refer to the same components, and the size of each component in the drawings may be exaggerated for clarity and convenience. Meanwhile, the embodiments described below are merely examples, and various modifications are possible from such embodiments.

[0032] Hereinafter, the terms "upper" and "above" may include not only what is directly above in contact with something, but also what is above without contact. Similarly, the terms "lower" and "below" may include not only what is directly below in contact with something, but also what is below without contact.

[0033] The singular expression includes the plural expression unless the context clearly dictates otherwise. Furthermore, when a part "includes," "comprises," or "has" a certain element, it does not mean that it excludes other elements, but that it may further include other elements, unless otherwise specified to the contrary.

[0034] Unless explicitly stated or stated to the contrary, steps constituting a method may be performed in any suitable order, and are not necessarily limited to the order of the steps described. The use of any examples or exemplary terms is merely for the purpose of illustrating the technical idea, and the scope of the invention is not limited by the examples or exemplary terms, except as limited by the scope of the claims.

[0035] In the following description, when ordinal numbers such as "first" and "second" are used, unless otherwise specified, they are used for convenience and do not stipulate any particular order.

[0036] The semiconductor module 100, camera module 200, and camera 300 according to this embodiment will be described.

[0037] As shown in Fig. 1, camera 300 includes camera module 200. Camera module 200 includes semiconductor package 100. Camera 300 can be installed as an imaging unit in various electronic devices, including mobile terminals such as smartphones and tablet terminals, and imaging devices such as digital still cameras and video cameras. In camera 300, incident light L received is incident on solid-state imaging element 10 of semiconductor package 100 through optical unit 230.

[0038] As shown in FIG. 1, the semiconductor package 100 is a package including a solid-state imaging element 10 consisting of a CMOS image sensor, a circuit board 20, a protective member 30, an annular sealing portion 40, an electronic component 50, a semiconductor element 60, and a sealing resin layer 70.

[0039] The solid-state imaging device 10 has a chip substrate 11 made of silicon or the like. An IC circuit pattern or the like is formed on a first surface 11a of the chip substrate 11, and the chip substrate 11 converts received light into an electrical signal and outputs the signal as a pixel signal. The solid-state imaging device 10 has a light-receiving region R in which a plurality of pixels that convert incident light into an electrical signal are arranged in rows and columns, and can be configured as a CMOS image sensor that is equipped with on-chip lenses (microlenses) 12 as well as color filters, photodiodes, pixel circuits, and the like (not shown). As shown in FIG. 2, the light-receiving region R can correspond to the formation region (dot-hatched portion) of the on-chip lenses 12, for example.

[0040] The chip substrate 11 has a first surface 11a, which is the surface on the side where light is incident, and a second surface 11b, which is the surface inside the substrate opposite the first surface 11a. In Fig. 1, the first surface 11a of the chip substrate 11 is the upper surface of the chip substrate 11, and the second surface 11b is the lower surface of the chip substrate 11. The solid-state imaging element 10 is disposed inside the second surface 20b of the circuit board 20 so as to be electrically connected to the wiring 21 through the first connection terminal 13 formed on the first surface 11a of the chip substrate 11.

[0041] First connection terminals 13 made of solder bumps or the like that are electrically connected to the circuit board 20 are formed on the first surface 11a of the chip substrate 11 outside the light receiving region R (outside the on-chip lens 12). The solid-state imaging element 10 is disposed on the second surface 20b of the circuit board 20, inside the semiconductor element 60, so as to be electrically connected to the circuit board 20 through the first connection terminals 13. In other words, the first connection terminals 13 are connected to the inside of the second surface 20b of the circuit board 20.

[0042] In the solid-state imaging device 10, an annular sealing portion 40 is formed so as to surround the on-chip lens 12 and the first connection terminal 13 arranged in the light receiving region R on the chip substrate 11 (see FIG. 2).

[0043] The first connection terminals 13 and the annular sealing portion 40 may be formed on the outer peripheral portion 14 of the first surface 11a of the chip substrate 11. The outer peripheral portion 14 is a certain area that is outside the light receiving region R of the first surface 11a of the chip substrate 11 and is inward from the outer periphery of the first surface 11a.

[0044] The height of the solid-state imaging element 10 can be adjusted by grinding the second surface 11b of the chip substrate 11 so that the chip height, which is the length in the thickness direction of the semiconductor element 60, is approximately equal. Note that "approximately equal" includes a form in which there is no difference in chip height (difference in distance to the heat sink 320) with the semiconductor element 60 being compared, and the height is completely the same, and a form in which the difference in chip height (difference in distance to the heat sink 320) is 200 μm or less, which is a thickness that allows the adhesive layer 330 to absorb height variations.

[0045] The circuit board 20 is composed of an interposer board (relay board) and electrically connects the solid-state imaging element 10, electronic components 50, semiconductor element 60, etc. through wiring 21 formed within the board. The circuit board 20 is formed in the shape of a rectangular frame having a window 23 in the center so that light can enter the light-receiving region R of the solid-state imaging element 10. The circuit board 20 is arranged so as to cover the outer peripheral portion 14 of the solid-state imaging element 10.

[0046] The circuit board 20 has a first surface 20a, which is the surface on the side where light is incident, and a second surface 20b, which is the surface inside the board opposite to the first surface 20a. In Fig. 1, the first surface 20a of the circuit board 20 is the upper surface of the circuit board 20, and the second surface 20b is the lower surface of the circuit board 20.

[0047] From the viewpoint of improving stress relaxation due to temperature changes, it is preferable to appropriately select a resin for the circuit board 20 so that the linear expansion coefficient is 6 ppm / °C or less. The protective member 30 mounted on the circuit board 20 is made of, for example, borosilicate glass (7 ppm / °C) or blue glass with IR-cutting properties (7 ppm / °C to 8 ppm / °C). Meanwhile, the solid-state imaging element 10 mounted on the circuit board 20 uses silicon (4 ppm / °C) as the material for the chip substrate 11. Because the linear expansion coefficients of the solid-state imaging element 10 and the protective member 30 differ, there is a risk of warping of the circuit board 20 due to heat generation when the camera is turned on, etc. In contrast, the circuit board 20 of this embodiment has a linear expansion coefficient of 6 ppm / °C or less, which is between the linear expansion coefficients of the solid-state imaging element 10 and the protective member 30. Therefore, the influence of the difference in the linear expansion coefficients between the solid-state imaging element 10 and the protective member 30 can be mitigated, thereby suppressing warping of the circuit board 20.

[0048] The circuit board 20 has a metal connection portion 22 for fixing the annular sealing portion 40. The connection portion 22 may simply function to fix the annular sealing portion 40, or may function as an electrode for electrical connection with other components.

[0049] The protective member 30 is made of a transparent material having optical transparency, such as a glass material or a resin material such as polyimide. The protective member 30 can be made of IR-cut protective glass (borosilicate glass, blue glass, etc.) or an IR-cut filter. The planar size of the protective member 30 is equal to or larger than the planar size of the light-receiving region R of the chip substrate 11.

[0050] The protective member 30 has a first surface 30a, which is the surface on the side where light is incident, and a second surface 30b, which is the surface opposite the first surface 30a within the protective member 30. In FIG. 1 , the first surface 30a of the protective member 30 is the upper surface of the protective member 30, and the second surface 30b is the lower surface of the protective member 30. Light that has passed through the protective member 30 passes through the window 23 of the circuit board 20 and is incident on the light-receiving region R of the solid-state imaging element 10.

[0051] As shown in FIG. 1, the protective member 30 is joined by a joining portion 31 made of a sealant (DAM agent) or the like formed around the second surface 30b with the second surface 30b facing the window portion 23 of the circuit board 20.

[0052] The distance A1 from the surface of the on-chip lens 12 of the solid-state imaging element 10 to the second surface 30b of the protective member 30 is preferably 0.6 mm or more. This allows the semiconductor package 100 to attenuate the flare component that is reflected by the protective member 30 arranged above the solid-state imaging element 10 and then enters the solid-state imaging element 10 again.

[0053] As shown in Fig. 2, the annular sealing portion 40 is formed on the first surface 11a of the chip substrate 11 so as to surround the on-chip lens 12 and the first connection terminal 13 that are arranged in the light-receiving region R on the chip substrate 11. The annular sealing portion 40 can be formed by solder on the outer peripheral portion 14 of the first surface 11a. As shown in Fig. 1, the semiconductor package 100 has a sealed space S that is hermetically sealed by the protective member 30 that is arranged on the upper side via the circuit board 20 and the annular sealing portion 40 that is formed on the lower side. The on-chip lens 12, the first connection terminal 13, etc. are hermetically sealed within the sealed space S.

[0054] The annular sealing portion 40 can be formed using a known solder forming method simultaneously with the process of forming the first connection terminals 13 on the chip substrate 11. One example of a forming method for the annular sealing portion 40 is to apply a photosensitive insulating layer such as epoxy resin to the first surface 11a of the chip substrate 11, remove unnecessary portions of the insulating layer using a known photolithography method, and form a metal barrier layer using a known film formation process such as sputtering. Subsequently, the area other than the positions where the first connection terminals 13 and the annular sealing portion 40 are to be formed is covered with resist, solder is formed, and a plating process (Cu / Sn / Ag) is performed, and the unnecessary metal barrier layer and resist are removed. The chip substrate 11 is completed by removing the metal barrier layer and resist. Furthermore, the thickness of the solid-state imaging device 10 on which the first connection terminals 13 and the annular sealing portion 40 are formed can also be adjusted by grinding at least a portion of the second surface 11b of the chip substrate 11 using a grinding process. When the thickness of the second surface 11b of the chip substrate 11 is adjusted by a grinding process or the like, the second surface 11b has a ground surface at the ground location.

[0055] The electronic components 50 are passive elements such as resistors and capacitors, and constitute peripheral circuits of the semiconductor package 100 and the camera module 200. The electronic components 50 are mounted on the first surface 20a of the circuit board 20, and are electrically connected to the solid-state imaging element 10 and the semiconductor element 60 through wiring 21.

[0056] The semiconductor element 60 is a semiconductor component other than the solid-state imaging element 10 in the semiconductor package 100. The semiconductor element 60 can be one or more elements selected from a semiconductor memory, an ISP, a GPU (Graphics Processing Unit), and the like.

[0057] The semiconductor element 60 has a first surface 60a which is the surface on the side where light is incident, and a second surface 60b which is the surface inside the semiconductor element 60 opposite to the first surface 60a. In FIG. 1 , the first surface 60a of the semiconductor element 60 is the upper surface of the semiconductor element 60, and the second surface 60b is the lower surface of the semiconductor element 60. The semiconductor element 60 is disposed on the second surface 20b of the circuit board 20 outside the solid-state imaging element 10 so as to be electrically connected to the wiring 21 through second connection terminals 61 formed on the first surface 60a. In other words, the second connection terminals 61 are connected to the outside of the second surface 20b of the circuit board 20.

[0058] When multiple semiconductor elements 60 with different chip heights are mounted on circuit board 20, the difference in chip height between the elements is preferably 200 μm or less. This allows the adhesive layer 330 to absorb the height differences between the semiconductor elements 60 of semiconductor package 100 when camera module 200 is placed on heat sink 320 of camera 300. Note that the height of multiple semiconductor elements 60 mounted on circuit board 20 can be adjusted by grinding at least a portion of second surface 60b of at least one semiconductor element 60 so that the chip heights of the elements are approximately equal.

[0059] The sealing resin layer 70 is made of an insulating thermosetting resin such as epoxy resin, and is formed so as to cover the side surface 62 of the semiconductor element 60 and the second connection terminals 61 .

[0060] From the viewpoint of suppressing deformation of the semiconductor element 60 due to temperature changes (such as warpage of the element surface), it is preferable to appropriately select the resin used for the encapsulating resin layer 70 so that the linear expansion coefficient is 3 ppm / °C or more and 25 ppm / °C or less. The linear expansion coefficient of the encapsulating resin layer 70, 3 ppm / °C, which is the lower limit of the above numerical range, is close to the value of silicon, which is the chip material of the semiconductor element 60, and the linear expansion coefficient of the encapsulating resin layer 70, 25 ppm / °C, which is the upper limit, is close to the value of the resin, such as epoxy resin, used in the circuit board 20. Therefore, if the linear expansion coefficient of the encapsulating resin layer 70 is set within the above numerical range, deformation of the semiconductor element 60 due to temperature changes, etc. can be minimized.

[0061] When the chip heights (length in the thickness direction) of multiple semiconductor elements 60 mounted on the circuit board 20 are different, the sealing resin layer 70 can be formed to cover the second surface 60b of the semiconductor element 60 with a lower chip height so that the height positions of the semiconductor elements 60 from the circuit board 20 are aligned.

[0062] The sealing resin layer 70 may be integrally formed using the same type of resin, or may be formed as a layer using other materials, such as an underfill material primarily made of epoxy resin, in areas where it is difficult for resin to penetrate, such as around the first connection terminal 13.

[0063] As described above, the semiconductor package 100 includes the electronic component 50 mounted on the first surface 20a of the circuit board 20, and the solid-state imaging device 10 and the semiconductor device 60 mounted on the second surface 20b, as shown in FIG. 1 . As described in the “Problems to be Solved by the Invention” section, semiconductor modules used in conventional camera modules lack sufficient mounting space for semiconductor devices such as an ISP on the circuit board on which the solid-state imaging device is mounted, requiring the solid-state imaging device and other semiconductor devices to be mounted separately and at separate locations on the mounting board. Meanwhile, the planar size of the solid-state imaging device 10 has been steadily increasing year by year in pursuit of higher-resolution images, and the size of the circuit board 20 surrounding the solid-state imaging device has naturally also been increasing. In light of these circumstances, the inventors of the present application have developed a semiconductor package 100 that effectively utilizes the extra space created by the expansion of the circuit board 20, thereby reducing the mounting area of ​​the module and shortening the mounting distance between the solid-state imaging device 10, the electronic component 50, and the semiconductor device 60 without using connecting components such as flexible substrates, thereby minimizing signal transmission loss.

[0064] The camera module 200 includes the semiconductor package 100 and an optical unit 230. In the camera module 200, the semiconductor package 100 is disposed below the optical unit 230 (on the opposite side of the optical unit 230 from the light incident side), as shown in FIG.

[0065] The optical section 230 collects light from the subject and guides it to the solid-state imaging device 10. The optical section 230 includes a lens section 210 and an actuator 220.

[0066] Lens unit 210 has a lens group consisting of multiple lenses (not shown), and forms a subject image on light receiving region R of solid-state imaging device 10. Actuator 220 is fixed to housing 310 of camera 300, and drives a predetermined lens included in the lens group, for example, in a direction facing solid-state imaging device 10 (up and down direction in FIG. 1) and in a horizontal direction (left and right direction and forward / backward direction in FIG. 1). This realizes at least one of autofocus and image stabilization functions.

[0067] However, the actuator 220 may be a simple lens holder that does not have the autofocus or image stabilization functions. In this case, the autofocus and image stabilization functions can be realized by image processing or the like.

[0068] The camera 300 includes the above-described camera module 200, a housing 310, a heat sink 320, and an adhesive layer 330.

[0069] Camera module 200 is thermally connected to heat sink 320 installed in housing 310 of camera 300 via thermally conductive adhesive layer 330. This allows effective heat dissipation from solid-state imaging element 10 and semiconductor element 60, which generate high heat during startup, among the components of semiconductor package 100.

[0070] The heat sink 320 is a thermally conductive material such as a graphite sheet, metal parts, or a vapor chamber, and from the standpoint of heat dissipation, it is preferable to use a material with a thermal conductivity of 150 W / mK or more, which is lower than the thermal conductivity of silicon (168 W / mK), so as to obtain a necessary and sufficient heat dissipation effect.

[0071] The adhesive layer 330 is a thermally conductive adhesive and is applied to the bottom of the semiconductor package 100. When the solid-state imaging element 10 or the semiconductor element 60 is located on the bottom of the semiconductor package 100, the adhesive layer 330 is applied to the second surface 20b of the solid-state imaging element 10 or the second surface 60b of the semiconductor element 60, and when these elements are covered with the sealing resin layer 70, the adhesive layer 330 is applied to the surface of the sealing resin layer 70. From the viewpoint of heat dissipation, it is preferable to use an adhesive having a thermal conductivity of 3 W / mK or more for the adhesive layer 330.

[0072] Next, a description will be given of methods for manufacturing the semiconductor package 100, camera module 200, and camera 300 according to this embodiment. The method for manufacturing the semiconductor package 100 includes steps 1 to 6 shown below, the method for manufacturing the camera module 200 includes step 7, and the method for manufacturing the camera 300 includes step 8. Figures 3A to 3H show configuration diagrams of steps 1 to 8.

[0073] (Process 1) 3A, in step 1, electronic components 50 are mounted on first surface 20a of circuit board 20. The types, number, and mounting positions of electronic components 50 mounted on circuit board 20 are appropriately set according to the specifications of camera module 200, etc.

[0074] (Process 2) In step 2, as shown in Fig. 3B, a sealant is applied to the periphery of window portion 23 of circuit board 20, and second surface 30b of protective member 30 is bonded to window portion 23 while facing it. In step 2, the sealant is cured to form bonded portion 31.

[0075] (Step 3) 3C, in step 3, the solid-state imaging element 10 is flip-chip mounted on the second surface 20b of the circuit board 20. On the first surface 11a of the chip substrate 11 of the solid-state imaging element 10, an on-chip lens 12 and other components that constitute the image sensor are mounted, and first connection terminals 13 and an annular sealing portion 40 are also formed. In step 3, the first connection terminals 13 of the solid-state imaging element 10 are connected to the wiring 21 of the circuit board 20, and the solid-state imaging element 10 and the circuit board 20 are joined by the annular sealing portion 40, thereby forming a sealed space S.

[0076] (Step 4) 3D, in step 4, the semiconductor element 60 is flip-chip mounted on the second surface 20b of the circuit board 20. In step 4, the second connection terminals 61 of the semiconductor element 60 are connected to the wiring 21 of the circuit board 20.

[0077] (Step 5) 3E, step 5 is a process of forming the sealing resin layer 70. The sealing resin layer 70 is formed by applying a resin such as an epoxy resin to cover the side surface 62 of the semiconductor element 60 and the second connection terminal 61.

[0078] (Step 6) In step 6, as shown in FIG. 3F, the second surface 11b of the chip substrate 11 of the solid-state imaging element 10 and the second surface 60b of the semiconductor element 60 are back-ground to a predetermined chip thickness. This exposes the second surface 11b of the chip substrate 11 of the solid-state imaging element 10 and the second surface 60b of the semiconductor element 60. In step 6, the second surface 11b of the chip substrate 11 of the solid-state imaging element 10 and the second surface 60b of the semiconductor element 60 may be ground to be completely exposed as shown in FIG. 3F, or may be ground to leave at least a portion of the second surface 60b of the semiconductor element 60 covered with the sealing resin layer 70. The semiconductor package 100 is completed through steps 1 to 6.

[0079] (Step 7) 3G, in step 7, the semiconductor package 100 produced in step 6 is assembled with an optical unit 230 to produce a camera module 200. The optical unit 230 is disposed on the upper part of the semiconductor package 100, which is the light incident side.

[0080] (Step 8) In step 8, as shown in Fig. 3H, camera module 200 produced in step 7 is placed on heat sink 320 to produce camera 300. Camera module 200 is mounted on heat sink 320 via adhesive layer 330 having thermal conductivity to dissipate heat from second surface 11b of chip substrate 11 of solid-state imaging element 10 located at the bottom and second surface 60b of semiconductor element 60. In step 8, camera module 200 is mounted on heat sink 320, and other components are also assembled, to produce camera 300.

[0081] Each of the above-described manufacturing methods may, as necessary, include steps of performing processing other than steps 1 to 8. The order of performing each step may also be changed as appropriate, provided that the configurations and functions of the semiconductor package 100, camera module 200, and camera 300 to be manufactured are guaranteed.

[0082] Next, modified examples of the present invention will be described. In each modified example described below, the same components as those in the above-described embodiment are designated by the same reference numerals, and their description will be omitted. Furthermore, points not specifically mentioned in each modified example can be configured in the same way as in the above-described embodiment. Furthermore, each modified example can be implemented by appropriately selecting necessary components from the components shown in each modified example and combining them with other forms, within the scope of the gist of the present invention.

[0083] A semiconductor package 100A, a camera module 200A, and a camera 300A according to a first modified example of the present invention will be described.

[0084] As shown in FIG. 4, the camera 300A of the first modified example includes a semiconductor package 100A and a camera module 200A.

[0085] A third connection terminal 24 is formed on the first surface 20a of the circuit board 20, and is electrically connected to the solid-state imaging element 10. The solid-state imaging element 10 is electrically connected to the third connection terminal 24 by wire bonding using a wire 15 made of, for example, gold, aluminum, copper, or the like.

[0086] The semiconductor package 100A of the first modified example differs from the semiconductor package 100 described above in that the connection mode of the solid-state imaging element 10 to the circuit board 20 has been changed from the lower part of the board to the upper part of the board. Therefore, the semiconductor packages 100 and 100A can be selected to be more suitable for the configuration of the circuit board 20 designed in accordance with the specifications of the camera 300.

[0087] A semiconductor package 100B, a camera module 200B, and a camera 300B according to a second modified example of the present invention will be described.

[0088] 5, in the camera 300B of the second modification, a fourth connection terminal 25 that electrically connects to the mounting board 400 is formed on the first surface 20a of the circuit board 20. The fourth connection terminal 25 is formed on the outside of the protective member 30 that is disposed on the first surface 20a of the circuit board 20. The mounting board 400 is connected to an external board (not shown). The mounting board 400 functions as a wiring layer that exchanges control signals between the external board and the solid-state imaging element 10 and the semiconductor element 60 that constitute the semiconductor package 100B. The control signals include electrical signals for supplying power to the solid-state imaging element 10 and the semiconductor element 60, drive signals for performing various drive controls, and the like.

[0089] In the semiconductor package 100B, from the viewpoint of stress relaxation, the difference in the linear expansion coefficient between the circuit board 20 and the mounting board 400 is preferably 4 ppm / °C or less. This reduces the difference in the linear expansion coefficient between the circuit board 20 and the mounting board 400, thereby improving the solder connection reliability and simultaneously reducing warpage of the camera module 200 and the solid-state imaging element 10.

[0090] In the camera module 200B, the size of the optical unit 230 can be set appropriately depending on the specifications of the protective member 30 and the mounting substrate 400. The specifications of the protective member 30 and the mounting substrate 400 are determined by the size, arrangement, and the like of each component. In the camera module 200B, the size can be set to a small size so that the optical unit 230 does not interfere with the protective member 30. As shown in FIG. 5 , in the camera module 200B, the width of the optical unit 230 (the length in the direction perpendicular to the thickness direction of the lens unit 210) can be made shorter than the width of the circuit board 20 (the length in the direction perpendicular to the thickness direction of the circuit board 20). This enables high-density mounting in the camera module 200B. Furthermore, in the camera module 200B, the optical unit 230 can also be made larger within the limits of the mounting substrate 400.

[0091] In the semiconductor package 100B of the second modified example, the fourth connection terminal 25 is formed on the first surface 20a of the circuit board 20 outside the protective member 30. Therefore, when the camera module 200B is viewed from above the mounting board connected to the fourth connection terminal 25, the mounting area of ​​the optical unit 230 is substantially the same as the imaging area of ​​the solid-state imaging element 10, which contributes to high-density mounting. Furthermore, the size of the optical unit 230 in the camera module 200B can be set appropriately according to the specifications of the protective member 30 and the mounting board 400. High-density mounting can be achieved in the camera module 200B, for example, by miniaturizing the optical unit 230 in a manner that does not interfere with the protective member 30.

[0092] As described above, the semiconductor packages 100, 100A, and 100B according to the present invention include a solid-state imaging element 10 having a chip substrate 11, and a semiconductor element 60, and a circuit board 20 is arranged on the outer periphery of a first surface 11a of the chip substrate 11, which is the surface on which light is incident, and the circuit board 20 has the first surface 20a, which is the surface on which light is incident, and a second surface 20b opposite to the first surface 20a of the circuit board 20, and the semiconductor element 60 is arranged on the second surface 20b of the circuit board 20.

[0093] In the semiconductor packages 100, 100A, and 100B, the solid-state imaging element 10 and the semiconductor element 60 are arranged on the second surface 20b of the circuit board 20, which reduces the mounting area within a product such as a smartphone and reduces the number of connecting components such as flexible boards. In addition, since the solid-state imaging element 10 and the semiconductor element 60 are arranged close to each other, transmission loss of electrical signals between the components can be reduced.

[0094] Camera modules 200, 200A, 200B according to the present invention have semiconductor packages 100, 100A, 100B and an optical unit 230 including a lens unit 210, and the semiconductor packages 100, 100A, 100B are arranged below the lens unit 210.

[0095] With this configuration, camera modules 200, 200A, and 200B can reduce the mounting area within a product such as a smartphone, and can also reduce the number of connecting parts such as flexible substrates.

[0096] The cameras 300, 300A, 300B according to the present invention have camera modules 200, 200A, 200B and a heat sink 320, and the solid-state imaging element 10 and the semiconductor element 60 mounted in the semiconductor packages 100, 100A, 100B of the camera modules 200, 200A, 200B are thermally connected to the heat sink 320 via a thermally conductive adhesive layer 330.

[0097] With this configuration, the cameras 300, 300A, and 300B can effectively dissipate heat generated from the solid-state imaging device 10 and the semiconductor device 60 when the camera is operating. [Explanation of symbols]

[0098] 100, 100A, 100B semiconductor packages, 10 solid-state image sensor, 11 chip substrate, 11a: a first surface of a chip substrate; 11b a second surface of the chip substrate; 12 On-chip lens, 13 first connection terminal, 14 outer periphery; 15 wires, 20 circuit boards, 20a: a first surface of the circuit board; 20b second surface of the circuit board; 21 wiring, 22 connection part, 23 Window section, 24 third connection terminal, 25 fourth connection terminal, 30 protective member, 30a: a first surface of the protective member; 30b: a second surface of the protective member; 31 joint, 40 annular seal, 50 electronic components, 60 semiconductor elements, 60a: a first surface of a semiconductor element; 60b: a second surface of the semiconductor element; 61 second connection terminal, 62 Side of semiconductor element, 70 Sealing resin layer, 200 camera modules, 210 lens part, 220 actuator, 230 Optics Department, 300 cameras, 310 housing, 320 heat sink, 330 adhesive layer, 400 mounting boards, L incident light, R light receiving area, S Sealed space.

Claims

1. A semiconductor package including a solid-state imaging device having a chip substrate and a semiconductor device, a circuit board is disposed on an outer peripheral portion of a first surface of the chip substrate, the first surface being a surface on which light is incident; the circuit board has a first surface on which the light is incident and a second surface opposite to the first surface of the circuit board; The semiconductor device is disposed on the second surface of the circuit board.

2. The semiconductor package according to claim 1 , wherein a light-transmitting protective member is disposed on the first surface of the circuit board so as to cover at least a light-receiving region of the solid-state imaging element.

3. the solid-state imaging element has a first connection terminal formed on the first surface of the chip substrate for electrically connecting to the circuit board; 2 . The semiconductor package according to claim 1 , further comprising an annular sealing portion formed outside the first connection terminal on the first surface of the chip substrate so as to surround the first connection terminal and a light receiving region of the solid-state imaging element.

4. 2. The semiconductor package of claim 1, wherein a second connection terminal for electrically connecting to the circuit board is formed on a first surface of the semiconductor element, and a sealing resin layer is formed to cover the side surface of the semiconductor element and the second connection terminal.

5. The semiconductor package according to claim 1, wherein a plurality of semiconductor elements having different chip heights are arranged on the second surface of the circuit board, and an encapsulating resin layer is formed on the second surface of at least one of the plurality of semiconductor elements.

6. 6. The semiconductor package according to claim 5, wherein a difference in chip height between the plurality of semiconductor elements is 200 [mu]m or less.

7. 2. The semiconductor package according to claim 1, wherein a plurality of semiconductor elements having approximately the same chip height are arranged on the second surface of the circuit board, and the second surface of at least one of the plurality of semiconductor elements has a ground surface.

8. a third connection terminal electrically connected to the solid-state imaging device is formed on the first surface of the circuit board; The semiconductor package according to claim 1 , wherein the solid-state imaging element is electrically connected to the third connection terminal by wire bonding.

9. a first connection terminal for electrically connecting the solid-state imaging element to the circuit board is formed on the first surface of the solid-state imaging element; a second connection terminal for electrically connecting the semiconductor element to the circuit board is formed on the first surface of the semiconductor element; the first connection terminal is connected to an inner side of the second surface of the circuit board; The semiconductor package according to claim 1 , wherein the second connection terminal is connected to an outer side of the second surface of the circuit board.

10. The semiconductor package according to claim 1 , wherein the semiconductor device is one or more devices selected from the group consisting of a semiconductor memory, an ISP, and a GPU.

11. the solid-state imaging device has an on-chip lens disposed in the light receiving region; The semiconductor package according to claim 2 , wherein the distance between the surface of the on-chip lens and the second surface of the protection member is 0.6 mm or more.

12. 3. The semiconductor package according to claim 2, wherein the circuit board has a linear expansion coefficient of 6 ppm / [deg.] C. or less.

13. The semiconductor package according to claim 2 , wherein a fourth connection terminal for electrically connecting to a mounting board is formed on an outer side of the protective member.

14. 14. The semiconductor package according to claim 13, wherein the difference in linear expansion coefficient between the circuit board and the mounting board is 4 ppm / [deg.] C. or less.

15. A semiconductor package according to any one of claims 1 to 14, and an optical part including a lens part, The semiconductor package is disposed below the lens portion.

16. The camera module according to claim 15 , wherein the optical unit has a size set appropriately according to specifications of the protective member and / or the mounting board.

17. The camera module according to claim 16 , wherein the optical unit has a widthwise length that is shorter than the widthwise length of the circuit board.

18. A camera module comprising: the camera module according to claim 15; and a heat sink; The solid-state imaging element and the semiconductor element mounted in the semiconductor package of the camera module are thermally connected to the heat sink via a thermally conductive adhesive layer.

19. 19. The camera according to claim 18, wherein the heat sink is made of a heat sink material having a thermal conductivity of 150 W / mK or more.

20. 19. The camera of claim 18, wherein the adhesive layer has a thermal conductivity of 3 W / mK or more.

Images