Semiconductor module and power conversion device

Abstract

To provide a semiconductor module and a power conversion device capable of reducing inductance while suppressing an increase in physical size.SOLUTION: The module 21 includes a P-terminal 80P, an N-terminal 80N, semiconductor elements 40H and 40L, and an encapsulant 30. The semiconductor elements 40H and 40L are arranged side by side in the X direction. The P-terminal 80P, the N-terminal 80N, and the semiconductor elements 40H and 40L constitute the upper and lower arm circuit 9 in which the semiconductor elements 40H are disposed on the P-terminal 80P side and the semiconductor elements 80PtN and 80N are connected in series between the P-terminal and the N-terminal 40H. 40L. The P-terminal 80P protrudes from the side surface 303 of the semiconductor device 40H of the encapsulant 30 in the X direction. The N-terminal 80N is exposed at the main surface 302 of the encapsulant 30.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The disclosure herein relates to a semiconductor module and a power conversion device. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device. The contents of the prior art document are incorporated by reference as an explanation of the technical elements in this specification. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-181823 Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Document 1, the P terminal, N terminal, upper arm element, and lower arm element are arranged such that the upper arm element is disposed on the P terminal side, and the upper arm element and the lower arm element are connected in series between the P terminal and the N terminal to form a series circuit. The upper arm element and the lower arm element are aligned in the Y direction. For connection to the capacitor, the P terminal and the N terminal protrude from the same side of the sealing body. The protruding portions of the P terminal and the N terminal are aligned in the X direction. Therefore, it is necessary to ensure a creepage distance between the P terminal and the N terminal. Furthermore, in a plan view in the thickness direction of the element, it is necessary to electrically connect the N terminal and the lower arm element while avoiding the upper arm element. There is a demand for semiconductor modules and power conversion devices that further reduce inductance without increasing their physical size.

[0005] An object of the present disclosure is to provide a semiconductor module and a power conversion device that can reduce inductance while suppressing an increase in size. [Means for solving the problem]

[0006] A semiconductor module according to one aspect of the disclosure includes: First terminal (80P, 80F), Second terminal (80N, 80S), a plurality of semiconductor elements (40) including first semiconductor elements (40H, 40F) and second semiconductor elements (40L, 40S) each having a first main electrode (41D) provided on one surface and a second main electrode (41S) formed on a surface opposite to the one surface in a plate thickness direction, and arranged side by side in a predetermined direction perpendicular to the plate thickness direction; an encapsulant (30) that encapsulates a plurality of semiconductor elements; Equipped with The first terminal, the second terminal, the first semiconductor element, and the second semiconductor element are arranged so that the first semiconductor element is disposed on the first terminal side, and the first semiconductor element and the second semiconductor element are connected in series between the first terminal and the second terminal to form a series circuit (9, 13); The first terminal protrudes from the side surface (303) of the sealing body on the first semiconductor element side in a predetermined direction to the outside of the sealing body, The second terminal is exposed to the outside of the sealing body from a main surface (302) which is one of the surfaces connected to the side surfaces of the sealing body.

[0007] According to the disclosed semiconductor module, in a configuration in which a first semiconductor element and a second semiconductor element are arranged side by side in a predetermined direction, only the first terminal of the series circuit protrudes from the side surface of the sealing body facing the first semiconductor element, and the second terminal of the series circuit is exposed from the main surface of the sealing body. This ensures a creepage distance between the first terminal and the second terminal. To electrically connect the second terminal and the second semiconductor element, it is not necessary to route the series circuit so as to avoid the first semiconductor element when viewed in a plan view in the plate thickness direction. As a result, inductance can be reduced while suppressing an increase in physical size. Furthermore, the first bus bar connected to the first terminal protruding from the side surface and the second bus bar connected to the second terminal exposed from the main surface can be drawn in the same direction and run parallel to each other, further reducing inductance.

[0008] Another aspect of the disclosed power conversion device is a semiconductor module (21) constituting an upper and lower arm circuit (9); a capacitor module (22) having a plurality of bus bars (222P, 222N) electrically connected to the semiconductor module; Equipped with The semiconductor module is First terminal (80P), A second terminal (80N), a plurality of semiconductor elements (40) including a first semiconductor element (40H) and a second semiconductor element (40L) each having a first main electrode (41D) provided on one surface and a second main electrode (41S) formed on a surface opposite to the one surface in a plate thickness direction, and arranged side by side in a predetermined direction perpendicular to the plate thickness direction; an encapsulant (30) that encapsulates a plurality of semiconductor elements; and one of the first semiconductor element and the second semiconductor element is an upper arm element constituting an upper arm (9H) of an upper / lower arm circuit formed by connecting the first semiconductor element and the second semiconductor element in series between the first terminal and the second terminal, and the other of the first semiconductor element and the second semiconductor element is a lower arm element constituting a lower arm (9L) of the upper / lower arm circuit; The first terminal protrudes from the side surface (303) of the sealing body on the first semiconductor element side in a predetermined direction to the outside of the sealing body, The second terminal is exposed to the outside of the sealing body from a main surface (302) that is one of the surfaces connected to the side surface of the sealing body, the capacitor module is disposed on the main surface of the semiconductor module in the plate thickness direction; The plurality of capacitor bus bars include a first bus bar (222P) electrically connected to the first terminal, and a second bus bar (222N) electrically connected to the second terminal and arranged parallel to the first bus bar so that the plate surfaces thereof face each other.

[0009] The semiconductor module of the disclosed power conversion device has a configuration similar to the semiconductor module described above. Therefore, it is possible to reduce inductance while suppressing an increase in size. Because the capacitor module is disposed on the main surface where the second terminal is exposed, it is possible to further shorten the length of the wiring connecting the semiconductor module and the capacitor module. Because the first bus bar and the second bus bar are disposed in parallel so that their plate surfaces face each other, it is possible to reduce inductance while suppressing an increase in size of the power conversion device as a whole.

[0010] The various aspects disclosed in this specification employ different technical means to achieve their respective objectives. The reference numerals in parentheses in the claims are intended to exemplarily indicate the corresponding parts of the embodiments described below, and are not intended to limit the technical scope. The objectives, features, and advantages disclosed in this specification will become more apparent by reference to the following detailed description and the accompanying drawings. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a diagram showing a power conversion circuit and a drive system to which the semiconductor device according to the first embodiment is applied; [Figure 2] FIG. 1 is a perspective view illustrating an example of a power conversion device. [Figure 3] FIG. 3 is a cross-sectional view taken along line III-III in FIG. 2. [Figure 4] FIG. 1 is a perspective view showing an example of a semiconductor module. [Figure 5] FIG. [Figure 6] FIG. 4 is a cross-sectional view corresponding to FIG. 3. [Figure 7] FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 5. [Figure 8] FIG. [Figure 9] FIG. 10 is a plan view showing a configuration in which the substrate on the source electrode side and the sealing body are omitted. [Figure 10] FIG. 10 is a plan view showing a configuration in which a sealing body is omitted. [Figure 11] FIG. 2 is a plan view showing the substrate on the source electrode side. [Figure 12] FIG. 10 is a plan view showing a reference example. [Figure 13] FIG. 10 is a diagram showing the magnetic field strength distribution of a reference example. [Figure 14] FIG. 10 is a diagram showing the magnetic field strength distribution of this example. [Figure 15] FIG. 10 is a cross-sectional view showing a modified example. [Figure 16] FIG. [Figure 17] FIG. 10 is a cross-sectional view showing a modified example. [Figure 18] FIG. [Figure 19] FIG. 10 is a cross-sectional view showing a semiconductor module according to a second embodiment. [Figure 20] FIG. 10 is a plan view showing a semiconductor module according to a third embodiment. [Figure 21] FIG. 10 is a plan view showing a configuration in which a sealing body is omitted. [Figure 22] FIG. 22 is a cross-sectional view taken along line XXII-XXII in FIG. 20. [Figure 23] FIG. 10 is a diagram illustrating another example of a series circuit. [Figure 24] FIG. 10 is a plan view showing a semiconductor module according to a fourth embodiment. [Figure 25] FIG. 10 is a plan view showing a configuration in which the substrate on the source electrode side, the sealing body, and the wiring member are omitted. [Figure 26] FIG. 10 is a plan view showing a configuration in which a sealing body is omitted. [Figure 27] FIG. 27 is a cross-sectional view taken along line XXVII-XXVII in FIG. 24. [Figure 28] FIG. 10 is a cross-sectional view showing a power conversion device according to a fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, several embodiments will be described with reference to the drawings. Note that in each embodiment, corresponding components are designated by the same reference numerals, and redundant description may be omitted. When only a portion of the configuration is described in each embodiment, the configuration of another embodiment previously described may be applied to the remaining portion of the configuration. Furthermore, in addition to the combinations of configurations explicitly stated in the description of each embodiment, configurations of several embodiments may be partially combined together even if not explicitly stated, provided that there is no particular problem with the combination.

[0013] (First embodiment) The semiconductor device of this embodiment is applied to, for example, a mobile body using a rotating electric machine as a drive source. Examples of the mobile body include electric vehicles such as battery electric vehicles (BEV), hybrid electric vehicles (HEV), and plug-in hybrid electric vehicles (PHEV), electric flying bodies such as drones and electric vertical take-off and landing aircraft (eVTOL), ships, construction machinery, and agricultural machinery. BEV is an abbreviation for Battery Electric Vehicle. HEV is an abbreviation for Hybrid Electric Vehicle. eVTOL is an abbreviation for electronic Vertical Take-Off and Landing aircraft. An example of application to a vehicle will be described below.

[0014] <Vehicle drive system> 1 shows an example of a vehicle drive system. The vehicle drive system 1 includes a DC power supply 2, a motor generator 3, and a power conversion circuit 4.

[0015] The DC power supply 2 is a DC voltage source composed of a rechargeable secondary battery. The secondary battery may be, for example, a lithium-ion battery or a nickel-metal hydride battery. The motor generator 3 is a three-phase AC rotating electric machine. The motor generator 3 functions as a drive source for the vehicle, that is, an electric motor. The motor generator 3 functions as a generator during regeneration. The power conversion circuit 4 converts power between the DC power supply 2 and the motor generator 3.

[0016] <Power conversion circuit> 1 shows an example of a power conversion circuit 4. The power conversion circuit 4 shown in FIG.

[0017] The smoothing capacitor 5 mainly smoothes the DC voltage supplied from the DC power supply 2. The smoothing capacitor 5 is connected to a P line 7, which is a power supply line on the high potential side, and an N line 8, which is a power supply line on the low potential side. The P line 7 is connected to the positive electrode of the DC power supply 2, and the N line 8 is connected to the negative electrode of the DC power supply 2. The positive electrode of the smoothing capacitor 5 is connected to the P line 7 between the DC power supply 2 and the inverter 6. The negative electrode of the smoothing capacitor 5 is connected to the N line 8 between the DC power supply 2 and the inverter 6. The smoothing capacitor 5 is connected in parallel to the DC power supply 2.

[0018] The inverter 6 is a DC-AC conversion circuit. In accordance with switching control by the control circuit, the inverter 6 converts a DC voltage into a three-phase AC voltage and outputs it to the motor generator 3. This drives the motor generator 3 to generate a predetermined torque. During regenerative braking of the vehicle, the inverter 6 converts the three-phase AC voltage generated by the motor generator 3 in response to rotational force from the wheels into a DC voltage in accordance with switching control by the control circuit and outputs it to the P line 7. In this way, the inverter 6 performs bidirectional power conversion between the DC power supply 2 and the motor generator 3.

[0019] The inverter 6 is configured to include upper and lower arm circuits 9 for three phases. The upper and lower arm circuits 9 are sometimes referred to as legs. Each upper and lower arm circuit 9 has an upper arm 9H and a lower arm 9L. The upper arm 9H and the lower arm 9L are connected in series between the P line 7 and the N line 8, with the upper arm 9H on the P line 7 side. Hereinafter, the upper arm 9H and the lower arm 9L may be simply referred to as arms 9H and 9L.

[0020] The connection point between the upper arm 9H and the lower arm 9L, i.e., the midpoint of the upper and lower arm circuit 9, is connected to the winding 3a of the corresponding phase in the motor generator 3 via an output line 10. The inverter 6 has six arms 9H, 9L. Each of the arms 9H, 9L is configured with a switching element. The number of switching elements constituting each of the arms 9H, 9L is not particularly limited. It may be one or more. In the illustrated upper arm 9H, two switching elements are connected in parallel. In the lower arm 9L, two switching elements are connected in parallel. In other words, each of the six arms 9H, 9L of the three-phase upper and lower arm circuit 9 is configured with two switching elements connected in parallel to each other.

[0021] The illustrated switching element is an n-channel MOSFET 11. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor. The two high-side MOSFETs 11 connected in parallel are turned on and off at the same timing by a common gate drive signal (drive voltage). The two low-side MOSFETs 11 connected in parallel are turned on and off at the same timing by a common gate drive signal (drive voltage).

[0022] A freewheeling diode 12 is connected in anti-parallel to each MOSFET 11. The diode 12 may be a parasitic diode (body diode) or an external diode. In the upper arm 9H, the drain of the MOSFET 11 is connected to the P line 7. In the lower arm 9L, the source of the MOSFET 11 is connected to the N line 8. The source of the MOSFET 11 in the upper arm 9H and the drain of the MOSFET 11 in the lower arm 9L are connected to each other. The anode of the diode 12 is connected to the source of the corresponding MOSFET 11, and the cathode is connected to the drain.

[0023] The switching element is not limited to the MOSFET 11. For example, an IGBT may be used. IGBT is an abbreviation for Insulated Gate Bipolar Transistor. In the case of an IGBT, a freewheeling diode is also connected in anti-parallel.

[0024] The power conversion circuit 4 may include a converter. The converter is a DC-DC conversion circuit configured to be able to convert a DC voltage into a DC voltage of a different value, for example. The converter is provided between the DC power supply 2 and the smoothing capacitor 5. The converter is configured to include, for example, a reactor and the above-mentioned upper and lower arm circuits 9. This configuration allows for voltage step-up and step-down. The power conversion circuit 4 may also include a filter capacitor. The filter capacitor is provided between the DC power supply 2 and the converter.

[0025] The power conversion circuit 4 may include a snubber circuit. The snubber circuit is connected in parallel to the upper and lower arm circuits 9. The snubber circuit reduces the inductance of the upper and lower arm circuits 9. The snubber circuit absorbs a transient high voltage, known as a switching surge, that occurs when switching elements (MOSFETs 11) that constitute the upper and lower arm circuits 9. This enables the inverter 6 to perform high-speed switching.

[0026] The power conversion circuit 4 may include a drive circuit for a switching element constituting the inverter 6 or the like. The drive circuit supplies a drive voltage to the gate of the MOSFET 11 of the corresponding arm based on a drive command from the control circuit. The drive circuit drives the corresponding MOSFET 11, i.e., turns it on and off, by applying the drive voltage. The drive circuit is sometimes referred to as a driver.

[0027] The power conversion circuit 4 may include a control circuit for the switching element. The control circuit generates a drive command for operating the MOSFET 11 and outputs it to the drive circuit. The control circuit generates the drive command based on, for example, a torque request input from a higher-level ECU (not shown) and signals detected by various sensors. ECU is an abbreviation for Electronic Control Unit.

[0028] The various sensors include, for example, a current sensor, a rotation angle sensor, and a voltage sensor. The current sensor detects the phase current flowing through the winding 3a of each phase. The rotation angle sensor detects the rotation angle of the rotor of the motor generator 3. The voltage sensor detects the voltage across the smoothing capacitor 5. The control circuit outputs, for example, a PWM signal as a drive command. The control circuit is configured with, for example, a processor and a memory. PWM is an abbreviation for Pulse Width Modulation.

[0029] <Power conversion device> Fig. 2 shows an example of a power converter including a semiconductor module, and Fig. 3 is a cross-sectional view taken along line III-III in Fig. 2.

[0030] The power conversion device 20 provides the above-described power conversion circuit 4. The power conversion device 20 includes a semiconductor module 21, a capacitor module 22, and a cooler 23. The power conversion device 20 may include a housing that houses other elements that constitute the power conversion device 20.

[0031] In the following, the thickness direction of a semiconductor element (semiconductor substrate) is referred to as the Z direction. The direction perpendicular to the Z direction is referred to as the X direction, and the direction perpendicular to both the X and Z directions is referred to as the Y direction. The X, Y, and Z directions are orthogonal to one another. Unless otherwise specified, the shape viewed from the Z direction, in other words, the shape along the XY plane defined by the X and Y directions, is referred to as the planar shape. The planar view from the Z direction may sometimes be simply referred to as the planar view.

[0032] The detailed structure of the semiconductor modules 21 will be described later. The illustrated power conversion device 20 includes three semiconductor modules 21. Each semiconductor module 21 configures one phase of the upper and lower arm circuits 9. The semiconductor modules 21 are lined up in the Y direction.

[0033] The capacitor module 22 provides the smoothing capacitor 5 of the power conversion circuit 4. It includes a capacitor element 221, a P bus bar 222P, an N bus bar 222N, an insulating member 223, and DC terminal portions 224P and 224N. The capacitor module 22 includes a case and a sealing resin body (not shown). The capacitor module 22 is aligned in the X direction relative to the semiconductor module 21. The case has a cylindrical shape with a bottom. The case may be formed using a metal material such as aluminum, or may be formed using a resin material. The case may be formed using a metal laminate film. The sealing resin body is formed using an electrically insulating resin material such as epoxy resin. The sealing resin body is filled into the case and seals the capacitor element 221 and portions of the P bus bar 222P and the N bus bar 222N.

[0034] The capacitor element 221 is housed in a case. The illustrated capacitor element 221 is a film capacitor element. The capacitor element 221 is formed, for example, by winding a film around the Z direction as its axis. The capacitor element 221 has electrodes (not shown) on both end surfaces in the Z direction. As an example, the negative electrode is provided on the upper surface, and the positive electrode is provided on the lower surface. The capacitor module 22 includes at least one capacitor element 221. The illustrated capacitor module 22 includes three capacitor elements 221 lined up in the Y direction.

[0035] P bus bar 222P and N bus bar 222N are plate materials made of a metal with good conductivity, such as Cu. P bus bar 222P is connected to the positive electrode of capacitor element 221. N bus bar 222N is connected to the negative electrode of capacitor element 221. P bus bar 222P and N bus bar 222N protrude from the upper surface of the sealing resin body to the outside. The plate surfaces of the protruding portions of P bus bar 222P and N bus bar 222N face each other at least in the extension direction (longitudinal direction) to reduce inductance. Insulating member 223 is interposed between the protruding portions of P bus bar 222P and N bus bar 222N in the opposing region.

[0036] The DC terminal portions 224P, 224N are terminal portions for electrically connecting the capacitor element 221 to a DC power supply (DC power supply 2). The DC terminal portion 224P is electrically connected to the positive electrode of the DC power supply. The DC terminal portion 224N is electrically connected to the negative electrode of the DC power supply. The illustrated DC terminal portion 224P is connected to the P bus bar 222P. The DC terminal portion 224N is connected to the N bus bar 222N.

[0037] The cooler 23 cools other elements constituting the power conversion device 20, which are arranged on the cooler 23. The cooler 23 may be, for example, a heat sink. The heat sink may have fins on the back side. The cooler 23 may have a flow path through which a refrigerant flows. The refrigerant may be, for example, a phase-change refrigerant such as water or ammonia, or a phase-non-change refrigerant such as an ethylene glycol-based refrigerant. The refrigerant may be, for example, LLC. LLC is an abbreviation for long life coolant.

[0038] The cooler 23 may be part of a housing that houses the semiconductor module 21, the capacitor module 22, etc., or may be provided separately from the housing. The cooler 23 and the components arranged on the cooler 23 may be thermally connected via a bonding material such as solder, or may be thermally connected via a thermally conductive member. The thermally conductive member may be referred to as TIM, GF, etc. TIM is an abbreviation for Thermal Interface Material. GF is an abbreviation for Gap Filler. The illustrated cooler 23 is a heat sink with fins on its back surface. The semiconductor module 21 is arranged on one surface of the cooler 23. The cooler 23 has a protrusion 231 that supports the semiconductor module 21.

[0039] Power conversion device 20 further includes bus bars 24 and insulating members 25. Bus bars 24 are metal plates made of a metal with good conductivity, such as Cu. Bus bars 24 may be configured as part of semiconductor module 21, or may be configured as elements separate from semiconductor module 21. Bus bars 24 include a P bus bar 24P, an N bus bar 24N, and an output bus bar 24A.

[0040] The P bus bar 24P and the N bus bar 24N are wiring members that electrically connect the semiconductor module 21 and the capacitor module 22. The P bus bar 24P electrically connects the P terminal 80P of the semiconductor module 21 and the P bus bar 222P of the capacitor module 22. The N bus bar 24N electrically connects the N terminal 80N of the semiconductor module 21 and the N bus bar 222N of the capacitor module 22. To reduce inductance, the P bus bar 24P and the N bus bar 24N are arranged so that their plate surfaces face each other in at least a part of the extension direction (longitudinal direction). The P bus bar 24P and the N bus bar 24N run parallel to each other.

[0041] Insulating member 25 is interposed between P bus bar 24P and N bus bar 24N, and insulates and separates P bus bar 24P and N bus bar 24N. Insulating member 25 is, for example, a resin molded body. Insulating member 25 extends to a position where it overlaps with main surface 302 of sealing body 30 in a plan view in the Z direction. When P bus bar 24P and N bus bar 24N are configured as elements separate from semiconductor module 21, P bus bar 24P, N bus bar 24N, and insulating member 25 may be referred to as a bus bar unit.

[0042] The output bus bar 24A is a wiring member that electrically connects the semiconductor module 21 and the motor generator 3. The output bus bar 24A is connected to the output terminal 80A of the semiconductor module 21. A bus bar provided in an output terminal block or a current sensor (not shown) may also serve as the output bus bar 24A.

[0043] The power conversion device 20 may be configured without the P bus bar 24P and the N bus bar 24N. In this case, the P bus bar 222P of the capacitor module 22 is connected to the P terminal 80P of the semiconductor module 21, and the N bus bar 222N is connected to the N terminal 80N.

[0044] <Semiconductor module> FIG. 4 is a perspective view of an example of a semiconductor module. FIG. 5 is a see-through view of the encapsulant shown in FIG. 4 . A cooler is also shown in FIGS. 4 and 5 . FIG. 6 is a cross-sectional view corresponding to FIG. 3 . FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 5 . Bus bars connected to the terminals are also shown in FIGS. 6 and 7 . The internal structure of the encapsulant is expanded in the Z direction to facilitate understanding. FIG. 8 is a top plan view of a semiconductor module. FIG. 9 is a plan view showing the configuration of FIG. 8 , omitting the substrate and encapsulant on the source electrode side. FIG. 10 is a plan view showing the configuration of FIG. 8 , omitting the encapsulant. In FIG. 10 , to clarify the positional relationship, the surface metal body of the substrate on the source electrode side is indicated by a solid line, and the surface metal body of the substrate on the drain electrode side is indicated by a partially dashed line. The semiconductor element, front-to-back connections, and joints are also shown by solid lines. FIG. 11 is a plan view showing the substrate on the source electrode side.

[0045] As described above, the semiconductor module 21 constitutes the upper and lower arm circuits 9, i.e., the inverter 6. The illustrated semiconductor module 21 constitutes one of the upper and lower arm circuits 9, which are series circuits, i.e., one phase of the upper and lower arm circuit 9. The semiconductor module 21 may also be referred to as a semiconductor device, a power module, or the like. As shown in FIGS. 2 to 11 , the semiconductor module 21 includes a sealing body 30, a semiconductor element 40, substrates 50 and 60, a conductive spacer 70, a joint portion 71, and an external connection terminal. The semiconductor module 21 further includes a relay substrate 90.

[0046] The sealing body 30 seals some of the other elements that make up the semiconductor module 21. The remaining parts of the other elements are exposed to the outside of the sealing body 30. The sealing body 30 is formed using a resin material. The sealing body 30 is, for example, a resin molded body. The sealing body 30 shown in the example is molded by a transfer molding method using epoxy resin as the material.

[0047] The sealing body 30 has a substantially rectangular planar shape. The sealing body 30 has main surfaces 301 and 302 and side surfaces 303, 304, 305, and 306 as surfaces forming its outer periphery. The main surface 302 is the surface opposite the main surface 301 in the Z direction. The main surfaces 301 and 302 are, for example, substantially flat surfaces. Of the main surfaces 301 and 302, the surface on which the second terminal (N terminal 80N) is exposed may be referred to as the top surface, and the other may be referred to as the bottom surface. In the illustrated semiconductor module 21, the main surface 302 is the top surface. The side surfaces 303, 304, 305, and 306 are continuous with the main surfaces 301 and 302. The side surface 304 is the surface opposite the side surface 303 in the X direction. The side surface 306 is the surface opposite the side surface 305 in the Y direction.

[0048] The semiconductor element 40 is formed by forming a switching element on a semiconductor substrate made of silicon (Si) or a wide bandgap semiconductor with a wider bandgap than silicon. Examples of wide bandgap semiconductors include silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), and diamond. The semiconductor element 40 is sometimes called a power element or a semiconductor chip.

[0049] The illustrated semiconductor element 40 includes the n-channel MOSFET 11 formed on a semiconductor substrate made of SiC. The MOSFET 11 has a vertical structure such that a main current flows in the thickness direction of the semiconductor element 40 (semiconductor substrate), i.e., in the Z direction. The semiconductor element 40 has main electrodes of a switching element on both sides of the semiconductor element 40 in the thickness direction, i.e., in the Z direction. The semiconductor element 40 has, as main electrodes, a drain electrode 41D on one side and a source electrode 41S on the back side. When the diode 12 is a parasitic diode, the source electrode 41S also serves as an anode electrode, and the drain electrode 41D also serves as a cathode electrode. The diode 12 may be formed on a chip separate from the MOSFET 11. The drain electrode 41D is a main electrode on the high-potential side, and the source electrode 41S is a main electrode on the low-potential side.

[0050] The semiconductor element 40 has a generally rectangular shape in plan view. The semiconductor element 40 has a pad 41P formed on the back surface at a position different from the source electrode 41S. The source electrode 41S and the pad 41P are exposed from a protective film (not shown) formed on the back surface of the semiconductor substrate. The drain electrode 41D is formed on almost the entire surface. The source electrode 41S is formed on a portion of the back surface of the semiconductor element 40. The pad 41P is a signal electrode. The pad 41P includes a pad for a gate electrode. The illustrated pad 41P is formed at the end opposite the formation region of the source electrode 41S in the X direction.

[0051] The semiconductor module 21 includes a plurality of semiconductor elements 40. The plurality of semiconductor elements 40 may include a plurality of types of semiconductor elements with different specifications. As in the illustrated semiconductor module 21, all of the semiconductor elements 40 may have a common configuration. The plurality of semiconductor elements 40 include a semiconductor element 40H that constitutes an upper arm 9H and a semiconductor element 40L that constitutes a lower arm 9L. The semiconductor element 40H may be referred to as an upper arm element, and the semiconductor element 40L may be referred to as a lower arm element.

[0052] The semiconductor elements 40H and 40L are aligned in the X direction. The semiconductor elements 40H and 40L are arranged at approximately the same position as each other in the Z direction. The drain electrodes 41D of the semiconductor elements 40H and 40L face the substrate 50. The source electrodes 41S of the semiconductor elements 40H and 40L face the substrate 60. If the number of switching elements constituting each arm 9H and 9L is, for example, two, the semiconductor module 21 includes two semiconductor elements 40H and two semiconductor elements 40L. The two semiconductor elements 40H are aligned in the Y direction. Similarly, the two semiconductor elements 40L are aligned in the Y direction.

[0053] Semiconductor element 40H is disposed such that pad 41P is located on the side surface 303 side relative to source electrode 41S. Semiconductor element 40L is disposed such that pad 41P is located on the side surface 304 side relative to source electrode 41S.

[0054] The substrates 50 and 60 are arranged to sandwich the multiple semiconductor elements 40 in the Z direction. The substrates 50 and 60 are arranged so that at least a portion of each substrate faces the other in the Z direction. The substrates 50 and 60 contain all of the multiple semiconductor elements 40 in a planar view. The substrate 50 is arranged on the drain electrode 41D side. The substrate 60 is arranged on the source electrode 41S side. The substrate 50 is electrically connected to the drain electrode 41D and provides a wiring function. The substrate 60 is electrically connected to the source electrode 41S and provides a wiring function. The substrates 50 and 60 provide a heat dissipation function that dissipates heat generated by the semiconductor elements 40.

[0055] The substrate 50 includes an insulating substrate 51, a front metal body 52, and a back metal body 53. The substrate 60 includes an insulating substrate 61, a front metal body 62, a back metal body 63, a front-back connection portion 64, and a metal block body 65. The insulating substrates 51, 61 are substrates containing an electrically insulating material such as resin or ceramic. Exemplary insulating substrates 51, 61 include epoxy resin as a material. The insulating substrate 51 is interposed between the front metal body 52 and the back metal body 53 so as to electrically isolate the front metal body 52 and the back metal body 53. The insulating substrate 61 is interposed between the front metal body 62 and the back metal body 63 so as to electrically isolate the front metal body 62 and the back metal body 63. The front metal body 52 is disposed on the front surface of the insulating substrate 51, and the back metal body 53 is disposed on the back surface of the insulating substrate 51. A front surface metal body 62 is disposed on the front surface of the insulating substrate 61, and a back surface metal body 63 is disposed on the back surface of the insulating substrate 61.

[0056] The front surface metal bodies 52, 62 and the back surface metal bodies 53, 63 are provided as metal plates or metal foils. The front surface metal bodies 52, 62 and the back surface metal bodies 53, 63 are made of a metal with good electrical and thermal conductivity, such as Cu or Al. The front surface metal bodies 52, 62 are patterned. The front surface metal bodies 52, 62 may have a plating film of Ni or Au on the metal surface. The front surface metal body 52 has a P wiring 521, a relay wiring 522, and an island 523. The P wiring 521, the relay wiring 522, and the island 523 are electrically isolated by a predetermined gap (spacing). The gap is filled with the sealing body 30.

[0057] The P wiring 521 is connected to the P terminal 80P and the drain electrode 41D of the semiconductor element 40H. The P wiring 521 electrically connects the P terminal 80P and the drain electrode 41D of the semiconductor element 40H. The relay wiring 522 is connected to the drain electrode 41D of the semiconductor element 40L, the joint part 71, and the output terminal 80A. The relay wiring 522 electrically connects the output terminal 80A and the drain electrode 41D of the semiconductor element 40L. A relay substrate 90 is mounted on the island 523.

[0058] The illustrated P wiring 521 has a substantially U-shape in plan view. The P wiring 521 has a base extending in the Y direction and a pair of extension portions that are connected to the base and extend from both ends of the base in the X direction toward the side surface 303. The base is provided so as to overlap the semiconductor element 40H in plan view. An island 523 is provided between the extension portions. A relay substrate 90H is disposed on the island 523. The relay wiring 522 also has a substantially U-shape in plan view. The relay wiring 522 has a base extending in the Y direction and a pair of extension portions that are connected to the base and extend from both ends of the base in the X direction toward the side surface 304. The base is provided so as to overlap the semiconductor element 40L in plan view. The island 523 is provided between the extension portions. A relay substrate 90L is disposed on the island 523. The P wiring 521 and the relay wiring 522 are aligned in the X direction so that their bases face each other.

[0059] P terminal 80P is connected to the P wiring 521 near the end on the side surface 303 side. Drain electrode 41D of semiconductor element 40H is connected to P wiring 521 at a position closer to relay wiring 522 than the joint with P terminal 80P. Output terminal 80A is connected to the relay wiring 522 near the end on the side surface 304 side. Drain electrode 41D of semiconductor element 40L is connected to relay wiring 522 at a position closer to P wiring 521 than the joint with output terminal 80A. Joint portion 71 is connected to relay wiring 522 at a position closer to P wiring 521 than the joint with semiconductor element 40L.

[0060] The surface metal body 62 has an N wiring 621 and a relay wiring 622. The N wiring 621 and the relay wiring 622 are electrically separated by a predetermined gap (spacing). This gap is filled with the sealing body 30. The N wiring 621 is connected to the source electrode 41S of the semiconductor element 40L. The relay wiring 622 is connected to the source electrode 41S of the semiconductor element 40H and a joint 71. The relay wiring 622 electrically connects the source electrode 41S of the semiconductor element 40H and the drain electrode 41D of the semiconductor element 40L via the joint 71.

[0061] The illustrated N wiring 621 has a substantially U-shape in plan view. The N wiring 621 has a base extending in the Y direction and a pair of extension portions that are connected to the base and extend from both ends of the base in the X direction toward the side surface 303. The base is provided so as to overlap with the semiconductor element 40L in plan view. The relay wiring 622 has a substantially convex shape in plan view. The relay wiring 622 has a base extending in the Y direction and an extension portion that is connected to the base and extends from the center of the base in the X direction toward the side surface 304. The base is provided so as to overlap with the semiconductor element 40H in plan view. The extension portion of the relay wiring 622 is disposed between the pair of extension portions of the N wiring 621. The N wiring 621 and the relay wiring 622 are aligned in the X direction. The extension portion of the N wiring 621 and the extension portion of the relay wiring 622 are aligned in the Y direction.

[0062] The source electrode 41S of the semiconductor element 40L is connected to the base of the N wiring 621. The source electrode 41S of the semiconductor element 40H is connected to the base of the relay wiring 622. The joint portion 71 is connected to the extended portion of the relay wiring 622.

[0063] The back surface metal body 53 is electrically isolated from the front surface metal body 52 by the insulating base material 51. The illustrated back surface metal body 53 is a so-called solid conductor arranged over almost the entire back surface of the insulating base material 51. The back surface metal body 53 is exposed from the main surface 301 of the encapsulant 30. The back surface metal body 53 is exposed and is approximately flush with the main surface 301. The back surface metal body 63 is electrically connected to the N wiring 621 of the front surface metal body 62 by a front-back connection portion 64. The back surface metal body 63 is electrically isolated from the relay wiring 622 by the insulating base material 61. The illustrated back surface metal body 63 is a so-called solid conductor arranged over almost the entire back surface of the insulating base material 61. The back surface metal body 53 is covered by the encapsulant 30. The back surface metal body 63 is arranged so as to overlap all of the P wiring 521 and most of the relay wiring 522 in a plan view.

[0064] The front-back connection portion 64 electrically connects the front metal body 62 and the back metal body 63. The front-back connection portion 64 electrically connects the N wiring 621 and the back metal body 63. The front-back connection portion 64 may be configured, for example, to include a through portion that penetrates the insulating substrate 61 in the Z direction and a conductor that is disposed in the through portion and electrically connects the front metal body 62 and the back metal body 63. The exemplary front-back connection portion 64 has a through hole 641 that penetrates the insulating substrate 61 and the front metal body 62 with the back metal body 63 at the bottom, and a conductor 642 that is disposed in the through hole 641. The through hole 641 is formed, for example, by drilling or laser processing. The conductor 642 is a joining material such as solder. The front-back connection portion 64 is provided on each extended portion of the N wiring 621.

[0065] The metal block 65 is a metal member connected to the back surface metal body 63. The metal block 65 is disposed on the surface of the back surface metal body 63 opposite to the surface on the insulating substrate 61 side. The metal block 65 is made of a metal material such as Cu that has good electrical and thermal conductivity. The metal block 65 is exposed from the main surface 302 of the sealing body 30.

[0066] The illustrated metal block body 65 has a generally rectangular shape in plan view with the Y direction as the longitudinal direction. The metal block body 65 is exposed to the outside of the sealing body 30, approximately flush with the main surface 302. The metal block body 65 is provided at a position closer to the side surface 303 than the semiconductor element 40H in the X direction. The metal block body 65 is provided so as to overlap the connection portion between the P terminal 80P and the P wiring 521 in a plan view. In other words, the metal block body 65 is electrically connected to the back surface metal body 63 at a position close to the side surface 303.

[0067] The conductive spacer 70 functions as a spacer to ensure a predetermined distance between the semiconductor element 40 and the substrate 60. The conductive spacer 70 ensures a height required to electrically connect the corresponding signal terminal 81 to, for example, the pad 41P of the semiconductor element 40. The conductive spacer 70 is located midway along the electrical and thermal conduction path between the source electrode 41S of the semiconductor element 40 and the substrate 60, providing wiring and heat dissipation functions. The conductive spacer 70 includes a metal material with good electrical and thermal conductivity, such as Cu. The conductive spacer 70 may have a plating film on its surface. The conductive spacer 70 is a generally rectangular columnar body having approximately the same size as the source electrode 41S in a planar view.

[0068] The conductive spacers 70 may also be referred to as terminals or the like. The semiconductor module 21 includes the same number of conductive spacers 70 as the semiconductor elements 40. Specifically, the conductive spacers 70 include conductive spacers 70H and 70L. The conductive spacer 70H electrically connects the source electrode 41S of the semiconductor element 40H to the relay wiring 622. The conductive spacer 70L electrically connects the source electrode 41S of the semiconductor element 40L to the N wiring 621.

[0069] The joint 71 electrically connects the relay wirings 522, 622. That is, the joint 71 electrically connects the upper arm 9H and the lower arm 9L. The joint 71 is provided between the semiconductor element 40H and the semiconductor element 40L in the X direction. The joint 71 is disposed in an overlapping region of the relay wirings 522, 622 in a plan view. The joint 71 may include a bonding material or a metal member. The joint 71 may include a bonding material and a metal member. The illustrated joint 71 includes a metal columnar body provided separately from the surface metal bodies 52, 62. The joint 71 extends in the Z direction. One end of the joint 71 is connected to the relay wiring 522, and the other end is connected to the relay wiring 622.

[0070] The joint portion 71 may be integrally connected to the surface metal bodies 52, 62. In other words, the joint portion 71 may be provided integrally with the surface metal bodies 52, 62 as part of the substrates 50, 60. A part of the joint portion 71 may be provided as part of the substrate 50, and another part of the joint portion 71 may be provided as part of the substrate 60.

[0071] The external connection terminals are terminals for electrically connecting the semiconductor module 21 to external devices. The external connection terminals are formed using a metal material with good conductivity, such as Cu. The external connection terminals are exposed to the outside of the sealing body 30. The external connection terminals include a main terminal 80 and a signal terminal 81. The main terminal 80 is electrically connected to a main electrode of the semiconductor element 40. The main terminals 80 include a P terminal 80P, an N terminal 80N, and an output terminal 80A. The P terminal 80P and the N terminal 80N are sometimes referred to as power supply terminals. The output terminal 80A is sometimes referred to as an O terminal, an AC terminal, etc.

[0072] The P terminal 80P protrudes from the side surface 303 to the outside of the sealing body 30. The P terminal 80P is connected to the vicinity of one end of the P wiring 521 in the X direction. A portion of the P terminal 80P is covered by the sealing body 30, and another portion protrudes to the outside of the sealing body 30. A joint portion of the P terminal 80P with the P wiring 521 is covered by the sealing body 30. The illustrated P terminal 80P extends approximately in the X direction. The semiconductor module 21 includes two P terminals 80P. The P terminals 80P are connected to each of a pair of extension portions of the P wiring 521. The P terminal 80P is electrically connected to the drain electrode 41D of the semiconductor element 40H via the P wiring 521.

[0073] The N terminal 80N is exposed to the outside of the sealing body 30 from the main surface 302. The illustrated N terminal 80N is a portion of the metal block body 65 that is exposed on the main surface 302. The N terminal 80N is exposed to be approximately flush with the main surface 302. The N terminal 80N is electrically connected to the source electrode 41S of the semiconductor element 40L via the metal block body 65, the back surface metal body 63, the front / back connection portion 64, the N wiring 621, and the conductive spacer 70L.

[0074] The output terminal 80A protrudes from the side surface 304 to the outside of the sealing body 30. The output terminal 80A is connected to the relay wiring 522 near one end in the X direction. A portion of the output terminal 80A is covered by the sealing body 30, and another portion protrudes to the outside of the sealing body 30. The joint portion of the output terminal 80A with the relay wiring 522 is covered by the sealing body 30. The illustrated output terminal 80A extends generally in the X direction. The semiconductor module 21 includes two output terminals 80A. The output terminals 80A are connected to the pair of extension portions of the relay wiring 522, respectively. The output terminal 80A is electrically connected to the drain electrode 41D of the semiconductor element 40L via the relay wiring 522. The output terminal 80A is electrically connected to the source electrode 41S of the semiconductor element 40H via the relay wiring 522, the joint portion 71, the relay wiring 622, and the conductive spacer 70H.

[0075] The signal terminals 81 are electrically connected to the corresponding pads 41P of the semiconductor element 40. A portion of the signal terminals 81, including the connection portion with the pads 41P, is covered by the sealing body 30, and another portion protrudes from the sealing body 30. The signal terminals 81 include signal terminals 81H and 81L. The signal terminal 81H is electrically connected to the pad 41P of the semiconductor element 40H. The signal terminal 81L is electrically connected to the pad 41P of the semiconductor element 40L. The illustrated signal terminals 81 are connected to the corresponding pads 41P via bonding wires (not shown).

[0076] The signal terminal 81 is substantially L-shaped in the ZX plane. The signal terminal 81H extends in the Y direction and protrudes from the side surface 303 to the outside of the sealing body 30. The signal terminal 81H is bent outside the sealing body 30 and extends toward the main surface 302 in the Z direction. The signal terminal 81H is disposed between the pair of P terminals 80P in the X direction. The signal terminal 81L extends in the Y direction and protrudes from the side surface 304 to the outside of the sealing body 30. The signal terminal 81L is bent outside the sealing body 30 and extends toward the main surface 302 in the Z direction. The signal terminal 81L is disposed between the pair of output terminals 80A in the X direction.

[0077] The relay board 90 electrically connects the signal terminals 81 and the pads 41P. The relay board 90 is a printed circuit board. The relay board 90 has wiring arranged on an insulating base material. The relay board 90 is arranged on the island 523. The relay board 90 includes relay boards 90H and 90L. The pads 41P of the semiconductor element 40H and the signal terminals 81H are electrically connected via the wiring of the relay board 90H. The pads 41P of the semiconductor element 40L and the signal terminals 81H are electrically connected via the wiring of the relay board 90L. Note that the semiconductor module 21 may not include the relay board 90. For example, the signal terminals 81 and the corresponding pads 41P may be connected by bonding wires.

[0078] The semiconductor module 21 includes a bonding material (not shown). The bonding material may be solder or a sintered material. The drain electrode 41D of the semiconductor element 40 is connected to the surface metal body 52 via a bonding material. The source electrode 41S of the semiconductor element 40 is connected to the conductive spacer 70 via a bonding material. The conductive spacer 70 is connected to the surface metal body 62 via a bonding material. The joint portion 71 is connected to the surface metal bodies 52, 62 via a bonding material, for example. The multiple bonding materials may be made of a common material, or the material of some of the bonding materials may be different from the material of the other bonding materials.

[0079] The P terminal 80P and the output terminal 80A may be connected to the front surface metal body 52 by the above-mentioned bonding material. The P terminal 80P and the output terminal 80A may be solid-state bonded to the front surface metal body. Examples of solid-state bonding include ultrasonic bonding, room temperature bonding, friction stir bonding, diffusion bonding, and friction welding. The metal block body 65 constituting the N terminal 80N may be connected to the back surface metal body 63 by the above-mentioned bonding material.

[0080] As described above, in the semiconductor module 21, the sealing body 30 seals the multiple semiconductor elements 40 that constitute one phase of the upper and lower arm circuits 9. The sealing body 30 integrally seals the multiple semiconductor elements 40, part of the substrate 50, part of the substrate 60, the multiple conductive spacers 70, the joint portion 71, and parts of the external connection terminals. The sealing body 30 seals the insulating base materials 51, 61, the front surface metal bodies 52, 62, and the back surface metal body 63 of the substrates 50, 60.

[0081] The semiconductor element 40 is disposed between the substrates 50 and 60 in the Z direction. The semiconductor element 40 is sandwiched between the substrates 50 and 60, which are disposed opposite each other. This allows heat from the semiconductor element 40 to be dissipated to both sides in the Z direction. The semiconductor module 21 has a double-sided heat dissipation structure. The back surface metal body 53 is exposed from the sealing body 30 and is approximately flush with the main surface 301. The back surface metal body 63 is covered by the sealing body 30. The metal block body 65 connected to the back surface metal body 63 is exposed from the sealing body 30 and is approximately flush with the main surface 302. This structure can improve heat dissipation.

[0082] Alternatively, the sealing body 30 may be molded so as to completely cover the substrates 50 and 60, and then cut after molding to expose the back surface metal body 53 and the metal block body 65 (N terminal 80N) from the sealing body 30. For example, by cutting the sealing body 30 together with a portion of the metal block body 65, the metal block body 65 becomes approximately flush with the main surface 302. Alternatively, the sealing body 30 may be molded while the back surface metal body 53 and the metal block body 65 are pressed against the cavity wall surface of a molding die and in close contact with each other. In this case, when the sealing body 30 is molded, the back surface metal body 53 and the metal block body 65 are exposed from the sealing body 30 and approximately flush with the corresponding main surfaces 301 and 302. This eliminates the need for cutting after molding.

[0083] <Summary of the First Embodiment> The semiconductor module 21 of this embodiment includes a first terminal, a second terminal, a plurality of semiconductor elements 40 including a first semiconductor element and a second semiconductor element aligned in a predetermined direction perpendicular to the plate thickness direction, and a sealing body 30 that seals the plurality of semiconductor elements 40. The first terminal, the second terminal, the first semiconductor element, and the second semiconductor element are arranged on the first terminal side, and the first semiconductor element and the second semiconductor element form a series circuit in which the first semiconductor element and the second semiconductor element are connected in series between the first terminal and the second terminal. The first terminal protrudes from the sealing body 30 in a predetermined direction from a side surface 303 of the sealing body 30 facing the first semiconductor element, and the second terminal is exposed from the sealing body 30 from a main surface 302, which is one of the surfaces of the sealing body 30 that are continuous with the side surface 303.

[0084] In the illustrated semiconductor module 21, the P terminal 80P corresponds to the first terminal, and the N terminal 80N corresponds to the second terminal. The semiconductor element 40H corresponds to the first semiconductor element, and the semiconductor element 40L corresponds to the second semiconductor element. The Z direction corresponds to the plate thickness direction, and the X direction corresponds to the predetermined direction. The upper and lower arm circuits 9 correspond to the series circuit.

[0085] As described above, in a configuration in which the first element and the second element are aligned in a predetermined direction, only the first terminal of the series circuit protrudes from the side surface 303 of the sealing body 30, and the second terminal of the series circuit is exposed from the main surface 302 of the sealing body. This ensures a sufficient creepage distance between the first terminal and the second terminal. Furthermore, to electrically connect the second terminal and the second semiconductor element, it is not necessary to route the series circuit so as to avoid the first semiconductor element when viewed in a plan view in the plate thickness direction. For example, it is not necessary to extend the N wiring 621 toward the side surface 303 so as to avoid the relay wiring 622 to which the semiconductor element 40H is connected. As a result, it is possible to reduce inductance while suppressing an increase in size.

[0086] According to the above structure, the first bus bar connected to the first terminal protruding from side surface 303 and the second bus bar connected to the second terminal exposed from main surface 302 can be drawn in the same direction and run parallel to each other, thereby further reducing inductance.

[0087] Here, Fig. 12 is a plan view showing a reference example of a semiconductor module. Fig. 13 is a diagram showing the magnetic field strength distribution of the reference example. Fig. 14 is a diagram showing the magnetic field strength distribution of the configuration (this example) exemplified in this embodiment. Figs. 13 and 14 show simulation results. Figs. 13 and 14 also show a capacitor module and a bus bar connecting the semiconductor module and the capacitor module. In Figs. 13 and 14, the higher the magnetic field strength, the denser the dots.

[0088] The semiconductor module 21R of the reference example shown in FIG. 12 has the configuration described in Japanese Patent Application Laid-Open No. 2022-181823 (see, for example, FIGS. 3 and 4). The semiconductor module 21R includes a sealing body 30, semiconductor elements 40H and 40L, substrates 50 and 60, a joint portion 71, and an external connection terminal. Unlike the semiconductor module 21, the semiconductor module 21R has an N-terminal 80N drawn out from the side surface 303. The N-terminal 621 of the front surface metal body 62 has a base and a pair of extension portions. The pair of extension portions extend toward the side surface 303 in a detour to avoid the relay wiring 622. The N-terminals 80N are connected to the tip portions of the pair of extension portions, respectively. The N-terminals 80N protrude from the side surface 303 to the outside of the sealing body 30. The N-terminal 80N and the P-terminal 80P are arranged side by side in the X direction with their side surfaces facing each other. The P wiring 521 of the front surface metal body 52 is widened in the Y direction so as to face the extended portion of the N wiring 621 .

[0089] In this structure in which the P terminal 80P and the N terminal 80N are drawn out from the same side surface 303, current concentration was observed at the extended portion of the N wiring 621 and the portion of the P terminal 80P and the N terminal 80N facing each other on the side surfaces, as shown in FIG. 13. As a result, the total inductance of the semiconductor module 21R and the bus bar was 7.4 nH. On the other hand, in a structure in which the P terminal 80P is drawn out from the side surface 303 and the N terminal 80N is exposed from the main surface 302, no local current concentration was observed, as shown in FIG. 14. As a result, the total inductance of the semiconductor module 21R and the bus bar was 5.0 nH. As such, the simulation results clearly demonstrate that inductance can be reduced while suppressing an increase in size.

[0090] As illustrated, semiconductor module 21 may include a first bus bar electrically connected to the first terminal and a second bus bar electrically connected to the second terminal and arranged parallel to the first bus bar with their plate surfaces facing each other. In a configuration in which semiconductor module 21 includes bus bars 24, P bus bar 24P corresponds to the first bus bar, and N bus bar 24N corresponds to the second bus bar. Arranging the first bus bar and the second bus bar parallel to each other can further reduce inductance in semiconductor module 21.

[0091] As shown in the example, semiconductor module 21 may be configured to include an insulating member interposed between the first bus bar and the second bus bar, and the insulating member may extend to a position where it overlaps with main surface 302 of sealing body 30. Insulating member 25 interposed between P bus bar 24P and N bus bar 24N corresponds to the insulating member. In this configuration, in which the second terminals are exposed from main surface 302, it is possible to ensure insulation between the first bus bar and the second bus bar while reducing inductance by running them side by side.

[0092] As illustrated, the semiconductor module 21 may include a substrate including a first wiring and a second wiring as a surface metal body, with the first main electrode of the first semiconductor element connected to the first wiring and the first main electrode of the second semiconductor element connected to the second wiring. Furthermore, the series circuit may include the first wiring and the second wiring, the sealing body 30 seals the semiconductor element 40 and the substrate, and the first terminal is electrically connected to the first semiconductor element via the first wiring. In the illustrated semiconductor module 21, the substrate 50 corresponds to the substrate, and the surface metal body 52 corresponds to the surface metal body. The P wiring 521 corresponds to the first wiring, and the relay wiring 522 corresponds to the second wiring. Using a substrate can simplify the electrical connection structure of the series circuit including the semiconductor element 40 while achieving the above-described effects.

[0093] As illustrated, one of the first semiconductor element and the second semiconductor element may be an upper arm element that constitutes the upper arm 9H of the upper / lower arm circuit 9, and the other may be a lower arm element that constitutes the lower arm 9L of the upper / lower arm circuit 9. This makes it possible to achieve the above-described effects in the upper / lower arm circuit 9, which is a series circuit, that is, in the semiconductor module 21 that constitutes the inverter 6.

[0094] As illustrated, the semiconductor module 21 may include a second substrate including third and fourth wiring as the second front-surface metal body, and a joint portion 71. The second main electrode of the first semiconductor element may be electrically connected to the third wiring, and the second main electrode of the second semiconductor element may be electrically connected to the second back-surface metal body via the fourth wiring. The third wiring is provided so as to overlap at least a portion of the first wiring and the first semiconductor element in a plan view in the plate thickness direction, and the fourth wiring is provided so as to overlap at least a portion of the second wiring and the second semiconductor element in a plan view, and is aligned in a predetermined direction relative to the third wiring. The joint portion 71 electrically connects the second wiring and the third wiring. In addition, the second terminal may be a metal member connected to the second back-surface metal body, and the second back-surface metal body and the first wiring may face each other in the plate thickness direction.

[0095] In the illustrated semiconductor module 21, the substrate 50 corresponds to the first substrate, and the substrate 60 corresponds to the second substrate. The front surface metal body 62 corresponds to the second front surface metal body, and the back surface metal body 63 corresponds to the second back surface metal body. The relay wiring 622 corresponds to the third wiring, and the N wiring 621 corresponds to the fourth wiring. The metal block body 65 corresponds to the metal member. By using two substrates 50 and 60, the electrical connection structure of the series circuit including the semiconductor element 40 can be further simplified. Furthermore, since the second back surface metal body is used as wiring electrically connecting the second main electrode and the second terminal of the second semiconductor element, it is not necessary to extend the fourth wiring toward the side surface 303 so as to avoid the third wiring in a plan view in the plate thickness direction. This eliminates an increase in the physical size. Since the second back surface metal body faces the first wiring in the plate thickness direction, inductance can be reduced.

[0096] As illustrated, a through-hole may be provided in the second insulating base material of the second substrate, and the fourth wiring and the second back surface metal body may be electrically connected by a conductor arranged in the through-hole. The insulating base material 61 corresponds to the second insulating base material, and the through-hole 641 corresponds to the through-hole. The conductor 642 corresponds to the conductor. This allows the second main electrode of the second semiconductor element to be electrically connected to the second terminal without adding any components in a configuration including a first substrate and a second substrate. Note that a notch may also serve as the through-hole.

[0097] As shown in the example, the second terminal may be provided at a position closer to the side surface 303 than the first semiconductor element in a predetermined direction. This increases the opposing distance between the second back surface metal body and the first wiring in a configuration including a first substrate and a second substrate, thereby effectively reducing inductance. As shown in the example, in a configuration in which a first bus bar is connected to the first terminal and a second bus bar is connected to the second terminal, at least a portion of the second bus bar may be configured to oppose the first wiring in the plate thickness direction. This reduces inductance.

[0098] As illustrated, the second terminal may be provided so as to overlap the connection portion between the first terminal and the first wiring in plan view, thereby increasing the opposing distance between the second back surface metal body and the first wiring in a configuration including a first substrate and a second substrate, thereby effectively reducing inductance.

[0099] As illustrated, a signal terminal may be provided that is electrically connected to the semiconductor element 40 and protrudes from the side surface 303 of the sealing body 30 together with the first terminal. In the illustrated semiconductor module 21, the signal terminal 81H corresponds to the signal terminal. The signal terminal is configured as part of the lead frame together with the first terminal. This simplifies the configuration. In the illustrated semiconductor module 21, the P terminal 80P, the output terminal 80A, and the signal terminals 81H and 81L are configured as part of the lead frame.

[0100] <Modification> Although an example in which the P terminal 80P protrudes from the side surface 303 and the N terminal 80N is exposed on the main surface 302 has been shown, this is not limiting. A configuration in which the N terminal 80N protrudes from the side surface 303 and the P terminal 80P is exposed on the main surface 302 may also be used. The semiconductor element 40L is disposed on the side surface 303 side. The substrate on the main surface 301 side has, as a surface metal body, an N wiring and a relay wiring disposed on the side surface 303 side. The source electrode 41S and the N terminal of the semiconductor element 40L are connected to the N wiring. The N terminal protrudes from the side surface 303 to the outside of the encapsulant 30. The source electrode 41S and the output terminal 80A of the semiconductor element 40H are connected to the relay substrate. The substrate on the main surface 302 side has, as a surface metal body, a P wiring and a relay wiring disposed on the side surface 303 side. The drain electrode 41D of the semiconductor element 40L is connected to the relay wiring. The drain electrode 41D of the semiconductor element 40H is connected to the P wiring. The P wiring is connected to the P terminal 80P via the front and back connection portion, the back metal body, and the metal block body.

[0101] Although an example has been shown in which the metal block body 65 (metal member) forms the N terminal 80N (second terminal), this is not limiting. For example, as shown in Fig. 15, a portion of the back surface metal body 63 that is exposed from the main surface 302 of the sealing body 30 may be the N terminal 80N. Fig. 15 corresponds to Fig. 6.

[0102] The configuration of the front-back connection portion 64 is not limited to the above example. For example, as shown in FIG. 16, the N wiring 621 (fourth wiring) and the back surface metal body 63 may be electrically connected at the outer peripheral edge of the substrate 60 (second substrate). FIG. 16 corresponds to FIG. 11. In FIG. 16, a welded portion 643 forms the front-back connection portion 64. In FIG. 16, the back surface metal body 63 protrudes from the insulating base material 61 in the X direction. The welded portion 643 is formed by welding the protruding portion of the back surface metal body 63 to the N wiring 621. The welded portion 643 extends in the Y direction along the outer peripheral edge. The insulating base material 61 may be melted by heating to connect the N wiring 621 and the back surface metal body 63.

[0103] As shown in FIG. 17 , a wiring member 644 may form the front / back connection portion 64. The wiring member 644 is, for example, a metal plate such as a clip, a flexible substrate, or the like. One end of the wiring member 644 is connected to the N wiring 621, and the other end is connected to the back surface metal body 63. The wiring member 644 is substantially U-shaped in the ZX plane. The shape and arrangement of the wiring member 644 are not limited to the example shown in FIG. 17 . For example, in the board configuration shown in FIG. 16 , the protruding portion of the back surface metal body 63 and the N wiring 621 may be electrically connected by the wiring member 644. A metal member (wiring member 644) such as a metal block may be disposed on the side of the board 60, and the metal member may be joined to the N wiring 621 and the back surface metal body 63.

[0104] In the example shown in FIG. 18, the N wiring 621 has only a base portion. A portion of the insulating base material 61 corresponding to the extended portion of the N wiring 621 has been removed. The insulating base material 61 has a removed portion 645. The removed portion 645 is a notch. The back surface metal body 63 has an exposed portion 646 that is exposed on the front surface metal body 62 side through the removed portion 645. The exposed portion 646 is electrically connected to the N wiring 621 via a wiring member 644 such as a clip, a bonding wire, or a flexible substrate. FIG. 18 corresponds to FIG. 11.

[0105] (Second embodiment) This embodiment is a modification of the previous embodiment, and the description of the previous embodiment can be used. In the previous embodiment, the second main electrode of the second semiconductor element and the second back surface metal body were electrically connected via the front / back connection portion of the second substrate. The second main electrode of the second semiconductor element and the second back surface metal body may be electrically connected by a different connection structure. In the previous embodiment, the second substrate was arranged so as to overlap with the second semiconductor element in a plan view. Alternatively, the second substrate may be arranged so as not to overlap with the second semiconductor element.

[0106] Fig. 19 is a cross-sectional view showing an example of a semiconductor module according to this embodiment. Fig. 19 corresponds to Fig. 7. That is, bus bars connected to the terminals are also shown.

[0107] 19 includes a sealing body 30, semiconductor elements 40H and 40L, substrates 50 and 60, a conductive spacer 70, a joint portion 71, and external connection terminals, as in the configuration described in the preceding embodiment. The P-terminal 80P protrudes from a side surface 303. The N-terminal 80N is exposed on a main surface 302 of the sealing body 30. The N-terminal 80N is formed by a metal block body 65 connected to a back surface metal body 63.

[0108] The substrate 60 is arranged so as to overlap the semiconductor element 40H and the joint portion 71 in a plan view, but not the semiconductor element 40L. The substrate 60 is arranged so as to overlap the entire P wiring 521 and part of the relay wiring 522 in a plan view. The front surface metal body 62 has only the relay wiring 622. The substrate 60 has a configuration in which the portion on the N wiring 621 side is removed from the configuration described in the preceding embodiment.

[0109] The semiconductor module 21 includes a wiring member 72. The wiring member 72 is a metal member such as a clip or a bonding wire. One end of the wiring member 72 is connected to the conductive spacer 70L, and the other end is connected to the rear surface metal body 63 near the end of the side surface 304. The wiring member 72 electrically connects the conductive spacer 70L and the rear surface metal body 63. The other configurations are the same as those described in the preceding embodiment.

[0110] <Summary of the second embodiment> As illustrated, the second substrate may be disposed so as to overlap the first semiconductor element but not the second semiconductor element in a plan view in the plate thickness direction. Then, the second main electrode of the second semiconductor element and the second back surface metal body may be electrically connected by a wiring member 72, and the metal member connected to the second back surface metal body may be used as the second terminal. The second back surface metal body and the first wiring may be opposed to each other in the plate thickness direction. In the illustrated semiconductor module 21, the semiconductor element 40H corresponds to the first semiconductor element, and the semiconductor element 40L corresponds to the second semiconductor element. The back surface metal body 63 corresponds to the second back surface metal body, and the P wiring 521 corresponds to the first wiring. The N terminal 80N is equivalent to the second terminal.

[0111] 6 and 7, the second back surface metal body is used as wiring that electrically connects the second main electrode and the second terminal of the second semiconductor element, so there is no need to extend the fourth wiring toward the side surface 303 to avoid the third wiring in a plan view in the plate thickness direction. This makes it possible to suppress an increase in the physical size. Since the second back surface metal body faces the first wiring in the plate thickness direction, inductance can be reduced.

[0112] It is also possible to combine the configuration described in the modified example of the preceding embodiment, in which the N-terminal 80N protrudes from the side surface 303 and the P-terminal 80P is exposed on the main surface 302, with the configuration using the wiring member 72. It is also possible to combine the configuration in which the portion of the back surface metal body 63 exposed on the main surface 302 of the sealing body 30 serves as the N-terminal 80N with the configuration using the wiring member 72.

[0113] (Third embodiment) This embodiment is a modification based on the previous embodiment, and the description of the previous embodiment can be used. In the previous embodiment, the second main electrode of the second semiconductor element and the second terminal are electrically connected via the second back surface metal body of the second substrate. The second main electrode of the second semiconductor element and the second back surface metal body may be electrically connected by a different connection structure. In the previous embodiment, a second substrate is provided. Alternatively, a configuration without a second substrate may be used.

[0114] Fig. 20 is a plan view showing an example of a semiconductor module according to this embodiment. Fig. 20 corresponds to Fig. 8. Fig. 21 is a plan view showing a configuration in which the sealing body is omitted from Fig. 20. Fig. 22 is a cross-sectional view taken along line XXII-XXII in Fig. 20. As with Figs. 6 and 7, Fig. 22 also shows bus bars connected to terminals. In addition, to make the internal structure of the sealing body easier to understand, the view is expanded in the Z direction.

[0115] 20 to 22 includes a sealing body 30, semiconductor elements 40H and 40L, a substrate 50, a wiring member 73, a metal block 74, and external connection terminals. The semiconductor module 21 does not include a substrate 60, a conductive spacer 70, or a joint portion 71. The P-terminal 80P protrudes from a side surface 303. The N-terminal 80N is exposed on a main surface 302 of the sealing body 30.

[0116] The semiconductor element 40 and the substrate 50 have the same configuration as those shown in the preceding embodiment. One end of the wiring member 73 is connected to the source electrode 41S of the semiconductor element 40H, and the other end is connected to the relay wiring 522 at a position closer to the side surface 303 than the joint portion of the semiconductor element 40L. The wiring member 73 electrically connects the source electrode 41S of the semiconductor element 40H to the relay wiring 522. The wiring member 73 is a metal member such as a clip or a bonding wire, a flexible substrate, or the like. For example, the wiring member 73 is provided for each semiconductor element 40H.

[0117] The metal block 74 is connected to the source electrode 41S of the semiconductor element 40L in place of the conductive spacer 70L. The metal block 74 contains a metal material with good electrical and thermal conductivity, such as Cu. The metal block 74 is a columnar body with a generally rectangular shape in plan view and is approximately the same size as the source electrode 41S. The metal block 74 extends in the Z direction. One end of the metal block 74 is connected to the source electrode 41S of the semiconductor element 40L, and the other end is exposed on the main surface 302. The end face of the metal block 74 is exposed and generally flush with the main surface 302. The end face of the metal block 74 forms an N terminal 80N. The N terminal 80N is located at a position overlapping the semiconductor element 40L in plan view.

[0118] An N bus bar 24N is connected to the N terminal 80N. The N bus bar 24N extends from the N terminal 80N in the X direction toward the side surface 303, i.e., toward the capacitor module 22. The N bus bar 24N is arranged to overlap with a portion of the relay wiring 522, the wiring member 73, and the P wiring 521 in a plan view. The width of the N bus bar 24N is approximately equal to the width of the substrate 50. The N bus bar 24N runs parallel to the P bus bar 24P. The other configurations are the same as those described in the preceding embodiment.

[0119] <Summary of the third embodiment> As illustrated, the second main electrode of the first semiconductor element may be electrically connected to the second wiring via the wiring member 73, and the metal member electrically connected to the second main electrode of the second semiconductor element may serve as the second terminal. In the illustrated semiconductor module 21, the semiconductor element 40H corresponds to the first semiconductor element, and the relay wiring 522 corresponds to the second wiring. The metal block 74 corresponds to the metal member, and the N-terminal 80N corresponds to the second terminal.

[0120] This eliminates the need for the substrate 60, and uses a wiring member 73 instead of the conductive spacer 70H and the joint portion 71. Furthermore, a metal block 74 (metal member) is used instead of the conductive spacer 70L. Therefore, compared to a configuration using two substrates 50, 60, the electrical connection structure of the series circuit including the semiconductor element 40 can be simplified. Because the metal block 74 (metal member) is exposed on the main surface 302 and serves as the N terminal 80N (second terminal), it is not necessary to route the series circuit to avoid the semiconductor element 40H (first semiconductor element) when viewed in a plan view in the plate thickness direction. Furthermore, the N bus bar 24N (second bus bar) connected to the N terminal 80N faces a portion of the relay wiring 522, the wiring member 73, and the P wiring 521. As a result, inductance can be reduced while suppressing an increase in size.

[0121] (Fourth embodiment) This embodiment is a modification of the preceding embodiment, and the description of the preceding embodiment can be used. In the preceding embodiment, the configuration of the semiconductor module and the power conversion device is applied to an upper and lower arm circuit. Alternatively, the semiconductor module and the power conversion device may be applied to a series circuit different from the upper and lower arm circuit.

[0122] 23 is a diagram showing another example of a series circuit. The series circuit is a shutoff circuit 13 in which two switching elements are connected in series between a first terminal and a second terminal. The switching elements are, for example, MOSFETs 14. The shutoff circuit 13 includes two MOSFETs 14. The diodes 15 are parasitic diodes of the corresponding MOSFETs 14. The diodes 15 are connected in anti-parallel to the corresponding MOSFETs 14. The two MOSFETs 14 are connected so that the forward directions of the diodes 15 are opposite to each other. The illustrated shutoff circuit 13 is a common-source type shutoff circuit in which the sources of the two MOSFETs 14 are connected in common. Instead of a common-source type shutoff circuit, a common-drain type shutoff circuit in which the drains of the two MOSFETs 14 are connected in common may also be used.

[0123] Fig. 24 is a plan view showing an example of a semiconductor module according to this embodiment. Fig. 24 corresponds to Fig. 8. Fig. 25 is a plan view showing a configuration in which the substrate on the source electrode side, the sealing body, and the wiring member are omitted from Fig. 24. Fig. 26 is a plan view showing a configuration in which the sealing body is omitted from Fig. 24. Fig. 27 is a cross-sectional view taken along line XXVII-XXVII in Fig. 24. As with Figs. 6 and 7, Fig. 27 also shows bus bars connected to terminals. In addition, the internal structure of the sealing body is shown expanded in the Z direction to make it easier to understand.

[0124] As shown in FIGS. 24 to 27, the semiconductor module 21 includes a sealing body 30, a semiconductor element 40, substrates 50 and 60, a conductive spacer 70, and external connection terminals. The semiconductor element 40F and 40S are included. The substrate 50, like the preceding embodiment, includes an insulating base material 51, a front surface metal body 52, and a back surface metal body 53. The substrate 60 includes an insulating base material 61, a front surface metal body 62, and a back surface metal body 63. The substrate 50 includes wirings 524 and 525 as the front surface metal body 52. ​​The substrate 60 includes wirings 623 as the front surface metal body 62. The substrate 60 has a metal block body 65 connected to the back surface metal body 63. The external connection terminals include main terminals 80F and 80S as the main terminals 80.

[0125] The semiconductor elements 40F, 40S are arranged side by side in the X direction with the semiconductor element 40F on the side surface 303 side. The wiring 524, 525 are arranged side by side in the X direction with the wiring 524 on the side surface 303 side. The illustrated wiring 524, 525 both have a substantially rectangular shape in plan view. The drain electrode 41D of the semiconductor element 40F and the main terminal 80F are connected to the wiring 524. The main terminal 80F is connected to the end of the wiring 524 on the side surface 303 side. The semiconductor element 40F is arranged at a position closer to the wiring 525 than to the connection portion of the wiring 524 with the main terminal 80F.

[0126] The wiring 525 is connected to the drain electrode 41D of the semiconductor element 40S and the suspension lead 82. The suspension lead 82 is used during manufacturing and does not function as an external connection terminal. A portion of the suspension lead 82 is removed by lead cutting, and the suspension lead 82 protrudes slightly from the side surface 304. The suspension lead 82 is connected to the end of the wiring 525 on the side surface 304 side. The semiconductor element 40S is disposed at a position on the wiring 525 closer to the wiring 524 than the connection portion with the suspension lead 82.

[0127] The wiring 623 is provided so as to overlap, in a plan view, at least a portion of the wiring 524, at least a portion of the wiring 525, the semiconductor element 40F, and the semiconductor element 40S. The wiring 623 extends in the X direction. The wiring 623 is connected to the source electrode 41S of the semiconductor element 40F via a conductive spacer 70F, and is connected to the source electrode 41S of the semiconductor element 40S via a conductive spacer 70S.

[0128] The metal block 65 is exposed on the main surface 302 of the sealing body 30. The exposed portion of the metal block 65 forms the main terminal 80S. The main terminal 80S extends in the Y direction. The main terminal 80S is provided at a position closer to the side surface 303 than the semiconductor element 40F in the X direction. The main terminal 80S is provided so as to overlap the connection portion between the main terminal 80F and the wiring 524 in a plan view.

[0129] The semiconductor module 21 further includes a wiring member 75. The wiring member 75 electrically connects the wiring 525 and the back surface metal body 63. The wiring member 75 is a metal member such as a clip or a bonding wire, a flexible substrate, or the like. In the illustrated wiring member 75, one end is connected to the suspension lead 82, and the other end is connected to the back surface metal body 63. The wiring member 75 is connected to a connection portion of the suspension lead 82 with the wiring 525. The wiring member 75 is connected near the end of the back surface metal body 63 on the side surface 304 side. A wiring member 75 is provided for each suspension lead 82.

[0130] Bus bars 26 are connected to main terminals 80F, 80S. Bus bars 26 include bus bar 26F connected to main terminal 80F and bus bar 26S connected to main terminal 80S. To reduce inductance, bus bars 26F, 26S are arranged so that their plate surfaces face each other in at least a portion of the extension direction (longitudinal direction). Bus bars 26F, 26S run parallel to each other.

[0131] An insulating member 27 may be interposed between the bus bars 26F and 26S. The insulating member 27 is interposed between the bus bars 26F and 26S to insulate and separate the bus bars 26F and 26S. The insulating member 27 is, for example, a resin molded body. In a plan view in the Z direction, the insulating member 27 extends to a position overlapping with the main surface 302 of the sealing body 30. The other configurations are the same as those described in the preceding embodiment.

[0132] <Summary of the Fourth Embodiment> As illustrated, the first semiconductor element and the second semiconductor element may form a common-source or common-drain type interruption circuit 13. In the illustrated semiconductor module 21, main terminal 80F corresponds to the first terminal, and main terminal 80S corresponds to the second terminal. Semiconductor element 40F corresponds to the first semiconductor element, and semiconductor element 40S corresponds to the second semiconductor element. This makes it possible to achieve the above-mentioned effects in semiconductor module 21 that forms interruption circuit 13, which is a series circuit. Use of substrate 50 (substrate) simplifies the electrical connection structure of the series circuit including semiconductor element 40, while suppressing an increase in size and reducing inductance.

[0133] As illustrated, the semiconductor module 21 may include a first substrate and a second substrate, and the second front-surface metal body may be provided so as to overlap at least a portion of the first wiring, at least a portion of the second wiring, the first semiconductor element, and the second semiconductor element in a plan view in the plate thickness direction. The second main electrodes of the first semiconductor element and the second semiconductor element may be electrically connected to the second front-surface metal body, and the second wiring may be electrically connected to the second back-surface metal body via a wiring member. Furthermore, the second terminal may be a metal member connected to the second back-surface metal body, and the second back-surface metal body and the first wiring may face each other in the plate thickness direction.

[0134] In the illustrated semiconductor module 21, the substrate 50 corresponds to the first substrate, and the substrate 60 corresponds to the second substrate. The front surface metal body 62 corresponds to the second front surface metal body, and the back surface metal body 63 corresponds to the second back surface metal body. The wiring 524 corresponds to the first wiring, and the wiring 525 corresponds to the second wiring. The wiring member 75 corresponds to the wiring member, and the metal block body 65 corresponds to the metal member. By using two substrates 50 and 60, the electrical connection structure of the series circuit including the semiconductor element 40 can be further simplified. Furthermore, because the second back surface metal body is used as wiring electrically connecting the first main electrode and the second terminal of the second semiconductor element, there is no need to extend the second wiring toward the side surface 303 so as to avoid the first wiring in a plan view in the plate thickness direction. This eliminates an increase in the physical size. The second back surface metal body faces the first wiring in the plate thickness direction, thereby reducing inductance.

[0135] As shown in the example, the second terminal may be provided at a position closer to the side surface 303 than the first semiconductor element in a predetermined direction. This increases the opposing distance between the second back surface metal body and the first wiring in a configuration including a first substrate and a second substrate, thereby effectively reducing inductance. As shown in the example, in a configuration in which a first bus bar is connected to the first terminal and a second bus bar is connected to the second terminal, at least a portion of the second bus bar may be configured to oppose the first wiring in the plate thickness direction. This reduces inductance.

[0136] As illustrated, the second terminal may be provided so as to overlap the connection portion between the first terminal and the first wiring in plan view, thereby increasing the opposing distance between the second back surface metal body and the first wiring in a configuration including a first substrate and a second substrate, thereby effectively reducing inductance.

[0137] The semiconductor module 21 may include a relay substrate 90 as in the configuration described in the preceding embodiment.

[0138] (Fifth embodiment) This embodiment is a modification of the previous embodiment, and the description of the previous embodiment can be used. In the previous embodiment, the semiconductor module and the capacitor module are arranged in the X direction. Alternatively, the semiconductor module and the capacitor module may be arranged in the Z direction, i.e., stacked in the Z direction.

[0139] Fig. 28 is a cross-sectional view showing an example of a power converter according to this embodiment. Fig. 28 corresponds to Fig. 6. In Fig. 28, for the sake of convenience, the entire capacitor module 22 is shown with metallic hatching.

[0140] The power conversion device 20 includes a semiconductor module 21 and a capacitor module 22. The semiconductor module 21 can be any of the semiconductor modules 21 constituting the upper and lower arm circuits 9 described in the preceding embodiments. The illustrated semiconductor module 21 has a substrate 60 having a front and back connection portion 64 (see FIGS. 6 and 7). The P terminal 80P protrudes from the side surface 303 to the outside of the sealing body 30. The N terminal 80N is formed by exposing a metal block body 65 connected to a back metal body 63 on the main surface 302.

[0141] The capacitor module 22 is disposed on the main surface 302 of the semiconductor module 21. The capacitor module 22 is disposed in a stacked manner on the semiconductor module 21 in the Z direction. The P bus bar 222P extends in the X direction from a main body including the capacitor element 221, a case, and a sealing body (not shown). The P bus bar 222P extends along the main surface 302, bends on the side surface 303, and is connected to the P terminal 80P. The N bus bar 222N extends in the X direction from the main body. The N bus bar 222N extends along the main surface 302 and is connected to the N terminal 80N. The P bus bar 222P and the N bus bar 222N are disposed parallel to each other with their plate surfaces facing each other in the Z direction. The P bus bar 222P and the back surface metal body 63 are disposed opposite each other in the Z direction. The N bus bar 222N and the P wiring 521 are disposed opposite each other in the Z direction. The other configurations are the same as those described in the preceding embodiment.

[0142] <Summary of the Fifth Embodiment> The power conversion device 20 of this embodiment has a configuration similar to that of the semiconductor module 21 constituting the upper and lower arm circuits 9 described in the preceding embodiment. The P terminal 80P protrudes from the side surface 303 to the outside of the sealing body 30. The N terminal 80N is formed by a metal block body 65 connected to the back surface metal body 63 and exposed on the main surface 302. The capacitor module 22 is arranged on the main surface 302 of the semiconductor module 21 in the plate thickness direction. The bus bars included in the capacitor module 22 include a first bus bar electrically connected to the first terminal and a second bus bar electrically connected to the second terminal and arranged parallel to the first bus bar so that the plate surfaces thereof face each other.

[0143] In the illustrated power conversion device 20, the P terminal 80P corresponds to the first terminal, and the N terminal 80N corresponds to the second terminal. The semiconductor element 40H corresponds to the first semiconductor element, and the semiconductor element 40L corresponds to the second semiconductor element. The Z direction corresponds to the plate thickness direction, and the X direction corresponds to the predetermined direction. The upper and lower arm circuits 9 correspond to the series circuit. The P bus bar 222P corresponds to the first bus bar, and the N bus bar 222N corresponds to the second bus bar.

[0144] Because the capacitor module 22 has the same configuration as the semiconductor module 21 constituting the upper and lower arm circuits 9 described in the preceding embodiment, it is possible to reduce inductance while suppressing an increase in the size of the semiconductor module 21. In addition, because the capacitor module 22 is disposed on the main surface 302 where the second terminals are exposed, it is possible to further shorten the length of the wiring connecting the semiconductor module 21 and the capacitor module 22. Because the P bus bar 222P and the N bus bar 222N are disposed in parallel so that their plate surfaces face each other, it is possible to reduce inductance. As a result, it is possible to further reduce inductance in the power conversion device 20. In addition, it is possible to reduce the size of the power conversion device 20.

[0145] As shown in the example, P bus bar 222P may be arranged with the plate surfaces facing back surface metal body 63. N bus bar 222N may be arranged with P wiring 521 with the plate surfaces facing P wiring 521. This can further reduce inductance.

[0146] The semiconductor module 21 is not limited to a configuration including the front-back connector 64. The semiconductor module 21 may be configured to include a wiring member 72 (see FIG. 19) or a wiring member 73 and a metal block body 74 (see FIG. 22). The front-back connector 64 may also be configured in any of the various ways shown in the preceding embodiments.

[0147] (Other embodiments) The disclosure in this specification and drawings, etc. is not limited to the exemplified embodiments. The disclosure encompasses the exemplified embodiments and modifications thereto by those skilled in the art. For example, the disclosure is not limited to the combinations of parts and / or elements shown in the embodiments. The disclosure can be implemented in various combinations. The disclosure can have additional parts that can be added to the embodiments. The disclosure encompasses the omission of parts and / or elements from the embodiments. The disclosure encompasses the substitution or combination of parts and / or elements between one embodiment and another embodiment. The disclosed technical scope is not limited to the description of the embodiments. Some disclosed technical scopes are defined by the claims, and should be interpreted as including all modifications within the meaning and scope equivalent to the claims.

[0148] The disclosure in the specification, drawings, etc. is not limited by the claims. The disclosure in the specification, drawings, etc. encompasses the technical ideas described in the claims, and extends to more diverse and broader technical ideas than the technical ideas described in the claims. Therefore, various technical ideas can be extracted from the disclosure in the specification, drawings, etc. without being bound by the claims.

[0149] When an element or layer is referred to as being "on," "coupled," "connected," or "bonded," it may be directly on, coupled, connected, or bonded to another element or layer, and intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly coupled," "directly connected," or "directly bonded" to another element or layer, no intervening elements or layers are present. Other terms used to describe relationships between elements should be construed in a similar manner (e.g., "between" vs. "directly between," "adjacent" vs. "directly adjacent," etc.). As used in this specification, the term "and / or" includes any and all combinations of one or more of the associated listed items. That is, reference to A and / or B means at least one of A and B.

[0150] Spatially relative terms such as "inside," "outside," "back," "below," "low," "top," "top," and the like are used herein to facilitate the description of one element or feature's relationship to other elements or features, as illustrated. Spatially relative terms may be intended to encompass different orientations of the device during use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures were turned over, elements described as "below" or "directly below" other elements or features would then be oriented "above" the other elements or features. Thus, the term "bottom" can encompass both an orientation of top and bottom. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used in this specification would be interpreted accordingly.

[0151] Although the semiconductor module 21 is exemplified as a 2-in-1 package that provides the upper and lower arm circuits 9 for one phase, the present invention is not limited to this. The semiconductor module 21 may be any module that provides a series circuit in which the first semiconductor element is disposed on the first terminal side and the first semiconductor element and the second semiconductor element are connected in series between the first terminal and the second terminal. The semiconductor module 21 may also be a 6-in-1 package that provides the upper and lower arm circuits 9 for three phases, for example.

[0152] (Disclosure of technical ideas) This specification discloses multiple technical ideas described in the following multiple clauses. Some clauses may be written in a multiple dependent form, with the subsequent clause referring to the preceding clause as an alternative. Furthermore, some clauses may be written in a multiple dependent form, referring to another multiple dependent clause. These multiple dependent clauses define multiple technical ideas.

[0153] <Technical philosophy 1> First terminal (80P, 80F), Second terminal (80N, 80S), a plurality of semiconductor elements (40) including first semiconductor elements (40H, 40F) and second semiconductor elements (40L, 40S) each having a first main electrode (41D) provided on one surface and a second main electrode (41S) formed on a surface opposite to the one surface in a plate thickness direction, and arranged side by side in a predetermined direction perpendicular to the plate thickness direction; an encapsulant (30) that encapsulates the plurality of semiconductor elements; Equipped with the first terminal, the second terminal, the first semiconductor element, and the second semiconductor element are arranged on the first terminal side, and form a series circuit (9, 13) in which the first semiconductor element and the second semiconductor element are connected in series between the first terminal and the second terminal; the first terminal protrudes from a side surface (303) of the sealing body on the first semiconductor element side in the predetermined direction to the outside of the sealing body; The second terminal is exposed to the outside of the sealing body from a main surface (302) that is one of the surfaces of the sealing body that is continuous with the side surface.

[0154] <Technical philosophy 2> a first bus bar (24P, 26F) electrically connected to the first terminal; A semiconductor module according to Technical Idea 1, comprising: a second bus bar (24N, 26S) electrically connected to the second terminal and arranged parallel to the first bus bar so that their plate surfaces face each other.

[0155] <Technical philosophy 3> an insulating member (25, 27) interposed between the first bus bar and the second bus bar; The semiconductor module according to Technical Concept 2, wherein the insulating member extends to a position overlapping the main surface of the sealing body.

[0156] <Technical philosophy 4> The substrate (50) includes an insulating base material (51), a front surface metal body (52) disposed on the front surface of the insulating base material and including first wiring (521, 524) and second wiring (522, 525) aligned in the predetermined direction relative to the first wiring, and a back surface metal body (53) disposed on the back surface of the insulating base material, the first main electrode of the first semiconductor element is connected to the first wiring; the first main electrode of the second semiconductor element is connected to the second wiring; the series circuit includes the first wiring and the second wiring, the sealing body seals the semiconductor element and the substrate, The semiconductor module according to any one of Technical Concepts 1 to 3, wherein the first terminal is electrically connected to the first semiconductor element via the first wiring.

[0157] <Technical philosophy 5> one of the first semiconductor element and the second semiconductor element is an upper arm element constituting an upper arm (9H) of an upper / lower arm circuit (9); The semiconductor module according to Technical Concept 4, wherein the other of the first semiconductor element and the second semiconductor element is a lower arm element that constitutes a lower arm (9L) of the upper and lower arm circuit.

[0158] <Technical philosophy 6> the substrate is a first substrate having a first insulating base material that is the insulating base material, a first front surface metal body that is the front surface metal body, and a first back surface metal body that is the back surface metal body, a second substrate (60) having a second insulating base (61); a second front surface metal body (62) including third wiring (622) arranged on a surface of the second insulating base and arranged so as to overlap at least a portion of the first wiring and the first semiconductor element in a plan view in the plate thickness direction, and fourth wiring (621) arranged so as to overlap at least a portion of the second wiring and the second semiconductor element in the plan view and aligned in the predetermined direction with respect to the third wiring; and a second back surface metal body (63) arranged on a back surface of the second insulating base; a joint portion (71) that electrically connects the second wiring and the third wiring, the second main electrode of the first semiconductor element is electrically connected to the third wiring; the second main electrode of the second semiconductor element is electrically connected to the second back surface metal body via the fourth wiring, the second terminal is a part of the second back surface metal body or a metal member (65) connected to the second back surface metal body, The semiconductor module according to Technical Idea 5, wherein the second back surface metal body and the first wiring face each other in the plate thickness direction.

[0159] <Technical philosophy 7> The semiconductor module according to Technical Idea 6, wherein the fourth wiring and the second back surface metal body are electrically connected at the outer peripheral edge of the second substrate.

[0160] <Technical philosophy 8> The second insulating substrate has a through portion (641), The semiconductor module according to Technical Idea 6, wherein the fourth wiring and the second back surface metal body are electrically connected by a conductor (642) arranged in the through portion.

[0161] <Technical philosophy 9> the second insulating substrate is partially removed; The second back surface metal body has an exposed portion (646) exposed to the second front surface metal body side, The semiconductor module according to Technical Concept 6, wherein the fourth wiring and the exposed portion are electrically connected via a wiring member (644).

[0162] <Technical Thought 10> the substrate is a first substrate having a first insulating base material that is the insulating base material, a first front surface metal body that is the front surface metal body, and a first back surface metal body that is the back surface metal body, a second substrate (60) including a second insulating base (61), a second front surface metal body (62) disposed on the front surface of the second insulating base and electrically connected to the second main electrode of the first semiconductor element, and a second rear surface metal body (63) disposed on the rear surface of the second insulating base, the second substrate (60) being arranged so as to overlap the first semiconductor element but not the second semiconductor element in a plan view in the plate thickness direction; a joint portion (71) that electrically connects the second surface metal body and the second wiring; a wiring member (72) that electrically connects the second main electrode of the second semiconductor element and the second back surface metal body, the second terminal is a part of the second back surface metal body or a metal member (65) connected to the second back surface metal body, The semiconductor module according to Technical Idea 5, wherein the second back surface metal body and the first wiring face each other in the plate thickness direction.

[0163] <Technical Thought 11> the second main electrode of the first semiconductor element is electrically connected to the second wiring via a wiring member (73); The semiconductor module according to Technical Concept 5, wherein the second terminal is a metal member (74) electrically connected to the second main electrode of the second semiconductor element.

[0164] <Technical Thought 12> The semiconductor module according to Technical Concept 4, wherein the first semiconductor element and the second semiconductor element form a source common type or drain common type interruption circuit (13).

[0165] <Technical Thought 13> the substrate is a first substrate having a first insulating base material that is the insulating base material, a first front surface metal body that is the front surface metal body, and a first back surface metal body that is the back surface metal body, a second substrate (60) having a second insulating base material (61), a second front surface metal body (62) arranged on the front surface of the second insulating base material, and a second rear surface metal body (63) arranged on the rear surface of the second insulating base material; the second surface metal body is provided so as to overlap at least a portion of the first wiring, at least a portion of the second wiring, the first semiconductor element, and the second semiconductor element in a plan view in the plate thickness direction; the second main electrode of the first semiconductor element and the second main electrode of the second semiconductor element are electrically connected to the second surface metal body; The second wiring is electrically connected to the second back surface metal body via a wiring member (75), the second terminal is a part of the second back surface metal body or a metal member (65) connected to the second back surface metal body, The semiconductor module according to Technical Idea 12, wherein the second back surface metal body and the first wiring face each other in the plate thickness direction.

[0166] <Technical Thought 14> A semiconductor module described in any one of Technical Ideas 6 to 10, 13, wherein the second terminal is provided at a position closer to the side (303) of the sealing body from which the first terminal protrudes than the first semiconductor element in the specified direction.

[0167] <Technical Thought 15> The semiconductor module according to any one of Technical Concepts 6 to 10 and 13, wherein the second terminal is provided so as to overlap a connection portion between the first terminal and the first wiring in the plan view.

[0168] <Technical Thought 16> The semiconductor module according to any one of Technical Ideas 1 to 15, further comprising signal terminals (81H, 81F) electrically connected to the semiconductor element and protruding from the side surface (303) of the sealing body together with the first terminal. [Explanation of symbols]

[0169] 1... drive system, 2... DC power supply, 3... motor generator, 3a... winding, 4... power conversion circuit, 5... smoothing capacitor, 6... inverter, 7... P line, 8... N line, 9... upper and lower arm circuits, 9H... upper arm, 9L... lower arm, 10... output line, 11, 14... MOSFET, 12, 15... diode, 13... interrupter circuit, 20... semiconductor device, 21... semiconductor module, 22... capacitor module, 221... capacitor element, 222N... N bus bar, 222P...P bus bar, 223...insulating member, 224N, 224P...DC terminal portion, 23...cooler, 231...protruding portion, 24...bus bar, 24A...output bus bar, 24N...N bus bar, 24P...P bus bar, 241N, 241P...detection terminal, 25...insulating member, 26...bus bar, 26F...first bus bar, 26S...second bus bar, 27...insulating member, 30...sealing body, 301, 302...main surface, 303, 304, 305, 306...side surface, 40, 40F, 4 0H, 40L, 40S...Semiconductor element, 41D...Drain electrode, 41S...Source electrode, 41P...Pad, 50, 60...Substrate, 51, 61...Insulating base material, 52, 62...Surface metal body, 521...P wiring, 621...N wiring, 6211...Base, 6212...Convex portion, 522, 622...Relay wiring, 6221...Base, 6222...Convex portion, 523...Island, 524, 525, 623...Wiring, 53, 63...Back metal body, 631...Exposed portion, 64...Front and back connection portion, 641...Through Through hole, 642...conductor, 643...welding portion, 644...wiring member, 645...removed portion, 646...exposed portion, 65...metal block body, 70, 70F, 70H, 70L, 70S...conductive spacer, 71...joint portion, 72, 73, 75...wiring member, 74...metal block body, 80, 80F, 80S...main terminal, 0A...output terminal, 80N...N terminal, 80P...P terminal, 81, 81F, 81H, 81L, 81S...signal terminal, 82...hanging lead, 90, 90H, 90L...relay board

Claims

1. First terminals (80P, 80F); Second terminals (80N, 80S); a plurality of semiconductor elements (40) including first semiconductor elements (40H, 40F) and second semiconductor elements (40L, 40S) each having a first main electrode (41D) provided on one surface and a second main electrode (41S) formed on a surface opposite to the one surface in a plate thickness direction, and arranged side by side in a predetermined direction perpendicular to the plate thickness direction; an encapsulant (30) that encapsulates the plurality of semiconductor elements; Equipped with the first terminal, the second terminal, the first semiconductor element, and the second semiconductor element are arranged on the first terminal side, and form a series circuit (9, 13) in which the first semiconductor element and the second semiconductor element are connected in series between the first terminal and the second terminal; the first terminal protrudes from a side surface (303) of the sealing body on the first semiconductor element side in the predetermined direction to the outside of the sealing body; The second terminal is exposed to the outside of the sealing body from a main surface (302) that is one of the surfaces of the sealing body that is continuous with the side surface.

2. a first bus bar (24P, 26F) electrically connected to the first terminal; 2. The semiconductor module according to claim 1, further comprising: second bus bars (24N, 26S) electrically connected to the second terminals and arranged parallel to the first bus bars so that their plate surfaces face each other.

3. an insulating member (25, 27) interposed between the first bus bar and the second bus bar; The semiconductor module according to claim 2 , wherein the insulating member extends to a position overlapping the main surface of the sealing body.

4. The substrate (50) comprises an insulating base material (51), a front surface metal body (52) disposed on the front surface of the insulating base material and including first wiring (521, 524) and second wiring (522, 525) aligned in the predetermined direction relative to the first wiring, and a back surface metal body (53) disposed on the back surface of the insulating base material, the first main electrode of the first semiconductor element is connected to the first wiring; the first main electrode of the second semiconductor element is connected to the second wiring; the series circuit includes the first wiring and the second wiring, the sealing body seals the semiconductor element and the substrate, The semiconductor module according to claim 1 , wherein the first terminal is electrically connected to the first semiconductor element via the first wiring.

5. one of the first semiconductor element and the second semiconductor element is an upper arm element constituting an upper arm (9H) of an upper / lower arm circuit (9); 5. The semiconductor module according to claim 4, wherein the other of the first semiconductor element and the second semiconductor element is a lower arm element constituting a lower arm (9L) of the upper and lower arm circuit.

6. the substrate is a first substrate having a first insulating base material that is the insulating base material, a first front surface metal body that is the front surface metal body, and a first back surface metal body that is the back surface metal body, a second substrate (60) having a second insulating base material (61); a second front surface metal body (62) including third wiring (622) arranged on a surface of the second insulating base material and arranged so as to overlap at least a portion of the first wiring and the first semiconductor element in a plan view in the plate thickness direction, and fourth wiring (621) arranged so as to overlap at least a portion of the second wiring and the second semiconductor element in the plan view and aligned in the predetermined direction with respect to the third wiring; and a second back surface metal body (63) arranged on a back surface of the second insulating base material; a joint portion (71) that electrically connects the second wiring and the third wiring, the second main electrode of the first semiconductor element is electrically connected to the third wiring; the second main electrode of the second semiconductor element is electrically connected to the second back surface metal body via the fourth wiring, the second terminal is a part of the second back surface metal body or a metal member (65) connected to the second back surface metal body, The semiconductor module according to claim 5 , wherein the second back surface metal body and the first wiring face each other in the thickness direction.

7. The semiconductor module according to claim 6 , wherein the fourth wiring and the second back surface metal body are electrically connected at an outer peripheral edge of the second substrate.

8. The second insulating substrate has a through portion (641), 7. The semiconductor module according to claim 6, wherein the fourth wiring and the second back surface metal body are electrically connected by a conductor (642) arranged in the through portion.

9. the second insulating substrate is partially removed; The second back surface metal body has an exposed portion (646) exposed to the second front surface metal body side, The semiconductor module according to claim 6, wherein the fourth wiring and the exposed portion are electrically connected via a wiring member (644).

10. the substrate is a first substrate having a first insulating base material that is the insulating base material, a first front surface metal body that is the front surface metal body, and a first back surface metal body that is the back surface metal body, a second substrate (60) having a second insulating base material (61), a second front surface metal body (62) disposed on the front surface of the second insulating base material and electrically connected to the second main electrode of the first semiconductor element, and a second rear surface metal body (63) disposed on the rear surface of the second insulating base material, the second substrate (60) being arranged so as to overlap the first semiconductor element but not the second semiconductor element in a plan view in the plate thickness direction; a joint portion (71) that electrically connects the second surface metal body and the second wiring; a wiring member (72) that electrically connects the second main electrode of the second semiconductor element and the second back surface metal body, the second terminal is a part of the second back surface metal body or a metal member (65) connected to the second back surface metal body, The semiconductor module according to claim 5 , wherein the second back surface metal body and the first wiring face each other in the thickness direction.

11. The second main electrode of the first semiconductor element is electrically connected to the second wiring via a wiring member (73), 6. The semiconductor module according to claim 5, wherein the second terminal is a metal member (74) electrically connected to the second main electrode of the second semiconductor element.

12. 5. The semiconductor module according to claim 4, wherein the first semiconductor element and the second semiconductor element form a common-source or common-drain type interruption circuit (13).

13. the substrate is a first substrate having a first insulating base material that is the insulating base material, a first front surface metal body that is the front surface metal body, and a first back surface metal body that is the back surface metal body, The second substrate (60) includes a second insulating substrate (61), a second front surface metal body (62) disposed on the front surface of the second insulating substrate, and a second rear surface metal body (63) disposed on the rear surface of the second insulating substrate, the second surface metal body is provided so as to overlap at least a portion of the first wiring, at least a portion of the second wiring, the first semiconductor element, and the second semiconductor element in a plan view in the plate thickness direction, the second main electrode of the first semiconductor element and the second main electrode of the second semiconductor element are electrically connected to the second surface metal body; The second wiring is electrically connected to the second back surface metal body via a wiring member (75), the second terminal is a part of the second back surface metal body or a metal member (65) connected to the second back surface metal body, The semiconductor module according to claim 12 , wherein the second back surface metal body and the first wiring face each other in the thickness direction.

14. A semiconductor module according to any one of claims 6 to 10, and 13, wherein the second terminal is provided at a position closer to the side (303) of the sealing body from which the first terminal protrudes than the first semiconductor element in the predetermined direction.

15. 14. The semiconductor module according to claim 6, wherein the second terminal is provided so as to overlap a connection portion between the first terminal and the first wiring in the plan view.

16. The semiconductor module according to any one of claims 1 to 4, further comprising signal terminals (81H, 81F) electrically connected to the semiconductor element and projecting from the side surface (303) of the sealing body together with the first terminal.

17. a semiconductor module (21) constituting an upper and lower arm circuit (9); a capacitor module (22) having a plurality of bus bars (222P, 222N) electrically connected to the semiconductor module; Equipped with The semiconductor module includes: A first terminal (80P); A second terminal (80N); a plurality of semiconductor elements (40) including a first semiconductor element (40H) and a second semiconductor element (40L), each having a first main electrode (41D) provided on one surface and a second main electrode (41S) formed on a surface opposite to the one surface in a plate thickness direction, and arranged side by side in a predetermined direction perpendicular to the plate thickness direction; an encapsulant (30) that encapsulates the plurality of semiconductor elements; and one of the first semiconductor element and the second semiconductor element is an upper arm element constituting an upper arm (9H) of the upper and lower arm circuit formed by connecting the first semiconductor element and the second semiconductor element in series between the first terminal and the second terminal, and the other of the first semiconductor element and the second semiconductor element is a lower arm element constituting a lower arm (9L) of the upper and lower arm circuit, the first terminal protrudes from a side surface (303) of the sealing body on the first semiconductor element side in the predetermined direction to the outside of the sealing body; The second terminal is exposed to the outside of the sealing body from a main surface (302) that is one of the surfaces connected to the side surface of the sealing body, the capacitor module is disposed on the main surface of the semiconductor module in the plate thickness direction, The power conversion device, wherein the plurality of bus bars include a first bus bar (222P) electrically connected to the first terminal, and a second bus bar (222N) electrically connected to the second terminal and arranged parallel to the first bus bar so that their plate surfaces face each other.

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