Motor drive device and air conditioner

Abstract

To reduce a leakage current when a three phase motor is driven using three phase modulation.SOLUTION: The level shift circuit generates a second reference signal by shifting a relative signal level of the first reference signal with respect to a signal level of the carrier signal so that an average value of the signal level of the first reference signal increases or decreases by a predetermined shift amount with respect to an average value of the signal level of the carrier signal over a period longer than a cycle of the reference signal. The comparators 15-1 to 15-3 generate control signals by comparing the signal level of the second reference signal with the signal level of the carrier signal. The level shift circuit has a first shift amount when the three phase motor 4 operates at a first speed or with a first load, and has a second shift amount having an absolute value larger than an absolute value of the first shift amount when the three phase motor 4 operates at a second speed lower than the first speed or with a second load smaller than the first load.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a motor drive device and an air conditioner. [Background technology]

[0002] Three-phase motors are used in a variety of devices, such as compressors for air conditioners, etc. To drive a three-phase motor, an inverter circuit converts a DC voltage into an AC voltage to supply to the three-phase motor, and control signals for multiple switching elements of the inverter circuit are generated using, for example, pulse width modulation.

[0003] For example, Patent Document 1 discloses a motor drive control device that controls the drive of a three-phase motor, which performs two-phase modulation, in which pulse-width modulation signals are supplied to only two of the three phases, and three-phase modulation, in which pulse-width modulation signals are supplied to all three phases. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-118755 Summary of the Invention [Problem to be solved by the invention]

[0005] When comparing two-phase modulation with three-phase modulation, three-phase modulation tends to have a smaller ripple in the current flowing through the motor, making it more advantageous in terms of noise. However, three-phase modulation has a larger leakage current than two-phase modulation, and this difference is particularly noticeable during low-speed operation and light loads. Therefore, it is necessary to reduce the leakage current even in three-phase modulation.

[0006] An object of the present disclosure is to provide a motor drive device for driving a three-phase motor, which is capable of reducing leakage current compared to conventional motors when driving the three-phase motor using three-phase modulation, and to provide an air conditioner equipped with such a motor drive device. [Means for solving the problem]

[0007] A motor drive device according to one aspect of the present disclosure includes: A motor drive device that drives a three-phase motor, an inverter circuit including a plurality of switching elements, which converts a DC voltage into an AC voltage and supplies the AC voltage to the three-phase motor; a control circuit that generates control signals for the plurality of switching elements using pulse width modulation; The control circuit a first signal generating circuit that generates three first reference signals each representing a desired waveform of a phase voltage of the three-phase motor and each having a first period; a second signal generating circuit that generates a carrier signal having a second period that is shorter than the first period; a level shift circuit that generates three second reference signals by shifting the relative signal levels of the three first reference signals with respect to the signal level of the carrier signal so that an average value of the signal levels of the three first reference signals increases or decreases by a predetermined shift amount with respect to the average value of the signal level of the carrier signal over a period longer than the first period; a comparator that generates three control signals corresponding to the three second reference signals, respectively, by comparing the signal levels of the three second reference signals with the signal level of the carrier signal; The level shift circuit has a first shift amount when the three-phase motor is operating at a first speed or a first load, and has a second shift amount having an absolute value greater than the absolute value of the first shift amount when the three-phase motor is operating at a second speed lower than the first speed or a second load lower than the first load. [Effects of the Invention]

[0008] According to one aspect of the present disclosure, when a three-phase motor is driven using three-phase modulation, leakage current can be reduced more than conventionally. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a diagram showing a configuration of a motor system according to a first embodiment. [Figure 2] 2 is a block diagram showing the configuration of a control circuit 6 in FIG. 1. FIG. [Figure 3] 10 is a diagram showing the operation of the motor system according to the first comparative example when the three-phase motor 4 is operating at high speed or high load. FIG. [Figure 4] FIG. 4 is a diagram illustrating the operation of the motor system according to the first comparative example when the three-phase motor 4 is operating at low speed or low load. [Figure 5] 1. FIG. 4 is a diagram showing a first operation of the control circuit 6 for reducing leakage current when the three-phase motor 4 of FIG. 1 is operating at a low speed or a low load. [Figure 6] 1. FIG. 4 is a diagram illustrating a second operation of the control circuit 6 for reducing leakage current when the three-phase motor 4 of FIG. 1 is operating at a low speed or a low load. [Figure 7] 5 is a diagram for explaining generation of control signals S1 to S6 in the case of FIG. 4. FIG. [Figure 8] FIG. 6 is a diagram for explaining generation of control signals S1 to S6 in the case of FIG. 5. [Figure 9] FIG. 7 is a diagram for explaining generation of control signals S1 to S6 in the case of FIG. [Figure 10] FIG. 4 is a diagram for explaining calculation of leakage current according to the first embodiment. [Figure 11] 4 is a graph showing a simulation result of leakage current according to the first embodiment. [Figure 12] FIG. 10 is a diagram showing the waveform of a reference signal Vaa* generated in a control circuit of a motor drive device according to a modified example of the first embodiment. [Figure 13]FIG. 10 is a block diagram showing the configuration of a control circuit 6A of a motor system according to a second embodiment. [Figure 14] 10A and 10B are diagrams illustrating generation of control signals when the difference in pulse width of the control signals is sufficiently large in the motor system according to the second embodiment. [Figure 15] 10A and 10B are diagrams for explaining generation of control signals when the difference in pulse width of the control signals is small in the motor system according to the second comparative example. [Figure 16] 10A and 10B are diagrams illustrating generation of control signals when a positive bias voltage is superimposed on a reference signal and the difference in pulse width of the control signals is small in a motor system according to a second embodiment. [Figure 17] 10A and 10B are diagrams illustrating generation of control signals when a negative bias voltage is superimposed on a reference signal and the difference in pulse width of the control signals is small in a motor system according to a second embodiment. [Figure 18] FIG. 10 is a diagram showing the configuration of an air conditioner 100 according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, the embodiments will be described in detail with reference to the drawings as appropriate. However, in some cases, more detailed explanations than necessary will be omitted. For example, detailed explanations of already well-known matters and duplicate explanations of substantially identical configurations will be omitted. This is to avoid unnecessary redundancy in the following explanation and to facilitate understanding by those skilled in the art. Note that components with the same reference numerals have the same functions in each embodiment.

[0011] It should be noted that the present disclosure provides the accompanying drawings and the following description for the understanding of those skilled in the art, and is not intended to limit the subject matter described in the claims.

[0012] [First embodiment] [Configuration of the first embodiment] Fig. 1 is a diagram showing the configuration of a motor system according to Embodiment 1. The motor system in Fig. 1 includes an AC power supply 1, a rectifier circuit 2, an inverter circuit 3, a three-phase motor 4, a current detection circuit 5, a control circuit 6, DC buses B1 and B2, a capacitor C1, and a current detection resistor R1.

[0013] The AC power supply 1 supplies a single-phase or three-phase AC voltage and may include, for example, a 100V or 200V commercial AC power supply.

[0014] The rectifier circuit 2 rectifies the AC voltage supplied from the AC power supply 1. The rectifier circuit 2 includes, for example, a diode bridge. The rectifier circuit 2 may also include a power factor correction circuit. The capacitor C1 smoothes the rectified DC voltage. The rectified and smoothed DC voltage Vdc is sent to the inverter circuit 3 via positive and negative DC buses B1 and B2.

[0015] The inverter circuit 3 is a DC / AC power conversion circuit that converts a DC voltage Vdc into U-phase, V-phase, and W-phase AC voltages Vu, Vv, and Vw and supplies them to a three-phase motor 4. The inverter circuit 3 includes a full-bridge circuit including a plurality of, for example, six, switching elements Q1 to Q6. The switching elements Q1 and Q2 are connected in series between DC buses B1 and B2, and a node between the switching elements Q1 and Q2 is connected to a U-phase winding of the three-phase motor 4. The switching elements Q3 and Q4 are connected in series between DC buses B1 and B2, and a node between the switching elements Q3 and Q4 is connected to a V-phase winding of the three-phase motor 4. The switching elements Q5 and Q6 are connected in series between DC buses B1 and B2, and a node between the switching elements Q5 and Q6 is connected to a W-phase winding of the three-phase motor 4. The switching elements Q1, Q3, and Q5 connected to the positive DC bus B1 are also called the “upper arm circuit,” and the switching elements Q2, Q4, and Q6 connected to the negative DC bus B2 are also called the “lower arm circuit.” The switching elements Q1 to Q6 may be, for example, power transistors such as insulated gate bipolar transistors.

[0016] The three-phase motor 4 is driven by AC voltages Vu, Vv, and Vw supplied from the inverter circuit 3. The three-phase motor 4 includes a U-phase winding 4u, a V-phase winding 4v, and a W-phase winding 4w, with the windings 4u, 4v, and 4w connected to one another at a node N1. The voltages Vu, Vv, and Vw are applied to the windings 4u, 4v, and 4w, respectively. The three-phase motor 4 is installed in, for example, a compressor of an air conditioner.

[0017] The current detection resistor R1 is inserted into either the DC bus B1 or B2. The current detection circuit 5 detects the potential difference between both ends of the current detection resistor R1 to detect the current flowing through the current detection resistor R1, i.e., the current I0 flowing through the three-phase motor 4.

[0018] The DC voltage Vdc across the positive and negative DC buses B1, B2 is transmitted to the control circuit 6. The DC voltage Vdc may be input to the control circuit 6 via a voltage dividing resistor. The current I0 detected by the current detection circuit 5 is also transmitted to the control circuit 6. The control circuit 6 generates control signals S1 to S6 for the switching elements Q1 to Q6 using pulse width modulation based on the DC voltage Vdc and the current I0. The control circuit 6 estimates the position of the magnetic poles and the current speed (i.e., rotational speed) of the three-phase motor 4 based on the DC voltage Vdc and the current I0, and performs feedback control so that the three-phase motor 4 operates at a desired speed. The control signals S1 to S6 are applied to control terminals, e.g., gates, of the switching elements Q1 to Q6, respectively, to turn the switching elements Q1 to Q6 on and off, respectively.

[0019] According to Kirchhoff's law, the currents Iu, Iv, and Iw flowing through the windings 4u, 4v, and 4w of each phase of the three-phase motor 4 satisfy Iu + Iv + Iw = 0. For each cycle of the carrier signal (described below), the current I0 (also referred to as "current I0_1") when only one of the switching elements Q1, Q3, and Q5 in the upper arm circuit is turned on is detected, and the current I0 (also referred to as "current I0_2") when only two of the switching elements Q1, Q3, and Q5 are turned on is detected, thereby determining the currents Iu, Iv, and Iw of each phase of the three-phase motor 4. This allows the control circuit 6 to detect the currents Iu, Iv, and Iw of each phase of the three-phase motor 4 using a common current detection resistor R1. In order to accurately detect the currents I0_1 and I0_2 without being affected by switching noise when the switching elements transition from off to on (or on to off), it is necessary to set the time length Ton1 during which only one of the switching elements Q1, Q3, and Q5 is turned on and the time length Ton2 during which only two of the switching elements Q1, Q3, and Q5 are turned on to a predetermined time length Tdet or longer. For this reason, for example, as described in the second embodiment, the moment at which each of the switching elements Q1, Q3, and Q5 transitions from off to on may be advanced or delayed in time so that Ton1≧Tdet and Ton2≧Tdet are satisfied.

[0020] The inverter circuit 3 and the control circuit 6 are an example of a motor drive device. The motor drive device may further include at least some of a rectifier circuit 2, a capacitor C1, a resistor R1, and a current detection circuit 5.

[0021] The average value Vm = (Vu + Vv + Vw) / 3 of the voltages Vu, Vv, and Vw applied to the windings 4u, 4v, and 4w of the three-phase motor 4, respectively, is called the "common-mode voltage" or "zero-phase voltage." Furthermore, stray capacitance Cs occurs between the windings 4u, 4v, and 4w of the three-phase motor 4 and the conductors surrounding the three-phase motor 4, such as the chassis of a compressor equipped with the three-phase motor 4. In FIG. 1, the stray capacitance Cs is shown as the equivalent composite capacitance between node N1 and ground. A leakage current Ileak from the three-phase motor 4 flows through the stray capacitance Cs.

[0022] Fig. 2 is a block diagram showing the configuration of control circuit 6 in Fig. 1. Control circuit 6 includes reference signal generating circuit 11, variable voltage source 12, combiners 13-1 to 13-3, carrier signal generating circuit 14, comparators 15-1 to 15-3, buffers 16-1 to 16-3, and inverters 17-1 to 17-3.

[0023] The reference signal generating circuit 11 generates three reference signals Vu0 and Vu1 each having a predetermined period and each representing a desired waveform of each phase voltage of the three-phase motor 4 based on the DC voltage Vdc and the current I0. * ,Vv0 * ,Vw0 * Generates a reference signal Vu0 * ,Vv0 * ,Vw0 * Each of the reference signals Vu0 and Vu1 has a sine wave waveform, for example, and has a phase difference of 120 degrees. * ,Vv0 * ,Vw0 * has an amplitude that is variable depending on the amplitude of the desired voltages Vu, Vv, and Vw to be output from the inverter circuit 3. The reference signal generating circuit 11 generates a reference signal Vu0 based on the DC voltage Vdc and the current I0. * ,Vv0 * ,Vw0 * , and further determines the magnitude of the bias voltage Vz to be generated by the variable voltage source 12.

[0024] The variable voltage source 12 generates a variable bias voltage Vz under the control of the reference signal generating circuit 11 .

[0025] The combiners 13-1 to 13-3 combine the reference signals Vu0 * ,Vv0 * ,Vw0 * By superimposing a bias voltage Vz on the reference signal Vu0 * ,Vv0 * ,Vw0 * to generate a reference signal Vu having a shifted signal level. * ,Vv * ,Vw * Generate.

[0026] The carrier signal generating circuit 14 generates a reference signal Vu0 * ,Vv0 * ,Vw0 * The carrier signal Vt has a waveform of, for example, a triangular wave.

[0027] The comparators 15-1 to 15-3 receive three reference signals Vu * ,Vv * ,Vw * The signal level of each of the reference signals Vu is compared to the signal level of the carrier signal Vt. * If the signal level of the reference signal Vt is equal to or greater than the signal level of the carrier signal Vt, the output signal of the comparator 15-1 becomes high level, otherwise the output signal of the comparator 15-1 becomes low level. * ,Vw * The reference signal Vu is at a high level or a low level depending on the signal level of the reference signal Vu and the signal level of the carrier signal Vt. * ,Vv * ,Vw * The signal level of the carrier signal Vt is expressed, for example, in voltage.

[0028] Buffers 16-1 to 16-3 directly output the output signals of comparators 15-1 to 15-3 as control signals S1, S3, and S5, respectively. Inverters 17-1 to 17-3 invert the output signals of comparators 15-1 to 15-3 and output them as control signals S2, S4, and S6, respectively.

[0029] When the control signals S1 to S6 are at a high level, the corresponding switching elements Q1 to Q6 are turned on, and when the control signals S1 to S6 are at a low level, the corresponding switching elements Q1 to Q6 are turned off. Note that the control signals S1 and S2 have dead times to prevent the switching elements Q1 and Q2 from being turned on simultaneously, the control signals S3 and S4 have dead times to prevent the switching elements Q3 and Q4 from being turned on simultaneously, and the control signals S5 and S6 have dead times to prevent the switching elements Q5 and Q6 from being turned on simultaneously. For simplicity of illustration, a circuit for inserting dead times into the control signals S1 to S6 is omitted.

[0030] The variable voltage source 12 and the combiners 13-1 to 13-3 are an example of a level shift circuit.

[0031] The level shift circuit uses the reference signal Vu0 * ,Vv0 * ,Vw0 * The reference signal Vu0 is shifted relative to the signal level of the carrier signal Vt so that the average value of the signal level of the carrier signal Vt increases or decreases by a predetermined amount over a period longer than the period of the reference signal. * ,Vv0 * ,Vw0 * In the example of FIG. 2, the relative signal levels of the reference signal Vu0 and the carrier signal Vt are shifted. * ,Vv0 * ,Vw0 * The relative signal level of the reference signal Vu0 * ,Vv0 * ,Vw0 * The reference signal Vu0 is shifted by superimposing a variable bias voltage Vz on it. * ,Vv0 * ,Vw0 * When Vz=0, the signal level of the reference signal Vu0 * ,Vv0 * ,Vw0 * The bias voltage Vz is set so that the average signal level of the reference signal Vu0 matches the average signal level of the carrier signal Vt.* ,Vv0 * ,Vw0 * The three reference signals Vu0 and Vu1 are constant over a period longer than the period of the reference signal Vu1. * ,Vv0 * ,Vw0 * The same bias voltage Vz is superimposed on the

[0032] The level shift circuit has a first shift amount when the three-phase motor 4 is operating at a first speed or a first load. The level shift circuit has a second shift amount having an absolute value greater than the absolute value of the first shift amount when the three-phase motor 4 is operating at a second speed lower than the first speed or a second load lower than the first load. The speed of the three-phase motor 4 may be estimated based on, for example, the DC voltage Vdc and the current I0, or may be obtained using a speed sensor (not shown) attached to the three-phase motor 4. The load of the three-phase motor 4 may be represented by the amplitudes of the voltages Vu, Vv, and Vw, or by the current I0, or by the torque obtained using a torque sensor (not shown) attached to the three-phase motor 4.

[0033] The level shift circuit may have a shift amount whose absolute value increases as the speed or load of the three-phase motor 4 decreases.

[0034] The level shift circuit shifts the reference signal Vu when the three-phase motor 4 is operating at a speed lower than a predetermined threshold or at a load lower than a predetermined threshold. * ,Vv * ,Vw * The maximum signal level of the reference signal Vu * ,Vv * ,Vw * The shift amount may be determined so that the minimum value of the signal level of the carrier signal Vt coincides with the minimum value of the signal level of the carrier signal Vt.

[0035] The level shift circuit may have a shift amount whose absolute value increases in accordance with a decrease in the speed or load of the three-phase motor 4.

[0036] The amount of shift in the signal level is determined by the reference signal generating circuit 11 based on the speed or load of the three-phase motor 4 and the reference signal Vu0 * ,Vv0 * ,Vw0 * The variable voltage source 12, under the control of the reference signal generating circuit 11, generates a bias voltage Vz corresponding to the determined shift amount.

[0037] In this way, the level shift circuit generates a reference signal Vu with a shifted signal level. * ,Vv * ,Vw * Generate.

[0038] [Operation of the first embodiment]

[0039] 3 is a diagram showing the operation of the three-phase motor 4 of the motor system according to the first comparative example when it is operating at high speed or high load. The motor system according to the first comparative example has the same configuration as the motor system of FIG. 1 except that the variable voltage source 12 and the combiners 13-1 to 13-3 are removed from the control circuit 6 of FIG. 2. In this case, the reference signal Vu0 * ,Vv0 * ,Vw0 * is the reference signal Vu * ,Vv * ,Vw * The carrier signal Vt has a minimum value Vt0, a maximum value Vt2, and an average value Vt1. When the three-phase motor 4 is operating at high speed or under high load, the reference signal Vu * ,Vv * ,Vw * The amplitude of is relatively large.

[0040] 4 is a diagram showing the operation of the three-phase motor 4 of the motor system according to the first comparative example when the motor 4 is operating at a low speed or a low load. When the three-phase motor 4 is operating at a low speed or a low load, the reference signal Vu * ,Vv * ,Vw * The amplitude of becomes relatively small.

[0041] When the three-phase motor 4 is operating at low speed or low load, two-phase modulation can reduce the leakage current Ileak more than three-phase modulation. However, when a common current detection resistor R1 is used to detect the currents of each phase of the three-phase motor 4, two-phase modulation may result in the duration Ton1 during which only one of the switching elements Q1, Q3, and Q5 in the upper arm circuit is turned on being shorter than the duration Tdet required to detect the current I0. In this case, the duration Ton1 must be forcibly extended so that Ton1 ≥ Tdet in order to detect the current I0, or the current I0 must be estimated based on the previous conditions without being detected. In either case, control stability is reduced. Therefore, when a common current detection resistor R1 is used to detect the currents of the three-phase motor 4 and the three-phase motor 4 is operating at low speed or low load, it is necessary to perform three-phase modulation while still reducing the leakage current to the same extent as two-phase modulation.

[0042] Next, the operation of reducing leakage current by the motor drive device according to the embodiment will be described.

[0043] 5 is a diagram showing a first operation of the control circuit 6 for reducing leakage current when the three-phase motor 4 of FIG. 1 is operating at a low speed or a low load. * ,Vv0 * ,Vw0 * By superimposing a positive bias voltage Vz on the reference signal Vu * ,Vv * ,Vw * The average value Vav of the signal level of the carrier signal Vt is greater than the average value Vt1 of the signal level of the carrier signal Vt. * ,Vv * ,Vw * The maximum signal level of the carrier signal Vt may be determined to be equal to the maximum signal level Vt2 of the carrier signal Vt.

[0044] 6 is a diagram showing a second operation of the control circuit 6 for reducing leakage current when the three-phase motor 4 of FIG. 1 is operating at a low speed or a low load. * ,Vv0 * ,Vw0 * By superimposing a negative bias voltage Vz on the reference signal Vu * ,Vv * ,Vw * The average value Vav of the signal level of the carrier signal Vt is smaller than the average value Vt1 of the signal level of the carrier signal Vt. * ,Vv * ,Vw * The minimum signal level of the carrier signal Vt may be determined to be equal to the minimum signal level Vt0 of the carrier signal Vt.

[0045] 7 is a diagram for explaining the generation of the control signals S1 to S6 in the case of FIG. 4. T indicates the time length of one period of the carrier signal Vt. Va * is the time period of the reference signal Vu in a period equal to one period of the carrier signal Vt. * ,Vv * ,Vw * Vb indicates the signal with the highest signal level among * During the same period, the reference signal Vu * ,Vv * ,Vw * Vc indicates a signal with an intermediate signal level. * During the same period, the reference signal Vu * ,Vv * ,Vw * Sa, Sb, and Sc indicate the signals having the minimum signal level among the control signals S1, S3, and S5. * ,Vb * ,Vc * The corresponding signals are shown in the table below. * If the signal level of the reference signal Vb is equal to or greater than the signal level of the carrier signal Vt, the control signal Sa is at a high level, otherwise the control signal Sa is at a low level. * ,Vc *and the signal level of the carrier signal Vt, the level becomes high or low.

[0046] 8 is a diagram for explaining the generation of the control signals S1 to S6 in the case of FIG. * ,Vv0 * ,Vw0 * By superimposing a positive bias voltage Vz on the reference signal Va * ,Vb * ,Vc * As a result, the time during which the control signals Sa, Sb, and Sc are at a high level is longer than in the case of Fig. 7. However, the difference in the time length during which the control signals Sa and Sb are at a high level is the same as in Fig. 7, and the difference in the time length during which the control signals Sb and Sc are at a high level is the same as in Fig. 7.

[0047] 9 is a diagram for explaining the generation of the control signals S1 to S6 in the case of FIG. * ,Vv0 * ,Vw0 * By superimposing a negative bias voltage Vz on the reference signal Va * ,Vb * ,Vc * As a result, the time during which the control signals Sa, Sb, and Sc are at a high level is shorter than in the case of Fig. 7. However, the difference in the time length during which the control signals Sa and Sb are at a high level is the same as in Fig. 7, and the difference in the time length during which the control signals Sb and Sc are at a high level is the same as in Fig. 7.

[0048] Next, the principle of how the motor drive device according to the embodiment reduces leakage current will be described.

[0049] FIG. 10 is a diagram for explaining the calculation of leakage current according to the first embodiment. As the speed or load of the three-phase motor 4 decreases, the amplitude of the voltages Vu, Vv, and Vw applied to the three-phase motor 4 decreases, and therefore the difference in the duration during which the control signals S1, S3, and S5 are at a high level also decreases. When the speed or load of the three-phase motor 4 is sufficiently small so that the durations during which the control signals S1, S3, and S5 are at a high level can be considered to be approximately the same, the leakage current Ileak can be calculated based on the waveforms of the control signals Sa, Sb, and Sc (corresponding to the control signals S1, S3, and S5) shown in FIG. 10. The control signals Sa, Sb, and Sc have a duty ratio of 2α per one period T of the carrier signal Vt.

[0050] As the amplitude of the output voltage of the inverter circuit 3 decreases, the voltages Vu, Vv, Vw applied to the windings 4u, 4v, 4w of the three-phase motor 4 approach a square wave having a duty ratio of 2α.

[0051] The leakage current Ileak is expressed by the following equation using the common mode voltage Vm and the stray capacitance Cs:

[0052]

number

[0053] The common mode voltage Vm can be expanded in a Fourier series as follows:

[0054]

number

number

number

number

[0055] According to equations (2) to (5), the common mode voltage Vm contains a fundamental component equal to the frequency fc=1 / T of the carrier signal Vt, and the amplitude of the k-th harmonic component is inversely proportional to k.

[0056] The magnitude Z of the impedance of the stray capacitance Cs for the kth harmonic component of the frequency of the carrier signal Vt k is Z k =1 / (ω k ·Cs), where ω k = 2πk / T = 2πk fc. Therefore, the magnitude of the impedance Z k is inversely proportional to k.

[0057] It is known that the effect of leakage current Ileak on the human body decreases as the frequency increases. For example, in a frequency band above approximately 1 kHz, the effect of leakage current Ileak on the human body is proportional to approximately 1 / fc. Therefore, the magnitude of leakage current measured by connecting a low-pass filter that simulates this effect on the human body between the three-phase motor 4 and ground is regulated. The filter may include, for example, a parallel circuit of a resistor and a capacitor.

[0058] The fundamental wave component I1 and the fundamental wave component I2 of the carrier signal Vt contained in the leakage current Ileak k Harmonic component I k Since the magnitude of the impedance is inversely proportional to k, I k / I1=k×(a k / a1). Furthermore, as mentioned above, the low frequency components of the leakage current Ileak are likely to affect the human body, and the effect is roughly inversely proportional to the frequency. Taking these into consideration, the k-th harmonic component Ileak of the leakage current Ileak k The influence of the fundamental wave component I1 on the human body is (a k Therefore, the magnitude (relative value) of the leakage current Ileak', which takes into account the effect on the human body, can be approximated by the following formula:

[0059]

number

[0060] FIG. 11 is a graph showing the results of a simulation of leakage current according to the first embodiment. FIG. 11 shows the results of calculating leakage current Ileak' using equation (6) for n=10 and normalizing it by the leakage current value when α=0.25. When the control signals S1 to S6 of the inverter circuit 3 are generated using pulse width modulation, the carrier signal Vt has a frequency fc of approximately several kHz. The leakage current Ileak predominantly contains a fundamental component and low-order harmonic components. Considering the amplitude of each harmonic component of the common mode voltage Vm, which is determined by the coefficient α, the impedance characteristics of the stray capacitance Cs, and the low-pass characteristics of the measurement system for the leakage current Ileak, the leakage current Ileak' can be roughly calculated using equation (6).

[0061] As shown in FIG. 11, when the coefficient α varies, the leakage current Ileak' also varies. α=0.25 corresponds to the case in FIG. 4, α>0.25 corresponds to the case in FIG. 5, and α<0.25 corresponds to the case in FIG. 6. FIG. 11 shows that the leakage current Ileak' can be reduced whether α is increased or decreased from 0.25. FIG. 11 also shows that when the signal level of the reference signal is not shifted (i.e., when α=0.25), the leakage current Ileak' is at its maximum, and that the leakage current Ileak' decreases as the absolute value of the shift amount increases.

[0062] Reference signal Vu * ,Vv * ,Vw * The maximum signal level of the reference signal Vu * ,Vv * ,Vw * By determining the shift amount so that the minimum value of the signal level of Vt coincides with the minimum value of the signal level of the carrier signal Vt, the effect of reducing leakage current can be maximized without causing distortion in the output voltage of the inverter circuit 3.

[0063] Generally, the lower the speed of the three-phase motor 4 or the lighter the load on the three-phase motor 4, the smaller the amplitude of the voltage applied to each winding of the three-phase motor 4. Therefore, the leakage current can be reduced by increasing or decreasing the shift amount depending on the speed or load of the three-phase motor 4.

[0064] The leakage current Ileak is generated by fluctuations in the common-mode voltage Vm, i.e., the AC component propagating through the stray capacitance Cs. The AC component of the common-mode voltage Vm corresponds to the fundamental and harmonics of the carrier signal Vt. * ,Vv0 * ,Vw0 * Even if the signal level of the reference signal Vu0 is shifted to increase or decrease the voltages Vu, Vv, and Vw, the difference between the voltages Vu, Vv, and Vw does not change, and the operation of the three-phase motor 4 is hardly affected. * ,Vv0 * ,Vw0 * By shifting the signal levels of the common-mode voltages Vu, Vv, and Vw to increase or decrease them, the DC component of the common-mode voltage Vm increases, which in turn reduces the AC component of the common-mode voltage Vm, thereby reducing leakage current.

[0065] According to the motor drive device of this embodiment, when three-phase motor 4 is driven using three-phase modulation, leakage current Ileak can be reduced more than in the past.

[0066] According to the motor drive device of this embodiment, while performing three-phase modulation, it is possible to reduce leakage current to the same extent as when performing two-phase modulation.

[0067] According to the motor drive device of this embodiment, leakage current Ileak can be reduced particularly when the three-phase motor 4 is operating at a low speed or under a low load.

[0068] [Modification of the first embodiment] FIG. 12 shows a reference signal Vaa generated in a control circuit of a motor drive device according to a modification of the first embodiment. *1 is a diagram showing the waveform of a reference signal Vu0 generated by the reference signal generating circuit 11. * ,Vv0 * ,Vw0 * is not limited to having a sinusoidal waveform containing only a fundamental component, but may also contain harmonics, for example, the fundamental and third harmonics. * The reference signal Vaa includes a fundamental wave Vf and a third harmonic Vh. * contains the third harmonic Vh, the reference signal Vaa * The peak of the reference signal Vaa is lower than the peak of the fundamental wave Vf. * is the sinusoidal reference signal Vu0 * ,Vv0 * ,Vw0 * The reference signal Vaa can be shifted by a larger amount than when the reference signal Vaa is shifted, and the leakage current Ileak can be further reduced. * contains the third harmonic Vh, the reference signal Vaa * The waveform of the reference signal Vaa is closer to a square wave than the waveform of the fundamental wave Vf. * has a higher voltage utilization factor than the fundamental signal Vf. * The reference signal Vu0 has a waveform similar to that of * ,Vv0 * ,Vw0 * By generating a waveform of 1 / 2 V, the leakage current Ileak can be further reduced compared to when the waveform is sinusoidal.

[0069] [Advantages of the first embodiment] The motor drive device according to the first embodiment is a motor drive device for driving a three-phase motor 4 and includes an inverter circuit 3 and a control circuit 6. The inverter circuit 3 includes multiple switching elements, converts DC voltage to AC voltage, and supplies the AC voltage to the three-phase motor 4. The control circuit 6 generates control signals for the multiple switching elements using pulse width modulation. The control circuit 6 includes a reference signal generation circuit 11, a carrier signal generation circuit 14, a level shift circuit, and comparators 15-1 to 15-3. The reference signal generation circuit 11 generates three first reference signals, each of which represents a desired waveform of a phase voltage of the three-phase motor 4 and has a first period. The carrier signal generation circuit 14 generates a carrier signal having a second period that is shorter than the first period. The level shift circuit generates three second reference signals by shifting the signal levels of the three first reference signals relative to the signal level of the carrier signal so that the average value of the signal levels of the three first reference signals increases or decreases by a predetermined shift amount with respect to the average value of the signal level of the carrier signal over a period longer than the first period. The comparators 15-1 to 15-3 generate control signals by comparing the signal levels of the three second reference signals with the signal level of the carrier signal. The level shift circuit has a first shift amount when the three-phase motor 4 operates at a first speed or a first load, and has a second shift amount having an absolute value greater than the absolute value of the first shift amount when the three-phase motor 4 operates at a second speed lower than the first speed or a second load lower than the first load.

[0070] According to this configuration, when the three-phase motor 4 is driven using three-phase modulation, the leakage current Ileak can be reduced more than before.

[0071] According to the motor drive device of the first embodiment, the level shift circuit may have a third shift amount determined so that, when the three-phase motor 4 is operating at a speed lower than the first threshold value or at a load lower than the second threshold value, the maximum value of the signal levels of the three second reference signals matches the maximum value of the signal level of the carrier signal, or the minimum value of the signal levels of the three second reference signals matches the minimum value of the signal level of the carrier signal.

[0072] According to this configuration, the effect of reducing the leakage current Ileak can be maximized without causing distortion in the output voltage of the inverter circuit 3.

[0073] According to the motor drive device of the first embodiment, each of the three first reference signals may include a fundamental wave and a third harmonic.

[0074] According to this configuration, the leakage current Ileak can be further reduced when the three-phase motor 4 is driven using three-phase modulation.

[0075] According to the motor drive device of the first embodiment, the control circuit 6 may detect the current of each phase of the three-phase motor 4 using a common current detection resistor R1.

[0076] According to this configuration, it is not necessary to provide a current detection resistor for each winding of the three-phase motor 4, and the configuration of the motor system can be simplified.

[0077] [Second embodiment] As described above, by detecting the current I0_1 when only one of the switching elements Q1, Q3, and Q5 is turned on, and further detecting the current I0_2 when only two of the switching elements Q1, Q3, and Q5 are turned on, it is possible to use a common current detection resistor R1 to detect the currents Iu, Iv, and Iw of each phase of the three-phase motor 4. In order to accurately detect the currents I0_1 and I0_2, it is necessary to set the time length Ton1 during which only one of the switching elements Q1, Q3, and Q5 is turned on and the time length Ton2 during which only two of the switching elements Q1, Q3, and Q5 are turned on to be equal to or longer than the predetermined time length Tdet.

[0078] When the difference in pulse width between the control signals S1, S3, and S5 is sufficiently large, Ton1 ≧ Tdet and Ton2 ≧ Tdet are satisfied. However, when the difference in pulse width between the control signals S1, S3, and S5 is small, at least one of Ton1 ≧ Tdet and Ton2 ≧ Tdet is not satisfied, and the currents I0_1 and I0_2 may not be detected accurately.

[0079] In the second embodiment, a motor system is described that can accurately detect the currents Iu, Iv, and Iw of each phase of a three-phase motor 4 using a common current detection resistor R1, even when the difference in pulse width between control signals S1, S3, and S5 is small.

[0080] [Configuration of the second embodiment] Fig. 13 is a block diagram showing the configuration of a control circuit 6A of a motor system according to a second embodiment. The motor system according to the second embodiment includes a control circuit 6A of Fig. 13 instead of the control circuit 6 of Fig. 2. The control circuit 6A includes a reference signal generation circuit 11A instead of the reference signal generation circuit 11 of Fig. 2, and further includes delay circuits 18-1 to 18-3.

[0081] Under the control of the reference signal generating circuit 11A, the delay circuits 18-1 to 18-3 shift the relative temporal positions of the output signals of the comparators 15-1 to 15-3 within each period of the carrier signal Vt. As a result, within each period of the carrier signal Vt, the relative temporal positions of the control signals S1, S3, and S5 are shifted. At the same time, the relative temporal positions of the control signals S2, S4, and S6 are also shifted. Specifically, the delay circuits 18-1 to 18-3 shift the relative temporal positions of the control signals S1, S3, and S5 within each period of the carrier signal Vt so that the length of a first time period (time length Ton1) during which any two of the control signals S1, S3, and S5 are at low level and the remaining one is at high level is equal to or greater than a predetermined time length Tdet, and so that the length of a second time period (time length Ton2) during which any two of the control signals S1, S3, and S5 are at high level and the remaining one is at low level is equal to or greater than a predetermined time length Tdet. In other words, the delay circuits 18-1 to 18-3 shift the relative temporal positions of the control signals S1, S3, and S5 so as to satisfy Ton1≧Tdet and Ton2≧Tdet within each period of the carrier signal Vt.

[0082] Buffers 16-1 to 16-3 output the output signals of delay circuits 18-1 to 18-3 as time-shifted control signals S1, S3, and S5, respectively. Inverters 17-1 to 17-3 invert the output signals of delay circuits 18-1 to 18-3 and output them as time-shifted control signals S2, S4, and S6, respectively.

[0083] The reference signal generating circuit 11A generates the reference signal Vu0 * ,Vv0 * ,Vw0 * Furthermore, the reference signal generating circuit 11A generates a reference signal Vu0 having the determined amplitude and the magnitude of the bias voltage Vz. * ,Vv0 * ,Vw0 *The reference signal generating circuit 11A calculates the pulse widths of the output signals of the comparators 15-1 to 15-3 (i.e., the pulse widths of the control signals S1, S3, and S5) assuming that the bias voltage Vz having the determined magnitude is generated by the variable voltage source 12. Here, the pulse width indicates the length of time that the signal is at a high level. The reference signal generating circuit 11A determines the amount of time shift by the delay circuits 18-1 to 18-3 based on the pulse widths of the output signals of the comparators 15-1 to 15-3.

[0084] When the output signals of comparators 15-1 to 15-3 satisfy Ton1≧Tdet and Ton2≧Tdet, the relative temporal positions of the output signals of comparators 15-1 to 15-3 are not changed. On the other hand, when the output signals of comparators 15-1 to 15-3 do not satisfy at least one of Ton1≧Tdet and Ton2≧Tdet, the relative temporal positions of the output signals of comparators 15-1 to 15-3 are shifted so as to satisfy Ton1≧Tdet and Ton2≧Tdet.

[0085] If the amount of signal level shift is excessive, the pulse width of the output signals of comparators 15-1 to 15-3 will also be too large or too small, and it may be impossible to time-shift the output signals of comparators 15-1 to 15-3 so that Ton1≧Tdet and Ton2≧Tdet are satisfied. Therefore, reference signal generation circuit 11A determines the magnitude of bias voltage Vz under the condition that the control signals S1, S3, and S5 time-shifted by delay circuits 18-1 to 18-3 satisfy Ton1≧Tdet and Ton2≧Tdet. Under this condition, reference signal generation circuit 11A may determine the magnitude of bias voltage Vz so that it has as large an absolute value as possible, for example.

[0086] As a result, the level shift circuit (i.e., variable voltage source 12 and combiners 13-1 to 13-3) has a signal level shift amount determined so that the control signals S1, S3, and S5 shifted in time by delay circuits 18-1 to 18-3 satisfy Ton1 ≧ Tdet and Ton2 ≧ Tdet when three-phase motor 4 is operating at a speed lower than a predetermined threshold or with a load smaller than a predetermined threshold. This shift amount may have the maximum absolute value within the range of shift amounts in which the control signals S1, S3, and S5 shifted in time by delay circuits 18-1 to 18-3 satisfy Ton1 ≧ Tdet and Ton2 ≧ Tdet.

[0087] [Operation of the second embodiment] FIG. 14 is a diagram for explaining generation of control signals when the difference in pulse width of the control signals is sufficiently large in the motor system according to the second embodiment. Sa10, Sb10, Sc10 indicate control signals output from the delay circuits 18-1 to 18-3 when the bias voltage Vz=0. Sa11, Sb11, Sc11 indicate control signals output from the delay circuits 18-1 to 18-3 when the bias voltage Vz>0. Sa12, Sb12, Sc12 indicate control signals output from the delay circuits 18-1 to 18-3 when the bias voltage Vz<0. As described above with reference to FIGS. 7 to 9, the control signals Sa10, Sb10, Sc10, etc. are generated by controlling the reference signal Va among the control signals S1, S3, S5. * ,Vb * ,Vc * 7 to 9, the pulse widths of the control signals Sa10 to Sc10, etc. are varied to a sufficient extent so that Ton1 ≥ Tdet and Ton2 ≥ Tdet are satisfied. When the difference in pulse width between the control signals Sa10 to Sc10, etc. is large enough to satisfy Ton1 ≥ Tdet and Ton2 ≥ Tdet, the delay circuits 18-1 to 18-3 output the output signals of the comparators 15-1 to 15-3 as is without shifting them in time. As can be seen from FIGS. 7 to 9, the pulse widths of the control signals Sa, Sb, and Sc vary depending on the bias voltage Vz. However, regardless of changes in the bias voltage Vz, the control signals Sa10 to Sc10, etc. have constant time lengths Ton1 and Ton2.

[0088] FIG. 15 is a diagram illustrating generation of control signals when the difference in pulse widths of the control signals is small in a motor system according to a second comparative example. Sa20, Sb20, and Sc20 indicate control signals generated in a motor system without delay circuits 18-1 to 18-3. Sa21, Sb21, and Sc21 indicate control signals corrected to satisfy Ton1≧Tdet and Ton2≧Tdet in a motor system without delay circuits 18-1 to 18-3. When the difference in pulse widths of the control signals Sa20, Sb20, and Sc20 is small and Ton1≧Tdet and Ton2≧Tdet are not satisfied, it is possible to increase the pulse width of one of the control signals Sa20, Sb20, and Sc20 so that Ton1≧Tdet and Ton2≧Tdet are satisfied. In the example of FIG. 15, the pulse widths of the control signals Sa20 and Sb20 are increased. However, when the pulse widths of the control signals Sa20, Sb20, and Sc20 increase or decrease, distortion occurs in the waveforms of the corresponding AC voltages Vu, Vv, and Vw. Therefore, it is necessary to satisfy Ton1 ≧ Tdet and Ton2 ≧ Tdet without causing distortion in the waveforms of the AC voltages Vu, Vv, and Vw.

[0089] 16 is a diagram illustrating the generation of control signals when a positive bias voltage is superimposed on the reference signal and the difference in pulse width between the control signals is small in the motor system according to the second embodiment. * ,Vv0 * ,Vw0 * Sa31, Sb31, and Sc31 represent the control signals output from the comparators 15-1 to 15-3 when a bias voltage Vz1>0 is superimposed on the reference signal Vu0. * ,Vv0 * ,Vw0 * Sa32, Sb32, and Sc32 represent the control signals output from the comparators 15-1 to 15-3 when a bias voltage Vz2>0 (Vz1>Vz2) is superimposed on the reference signal Vu0. * ,Vv0 * ,Vw0 *10 shows the control signals output from the delay circuits 18-1 to 18-3 when a bias voltage Vz2 is superimposed on the reference signal Va. * ,Vb * ,Vc * correspond to the following:

[0090] Referring to FIG. 16, the control signals Sa30, Sb30, and Sc30 have pulse widths d1×2, d2×2, and d3×2, respectively. In the example of FIG. 16, the differences between the pulse widths d1, d2, and d3 are small, and neither Ton1≧Tdet nor Ton2≧Tdet is satisfied. In this case, the time lengths Ton1 and Ton2 can be extended by shifting the relative temporal positions of the control signals Sa30, Sb30, and Sc30. However, to satisfy Ton1≧Tdet and Ton2≧Tdet and to shift the relative temporal positions of the control signals Sa30, Sb30, and Sc30 within the period T of the carrier signal Vt, the pulse widths d2 and d3 must satisfy the following equation:

[0091] d2×2≦T-Tdet (1) d3×2≦T-Tdet×2 (2)

[0092] 7 to 9, the pulse width of the control signal changes depending on the magnitude of the bias voltage. Therefore, if either the condition of formula (1) or formula (2) is not satisfied, it is possible to generate a control signal having a pulse width that satisfies the conditions of formula (1) and formula (2) by reducing the absolute value of the bias voltage.

[0093] 16, the control signals Sa31, Sb31, and Sc31 have pulse widths d1a×2, d2a×2, and d3a×2 that are smaller than the pulse widths d1×2, d2×2, and d3×2, respectively, because the absolute value of the bias voltage is smaller than that of the control signals Sa30, Sb30, and Sc30 (|Vz1|>|Vz2|). In this case, the amount of change in the bias voltage is set so that the changed pulse widths d2a and d3a satisfy the following equation:

[0094] d2a×2≦T-Tdet (1a) d3a×2≦T-Tdet×2 (2a)

[0095] 16, the control signals Sa32, Sb32, and Sc32 are obtained by shifting the relative temporal positions of the control signals Sa31, Sb31, and Sc31 so that Ton1≧Tdet and Ton2≧Tdet are satisfied. In this case, the relative temporal positions of the control signals Sa31 to Sc31 may be shifted within the ranges of the corresponding time lengths d1a to d3a so that each control signal does not go low at the center of the period T of the carrier signal Vt.

[0096] According to the example of Figure 16, when the time lengths d2 and d3 satisfy the conditions of equations (1a) and (2a), the leakage current can be reduced by setting a positive bias voltage Vz while ensuring the time length Tdet required to detect the current I0.

[0097] The bias voltage Vz2 may have the maximum absolute value within the range of bias voltages that satisfy Ton1 ≥ Tdet and Ton2 ≥ Tdet, thereby minimizing the leakage current while ensuring the time length Tdet required to detect the current I0.

[0098] 17 is a diagram illustrating the generation of control signals when a negative bias voltage is superimposed on the reference signal and the difference in pulse width between the control signals is small in the motor system according to the second embodiment. * ,Vv0 * ,Vw0 * Sa34, Sb34, and Sc34 represent the control signals output from the comparators 15-1 to 15-3 when a bias voltage Vz3<0 is superimposed on the reference signal Vu0. * ,Vv0 * ,Vw0 * Sa35, Sb35, and Sc35 represent the control signals output from the comparators 15-1 to 15-3 when a bias voltage Vz4<0 (|Vz3|>|Vz4|) is superimposed on the reference signal Vu0. *,Vv0 * ,Vw0 * 10 shows the control signals output from the delay circuits 18-1 to 18-3 when a bias voltage Vz4 is superimposed on the reference signal Va. * ,Vb * ,Vc * correspond to the following:

[0099] Referring to Figure 17, the control signals Sa33, Sb33, and Sc33 have pulse widths d11 x 2, d12 x 2, and d13 x 2, respectively. In the example of Figure 17, the difference between the pulse widths d11, d12, and d13 is small, and neither Ton1 ≥ Tdet nor Ton2 ≥ Tdet is satisfied. In this case, the time lengths Ton1 and Ton2 can be extended by shifting the relative temporal positions of the control signals Sa33, Sb33, and Sc33. However, in order to shift the relative temporal positions of the control signals Sa33, Sb33, and Sc33 so as to satisfy Ton1 ≥ Tdet and Ton2 ≥ Tdet, the pulse widths d11 and d12 must satisfy the following equation:

[0100] d11×2≧Tdet×2 (3) d12×2≧Tdet (4)

[0101] If either of the conditions of equations (3) and (4) is not satisfied, a control signal having a pulse width that satisfies the conditions of equations (3) and (4) can be generated by reducing the absolute value of the bias voltage.

[0102] 17, the absolute value of the bias voltage for control signals Sa34, Sb34, and Sc34 is smaller than that for control signals Sa33, Sb33, and Sc33 (|Vz3|>|Vz4|), and so the control signals Sa34, Sb34, and Sc34 have pulse widths d11a×2, d12a×2, and d13a×2, respectively, which are larger than pulse widths d11×2, d12×2, and d13×2. In this case, the amount of change in the bias voltage is set so that the changed pulse widths d11a and d12a satisfy the following equation:

[0103] d11a×2≧Tdet×2 (3a) d12a×2≧Tdet (4a)

[0104] 17, the control signals Sa35, Sb35, and Sc35 are obtained by shifting the relative temporal positions of the control signals Sa34, Sb34, and Sc34 so that Ton1≧Tdet and Ton2≧Tdet are satisfied. In this case, the relative temporal positions of the control signals Sa34 to Sc34 may be shifted within the ranges of the corresponding time lengths d11a to d13a so that each control signal does not go low at the center of the period T of the carrier signal Vt.

[0105] According to the example of Figure 17, when the time lengths d11 and d12 satisfy the conditions of equations (3a) and (4a), the leakage current can be reduced by setting a negative bias voltage Vz while ensuring the time length Tdet required to detect the current I0.

[0106] The bias voltage Vz4 may have the maximum absolute value within the range of bias voltages that satisfy Ton1 ≥ Tdet and Ton2 ≥ Tdet, thereby minimizing the leakage current while ensuring the time length Tdet required to detect the current I0.

[0107] As mentioned above, the bias voltage Vz is * ,Vv0 * ,Vw0 * On the other hand, the reference signal generating circuit 11A may determine the amount of time shift by the delay circuits 18-1 to 18-3 for each period of the carrier signal Vt, for example, based on the pulse width of the output signals of the comparators 15-1 to 15-3.

[0108] The operating characteristics of the three-phase motor 4, such as its rotation speed, are determined mainly by the duty ratio of the control signals S1-S6 of each phase. Therefore, even if the control signals S1-S6 of each phase are shifted in time within each cycle of the carrier signal Vt, the three-phase motor 4 can be driven in substantially the same manner as before the shift.

[0109] The motor drive device according to this embodiment can generate control signals S1 to S6 so as to satisfy Ton1 ≥ Tdet and Ton2 ≥ Tdet, thereby enabling accurate detection of the currents of the phases of the three-phase motor 4 using a common current detection resistor R1.

[0110] The motor drive device according to this embodiment does not change the time lengths of the pulse widths of only one or two of the three control signals, as in the case of Fig. 15. Therefore, the motor drive device according to this embodiment can accurately detect the currents of each phase of the three-phase motor 4 using a common current detection resistor R1 without causing distortion in the waveforms of the AC voltages Vu, Vv, and Vw.

[0111] [Advantages of the second embodiment] The motor drive device according to the second embodiment may further include delay circuits 18-1 to 18-3 that shift the relative temporal positions of the three control signals within each cycle of the carrier signal. The delay circuits 18-1 to 18-3 shift the relative temporal positions of the three control signals within each cycle of the carrier signal so that the length of a first time period during which any two of the three control signals are at low level and the remaining one of the three control signals is at high level is equal to or longer than a predetermined time, and so that the length of a second time period during which any two of the three control signals are at high level and the remaining one of the three control signals is at low level is equal to or longer than a predetermined time.

[0112] According to this configuration, the current of each phase of the three-phase motor 4 can be accurately detected using a common current detection resistor R1.

[0113] According to the motor drive device of the second embodiment, the level shift circuit may have a fourth shift amount determined so that, when the three-phase motor is operating at a speed lower than the first threshold value or at a load lower than the second threshold value, the lengths of the first and second time periods for the three control signals having relative temporal positions shifted by the delay circuit are equal to or greater than a predetermined time length.

[0114] According to this configuration, the leakage current Ileak can be reduced more than conventionally when driving the three-phase motor 4 using three-phase modulation while accurately detecting the current of each phase of the three-phase motor 4 using a common current detection resistor R1.

[0115] According to the motor drive device of the second embodiment, the fourth shift amount may have the maximum absolute value within the range of shift amounts in which the lengths of the first and second time periods for the three control signals having relative temporal positions shifted by the delay circuits 18-1 to 18-3 are equal to or greater than a predetermined time length.

[0116] According to this configuration, the leakage current Ileak can be minimized when driving the three-phase motor 4 using three-phase modulation while accurately detecting the current of each phase of the three-phase motor 4 using a common current detection resistor R1.

[0117] [Third embodiment] FIG. 18 is a diagram showing the configuration of an air conditioner 100 according to the third embodiment. The air conditioner 100 includes an indoor unit 110 and an outdoor unit 120. The indoor unit 110 includes an indoor motor 111, an indoor fan 112, an indoor heat exchanger 113, and a controller 114. The outdoor unit 120 includes an indoor motor 121, an outdoor fan 122, an outdoor heat exchanger 123, a compressor 124, a three-phase motor 124a, an expansion valve 125, a four-way valve 126, and a motor drive device 127. The indoor unit 110 and the outdoor unit 120 are connected via refrigerant piping 230. The compressor 124 includes a three-phase motor 124a. The motor drive device 127 includes at least one inverter circuit 3 and a control circuit 6, and drives the three-phase motor 124a in the same manner as the motor drive device according to the first or second embodiment. This makes it possible to reduce the leakage current Ileak more than before when driving the three-phase motor 124a using three-phase modulation.

[0118] [Advantages of the third embodiment] The air conditioner 100 according to the third embodiment includes a three-phase motor 124 a and a motor driving device 127 .

[0119] With this configuration, when the three-phase motor 124a is driven using three-phase modulation, the leakage current Ileak can be reduced more than before.

[0120] [Other embodiments] As described above, the embodiments have been described as examples of the technology disclosed in this application. For this purpose, the accompanying drawings and detailed description have been provided. However, the technology in this disclosure is not limited to these, and can be applied to embodiments in which modifications, substitutions, additions, omissions, etc. are made as appropriate. Furthermore, the components described in the above embodiments can be combined to create new embodiments.

[0121] Therefore, the components shown in the accompanying drawings and detailed description may include not only components essential for solving the problem, but also components that are not essential for solving the problem in order to illustrate the above technology. Therefore, the fact that these non-essential components are shown in the accompanying drawings and / or detailed description should not be interpreted as immediately identifying these non-essential components as essential.

[0122] Furthermore, since the above-described embodiments are intended to illustrate the technology of the present disclosure, various modifications, substitutions, additions, omissions, etc. may be made within the scope of the claims or their equivalents.

[0123] The carrier signal Vt is not limited to a triangular wave, but may have other waveforms such as a sawtooth wave.

[0124] Reference signal Vu0 relative to the signal level of carrier signal Vt * ,Vv0 * ,Vw0 * To shift the relative signal levels of the reference signal Vu0 * ,Vv0 * ,Vw0 * Instead of superimposing the variable bias voltage Vz on the carrier signal Vt, the variable bias voltage Vz may be superimposed on the carrier signal Vt.

[0125] Reference signal Vu0 relative to the signal level of carrier signal Vt * ,Vv0 * ,Vw0 * As an alternative to analog signal processing, which involves superimposing a variable bias voltage Vz to shift the relative signal levels of the signals, digital signal processing may be used, in which case the signal levels are represented by digital values.

[0126] The functions of components 11-17-3 of control circuit 6 may be implemented as dedicated circuits, as programs running on one or more processors or microcontrollers, or a combination thereof. Similarly, the functions of components 11A-18-3 of control circuit 6A may be implemented as dedicated circuits, as programs running on one or more processors or microcontrollers, or a combination thereof.

[0127] [Summary of the embodiment] According to the motor drive device according to the first aspect of the present disclosure, A motor drive device that drives a three-phase motor, an inverter circuit including a plurality of switching elements, which converts a DC voltage into an AC voltage and supplies the AC voltage to the three-phase motor; a control circuit that generates control signals for the plurality of switching elements using pulse width modulation; The control circuit a first signal generating circuit that generates three first reference signals each representing a desired waveform of a phase voltage of the three-phase motor and each having a first period; a second signal generating circuit that generates a carrier signal having a second period that is shorter than the first period; a level shift circuit that generates three second reference signals by shifting the relative signal levels of the three first reference signals with respect to the signal level of the carrier signal so that an average value of the signal levels of the three first reference signals increases or decreases by a predetermined shift amount with respect to the average value of the signal level of the carrier signal over a period longer than the first period; a comparator that generates three control signals corresponding to the three second reference signals, respectively, by comparing the signal levels of the three second reference signals with the signal level of the carrier signal; The level shift circuit has a first shift amount when the three-phase motor is operating at a first speed or a first load, and has a second shift amount having an absolute value greater than the absolute value of the first shift amount when the three-phase motor is operating at a second speed lower than the first speed or a second load lower than the first load.

[0128] According to the motor drive device according to the second aspect of the present disclosure, in the motor drive device according to the first aspect, The level shift circuit has a third shift amount determined so that, when the three-phase motor is operating at a speed lower than a first threshold value or at a load lower than a second threshold value, the maximum value of the signal levels of the three second reference signals matches the maximum value of the signal level of the carrier signal, or the minimum value of the signal levels of the three second reference signals matches the minimum value of the signal level of the carrier signal.

[0129] According to a motor drive device according to a third aspect of the present disclosure, in the motor drive device according to the first or second aspect, Each of the three first reference signals includes a fundamental wave and a third harmonic wave.

[0130] According to a motor drive device according to a fourth aspect of the present disclosure, in the motor drive device according to one of the first to third aspects, The control circuit detects the current of each phase of the three-phase motor using a common current detection resistor.

[0131] According to a motor drive device according to a fifth aspect of the present disclosure, in the motor drive device according to the first aspect, The motor drive device further includes a delay circuit that shifts the relative temporal positions of the three control signals within each period of the carrier signal so that the length of a first time period during which any two of the three control signals are at a low level and the remaining one of the three control signals is at a high level is equal to or greater than a predetermined time length, and so that the length of a second time period during which any two of the three control signals are at a high level and the remaining one of the three control signals is at a low level is equal to or greater than the predetermined time length.

[0132] According to a motor drive device according to a sixth aspect of the present disclosure, in the motor drive device according to the fifth aspect, The level shift circuit has a fourth shift amount determined so that, when the three-phase motor is operating at a speed lower than a first threshold or a load lower than a second threshold, the lengths of the first and second time periods for the three control signals having relative temporal positions shifted by the delay circuit are equal to or greater than the predetermined time length.

[0133] According to a motor drive device according to a seventh aspect of the present disclosure, in the motor drive device according to the sixth aspect, The fourth shift amount has the maximum absolute value within a range of shift amounts in which the lengths of the first and second time periods for the three control signals having relative temporal positions shifted by the delay circuit are equal to or greater than the predetermined time length.

[0134] An air conditioner 100 according to an eighth aspect of the present disclosure comprises: A three-phase motor; The motor drive device according to any one of the first to seventh aspects is provided. [Industrial Applicability]

[0135] A motor drive device according to an aspect of the present disclosure can be applied to drive a motor of a compressor of an air conditioner, for example. [Explanation of symbols]

[0136] 1 AC power supply 2 Rectifier circuit 3. Inverter circuit 4 Three-phase motor 5 Current detection circuit 6,6A control circuit 11,11A reference signal generation circuit 12 Variable voltage source 13-1~13-3 Synthesizer 14 Carrier signal generation circuit 15-1~15-3 Comparator 16-1~16-3 buffer 17-1~17-3 Inverter 18-1~18-3 Delay circuit 100 Air conditioner 110 Indoor unit 111 Indoor motor 112 Indoor fan 113 Indoor heat exchanger 114 Controller 120 Outdoor unit 121 Indoor motor 122 Outdoor fan 123 Outdoor heat exchanger 124 Compressor 124a three-phase motor 125 Expansion valve 126 Four-way valve 127 Motor drive unit 130 Refrigerant piping B1, B2 DC bus C1 capacitor Cs stray capacitance Q1~Q6 switching elements R1 Current detection resistor

Claims

1. A motor drive device that drives a three-phase motor, an inverter circuit including a plurality of switching elements, which converts a DC voltage into an AC voltage and supplies the AC voltage to the three-phase motor; a control circuit that generates control signals for the plurality of switching elements using pulse width modulation; The control circuit a first signal generating circuit that generates three first reference signals each representing a desired waveform of a phase voltage of the three-phase motor and each having a first period; a second signal generating circuit that generates a carrier signal having a second period that is shorter than the first period; a level shift circuit that generates three second reference signals by shifting the relative signal levels of the three first reference signals with respect to the signal level of the carrier signal so that an average value of the signal levels of the three first reference signals increases or decreases by a predetermined shift amount with respect to the average value of the signal level of the carrier signal over a period longer than the first period; a comparator that generates three control signals corresponding to the three second reference signals, respectively, by comparing the signal levels of the three second reference signals with the signal level of the carrier signal; the level shift circuit has a first shift amount when the three-phase motor is operating at a first speed or a first load, and has a second shift amount having an absolute value greater than the absolute value of the first shift amount when the three-phase motor is operating at a second speed lower than the first speed or a second load lower than the first load. Motor drive device.

2. the level shift circuit has a third shift amount determined so that, when the three-phase motor is operating at a speed lower than a first threshold value or at a load lower than a second threshold value, the maximum value of the signal levels of the three second reference signals coincides with the maximum value of the signal level of the carrier signal, or the minimum value of the signal levels of the three second reference signals coincides with the minimum value of the signal level of the carrier signal.

2. The motor drive device according to claim 1.

3. each of the three first reference signals includes a fundamental wave and a third harmonic; 2. The motor drive device according to claim 1.

4. the control circuit detects the current of each phase of the three-phase motor using a common current detection resistor; 2. The motor drive device according to claim 1.

5. the motor drive device further includes a delay circuit that shifts the relative temporal positions of the three control signals within each period of the carrier signal so that a first time period during which any two of the three control signals are at a low level and the remaining one of the three control signals is at a high level is equal to or longer than a predetermined time period, and so that a second time period during which any two of the three control signals are at a high level and the remaining one of the three control signals is at a low level is equal to or longer than the predetermined time period.

2. The motor drive device according to claim 1.

6. the level shift circuit has a fourth shift amount determined so that, when the three-phase motor is operating at a speed lower than a first threshold or a load lower than a second threshold, the lengths of the first and second time periods for the three control signals having relative temporal positions shifted by the delay circuit are equal to or greater than the predetermined time length.

6. The motor drive device according to claim 5.

7. the fourth shift amount has a maximum absolute value within a range of shift amounts in which the lengths of the first and second time periods for the three control signals having the relative temporal positions shifted by the delay circuit are equal to or greater than the predetermined time length; 7. The motor drive device according to claim 6.

8. A three-phase motor; and a motor drive device according to any one of claims 1 to 6. Air conditioner.

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