Evaluation structure, method for producing evaluation structure, and method for evaluating resin-cured layer

Abstract

To provide a structure for evaluation capable of quickly and accurately evaluating a resin cured layer with a simple structure, a method for manufacturing the structure for evaluation, and a method for evaluating the resin cured layer.SOLUTION: The evaluation structure 1 includes a substrate 2, a cured resin layer 3 disposed on the substrate 2 and having a metal wiring layer 6 therein, a metal pad layer 4 disposed on the cured resin layer 3, and a solder layer 5 disposed on the metal pad layer 4, and the metal wiring layer 6 is separated from the metal pad layer 4 by the cured resin layer 3.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to an evaluation structure, a method for manufacturing an evaluation structure, and a method for evaluating a cured resin layer. [Background technology]

[0002] In recent years, with the miniaturization of electronic devices, there has been an increasing need for smaller and more highly integrated semiconductor packages to be mounted on electronic devices. Packaging technologies being considered for use in manufacturing semiconductor packages include FOWLP (Fan-Out Wafer Level Packaging), which provides solder balls directly to a semiconductor chip via a re-distribution layer (RDL) without using a circuit board (see, for example, Patent Document 1).

[0003] An evaluation structure called a TEG (Test Element Group) is used to evaluate the reliability of semiconductor packages and materials used in semiconductor packages. The evaluation structure is a structure that mimics the structure of an actual semiconductor package. The evaluation structure is configured by providing a substrate such as a glass wafer with a resin cured layer used as a rewiring layer, a metal pad layer, a solder layer, and the like. A metal wiring layer that mimics the pattern used in an actual semiconductor package is arranged on the resin cured layer (see, for example, Patent Document 2). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. WO2020 / 105485 [Patent Document 2] Patent Publication No. 2021-189403 Summary of the Invention [Problem to be solved by the invention]

[0005] When evaluating a semiconductor package using the evaluation structure described above, for example, a thermal cycle test is performed on the evaluation structure. In the thermal cycle test, the strength (crack resistance) of the cured resin layer used in the evaluation structure can be evaluated by checking the number of cycles until cracks occur in the cured resin layer.

[0006] When conducting a thermal cycle test, it is believed that the closer the structure of the evaluation structure is to an actual semiconductor package, the higher the evaluation accuracy of the cured resin layer. However, if the structure of the evaluation structure is made closer to an actual semiconductor package, the structure of the evaluation structure becomes more complex, which may lead to more complex and costly manufacturing processes for the evaluation structure. Furthermore, it is thought that the number of cycles required until cracks appear in the cured resin layer will increase, which may increase the time required for evaluation.

[0007] The present disclosure has been made to solve the above-mentioned problems, and aims to provide an evaluation structure that can evaluate a resin-cured layer quickly and accurately with a simple structure, a method for manufacturing an evaluation structure, and a method for evaluating a resin-cured layer. [Means for solving the problem]

[0008] The gist of the present disclosure is as follows.

[0009] [1] An evaluation structure comprising: a substrate; a resin-cured layer disposed on the substrate and having a metal wiring layer therein; a metal pad layer disposed on the resin-cured layer; and a solder layer disposed on the metal pad layer, wherein the metal wiring layer is separated from the metal pad layer by the resin-cured layer.

[0010] In this evaluation structure, a resin-cured layer having a metal wiring layer therein, a metal pad layer, and a solder layer are arranged on a substrate, thereby realizing a structure simulating an actual semiconductor package, and enabling accurate evaluation of the resin-cured layer. In this evaluation structure, no connecting members such as vias are arranged in the resin-cured layer, and the metal wiring layer inside the resin-cured layer is isolated from the metal pad layer by the resin-cured layer. Therefore, the structure of the evaluation structure is simplified, and the manufacturing process of the evaluation structure can be avoided from becoming complicated. Furthermore, the complexity of factors affecting the evaluation results due to the structure can be avoided. In a thermal cycle test using this evaluation structure, stress is easily applied to the resin-cured layer between the metal wiring layer and the metal pad layer. Therefore, the number of cycles until cracks occur in the resin-cured layer is reduced, allowing for rapid evaluation of the resin-cured layer.

[0011] [2] The evaluation structure according to [1], wherein the metal wiring layer is located closer to the metal pad layer in the thickness direction of the cured resin layer. This configuration allows sufficient stress to be applied to the cured resin layer between the metal wiring layer and the metal pad layer during a thermal cycle test. This allows for rapid evaluation of the cured resin layer.

[0012] [3] The evaluation structure according to [1] or [2], wherein the metal wiring layer overlaps the metal pad layer and extends outward beyond the metal pad layer when viewed in the thickness direction of the cured resin layer. This configuration prevents the metal wiring layer from being excessively small, thereby suppressing variations in shape when forming the metal wiring layer. Therefore, evaluation structures can be manufactured stably.

[0013] [4] The evaluation structure according to any one of [1] to [3], wherein the planar shape of the metal pad layer has a corner. With this configuration, the stress applied to the resin-cured layer located near the corner of the metal pad layer can be further increased during a thermal cycle test. Therefore, the number of cycles required for cracking to occur in the resin-cured layer is further reduced, allowing for more rapid evaluation of the resin-cured layer.

[0014] [5] The evaluation structure according to any one of [1] to [4], wherein the difference in average thermal expansion coefficient between the substrate and the cured resin layer at 373K to 423K is 10 ppm / K or more. By providing a sufficient difference in average thermal expansion coefficient between the substrate and the cured resin layer, the stress applied to the cured resin layer between the metal wiring layer and the metal pad layer in a thermal cycle test is sufficiently increased. Therefore, the number of cycles until cracks appear in the cured resin layer is significantly reduced, allowing for rapid evaluation of the cured resin layer.

[0015] [6] A method for manufacturing an evaluation structure, comprising: a preparation step of preparing a substrate; a first resin-cured layer formation step of forming a first resin-cured layer on the substrate; a metal wiring layer formation step of forming a metal wiring layer on the first resin-cured layer; a second resin-cured layer formation step of forming a second resin-cured layer on the first resin-cured layer so that the metal wiring layer is buried in the resin-cured layer; a metal pad layer formation step of forming a metal pad layer on the second resin-cured layer; and a solder layer formation step of forming a solder layer on the metal pad layer.

[0016] In this method for manufacturing an evaluation structure, a second resin-cured layer is formed on a first resin-cured layer so that the metal wiring layer is embedded in the resin-cured layer. Because no connecting members such as vias are formed in the resin-cured layer, drilling holes in the resin-cured layer is unnecessary, thereby avoiding complex manufacturing processes. The evaluation structure obtained by this method for manufacturing an evaluation structure has a structure that mimics an actual semiconductor package, allowing for accurate evaluation of the resin-cured layer. Furthermore, in the evaluation structure obtained by this method for manufacturing an evaluation structure, the metal wiring layer inside the resin-cured layer is isolated from the metal pad layer by the resin-cured layer. In a thermal cycle test using this evaluation structure, stress is more likely to be applied to the resin-cured layer between the metal wiring layer and the metal pad layer. Therefore, the number of cycles required for cracking to occur in the resin-cured layer is reduced, allowing for rapid evaluation of the resin-cured layer.

[0017] [7] A method for evaluating a resin-cured layer, comprising: conducting a thermal cycle test on the evaluation structure according to any one of [1] to [5]; and evaluating the crack resistance of the resin-cured layer based on the number of cycles until cracks appear in the resin-cured layer in the thermal cycle test.

[0018] In this evaluation method for a cured resin layer, the use of the evaluation structure described above allows the cured resin layer to be evaluated with high accuracy. In addition, the number of cycles required until cracks occur in the cured resin layer is reduced, allowing the cured resin layer to be evaluated quickly. [Effects of the Invention]

[0019] According to the present disclosure, a cured resin layer can be evaluated quickly and accurately with a simple structure. [Brief explanation of the drawings]

[0020] [Figure 1] FIG. 1 is a schematic cross-sectional view of an evaluation structure according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a schematic plan view of the evaluation structure shown in FIG. [Figure 3] 1 is a flowchart illustrating a method for manufacturing an evaluation structure according to an embodiment of the present disclosure. [Figure 4] FIG. 1(a) is a schematic cross-sectional view showing a preparation step, and FIG. 1(b) is a schematic cross-sectional view showing a first cured resin layer forming step. [Figure 5] 5(a) to 5(c) are schematic cross-sectional views showing a metal wiring layer forming step. [Figure 6] 5(a) and 5(b) are schematic cross-sectional views showing the steps subsequent to FIG. 5(c), and 5(c) is a schematic cross-sectional view showing the step of forming a second cured resin layer. [Figure 7] 10(a) to 10(c) are schematic cross-sectional views showing a metal pad layer forming step. [Figure 8] 7(a) and 7(b) are schematic cross-sectional views showing the steps subsequent to FIG. 7(c). [Figure 9]FIG. 1(a) is a schematic cross-sectional view showing a singulation step, and FIG. 1(b) is a schematic cross-sectional view showing a solder layer formation step. [Figure 10] 3(a) to 3(c) are schematic cross-sectional views illustrating a method for evaluating a cured resin layer according to an embodiment of the present disclosure. [Figure 11] FIG. 10 is a schematic cross-sectional view showing a modified example of the evaluation structure. DETAILED DESCRIPTION OF THE INVENTION

[0021] Hereinafter, preferred embodiments of an evaluation structure, a method for manufacturing an evaluation structure, and a method for evaluating a cured resin layer according to one aspect of the present disclosure will be described in detail with reference to the drawings.

[0022] In the following description, a numerical range indicated using "to" indicates a range that includes the numerical values ​​before and after "to" as the minimum and maximum values, respectively. Furthermore, in a numerical range that is stated in stages, the upper or lower limit value stated in one numerical range may be replaced with the upper or lower limit value of another numerical range that is stated in stages. The upper or lower limit value of a numerical range may be replaced with a value shown in the examples.

[0023] FIG. 1 is a schematic cross-sectional view of an evaluation structure according to an embodiment of the present disclosure. FIG. 2 is a schematic plan view thereof. The evaluation structure 1 shown in FIGS. 1 and 2 is a structure used for evaluating the reliability of, for example, a FOWLP-type semiconductor package in which solder balls are provided directly on a semiconductor chip via a rewiring layer. The evaluation structure 1 is fabricated to mimic the structure of an actual semiconductor package. A thermal cycle test is performed on the evaluation structure 1 instead of the actual semiconductor package, thereby evaluating the resin material (curable resin composition) used as the rewiring layer.

[0024] As shown in FIGS. 1 and 2 , the evaluation structure 1 includes a substrate 2, a cured resin layer 3, a metal pad layer 4, and a solder layer 5. The substrate 2 is the base of the evaluation structure 1. The substrate 2 can be, for example, a glass substrate, a silicon substrate, a resin substrate, a metal thin film substrate, a laminate, a copper-clad laminate, a silicon wafer whose surface has been modified with silicon dioxide, or a substrate having a metal thin film such as copper formed on its surface by sputtering. Examples of wafer materials include GaN, SiC, SiCN, and SiN. In this embodiment, the substrate 2 is a glass substrate. The thickness of the substrate 2 is, for example, approximately 0.1 mm to 2.0 mm. By setting the thickness of the substrate 2 to 0.1 mm or more, sufficient handling of the evaluation structure 1 can be ensured. By setting the thickness of the substrate 2 to 2.0 mm or less, the manufacturing cost of the evaluation structure 1 can be reduced.

[0025] The resin-cured layer 3 is a layer having a metal wiring layer 6 therein. The resin-cured layer 3 may be formed on one surface of the substrate 2 by applying and curing a resin material. The resin-cured layer 3 may be formed on one surface of the substrate 2 by laminating a film made of a resin material. In this embodiment, a first resin-cured layer 3A is formed on one surface of the substrate 2, a metal wiring layer 6 is formed on one surface of the first resin-cured layer 3A, and then a second resin-cured layer 3B is formed so that the metal wiring layer 6 is buried, thereby forming an integrated resin-cured layer 3 having the metal wiring layer 6 therein.

[0026] The resin material constituting the resin-cured layer 3 is not particularly limited, and examples thereof include photosensitive or non-photosensitive resin materials having electrical insulation properties. The resin material may be either a thermoplastic resin material or a thermosetting resin material. Examples of the resin material include materials containing polyimide, polybenzoxazole, phenol novolac, and polyhydroxystyrene. The thickness of the resin-cured layer 3 may be 0.4 μm to 200 μm, 4 μm to 80 μm, or 8 μm to 40 μm. By setting the thickness of the resin-cured layer 3 to 0.4 μm or more, defects in the resin-cured layer 3 can be suppressed. By setting the thickness of the resin-cured layer 3 to 200 μm or less, variations in the thickness of the resin-cured layer 3 can be suppressed. Note that the resin-cured layer in this embodiment is a high-strength resin layer that contains a resin material and can have metal wiring therein. The resin-cured layer may contain a cured product of a curable resin composition. The cured product of the curable resin composition may include both a completely cured product and a partially cured product (a product in which part of the composition remains uncured).

[0027] Considering the degree of stress applied in the thermal cycle test, the difference in average thermal expansion coefficient between the substrate 2 and the resin-cured layer 3 at 373K to 423K may be 10 ppm / K or more. The difference in average thermal expansion coefficient between the substrate 2 and the resin-cured layer 3 at 373K to 423K may be 100 ppm / K or more, or may be 200 ppm / K or more. By providing a sufficient difference in average thermal expansion coefficient between the substrate 2 and the resin-cured layer 3, the stress applied to the resin-cured layer 3 between the metal wiring layer 6 and the metal pad layer 4 in the thermal cycle test is sufficiently increased.

[0028] The metal wiring layer 6 is a layer that imitates the pattern of the metal wiring layer in an actual semiconductor package. The metal wiring layer 6 is formed by, for example, electrolytic plating. Other methods for forming the metal wiring layer 6 include a method using a thin film and a method using a metal paste. Examples of materials for forming the metal wiring layer 6 include copper, silver, gold, and aluminum. The pattern of the metal wiring layer 6 is a simplification of the pattern of the metal wiring layer in an actual semiconductor package. In this embodiment, a single-layer metal wiring layer 6 is disposed inside the resin-cured layer 3. The thickness of the metal wiring layer 6 may be, for example, 0.1 μm to 50 μm, 1 μm to 20 μm, or 2 μm to 10 μm. The planar shape of the metal wiring layer 6 is circular (see FIG. 2).

[0029] In this embodiment, as described above, a first resin-cured layer 3A is formed on one surface of the substrate 2, a metal wiring layer 6 is formed on one surface of the first resin-cured layer 3A, and then a second resin-cured layer 3B is formed so that the metal wiring layer 6 is buried. As a result, the entire surface of the metal wiring layer 6 is surrounded by the resin-cured layer 3. No via is provided between the metal wiring layer 6 and the metal pad layer 4 to electrically connect the metal wiring layer 6 and the metal pad layer 4, and only the resin-cured layer 3 made of the second resin-cured layer 3B exists. The metal wiring layer 6 is isolated from the metal pad layer 4 by the resin-cured layer 3 at a distance corresponding to the thickness of the second resin-cured layer 3B.

[0030] 1 , the metal wiring layer 6 is located closer to the metal pad layer 4 in the thickness direction of the resin-cured layer 3. More specifically, the center of the metal wiring layer 6 in the thickness direction is located closer to the metal pad layer 4 than the center of the resin-cured layer 3 in the thickness direction. A thickness T2 of the resin-cured layer 3 between the metal wiring layer 6 and the metal pad layer 4 is smaller than a thickness T1 of the resin-cured layer 3 between the metal wiring layer 6 and the substrate 2.

[0031] The metal pad layer 4 is a layer that imitates the pattern of a metal pad layer in an actual semiconductor package. The metal pad layer 4 is formed by, for example, electrolytic plating. Other methods for forming the metal pad layer 4 include a method using a thin film and a method using a metal paste. Examples of materials for forming the metal pad layer 4 include copper, silver, gold, and aluminum. The pattern of the metal pad layer 4 is a simplification of the pattern of a metal pad layer in an actual semiconductor package. In this embodiment, the metal pad layer 4 is disposed on one surface of the resin-cured layer 3 so as to face the metal wiring layer 6 in the thickness direction of the resin-cured layer 3. The thickness of the metal pad layer 4 may be, for example, 0.1 μm to 50 μm, 1 μm to 20 μm, or 2 μm to 10 μm. The planar shape of the metal pad layer 4 is circular (see FIG. 2).

[0032] 2, the above-mentioned metal wiring layer 6 is arranged so as to overlap the metal pad layer 4 and protrude outward beyond the metal pad layer 4 when viewed from the thickness direction of the resin-cured layer 3. In this embodiment, the planar shape of the metal pad layer 4 is one size smaller than the planar shape of the metal wiring layer 6. Furthermore, the metal pad layer 4 is arranged concentrically with the metal wiring layer 6 when viewed from the thickness direction of the resin-cured layer 3. As a result, when viewed from the thickness direction of the resin-cured layer 3, the entire metal pad layer 4 overlaps the metal wiring layer 6, and the entire peripheral portion of the metal wiring layer 6 protrudes outward beyond the metal pad layer 4.

[0033] The solder layer 5 is formed on one surface of the metal pad layer 4 by reflowing a solder material. Examples of the solder material include solder balls and solder paste. The solder layer 5 is formed, for example, by mounting solder balls on one surface of the metal pad layer 4 coated with flux, and then washing off the flux after reflow. Fluxes commonly used in solder bonding can be used. Examples of such fluxes include zinc chloride, a mixture of zinc chloride and an inorganic halide, a mixture of zinc chloride and an inorganic acid, a molten salt, phosphoric acid, a phosphoric acid derivative, an organic halide, hydrazine, an organic acid, an amine, and rosin. A single flux may be used, or two or more fluxes may be used in combination.

[0034] Next, a method for manufacturing the evaluation structure 1 described above will be described.

[0035] 3 is a flowchart showing a method for manufacturing an evaluation structure according to an embodiment of the present disclosure. As shown in FIG. 3, the method for manufacturing the evaluation structure 1 includes a preparation step S01, a first cured resin layer formation step S02, a metal wiring layer formation step S03, a second cured resin layer formation step S04, a metal pad layer formation step S05, a singulation step S06, and a solder layer formation step S07.

[0036] The preparation step S01 is a step of preparing a substrate 2. Here, as shown in FIG. 4(a), a glass substrate is prepared as the substrate 2. The first resin cured layer formation step S02 is a step of forming a first resin cured layer 3A on the substrate 2. In the first resin cured layer formation step S02, a resin material is applied to one surface of the substrate 2 by, for example, spin coating. By curing this, the first resin cured layer 3A is formed on one surface of the substrate 2, as shown in FIG. 4(b). In the first resin cured layer formation step S02, the first resin cured layer 3A may be formed on one surface of the substrate 2 by laminating a film formed from the resin material.

[0037] The metal wiring layer forming step S03 is a step of forming a metal wiring layer 6 on the first resin-cured layer 3A. In the metal wiring layer forming step S03, first, as shown in FIG. 5(a), a seed layer 11 is formed on the first resin-cured layer 3A. For example, sputtering is used to form the seed layer 11. The material for forming the metal wiring layer 6 (copper in this case) is used as the material for forming the seed layer 11. In this case, a resin film with copper foil or a copper paste may be used to form the seed layer 11. From the viewpoint of improving the adhesive strength of the metal wiring layer 6, a metal species other than copper may be used in combination with the material for forming the seed layer 11 as needed. Examples of such metal species include titanium, tungsten, tantalum, and nickel.

[0038] The thickness of the seed layer 11 is, for example, about 1 nm to 100 nm. By making the thickness of the seed layer 11 1 nm or more, it is possible to suppress the occurrence of defects in the seed layer 11. By making the thickness of the seed layer 11 100 nm or less, it is possible to shorten the sputtering processing time and suppress the occurrence of variations in the thickness of the seed layer 11.

[0039] After the seed layer 11 is formed, a resist layer 12 is formed in a predetermined pattern on the seed layer 11, as shown in Fig. 5(b). Next, as shown in Fig. 5(c), a plating layer 13 is formed on the seed layer 11 exposed from the resist layer 12. For example, electrolytic plating is used to form the plating layer 13. The material for forming the metal wiring layer 6 (copper in this case) is used as the material for forming the plating layer 13.

[0040] After the plating layer 13 is formed, the resist layer 12 on the seed layer 11 is removed as shown in FIG. 6(a). After the resist layer 12 is removed, the seed layer 11 remaining on the first resin-cured layer 3A is removed as shown in FIG. 6(b). The seed layer 11 is removed by, for example, etching. As a result, the metal wiring layer 6 made of the plating layer 13 is formed on the first resin-cured layer 3A.

[0041] The second resin-cured layer forming step S04 is a step of forming a second resin-cured layer 3B on the first resin-cured layer 3A. In the second resin-cured layer forming step S04, a resin material is applied to one surface of the first resin-cured layer 3A by, for example, spin coating. By curing this, a second resin-cured layer 3B is formed on one surface of the first resin-cured layer 3A, as shown in FIG. 6(c). As a result, the entire surface of the metal wiring layer 6 is surrounded by the resin-cured layer 3. In the second resin-cured layer forming step S04, the second resin-cured layer 3B may be formed on one surface of the first resin-cured layer 3A by laminating a film formed from a resin material. The first resin-cured layer 3A and the second resin-cured layer 3B may be made of the same material or different materials. The first resin-cured layer 3A and the second resin-cured layer 3B may be integrated.

[0042] The thickness of the second resin-cured layer 3B formed in the second resin-cured layer forming step S04 (the thickness of the second resin-cured layer 3B on the metal wiring layer 6) may be smaller than the thickness of the first resin-cured layer 3A formed in the first resin-cured layer forming step S02. In this case, the thickness T2 of the resin-cured layer 3 between the metal wiring layer 6 and the metal pad layer 4 becomes smaller than the thickness T1 of the resin-cured layer 3 between the metal wiring layer 6 and the substrate 2, and the metal wiring layer 6 can be positioned closer to the metal pad layer 4 in the thickness direction of the resin-cured layer 3 (see FIG. 1).

[0043] The metal pad layer forming step S05 is a step of forming a metal pad layer 4 on the second resin-cured layer 3B. In the metal pad layer forming step S05, first, as shown in FIG. 7(a), a seed layer 21 is formed on the second resin-cured layer 3B. For example, sputtering is used to form the seed layer 21. The material for forming the metal pad layer 4 (copper in this case) is used as the material for forming the seed layer 21. In this case, a resin film with copper foil or a copper paste may be used to form the seed layer 21. From the viewpoint of improving the adhesive strength of the metal pad layer 4, a metal species other than copper may be used in combination with the material for forming the seed layer 21 as needed. Examples of such metal species include titanium, tungsten, tantalum, and nickel.

[0044] The thickness of the seed layer 21 is, for example, about 1 nm to 100 nm. By making the thickness of the seed layer 21 1 nm or more, it is possible to suppress the occurrence of defects in the seed layer 21. By making the thickness of the seed layer 21 100 nm or less, it is possible to shorten the sputtering processing time and suppress the occurrence of variations in the thickness of the seed layer 21.

[0045] After the seed layer 21 is formed, a resist layer 22 is formed in a predetermined pattern on the seed layer 21, as shown in Fig. 7(b). Next, as shown in Fig. 7(c), a plating layer 23 is formed on the seed layer 21 exposed from the resist layer 22. For example, electrolytic plating is used to form the plating layer 23. For example, the material (copper in this case) used to form the metal wiring layer 6 is used as the material for forming the plating layer 23.

[0046] After the plating layer 23 is formed, the resist layer 22 on the seed layer 21 is removed as shown in FIG. 8(a). After the resist layer 22 is removed, the seed layer 21 remaining on the second resin-cured layer 3B is removed as shown in FIG. 8(b). The seed layer 21 is removed by, for example, etching. As a result, the metal pad layer 4 made of the plating layer 23 is formed on the second resin-cured layer 3B.

[0047] In this embodiment, as described above, after the second resin-cured layer 3B is formed on the first resin-cured layer 3A in the second resin-cured layer formation step S04, the metal pad layer formation step S05 is carried out without performing any processing such as drilling holes for via formation in the second resin-cured layer 3B. Therefore, only the resin-cured layer 3 formed by the second resin-cured layer 3B exists between the metal wiring layer 6 and the metal pad layer 4, and the metal wiring layer 6 is isolated from the metal pad layer 4 by the resin-cured layer 3 at a distance corresponding to the thickness of the second resin-cured layer 3B.

[0048] The singulation step S06 is a step for singulating the structure formed in the preparation step S01 through the metal pad layer formation step S05. Here, the substrate 2 and the cured resin layer 3 are diced using, for example, a blade or laser beam to form a plurality of chips, each consisting of a set of a metal wiring layer 6 and a metal pad layer 4. The solder layer formation step S07 is a step for forming a solder layer on the metal pad layer. In the solder layer formation step S07, as shown in FIG. 9(b), flux 31 is applied to one surface of the metal pad layer 4, and then a solder ball 32 is mounted on the solder layer. For example, after reflow at a maximum temperature of 260°C, the flux is removed from the metal pad layer 4 by cleaning as shown in FIG. 5, thereby obtaining the evaluation structure 1 shown in FIG. 1.

[0049] Next, a method for evaluating the cured resin layer using the evaluation structure 1 described above will be described.

[0050] In this evaluation method, as shown in FIG. 10(a), the evaluation structure 1 is placed in a thermal cycle test apparatus D. In the thermal cycle test, one cycle is defined as holding at a low temperature for a predetermined time and then holding at a high temperature for a predetermined time, and the strength (crack resistance) of the resin-cured layer 3 used in the evaluation structure 1 is evaluated by verifying the number of cycles until cracks occur in the resin-cured layer 3. In this embodiment, the resin-cured layer to be evaluated is the portion corresponding to the second resin-cured layer 3B. The portion corresponding to the first resin-cured layer 3A does not necessarily need to be included in the evaluation.

[0051] When evaluating the resin-cured layer 3, chips including evaluation structures 1 having resin-cured layers 3 made of different resin materials may be placed in a thermal cycle test device D. The number of samples for each type may be, for example, 3 to 100. The conditions for the thermal cycle test are not particularly limited, but may be, for example, a high-temperature side temperature of 85°C to 150°C, a low-temperature side temperature of -65°C to 0°C, and a holding time in each temperature range of 1 minute to 15 minutes.

[0052] In the thermal cycle test, stress is applied to the resin-cured layer 3 due to differences in the thermal expansion coefficient between the resin-cured layer 3 and the metal wiring layer 6 and the metal pad layer 4, and between the resin-cured layer 3 and the substrate 2. As the cycles of the thermal cycle test progress, this stress can cause cracks K to occur in the resin-cured layer 3 between the metal wiring layer 6 and the metal pad layer 4, as shown in FIG. 10(b). The cracks K start, for example, from the peripheral portion of the metal pad layer 4, where stress tends to concentrate, and progress toward the metal wiring layer 6, penetrating between the metal pad layer 4 and the metal wiring layer 6.

[0053] A general microscope or a scanning electron microscope (SEM) is used to observe the resin-cured layer 3. To check whether cracks K have occurred, the solder layer 5 and the metal pad layer 4 may be polished to expose the resin-cured layer 3 below the metal pad layer 4, as shown in FIG. 10(c). To check whether cracks K have occurred, the evaluation structure 1 may be polished so that at least the cross section of the resin-cured layer 3 in the thickness direction is exposed.

[0054] As described above, in the evaluation structure 1, by arranging the resin-cured layer 3 having the metal wiring layer 6 therein, the metal pad layer 4, and the solder layer 5 on the substrate 2, a structure simulating an actual semiconductor package is realized, allowing for accurate evaluation of the resin-cured layer 3. In the evaluation structure 1, no connecting members such as vias are arranged in the resin-cured layer 3, and the metal wiring layer 6 inside the resin-cured layer 3 is isolated from the metal pad layer 4 by the resin-cured layer 3. This simplifies the structure of the evaluation structure 1, avoiding the need for a complex manufacturing process for the evaluation structure 1. This also avoids the need for complex factors affecting the evaluation results due to the structure. In a thermal cycle test using the evaluation structure 1, stress is more likely to be applied to the resin-cured layer 3 between the metal wiring layer 6 and the metal pad layer 4. This reduces the number of cycles required for a crack K to appear in the resin-cured layer 3, allowing for rapid evaluation of the resin-cured layer 3.

[0055] In this embodiment, the metal wiring layer 6 is located closer to the metal pad layer 4 in the thickness direction of the resin-cured layer 3. With this configuration, sufficient stress can be applied to the resin-cured layer 3 between the metal wiring layer 6 and the metal pad layer 4 in the thermal cycle test. Therefore, the resin-cured layer 3 can be quickly evaluated.

[0056] In this embodiment, when viewed in the thickness direction of the resin-cured layer 3, the metal wiring layer 6 is arranged so as to overlap with the metal pad layer 4 and protrude outward beyond the metal pad layer 4. With this configuration, the metal wiring layer 6 is not made excessively small, thereby suppressing variations in shape when forming the metal wiring layer 6. Therefore, the evaluation structure 1 can be manufactured stably.

[0057] In this embodiment, the difference in average thermal expansion coefficient between the substrate 2 and the resin-cured layer 3 at 373K to 423K is 10 ppm / K or more. By providing a sufficient difference in average thermal expansion coefficient between the substrate and the resin-cured layer, the stress applied to the resin-cured layer 3 between the metal wiring layer 6 and the metal pad layer 4 in the thermal cycle test is sufficiently increased. Therefore, the number of cycles until cracks K occur in the resin-cured layer 3 is significantly reduced, allowing the resin-cured layer 3 to be evaluated quickly.

[0058] Various modifications can be made to the evaluation structure 1. For example, in the above embodiment, the planar shape of the metal wiring layer 6 is slightly larger than the planar shape of the metal pad layer 4, but the planar shape of the metal wiring layer 6 may be the same as the planar shape of the metal pad layer 4.

[0059] Furthermore, in the above embodiment, the planar shape of the metal pad layer 4 is circular, but as shown in FIG. 11 , for example, the planar shape of the metal pad layer 4 may have corners R. The corners R may be located at any position in the planar shape of the metal pad layer 4. The number of corners R may be either single or multiple. In the example of FIG. 11 , the planar shape of the metal pad layer 4 is square. The planar shape of the metal pad layer 4 having corners R is not limited to this, and may be other polygonal shapes, elliptical shapes with pointed ends in the long axis direction, or the like.

[0060] According to this configuration, it is possible to further increase the stress applied to the resin-cured layer 3 located near the corner R of the metal pad layer 4 in the thermal cycle test. Therefore, the number of cycles until cracks occur in the resin-cured layer 3 is further reduced, and the resin-cured layer 3 can be evaluated more quickly. Although not shown, when the planar shape of the metal pad layer 4 has a corner R, the planar shape of the metal wiring layer 6 may also have a corner. In this case, the planar shape of the metal pad layer 4 and the planar shape of the metal wiring layer 6 may be the same or different. [Explanation of symbols]

[0061] 1...Evaluation structure, 2...Substrate, 3...Resin cured layer, 3A...First resin cured layer, 3B...Second resin cured layer, 4...Metal pad layer, 5...Solder layer, R...Corner portion.

Claims

1. A substrate; a cured resin layer disposed on the substrate and having a metal wiring layer therein; a metal pad layer disposed on the resin-cured layer; a solder layer disposed on the metal pad layer; The metal wiring layer is separated from the metal pad layer by the cured resin layer.

2. 2. The evaluation structure according to claim 1, wherein the metal wiring layer is located closer to the metal pad layer in the thickness direction of the cured resin layer.

3. 2. The evaluation structure according to claim 1, wherein the metal wiring layer is arranged so as to overlap the metal pad and to protrude outward beyond the metal pad layer when viewed in the thickness direction of the cured resin layer.

4. 2. The evaluation structure according to claim 1, wherein the metal wiring layer has a planar shape that has corners.

5. 2. The evaluation structure according to claim 1, wherein the difference in average thermal expansion coefficient between the substrate and the cured resin layer at 373K to 423K is 10 ppm / K or more.

6. a preparation step of preparing a substrate; a first resin-cured layer forming step of forming a first resin-cured layer on the substrate; a metal wiring layer forming step of forming a metal wiring layer on the first cured resin layer; a second resin-cured layer forming step of forming a second resin-cured layer on the first resin-cured layer so that the metal wiring layer is buried in the resin-cured layer; a metal pad layer forming step of forming a metal pad layer on the second cured resin layer; and forming a solder layer on the metal pad layer.

7. A method for evaluating a resin-cured layer, comprising: performing a thermal cycle test on the evaluation structure according to any one of claims 1 to 5; and evaluating the crack resistance of the resin-cured layer based on the number of cycles until a crack occurs in the resin-cured layer in the thermal cycle test.

Images