Light receiving element and method of manufacturing the same

Abstract

To provide a light receiving element capable of reducing an electric field applied to a side surface of a mesa, and to provide a method of manufacturing the same.SOLUTION: A light-receiving element comprising: a first mesa; and a terrace, wherein the terrace extends outside the first mesa and includes a first semiconductor layer having a first conductivity type, the first mesa protrudes from the terrace and includes a second semiconductor layer having a second conductivity type, and a side surface of the first mesa has a shape perpendicular to the terrace or an inverted mesa shape inclined at an acute angle with respect to the terrace.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a light-receiving element and a method for manufacturing the same. [Background technology]

[0002] In the light receiving element, a mesa is formed to separate the elements (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-328036 Summary of the Invention [Problem to be solved by the invention]

[0004] Because foreign matter such as oxides adheres to the side of the mesa, surface states are easily formed. A high electric field applied to the side of the mesa increases surface leakage current. Therefore, the objective of this study is to provide a photodiode that can reduce the electric field applied to the side of the mesa, and a method for manufacturing the same. [Means for solving the problem]

[0005] The light-receiving element according to the present disclosure comprises a first mesa and a terrace, the terrace extending outside the first mesa and including a first semiconductor layer having a first conductivity type, the first mesa protruding beyond the terrace and including a second semiconductor layer having a second conductivity type, and the side of the first mesa has a shape perpendicular to the terrace or an inverted mesa shape inclined at an acute angle to the terrace. [Effects of the Invention]

[0006] According to the present disclosure, it is possible to provide a light-receiving element capable of reducing the electric field acting on the side surface of the mesa, and a method for manufacturing the same. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a plan view illustrating the light-receiving element according to the first embodiment. [Figure 2] FIG. 2 is a cross-sectional view illustrating an example of a light receiving element. [Figure 3] FIG. 3 is a cross-sectional view illustrating an example of a light receiving element. [Figure 4] 4A to 4C are cross-sectional views illustrating a method for manufacturing a light-receiving element. [Figure 5A] FIG. 5A is a plan view illustrating a method for manufacturing a light-receiving element. [Figure 5B] FIG. 5B is a cross-sectional view illustrating a method for manufacturing the light-receiving element. [Figure 6A] FIG. 6A is a plan view illustrating a method for manufacturing a light-receiving element. [Figure 6B] FIG. 6B is a cross-sectional view illustrating a method for manufacturing the light-receiving element. [Figure 7] FIG. 7 is a cross-sectional view illustrating an example of a light receiving element. [Figure 8] FIG. 8 is a cross-sectional view illustrating an example of a light receiving element. [Figure 9] FIG. 9 is a cross-sectional view illustrating a light-receiving element according to a comparative example. [Figure 10] FIG. 10 is a plan view illustrating the light receiving element according to the second embodiment. [Figure 11A] FIG. 11A is a cross-sectional view illustrating an example of a light receiving element. [Figure 11B] FIG. 11B is a cross-sectional view illustrating the light receiving element. [Figure 12A] FIG. 12A is a cross-sectional view illustrating a light-receiving element according to the third embodiment. [Figure 12B] FIG. 12B is a cross-sectional view illustrating the light-receiving element according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] [Description of the embodiments of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described.

[0009] One aspect of the present disclosure is a light-receiving element (1) comprising a first mesa and a terrace, wherein the terrace extends beyond the first mesa and includes a first semiconductor layer having a first conductivity type, the first mesa protrudes beyond the terrace and includes a second semiconductor layer having a second conductivity type, and the side of the first mesa has a shape perpendicular to the terrace or an inverted mesa shape inclined at an acute angle to the terrace. The portion of the first semiconductor layer included in the terrace functions as a conductor and has a high potential. Because the conductor portion is farther away from the first mesa, the change in potential between the first mesa and the conductor portion is gradual. This reduces the electric field acting on the side of the first mesa. (2) In (1) above, the first mesa may have a plurality of side surfaces, a first surface of the plurality of side surfaces having the vertical shape, and a second surface of the plurality of side surfaces having the inverted mesa shape. The electric field acting on the plurality of side surfaces can be reduced. (3) In (2) above, the first mesa may have a rectangular planar shape, the two first surfaces facing each other and having the vertical shape, and the two second surfaces facing each other and having the inverted mesa shape. The electric field can be reduced in all directions of the first mesa. (4) In the above (3), the two first planes may be the (011) plane and the (0-1-1) plane, and the two second planes may be the (01-1) plane and the (0-11) plane. This allows the electric field to be reduced in all directions of the first mesa. (5) In any of the above (1) to (4), the angle between the portion of the side surface of the first mesa that has the inverted mesa shape and the surface of the terrace may be 70 degrees or more and less than 90 degrees. Because the side surface has an inverted mesa shape, the electric field can be reduced. Coverage of the side surface with an insulating film can be improved. (6) In any of the above (1) to (5), the terrace may include a light absorbing layer stacked between the first semiconductor layer and the second semiconductor layer. In the portion where the first mesa is provided, the second semiconductor layer, the light absorbing layer, and the first semiconductor layer form a pin junction. The portion of the first semiconductor layer included in the terrace does not form a pin junction and functions as a conductor. By distancing the conductor portion from the pin junction, the electric field can be reduced. (7) In any one of (1) to (6) above, the light receiving element may be an avalanche photodiode and include a second mesa that extends between the first mesa and the terrace and protrudes beyond the terrace, the second mesa including a light absorbing layer, a third semiconductor layer, and a multiplication layer, the light absorbing layer being stacked between the first semiconductor layer and the second semiconductor layer, the third semiconductor layer being stacked between the light absorbing layer and the first semiconductor layer and having the second conductivity type, the multiplication layer being stacked between the third semiconductor layer and the first semiconductor layer, and a side surface of the second mesa may be perpendicular to the terrace or have an inverted mesa shape inclined at an acute angle to the terrace, thereby reducing an electric field acting on the side surface of the first mesa and the side surface of the second mesa. (8) A semiconductor device comprising: a step of sequentially stacking a first semiconductor layer having a first conductivity type, a light absorption layer, and a second semiconductor layer having a second conductivity type; and a step of forming a terrace and a mesa by etching the second semiconductor layer, wherein the terrace extends outside the mesa and includes the first semiconductor layer, the mesa protrudes beyond the terrace and includes the second semiconductor layer, and the side surface of the mesa may have a shape perpendicular to the terrace or an inverted mesa shape inclined at an acute angle to the terrace. (9) In the above (8), the step of forming the terrace and the mesa may include the steps of covering a part of the second semiconductor layer with a first mask and etching the part of the second semiconductor layer exposed from the first mask to form the vertical side surface, and covering another part of the second semiconductor layer with a second mask and etching the part exposed from the second mask to form the inverted mesa side surface. By performing etching according to the crystal plane, a mesa having a desired shape can be formed. (10) In the above (9), the etching time in the step of forming the side surface of the inverted mesa shape may be longer than the etching time in the step of forming the side surface of the vertical shape. A mesa having a desired shape can be formed.

[0010] [Details of the embodiments of the present disclosure] Specific examples of light-receiving elements and methods for manufacturing the same according to embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0011] First Embodiment FIG. 1 is a plan view illustrating a light-receiving element 100 according to the first embodiment. An insulating film, which will be described later, is shown in a see-through view. As shown in FIG. 1, the light-receiving element 100 is rectangular in plan view. Two sides of the light-receiving element 100 are parallel to the X-axis. The other two sides are parallel to the Y-axis. The Z-axis direction is the thickness direction of the light-receiving element 100. The X-axis direction, Y-axis direction, and Z-axis direction are perpendicular to each other.

[0012] The light-receiving element 100 has a mesa 10 (first mesa), a terrace 12, an electrode 14, and an electrode 16. The terrace 12 is a plate-shaped portion that is parallel to the XY plane and extends outside the mesa 10. The mesa 10 is provided inside the terrace 12 in the XY plane and protrudes beyond the terrace 12 in the Z-axis direction. The planar shape of the mesa 10 is rectangular. The apex of the mesa 10 may be curved. The length L1 of the light-receiving element 100 in the X-axis direction is, for example, 90 μm. The length L2 of the mesa 10 is, for example, 85 μm.

[0013] A recess 13 is provided in the terrace 12. An electrode 14 is spaced apart from the mesa 10 and provided in the recess 13. An electrode 16 is provided on the mesa 10. The electrode 16 is smaller than the mesa 10 and has a rectangular shape similar to the mesa 10. Bumps or bonding wires can be connected to the electrodes 14 and 16.

[0014] 2 and 3 are cross-sectional views illustrating the light-receiving element 100. Fig. 2 shows a cross section taken along line AA in Fig. 1. Fig. 3 shows a cross section taken along line BB in Fig. 1.

[0015] As shown in Figures 2 and 3, the light receiving element 100 has a substrate 30, a semiconductor layer 32 (first semiconductor layer), a light absorption layer 34, a semiconductor layer 36, a semiconductor layer 38, a semiconductor layer 40, a semiconductor layer 42, a semiconductor layer 44, and a contact layer 46 (second semiconductor layer).

[0016] On one surface of the substrate 30, a semiconductor layer 32, a light absorption layer 34, a semiconductor layer 36, a semiconductor layer 38, and a semiconductor layer 40 are stacked in this order. The central portion of the semiconductor layer 40 in the XY plane protrudes in the Z-axis direction more than the peripheral portion of the semiconductor layer 40. A semiconductor layer 42, a semiconductor layer 44, and a contact layer 46 are stacked in this order in the central portion of the semiconductor layer 40. The central portion of the semiconductor layer 40, the semiconductor layer 42, the semiconductor layer 44, and the contact layer 46 form a mesa 10. The semiconductor layer 40 and the substrate 30 are located below the mesa 10 and extend beyond the mesa 10. The substrate 30 and the peripheral portion of the semiconductor layer 40 form a terrace 12.

[0017] The upper surface of the semiconductor layer 40 becomes the surface of the terrace 12. The end faces of the semiconductor layer 40, the semiconductor layer 42, the semiconductor layer 44, and the contact layer 46 become the side surfaces of the mesa 10. The surface of the contact layer 46 is the upper surface of the mesa 10. The cross-sectional shape of the mesa 10 will be described later.

[0018] The insulating film 48 is a passivation film that covers the surface of the terrace 12 and the side and top surfaces of the mesa 10. The insulating film 48 has an opening on the mesa 10. The electrode 16 is provided on the mesa 10 and is in contact with the contact layer 46 through the opening in the insulating film 48. The electrode 16 is electrically connected to the contact layer 46. The recess 13 shown in FIG. 1 extends in the Z-axis direction to the semiconductor layer 32. The insulating film 48 has an opening in the recess 13. The electrode 14 is provided in the opening and is electrically connected to the semiconductor layer 32.

[0019] Fig. 1 shows the crystal directions (crystal orientations) of the semiconductor layers of the light-receiving element 100. In Fig. 1, the

[0011] direction is the upward direction. The [0-1-1] direction is the downward direction. The [0-11] direction is the rightward direction. The [01-1] direction is the leftward direction.

[0020] As shown in FIG. 1, mesa 10 is rectangular in plan view and has four side surfaces. Side surfaces 20 and 22 of mesa 10 are parallel to the Y-axis direction and face each other. Side surfaces 24 and 26 are parallel to the X-axis direction and face each other. Side surfaces 20 and 22 correspond to the first surface. Side surfaces 24 and 26 correspond to the second surface.

[0021] Side surface 20 is a (011) plane and is perpendicular to the

[0011] direction. Side surface 22 is a (0-1-1) plane and is perpendicular to the [0-1-1] direction. Side surface 24 is a (0-11) plane and is perpendicular to the [0-11] direction. Side surface 26 is a (01-1) plane and is perpendicular to the [01-1] direction.

[0022] 2 illustrates the XZ plane. When viewed from the XZ plane, mesa 10 is upright. That is, side surfaces 20 and 22 of mesa 10 are parallel to the Z-axis direction and perpendicular to terrace 12. An angle θ1 between side surfaces 20 and 22 and the upper surface of terrace 12 is 90 degrees.

[0023] 3 illustrates the YZ plane. When viewed from the YZ plane, mesa 10 has an inverted mesa shape. Side surface 24 and side surface 26 are inclined from the Z-axis direction and at an acute angle relative to terrace 12. Angle θ2 between side surface 24 and side surface 26 and terrace 12 is less than 90 degrees, for example, greater than or equal to 70 degrees and less than 90 degrees.

[0024] The substrate 30 is, for example, a semi-insulating semiconductor substrate, and is made of indium phosphide (InP). The substrate 30 is doped with, for example, iron (Fe). The thickness of the substrate 30 is, for example, 600 μm. The semiconductor layer 32 is, for example, made of n-type (first conductivity type) indium phosphide (n-InP). The semiconductor layer 32 is doped with, for example, silicon (Si). The impurity concentration is 1×10 18 cm -3 or more, for example, 1.85 × 10 18 cm -3 The thickness of the semiconductor layer 32 is, for example, 2 μm.

[0025] The light absorption layer 34 is formed of, for example, undoped indium gallium arsenide (i-InGaAs). The thickness of the light absorption layer 34 is, for example, 4 μm. The semiconductor layer 36 and the semiconductor layer 38 are formed of, for example, undoped indium gallium arsenide phosphide (i-InGaAsP). The thickness of each of these two layers is, for example, 0.025 μm.

[0026] The semiconductor layer 40 and the semiconductor layer 42 are made of, for example, i-InP. The thickness of the semiconductor layer 40 is, for example, 0.5 μm. The thickness of the semiconductor layer 42 is, for example, 0.1 μm. The undoped layer has a thickness of, for example, 1×10 15 cm -3The following impurities may be added. The semiconductor layer 44 is formed of, for example, p-type (second conductivity type) indium phosphide (p-InP). The semiconductor layer 44 is doped with, for example, zinc (Zn). The impurity concentration is 1×10 18 cm -3 For example, 1.8 × 10 18 cm -3 That's all. The thickness of the semiconductor layer 44 is, for example, 0.2 μm. The contact layer 46 is made of, for example, (p+)-InGaAs. The semiconductor layer 44 is doped with, for example, Zn. The impurity concentration is 2×10 19 cm -3 For example, 3.0 × 10 19 cm -3 That is all. The thickness of the contact layer 46 is, for example, 0.2 μm. The light receiving element 100 may be formed of compound semiconductor layers other than those mentioned above.

[0027] The insulating film 48 is a passivation film and is made of an insulator such as silicon nitride (SiN). The thickness of the insulating film 48 is, for example, 180 nm or more and 220 nm or less. The electrodes 14 and 16 are made of metal.

[0028] (Manufacturing method) 4, 5B, and 6B are cross-sectional views illustrating a method for manufacturing the light-receiving element 100. Figures 5A and 6A are plan views illustrating a method for manufacturing the light-receiving element 100. The steps are performed in the order of Figures 4, 5A and 5B, and 6A and 6B.

[0029] 4, for example, by metal organic chemical vapor deposition (MOCVD), semiconductor layer 32, light absorption layer 34, semiconductor layer 36, semiconductor layer 38, semiconductor layer 40, semiconductor layer 42, semiconductor layer 44, and contact layer 46 are epitaxially grown on the main surface of substrate 30. The main surface of substrate 30 is, for example, a (100) plane.

[0030] A mask (not shown) is formed on the upper surface of the contact layer 46. The mask has a rectangular planar shape. The four corners of the mask may be curved. The length of one side of the mask is approximately equal to the length L2 of the side of the upper surface of the mesa 10. Using the mask, dry etching is performed to remove the portion from the contact layer 46 to partway through the semiconductor layer 40. The dry etching forms side surfaces that include the portion from the contact layer 46 to partway through the semiconductor layer 40. The four side surfaces formed by dry etching are approximately perpendicular to the major surface of the substrate 30. One of the four side surfaces exposes the (011) plane of the semiconductor layer 40 from the contact layer 46. Another of the four side surfaces exposes the (0-1-1) plane of the semiconductor layer 40 from the contact layer 46. Another of the four side surfaces exposes the (0-11) plane of the semiconductor layer 40 from the contact layer 46. Another of the four side surfaces exposes the (01-1) plane of the semiconductor layer 40 from the contact layer 46. After dry etching, the mask is removed using buffered hydrofluoric acid.

[0031] As shown in FIG. 5A, the (011) planes of all the formed semiconductor layers are covered with a mask 50 (first mask). The (0-1-1) planes are covered with a mask 52 (first mask). The (0-11) planes and (01-1) planes are not covered by the mask and are exposed. After the mask is formed, dry etching, cleaning, and wet etching are performed in this order. Wet etching is performed, for example, under the following conditions: Etchant: Citric acid hydrogen peroxide Time: 90 seconds

[0032] The (0-11) plane is etched to form side surface 24 of mesa 10. The (01-1) plane is etched to form side surface 26. FIG. 5B shows a cross section taken along line BB in FIG. 5A. As shown in FIG. 5B, side surface 24 and side surface 26 have an inverted mesa shape. After etching, masks 50 and 52 are removed.

[0033] As shown in FIG. 6A, the (0-11) plane of the semiconductor layer is covered with a mask 54 (second mask). The (01-1) plane is covered with a mask 56 (second mask). The (011) plane and the (0-1-1) plane are not covered by the mask and are exposed. After the mask is formed, dry etching, cleaning, and wet etching are performed in this order. The wet etching is performed, for example, under the following conditions: Etchant: Citric acid hydrogen peroxide Time: 10 seconds

[0034] The (011) plane is etched to form the side surface 20 of the mesa 10. The (0-1-1) plane is etched to form the side surface 22. The terrace 12 is formed in the etched portion. FIG. 6B shows a cross section taken along line AA in FIG. 6A. As shown in FIG. 6B, the side surface 20 and the side surface 22 are perpendicular to the upper surface of the terrace 12. After etching, the masks 54 and 56 are removed.

[0035] For example, the insulating film 48 is formed by plasma enhanced chemical vapor deposition (CVD). An opening is formed in the insulating film 48. The electrodes 14 and 16 are formed by vacuum deposition and lift-off. Through the above steps, the light-receiving element 100 is formed.

[0036] The photodetector 100 detects light such as infrared light. When the photodetector 100 is used, a positive voltage is applied to the electrode 14, and a negative voltage is applied to the electrode 16. The n-type semiconductor layer 32, the i-type light absorption layer 34, the p-type semiconductor layer 44, and the contact layer 46 form a pin (positive-intrinsic-negative) junction. When a voltage is applied, a depletion layer expands from the mesa 10 to below the mesa 10. The photodetector 100 is a back-illuminated element. Light incident from the bottom surface of the substrate 30 is absorbed by the light absorption layer 34. By absorbing light, the light absorption layer 34 generates carriers (electron-hole pairs). The electric field applied to the depletion layer causes the carriers to move, which are output as photocurrent.

[0037] 7 and 8 are cross-sectional views illustrating a photodiode 100, enlarging one side of the mesa 10 of the photodiode 100. The semiconductor layer 32 to the contact layer 46 are shown, with the substrate 30 omitted. Some hatching is also omitted. FIG. 9 is a cross-sectional view illustrating a photodiode 110 according to a comparative example, illustrating a portion of the device, similar to FIG. 7 and others. The mesa 10 of the photodiode 110 has a forward mesa structure. The angle between the side surface 20 of the mesa 10 and the top surface of the terrace 12 is an obtuse angle, e.g., 110 degrees. All side surfaces of the mesa 10 have a forward mesa shape.

[0038] 7, 8, and 9, the arrows represent electric field vectors. Line C is an imaginary line segment. The area inside line C is region 57. The area outside line C is region 58. Region 57 includes mesa 10, where a pin junction exists. In region 57, the semiconductor layer is depleted, and the electric field is mainly oriented in the Z-axis direction. The semiconductor layer in region 58 is not included in the pin junction and functions as a conductor. This conductor portion is indicated by diagonal lines in the figures and is referred to as portion 59. Portion 59 has a higher electrical potential than the semiconductor layer in region 57.

[0039] In the example of FIG. 9 , portion 59 extends from near the junction interface between the p-type semiconductor layer 44 and the i-type semiconductor layer 42 in mesa 10 to terrace 12. That is, mesa 10 includes a pin junction and portion 59. Portion 59, which has high potential, is located within mesa 10. Within mesa 10, the electrical potential changes abruptly between portion 59 and the p-type semiconductor layer 44. Therefore, a high electric field is applied to the side surface of mesa 10. In particular, since portion 59 is close to the junction interface between the semiconductor layer 44 and the semiconductor layer 42, the electric field is concentrated near the junction interface. In other words, electric field lines are concentrated at the junction interface.

[0040] In the examples of FIGS. 7 and 8, mesa 10 includes a pin junction but does not include portion 59. Portion 59, which has a high potential, is located outside mesa 10 and is away from the semiconductor layers in mesa 10. Compared to the comparative example, the potential changes more gradually between portion 59 and mesa 10. Therefore, the electric field acting on the side surface of mesa 10 is reduced. The electric field is less likely to concentrate at the junction interface between semiconductor layer 44 and semiconductor layer 42. Compared to the comparative example, the electric field is reduced by approximately 10% to 20%.

[0041] According to the first embodiment, the photodiode 100 has a mesa 10 and a terrace 12. The terrace 12 includes layers from the substrate 30 to the semiconductor layer 40. The mesa 10 protrudes beyond the terrace 12 and includes layers from the semiconductor layer 40 to the contact layer 46. As shown in FIG. 2, the side surfaces 20 and 22 of the mesa 10 are perpendicular to the terrace 12. As shown in FIG. 3, the side surfaces 24 and 26 are inclined at an acute angle with respect to the terrace 12. As shown in FIGS. 7 and 8, a portion 59 having a high potential is located away from the mesa 10. This reduces the electric field acting on the side surface of the mesa 10, mitigating electric field concentration. This reduces surface leakage current. This improves the reliability of the photodiode 100.

[0042] As shown in FIG. 1, mesa 10 is rectangular in plan view and has four sides. Two sides 20 and 22 face each other and are perpendicular to the top surface of terrace 12. Two sides 24 and 26 face each other, forming an inverted mesa shape. The electric field can be reduced in all directions around mesa 10.

[0043] The side surfaces of the mesa 10 may have a vertical or inverted mesa shape, but not a normal mesa shape. For example, all four side surfaces may have a vertical shape. All four side surfaces may have an inverted mesa shape. The mesa 10 may have four or more side surfaces. The multiple side surfaces may have either a vertical shape or an inverted mesa shape. The shape of the side surfaces depends on the crystal plane.

[0044] As shown in FIG. 2, side surface 20 is a (011) plane. Side surface 22 is a (0-1-1) plane. These planes have a vertical shape. Side surface 24 is a (0-11) plane. Side surface 26 is a (01-1) plane. These planes have an inverted mesa shape. By performing etching according to the crystal direction, it is possible to manufacture mesa 10 with the desired shape.

[0045] A portion of the contact layer 46, the semiconductor layer 44, etc. is covered with a mask, and the portions exposed from the mask are etched. Another portion is covered with a mask, and etching is performed. The mesa 10 and the terrace 12 are formed by etching. Specifically, as shown in FIG. 5A, a mask 50 covers the (011) plane. A mask 52 covers the (0-1-1) plane. The exposed (0-11) plane and the (01-1) plane are etched to form the side surface 24 and the side surface 26. As shown in FIG. 6A, a mask 54 covers the (0-11) plane. A mask 56 covers the (01-1) plane. The exposed (011) plane and the (0-1-1) plane are etched to form the side surface 20 and the side surface 22.

[0046] Etching proceeds in the depth direction (Z-axis direction) and also in the lateral direction. The shape of the side surface is controlled by the etching time, etc. The wet etching time is short when creating vertical side surfaces, for example 10 seconds. The wet etching time is long when creating inverted mesa side surfaces, for example 90 seconds. By performing wet etching for a long time, the side etching progresses and the inverted mesa shape is formed. A mesa 10 of the desired shape can be formed. An anisotropic etchant such as citric acid / hydrogen peroxide is used as the etchant.

[0047] If the angle θ2 between the side surface 24 and the side surface 26 and the upper surface of the terrace 12 is too small, the insulating film 48 is difficult to form on the side surface. If the angle θ2 is greater than 90 degrees, the side surface will not have an inverted mesa shape. The angle θ2 is, for example, greater than or equal to 70 degrees and less than 90 degrees. This improves the coverage of the insulating film 48. The side surface will have an inverted mesa shape. The angle θ2 may be, for example, greater than or equal to 40 degrees, greater than or equal to 50 degrees, greater than or equal to 60 degrees, less than or equal to 80 degrees, or less than or equal to 85 degrees.

[0048] According to the first embodiment, the electric field applied to the semiconductor layer of the mesa 10 is low. On the other hand, the electric field is distributed outside the semiconductor layer and applied to the insulating film 48. If a high electric field is applied, there is a risk of dielectric breakdown of the insulating film 48. In consideration of the dielectric strength of the insulating film 48, the strength of the electric field applied to the insulating film 48 is set to, for example, 300 kV / cm or less.

[0049] The semiconductor layer 32 is n-type. The semiconductor layer 44 and the contact layer 46 are p-type. The light absorption layer 34 is i-type. These layers form a pin junction from the mesa 10 to below the mesa 10. Portion 59 is not included in the pin junction, functions as a conductor, and has a high potential. As shown in Figures 7 and 8, according to the first embodiment, portion 59 is located outside the mesa 10. The mesa 10 has a pin junction and is away from portion 59 with a high potential. This reduces the electric field acting on the side of the mesa 10. The contact layer 46 and other layers may be n-type, and the semiconductor layer 32 close to the substrate 30 may be p-type.

[0050] The semiconductor layers 40, 42, and 44 are made of InP. The oxidation reaction of InP produces indium oxide (In2O3) and phosphate (PO4 3- ) may occur. Oxides of these substances, carbon, etc. may adhere to the surface of the semiconductor layer. A surface with foreign matter attached thereto is unstable, and surface states are likely to form. According to the first embodiment, the surface leakage current can be reduced by reducing the electric field.

[0051] Second Embodiment FIG. 10 is a plan view illustrating a light receiving element 200 according to the second embodiment. The light receiving element 200 according to the second embodiment is an array sensor. Description of the same configuration as in the first embodiment will be omitted. The light receiving element 200 has a central portion 60 and an outer peripheral portion 62. The central portion 60 is located in the center of the surface of the light receiving element 200. The outer peripheral portion 62 is located on the outer periphery and surrounds the central portion 60. A recess 64 is provided between the central portion 60 and the outer peripheral portion 62. The recess 64 is a quadrangular annular groove and surrounds the central portion 60.

[0052] A plurality of mesas 10 are provided in the central portion 60. The mesas 10 are arranged in a two-dimensional grid. Each mesa 10 functions as a single photodiode. Terraces 12 are provided between the multiple mesas 10, separating the mesas 10. The terraces 12 are recessed from the mesas 10 in the Z-axis direction. The peripheral portion 62 is located at the same height as the mesas 10 in the Z-axis direction.

[0053] An electrode 16 is provided on the mesa 10. A bump 66 is provided on the electrode 16. A plurality of electrodes 63 are provided on the outer periphery 62. The bumps 66 are provided on the electrode 63. The electrodes 16 and 63 are made of metal. The bumps 66 are made of a metal such as indium (In). Although not shown in FIG. 10, an electrode is also provided in the recess 64. The electrode in the recess 64 and the electrode 63 in the outer periphery 62 are electrically connected by wiring.

[0054] 11A and 11B are cross-sectional views illustrating a photodetector 200, illustrating a cross section including one mesa 10. As shown in FIGS. 11A and 11B, semiconductor layers 40, 42, 44, and contact layer 46 form mesa 10. The portion of semiconductor layer 40 recessed from mesa 10, semiconductor layers 38, 36, and light absorption layer 34 extend from below mesa 10 to the outside of mesa 10, forming terrace 12. Semiconductor layer 32 and substrate 30 extend to central portion 60, recess 64, and peripheral portion 62. The upper surface of recess 64 is formed by semiconductor layer 32.

[0055] The terrace 12 protrudes from the recess 64, and the mesa 10 protrudes from the terrace 12. That is, the light-receiving element 200 has a two-step mesa structure.

[0056] 11A is the

[0011] direction. The left direction is the [0-1-1] direction. The side surface 20 of the mesa 10 is a (011) plane. The side surface 22 is a (0-1-1) plane. The side surfaces 20 and 22 are perpendicular to the terrace 12.

[0057] The right direction in FIG. 11B is the [0-11] direction. The left direction is the [01-1] direction. Side surface 24 of mesa 10 is a (0-11) plane. Side surface 26 is a (01-1) plane. Side surface 24 and side surface 26 form an inverted mesa shape.

[0058] According to the second embodiment, the side surfaces of each of the multiple mesas 10 are vertical or inverted. A pin junction is formed in the mesa 10. The semiconductor layer included in the terrace 12 and the semiconductor layer 32 in the recess 64 function as a conductor. The conductor is located away from each of the multiple mesas 10. This reduces the electric field.

[0059] In the terrace 12, the semiconductor layer 40, the semiconductor layer 38, the semiconductor layer 36, and the light absorption layer 34 do not form a pin junction. The semiconductor layer 32 in the recess 64 also does not form a pin junction. The semiconductor layers function as conductors in the terrace 12 and the recess 64. The potential difference between the terrace 12 and the recess 64 is small, making it difficult for a high electric field to occur. The side surface of the terrace 12 may be perpendicular to the surface of the recess 64, or may have an inverted mesa shape or a normal mesa shape.

[0060] Third Embodiment 12A and 12B are cross-sectional views illustrating a light-receiving element 300 according to the third embodiment. The light-receiving element 300 is an avalanche photodiode (APD). Descriptions of the same configuration as in the first or second embodiment will be omitted. The light-receiving element 300 has a mesa 10 (first mesa), a mesa 15 (second mesa), and a terrace 12.

[0061] 12A and 12B, a semiconductor layer 70 (first semiconductor layer), a semiconductor layer 71, a multiplication layer 72, an electric field control layer 73 (third semiconductor layer), a semiconductor layer 74, a current spreading layer (CSL) 75, a light absorption layer 76, a current spreading layer 77, a semiconductor layer 78, a semiconductor layer 79, and a contact layer 80 are stacked in this order on the upper surface of the substrate 30. The semiconductor layer 79 and the contact layer 80 correspond to the second semiconductor layer.

[0062] The central portion of semiconductor layer 70 protrudes in the Z-axis direction more than the outer periphery. Layers from semiconductor layer 71 to semiconductor layer 78 are stacked in the central portion of semiconductor layer 70. The central portion of semiconductor layer 78 protrudes more than the outer periphery. Semiconductor layer 79 is stacked in the central portion of semiconductor layer 78. A ring-shaped contact layer 80 is stacked on semiconductor layer 79.

[0063] Contact layer 80, semiconductor layer 79, and the central portion of semiconductor layer 78 form mesa 10. The height of mesa 10 is, for example, 300 nm. The layers from semiconductor layer 78 to the central portion of semiconductor layer 70 form mesa 15. Semiconductor layer 70 and substrate 30 extend outward from underneath mesa 10 and mesa 15, forming terrace 12.

[0064] The light-receiving element 300 has a two-tiered mesa structure. That is, the mesa 15 protrudes in the Z-axis direction from the terrace 12, and the mesa 10 protrudes from the mesa 15. The mesa 15 is located between the mesa 10 and the terrace 12.

[0065] The insulating film 48 covers the surface of the terrace 12, the side and top surfaces of the mesa 15, and the side and top surfaces of the mesa 10. The insulating film 48 has an opening in the portion covering the terrace 12. An electrode 14 is provided in this opening. The electrode 14 is ring-shaped and electrically connected to the semiconductor layer 70. The insulating film 48 has an opening in the portion covering the top surface of the mesa 10. A contact layer 80 is provided in this opening. An electrode 16 is provided on the top surface of the contact layer 80 and is electrically connected to the contact layer 80. The portion of the mesa 10 surrounded by the electrode 16 functions as the light-receiving region 11.

[0066] The right direction in FIG. 12A is the

[0011] direction. The left direction is the [0-1-1] direction. Side 20 of mesa 10 and side 81 of mesa 15 are (011) planes. Side 22 of mesa 10 and side 82 of mesa 15 are (0-1-1) planes. Side 20, side 22, side 81, and side 82 (collectively referred to as first planes) are perpendicular to the upper surface of terrace 12.

[0067] The right direction in FIG. 12B is the [0-11] direction. The left direction is the [01-1] direction. Side 24 of mesa 10 and side 83 of mesa 15 are (0-11) planes. Side 26 of mesa 10 and side 84 of mesa 15 are (01-1) planes. Side 24, side 26, side 83, and side 84 (collectively, second planes) are inclined with respect to the upper surface of terrace 12, forming an inverted mesa shape.

[0068] The semiconductor layer 70 is made of, for example, n-InGaAs. The thickness of the semiconductor layer 70 is, for example, 1300 nm. The semiconductor layer 71 is made of, for example, n-type aluminum indium arsenide (n-AlInAs). The thickness of the semiconductor layer 71 is, for example, 200 nm. The multiplication layer 72 is made of, for example, i-AlInAs. The thickness of the multiplication layer 72 is, for example, 1000 nm. The electric field control layer 73 is made of, for example, p-AlInAs. The thickness of the electric field control layer 73 is, for example, 100 μm.

[0069] The semiconductor layer 74 is formed of, for example, i-AlInAs. The thickness of the semiconductor layer 74 is, for example, 100 μm. The current spreading layer 75 and the current spreading layer 77 are formed of undoped indium aluminum gallium arsenide (i-InAlGaAs). The thickness of each of the current spreading layer 75 and the current spreading layer 77 is, for example, 100 nm. The light absorbing layer 76 is formed of, for example, i-InGaAs. The thickness of the light absorbing layer 76 is, for example, 1000 μm.

[0070] The semiconductor layer 78 is made of, for example, i-AlInAs. The thickness of the semiconductor layer 78 is, for example, 700 nm. The semiconductor layer 79 is made of, for example, (p+)-AlInAs. The thickness of the semiconductor layer 79 is, for example, 200 nm. The impurity concentration is, for example, 1×10 18 cm -3 The contact layer 80 is made of, for example, (p+)-InGaAs. The thickness of the contact layer 80 is, for example, 200 nm. The impurity concentration is, for example, 1×10 19 cm -3 is.

[0071] The p+-type contact layer 80 and semiconductor layer 79, and the layers from the i-type semiconductor layer 78 to the semiconductor layer 74, form a p-i junction. The p-type field control layer 73, the i-type multiplication layer 72, the n-type semiconductor layer 71, and the semiconductor layer 70 form a p-i junction. That is, the p-i conductivity types are aligned in the Z-axis direction from the top surface of the mesa 10. The semiconductor junction in this portion is referred to as a p-i junction. A p-i junction is formed in the Z-axis direction from the top surface of the mesa 15. The portion of the semiconductor layer 70 outside the mesas 10 and 15 is not included in the p-i junction or the p-i junction and functions as a conductor.

[0072] According to the third embodiment, the side surfaces of the mesas 10 and 15 have a vertical or inverted mesa shape. The conductive portions of the semiconductor layer 70 are located away from the mesas 10 and 15. In other words, high potentials are located away from the pip-in junction at the position of the mesa 10 and the pi-n junction at the position of the mesa 15. This reduces the electric field acting on the side surfaces of the mesas 10 and 15.

[0073] The operating voltage of an avalanche photodiode is several tens of volts, for example, about 70 V. Even when the operating voltage rises to several tens of volts, the electric field applied to the mesa can be reduced, and the surface leakage current can be reduced.

[0074] The third embodiment may be applied to an array-type avalanche photodiode. A plurality of mesas 10 and a plurality of mesas 15 are arranged in a central portion 60 of an array sensor as shown in FIG. 10. The semiconductor layer 70 and the substrate 30 extend to the central portion 60, a recess 64, and an outer peripheral portion 62. The side surfaces of the mesas 10 and 15 have the shapes shown in FIG. 11A or 11B.

[0075] Although the embodiments of the present disclosure have been described in detail above, the present disclosure is not limited to such specific embodiments, and various modifications and variations are possible within the scope of the gist of the present disclosure as described in the claims. [Explanation of symbols]

[0076] Mesa 10 and 15 11 Light receiving area 12 Terrace 13, 64 recess 14, 16, 63 electrodes 30 boards 34, 76 Light absorbing layer 46, 80 contact layer 32, 36, 38, 40, 42, 44, 70, 71, 74, 78, 79 Semiconductor layer 48 insulating film 57, 58 area 59 parts 72 Multiplication Layer 73 Electric field control layer 75, 77 Current spreading layer 20, 22, 24, 26, 81, 82, 83, 84 Side 50, 52, 54, 56 Masks 60 central part 62 Outer periphery 66 Bump 100, 110, 200, 300 Light receiving element

Claims

1. First Mesa and Equipped with a terrace, the terrace extends outside the first mesa and includes a first semiconductor layer having a first conductivity type; the first mesa protrudes beyond the terrace and includes a second semiconductor layer having a second conductivity type; The side surface of the first mesa is perpendicular to the terrace or has an inverted mesa shape inclined at an acute angle to the terrace.

2. the first mesa has a plurality of sides; a first surface of the plurality of side surfaces has the perpendicular shape; The light-receiving element according to claim 1 , wherein a second surface of the plurality of side surfaces has the inverted mesa shape.

3. the first mesa has a rectangular planar shape, The two first surfaces are opposite to each other and have the perpendicular shape; 3. The light-receiving element according to claim 2, wherein the two second surfaces are opposed to each other and have the inverted mesa shape.

4. the two first planes are a (011) plane and a (0-1-1) plane; 4. The light-receiving element according to claim 3, wherein the two second surfaces are a (01-1) surface and a (0-11) surface.

5. 3. The light-receiving element according to claim 1, wherein an angle between a portion of the side surface of the first mesa having the inverted mesa shape and a surface of the terrace is equal to or greater than 70 degrees and less than 90 degrees.

6. 3. The light-receiving element according to claim 1, wherein the terrace includes a light-absorbing layer laminated between the first semiconductor layer and the second semiconductor layer.

7. the light receiving element is an avalanche photodiode, a second mesa; the second mesa extends between the first mesa and the terrace and protrudes beyond the terrace; the second mesa includes a light absorption layer, a third semiconductor layer, and a multiplication layer; the light absorbing layer is laminated between the first semiconductor layer and the second semiconductor layer, the third semiconductor layer is stacked between the light absorbing layer and the first semiconductor layer and has the second conductivity type; the multiplication layer is stacked between the third semiconductor layer and the first semiconductor layer, 3. The light-receiving element according to claim 1, wherein the side surface of the second mesa has a shape perpendicular to the terrace or an inverted mesa shape inclined at an acute angle to the terrace.

8. a step of sequentially stacking a first semiconductor layer having a first conductivity type, a light absorbing layer, and a second semiconductor layer having a second conductivity type; and etching the second semiconductor layer to form a terrace and a mesa; the terrace extends outside the mesa and includes the first semiconductor layer; the mesa protrudes beyond the terrace and includes the second semiconductor layer; A method for manufacturing a light-receiving element, wherein the side surface of the mesa has a shape perpendicular to the terrace or an inverted mesa shape inclined at an acute angle to the terrace.

9. The step of forming the terrace and the mesa includes: a step of covering a portion of the second semiconductor layer with a first mask and etching a portion of the second semiconductor layer exposed from the first mask to form the vertically shaped side surface; 9. The method for manufacturing a light-receiving element according to claim 8, further comprising the step of covering another part of the second semiconductor layer with a second mask and etching the part exposed from the second mask to form a side surface of the inverted mesa shape.

10. 10. The method for manufacturing a light-receiving element according to claim 9, wherein an etching time in the step of forming the side surface of the inverted mesa shape is longer than an etching time in the step of forming the side surface of the perpendicular shape.

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