Programmable logic device, device evaluation system, internal signal acquisition method, and program

Abstract

To inexpensively and efficiently evaluate a programmable logic device.SOLUTION: A programmable logic device comprising: an internal signal acquisition circuit that acquires an internal signal which is a signal of an internal evaluation target circuit; and a data processing circuit that stores the acquired internal signal in a user-defined region of output data, and generates and outputs the internal signal as internal signal monitor data.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a programmable logic device, a device evaluation system, an internal signal acquisition method, and a program. [Background technology]

[0002] When evaluating an FPGA in real equipment, it is necessary to check the internal signals. For example, there is an evaluation system that enables observation of internal signals without being limited by the number of terminals of the product FPGA mounted on the product board, and that can perform logic verification of the product FPGA in real use when mounted on a product board (see, for example, Patent Document 1).

[0003] According to the technology disclosed in Patent Document 1, "the product FPGA mounted on the product board is equipped with a branching circuit that branches the external input signal input to the core logic. The evaluation board is equipped with an observation FPGA. The observation FPGA is equipped with an observation core logic that is logically equivalent to the core logic and an internal signal acquisition circuit that acquires the internal signal of the observation core logic. An external input signal that is used for the actual operation of the core logic is sent to the evaluation board, and the observation core logic operates equivalently to the actual operation of the core logic. The internal signal at that time is extracted and logic verification is performed (abstract excerpt)." [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-80332 Summary of the Invention [Problem to be solved by the invention]

[0005] The following analysis was performed by the inventors of the present disclosure.

[0006] According to the technology disclosed in Patent Document 1, FPGA user pins are not consumed for evaluation. However, it is necessary to prepare an evaluation board equipped with an observation FPGA equivalent to the core logic. Therefore, when building an evaluation environment, preparation work is required, and costs increase due to the parts and labor required.

[0007] The present disclosure has been made in consideration of the above circumstances, and one of its objects is to provide a technique that contributes to realizing efficient evaluation of programmable logic devices at low cost. [Means for solving the problem]

[0008] According to a first aspect of the present disclosure, an internal signal acquisition circuit for acquiring an internal signal which is a signal of an internal circuit to be evaluated; and a data processing circuit that stores the acquired internal signal in a user-defined area of ​​output data, generates it as internal signal monitor data, and outputs it.

[0009] According to a second aspect of the present disclosure, a programmable logic device as described above; and a test opposing device having a reception processing unit that receives the internal signal monitor data and presents it to a user.

[0010] According to a third aspect of the present disclosure, Acquire an internal signal, which is a signal of a circuit to be evaluated inside the programmable logic device; storing the acquired internal signal in a user-defined area of ​​output data to generate internal signal monitor data; An internal signal acquisition method is provided that outputs to a test counterpart device.

[0011] According to a fourth aspect of the present disclosure, Programmable logic devices an internal signal acquisition circuit for acquiring an internal signal which is a signal of an internal circuit to be evaluated; A program is provided for causing the circuit to function as a data processing circuit that stores the acquired internal signal in a user-defined area of ​​output data, generates it as internal signal monitor data, and outputs it.

[0012] These programs can be recorded on a computer-readable storage medium. The storage medium can be a non-transitory medium such as a semiconductor memory, a hard disk, a magnetic recording medium, or an optical recording medium. The present disclosure can also be embodied as a computer program product. [Effects of the Invention]

[0013] The present disclosure can contribute to realizing efficient evaluation of programmable logic devices at low cost. [Brief explanation of the drawings]

[0014] [Figure 1] 1A is a diagram illustrating an example of the overall configuration of a device evaluation system according to the present disclosure, and FIG. 1B is a block diagram illustrating an example of an FPGA according to the present disclosure. [Figure 2] 10 is a flowchart of an internal signal acquisition process according to the present disclosure. [Figure 3] 1A is a block diagram of an example of an FPGA of the present disclosure, FIG. 1B is a hardware configuration diagram of an example of a relevant part of the FPGA of the present disclosure, and FIG. 1C is a functional block diagram of an example of a test opposing device of the present disclosure. [Figure 4] 1A is a diagram showing an example of a data format of an IP packet, and FIGS. 1B and 1C are diagrams for explaining an internal signal monitor data transmission process according to the present disclosure. [Figure 5] FIG. 10 is a diagram for explaining an example configuration of internal signal monitor data of the present disclosure. [Figure 6] 1A is a diagram for explaining an example of a method for selecting a circuit to be evaluated according to the present disclosure, and FIG. 1B is a diagram for explaining an example of a connection configuration of an FPGA according to the present disclosure. [Figure 7]10A and 10B are diagrams for explaining the necessity of the trigger condition of the present disclosure. [Figure 8] 10A and 10B are diagrams illustrating an example of a first trigger pattern of the present disclosure. [Figure 9] FIG. 10 is a diagram for explaining an example of a second trigger pattern of the present disclosure. [Figure 10] 1A and 1B are configuration diagrams showing an example of the hardware configuration of an FPGA and a test opposing device according to the present disclosure, respectively. DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Note that reference numerals in the drawings are assigned to each element for convenience as an example to facilitate understanding, and are not intended to limit the present disclosure to the illustrated aspects. Furthermore, connecting lines between blocks in the drawings and the like referred to in the following description include both bidirectional and unidirectional lines. Unidirectional arrows are used to schematically indicate the flow of the main signal (data) and do not exclude bidirectionality. Furthermore, in the following description, "A and / or B" means A or B, or A and B.

[0016] <<First Embodiment>> An outline of this embodiment will be described. In this embodiment, in actual device evaluation of a programmable logic device (PLD), which is a rewritable semiconductor device, observation of internal signals, which are output signals of a circuit to be evaluated inside the device, is facilitated.

[0017] In the following, this embodiment will be described taking as an example a case where an FPGA (Field Programmable Gate Array) is used as a programmable logic device.

[0018] An FPGA is a large-scale integrated circuit (LSI) that integrates on a single chip a large number of LUTs (Look-up Tables) with a static RAM (random access memory), flip-flops (FF), a switch matrix that connects them together called an interconnect, and other elements. By controlling the contents of the LUTs and the internal wiring state of the interconnect, it is possible to achieve the desired logical operation within the range of its integration level. The settings of the LUTs and interconnects are programmable. In other words, the logical operation of an FPGA can be rewritten any number of times.

[0019] In this embodiment, verification (hereinafter also referred to as evaluation) of a programmed logic circuit inside an FPGA is performed. Hereinafter, the logic circuit (macro) to be evaluated is referred to as the evaluation target circuit. Figure 1(a) is an overall configuration diagram of a device evaluation system 100 of this embodiment.

[0020] As shown in the figure, the device evaluation system 100 of this embodiment includes an FPGA 200 mounted on a board 209 and a test facing device 300.

[0021] The test opposing device 300 receives the internal signals of the circuit under evaluation transmitted from the FPGA 200 and presents them to the user. For example, it is realized by a server or a PC (Personal Computer).

[0022] The FPGA 200 of this embodiment processes and transmits frame data and packet data. In particular, the transmission data to be output (hereinafter referred to as output data) has an area (user-defined area) where the user can store any data.

[0023] 1B is a block diagram of a circuit configuration newly provided in the FPGA 200 of this embodiment to realize this embodiment. As shown in this figure, the FPGA 200 of this embodiment includes an internal signal acquisition circuit 210 and a data processing circuit 220.

[0024] The internal signal acquisition circuit 210 acquires an internal signal, which is an evaluation target signal, of the internal circuit under evaluation. In this embodiment, for example, a branch circuit is provided downstream of the circuit under evaluation, and an internal signal output from the circuit under evaluation is acquired for evaluation. The internal signal is data other than data output to the outside as normal data, and is used to evaluate whether the circuit under evaluation is operating correctly.

[0025] In this embodiment, the internal signal acquisition circuit 210 may acquire an internal signal when, for example, a predetermined trigger occurs.

[0026] The data processing circuit 220 outputs the internal signal acquired by the internal signal acquisition circuit 210. In this embodiment, the data processing circuit 220 stores the acquired internal signal in a user-defined area of ​​the output data of the FPGA 200 and generates it as internal signal monitor data. Then, the generated internal signal monitor data is output to the test opposing device 300.

[0027] The data processing circuit 220 generates and outputs, for example, all output data output from each unit of the FPGA 200. That is, in addition to the internal signal monitor data described above, the data processing circuit 220 also receives normal data output while the FPGA 200 is operating from each internal circuit, generates and outputs the normal data as output data. Hereinafter, normal data will be referred to as normal data. In this embodiment, the data processing circuit 220 generates and outputs the internal signal monitor data, for example, at a timing when there is no communication of normal data.

[0028] [Internal signal acquisition processing] Here, a flow of the internal signal acquisition process in the device evaluation system 100 of this embodiment will be described. Fig. 2 shows the processing flow of the internal signal acquisition process of this embodiment. This process is started when the above-mentioned internal signal acquisition trigger occurs.

[0029] The internal signal acquisition circuit 210 of the FPGA 200 acquires an internal signal and passes it to the data processing circuit 220 (step S1101).

[0030] The data processing circuit 220 stores the received internal signal in a user-defined area of ​​the output data, generates internal signal monitor data (step S1102), and outputs it to the test opposing device 300 (step S1103).

[0031] The test opposing device 300 receives (captures) the internal signal monitor data transmitted from the FPGA 200 (step S1201), and displays it on a display or the like provided in the device itself (step S1202).

[0032] As described above, according to the device evaluation system 100 of this embodiment, the internal signals of the circuit under evaluation of the FPGA 200 are stored in a user-defined area of ​​the output data and sent to the test facing device 300. Therefore, the user can observe the internal signals of the circuit under evaluation by looking at the internal signal monitor data displayed on the test facing device 300.

[0033] Generally, when checking internal signals during actual evaluation of FPGA 200, a monitor pin is mounted on board 209, and the internal signal of FPGA 200 is assigned to the monitor pin output, and the monitor pin is observed with a logic analyzer, or a dedicated circuit for monitoring internal signals is built into FPGA 200, and a dedicated connector is mounted on board 209 to check the signals using a dedicated application.

[0034] In the former case, it is necessary to assign pins of the FPGA 200 for monitoring internal signals, which consumes user pins for evaluation. The monitor pins must be mounted on the board 209, which occupies the mounting surface of the board 209 and incurs component costs for evaluation. In addition, advance preparation such as preparing a logic analyzer for observing internal signals is required.

[0035] The latter requires incorporating a dedicated circuit for monitoring internal signals into FPGA 200 and mounting a dedicated connector on board 209. This occupies space on the mounting surface of board 209 and incurs component costs for evaluation. Also, a terminal with a dedicated application installed is required to check the internal signals.

[0036] Recently, programmable logic devices such as FPGA 200 have become smaller, making it difficult to secure an area on board 209 for mounting evaluation monitor pins and dedicated connectors. For this reason, when implementing these conventional methods, it may even be necessary to create a separate evaluation board 209.

[0037] In other words, as devices become smaller, development of devices often involves a two-step process: first, evaluation is performed using an evaluation board equipped with evaluation components and interfaces, etc., and then, after evaluation is complete, these evaluation components and interfaces, etc. are removed to miniaturize the board.

[0038] According to this embodiment, evaluation of the FPGA 200 in an actual device can be achieved in a system evaluation environment without the need to pull out monitor pins for internal signals or prepare dedicated applications and terminals. This reduces the number of components mounted on the board. Furthermore, evaluation can be achieved on the final board without using evaluation components, interfaces, etc.

[0039] That is, according to the device evaluation system 100 of this embodiment, component costs for monitor pins and dedicated connectors mounted on the board for monitoring internal signals of the FPGA 200 can be reduced, and the need for FPGA 200 monitor pin assignment is eliminated, allowing for user I / O pins to be secured. Furthermore, component removal also ensures component mounting area on the board. Furthermore, there is no need to prepare a logic analyzer for monitoring internal signals of the FPGA 200 or a terminal with a dedicated application installed, reducing equipment costs and the number of preparation steps required for building an evaluation environment. This reduces the preparation time and equipment costs for evaluation.

[0040] Furthermore, according to this embodiment, it is possible to reduce the number of evaluation components in a small programmable logic device such as FPGA 200. This makes it possible to evaluate the board in its final form without having to go through the process of creating an evaluation board as a prototype on which evaluation components are mounted and then performing evaluation.

[0041] According to this embodiment, programmable logic devices can be evaluated efficiently at low cost.

[0042] <<Second embodiment>> Next, a second embodiment of the present disclosure will be described. This embodiment is an embodiment that embodies the first embodiment in more detail. In this embodiment, components with the same names as those in the first embodiment basically have the same functions as those in the first embodiment. Hereinafter, this embodiment will be described, focusing on the differences from the first embodiment.

[0043] In this embodiment, a device is devised so that desired internal signals among the internal signals of the circuit under evaluation can be stored in the user-defined area.

[0044] The device evaluation system 100 of this embodiment basically has the same configuration as the device evaluation system 100 of the first embodiment shown in FIG. 1( a ), and includes an FPGA 200 and a test opposing device 300 .

[0045] [FPGA] 3A, the FPGA 200 of this embodiment includes an internal signal acquisition circuit 210, a data processing circuit 220, a setting circuit 230, a selection circuit 240, and a trigger setting register 250. The FPGA 200 also includes a buffer 260.

[0046] As in the first embodiment, the internal signal acquisition circuit 210 acquires an internal signal, which is an evaluation target signal, of an internal evaluation target circuit of the FPGA 200. In this embodiment, the internal signal acquisition circuit 210 acquires an internal signal of an evaluation target circuit selected by the selection circuit 240 from one or more evaluation target circuits included in the FPGA 200.

[0047] 3(b), the internal signal acquisition circuit 210 is realized by a branching circuit 291 that branches a signal required for evaluation and a selective synchronization circuit 292, which are arranged in the subsequent stage of the evaluation target circuit 290. The internal signal of the evaluation target circuit 290 is transmitted to a packet transmission circuit 293 that realizes the data processing circuit 220 via the branching circuit 291 and the selective synchronization circuit 292. The selective synchronization circuit 292 is a circuit that is configured by, for example, a register, a multiplexer, etc., and holds an internal signal and outputs it in synchronization with a clock signal (a counter, which will be described later).

[0048] As in the first embodiment, the data processing circuit 220 stores the internal signal acquired by the internal signal acquisition circuit 210 in a user-defined area of ​​the output data to generate internal signal monitor data, and outputs the data to the test facing device 300. The data format of this output data is a format used for normal data that the FPGA 200 outputs to an external device (here, the test facing device 300) during normal operation.

[0049] 4(a) shows a typical IP packet 400 as an example of the format of output data generated by the data processing circuit 220 of this embodiment. The data processing circuit 220 of this embodiment stores an internal signal in a user-defined area (IP Data in this figure) 401, which is an area where the user can freely store any data, and generates internal signal monitor data 410.

[0050] As described above, during evaluation of the evaluation target circuit 290, normal data that is output during normal operation is also generated from the FPGA 200. The data processing circuit 220 also outputs the generated normal data to an external device (here, the test facing device 300). The data processing circuit 220 outputs internal signal monitor data to the test facing device 300 at a timing when there is no communication of this normal data.

[0051] 4(b) and 4(c) are diagrams for explaining the operation of the data processing circuit 220 of this embodiment when outputting internal signal monitor data 410. As shown in FIG. 4(b), the data processing circuit 220 stores the internal signal in the same output data format (e.g., IP packet 400) as the normal data 420, and transmits the internal signal monitor data 410 to the test opposing device 300.

[0052] 4(c), the data processing circuit 220 transmits the generated internal signal monitor data 410 at a timing when there is no communication of normal data 420. The FPGA 200 has a buffer 260 with a capacity corresponding to the maximum data length of the normal data 420. The data processing circuit 220 temporarily stores the normal data 420 generated during transmission of the internal signal monitor data 410 in this buffer 260 and puts the data 420 on hold before transmission.

[0053] Furthermore, the data processing circuit 220 of this embodiment stores the internal signal acquired for each trigger condition, which will be described later, in the user-defined area 401. The trigger conditions will be described later.

[0054] An example of storing an internal signal for each trigger condition in the user-defined area 401 is shown in FIG. 5. As shown in this figure, the data processing circuit 220 divides the user-defined area 401 in advance for each trigger condition. The data processing circuit 220 stores the internal signal in the divided area according to the trigger condition. When storing the internal signal in the user-defined area 401, the data processing circuit 220 adds a dedicated header as shown in this figure.

[0055] The setting circuit 230 sets the timing for outputting the internal signal to the data processing circuit 220 as a register setting in the trigger setting register 250. Note that the register setting may be stored in an external storage area configured by a nonvolatile memory such as a flash memory prepared separately from the FPGA 200. In this case, for example, when the power is turned on, the data stored in this nonvolatile memory is loaded into the trigger setting register 250. This register setting is one of the above-mentioned trigger conditions.

[0056] The selection circuit 240 selects an evaluation target circuit 290 for storing the acquired internal signal in the user-defined area 401. An image of the selection by the selection circuit 240 is shown in FIG. 6(a). In this embodiment, the FPGA 200 is assumed to have one or more evaluation target circuits 290 therein, which are circuits to be evaluated. The selection circuit 240 selects one evaluation target circuit 290 from among these in accordance with an instruction from the user. In this embodiment, this is set in a register, which will be described later. The internal signal acquisition circuit 210 acquires the internal signal according to the selection result. Note that the evaluation target circuit 290 may be set to a default value that can be changed arbitrarily by register setting.

[0057] The trigger setting register 250 stores a register setting, which is one of the trigger conditions. The value set in the register is referenced and used by the internal signal acquisition circuit 210 and the selection circuit 240. That is, the internal signal acquisition circuit 210 acquires an internal signal in accordance with the register setting and outputs it to the data processing circuit 220. The register setting will be described in detail later.

[0058] 6(b), within the FPGA 200, the internal signal acquisition circuit 210 and the data processing circuit 220 are configured, for example, by a multiplexer. A signal to be monitored within the FPGA 200 is input to the internal signal acquisition circuit 210. The internal signal acquisition circuit 210 selects the signal to be monitored in accordance with the trigger setting register 250 and the selection conditions of the selection circuit 240, and outputs the selected signal as internal signal monitor data. Furthermore, normal data and internal signal monitor data are input to the data processing circuit 220. The data processing circuit 220 selects and outputs the internal signal monitor data in accordance with an arbitration circuit that prioritizes normal data.

[0059] [Test device] As shown in Fig. 3(c), the test opposing device 300 of this embodiment includes a receiving processor 310. The receiving processor 310 receives output data transmitted from the FPGA 200 and extracts data such as internal signals stored in the user-defined area 401. The extracted data is output to, for example, an output device included in the device itself. The output device may be, for example, a display.

[0060] [Register settings] As described above, there are two types of trigger conditions (trigger patterns: first trigger pattern and second trigger pattern) that are set as triggers for outputting an internal signal. Of these, the first trigger pattern limits the period during which the internal signal is output to the data processing circuit 220. This controls the amount of internal signals stored in the user-defined area 401 by the data processing circuit 220. The necessary information is set in advance by the setting circuit 230.

[0061] As described above, the data processing circuit 220 of this embodiment stores internal signals in the user-defined area 401 of the output data. The size of the user-defined area 401 is predetermined. For this reason, as shown in FIG. 7(a), if the internal signals are constantly sampled, there is a possibility that the desired information will not be stored within the storage limit of the user-defined area 401.

[0062] Therefore, in this embodiment, as shown in Figure 7(b), by setting a trigger to output an internal signal to the data processing circuit 220, the internal signals received by the data processing circuit 220 can be reduced and the necessary internal signals can be stored in the user-defined area 401.

[0063] The first trigger pattern is a pattern that is realized by setting in advance a desired number of internal signals for a desired period for each of the evaluation target circuits 290 included in the FPGA 200.

[0064] 8(a) shows an example of the register setting 251. Here, for each piece of information specifying the evaluation target circuit 290 (hereinafter simply referred to as evaluation target circuit information 252; 1 to K (K is an integer of 2 or more)), a reference counter 253, a start count 254, and a sampling count 255 are set. In accordance with this register setting 251, the internal signal acquisition circuit 210 operates and outputs an internal signal.

[0065] The reference counter 253 is information specifying a counter to be used when an internal signal is output from the selective synchronization circuit 292 to the data processing circuit 220. In this embodiment, a plurality of counters with different time intervals are prepared in advance. For example, counters 1 to K shown in FIG. 8(b) are used. The reference counter 253 determines the interval (sampling interval) at which the internal signal is output to the data processing circuit 220.

[0066] The start count 254 is the count at which output of an internal signal begins. For example, upon receiving an instruction to acquire an internal signal from a user, the internal signal acquisition circuit 210 starts counting according to the reference counter 253. Then, when the count reaches the count set as the start count 254, the internal signal acquisition circuit 210 starts outputting the internal signal to the data processing circuit 220. In response to this, the data processing circuit 220 starts generating internal signal monitor data 410.

[0067] The sampling count 255 indicates the number of times to output the internal signal. The internal signal acquisition circuit 210 outputs the internal signal to the data processing circuit 220 for the number of times specified by the sampling count 255, at intervals of the reference counter 253, from the start count 254.

[0068] A specific example is shown in Fig. 8(b). Here, as an example, a case is illustrated in which an evaluation target circuit 290 whose evaluation target circuit information 252 in Fig. 8(a) is 2 is selected. The setting values ​​are as shown in Fig. 8(a). That is, the reference counter 253 is counter 2, the start count 254 is 3, and the number of samplings 255 is N (N is an integer equal to or greater than 1).

[0069] In this way, by register setting 251, the internal signal acquisition circuit 210 outputs an internal signal when the count of counter 2 reaches 3. Thereafter, the output continues according to the interval of counter 2. Then, after outputting N times, the output stops. In other words, the output stops when the counter of counter 2 reaches N+3.

[0070] The second trigger pattern is a pattern that is triggered by a fault notification, etc. When a predetermined fault notification, etc. is output, the internal signal acquisition circuit 210 outputs an internal signal related to the fault notification to the data processing circuit 220.

[0071] An image of the second trigger pattern is shown in Fig. 9. As shown in this figure, when the internal signal acquisition circuit 210 detects that a fault notification, which is issued when a predetermined fault is detected, has been output from the evaluation target circuit 290, it uses this as a trigger to output a related internal signal to the data processing circuit 220. In response to this, the data processing circuit 220 stores the internal signal as internal signal monitor data 410 in an area of ​​the user definition area 401 allocated to the second trigger pattern.

[0072] The second trigger pattern may be set to a different trigger pattern for each notification of a different failure. In this case, the second trigger pattern and the third trigger pattern are set to different trigger patterns.

[0073] 5, one user-defined area 401 is divided into an area for storing an internal signal acquired by a first trigger pattern and an area for storing an internal signal acquired by a second trigger pattern, and the respective internal signals are stored in the area. However, if different trigger patterns are set for different fault notifications, the user-defined area 401 is further divided into areas for storing the respective trigger patterns.

[0074] The flow of the internal signal acquisition process in this embodiment is the same as in the first embodiment, and therefore a description thereof will be omitted here.

[0075] As described above, according to this embodiment, the device evaluation system 100 has the same configuration as in the first embodiment, and therefore, the same effects as in the first embodiment can be obtained.

[0076] Furthermore, according to this embodiment, a trigger for storing an internal signal in the user-defined area 401 is determined in advance. Therefore, the required internal signal can be output to the test opposing device 300 more efficiently than when the internal signal is stored all the time.

[0077] Therefore, in this embodiment as well, it is possible to evaluate a programmable logic device efficiently at low cost.

[0078] <Variation 1> In the second embodiment, when the trigger condition is the register setting 251, only one evaluation target circuit 290 can be selected, but this is not limiting. For example, the register setting 251 may be configured so that multiple evaluation target circuits 290 can be selected.

[0079] In this case, in the register setting 251, the set values ​​are set so that the sampling periods of the multiple evaluation target circuits selected at the same time do not overlap.

[0080] Furthermore, the register settings 251 may be registered for each evaluation target circuit 290 .

[0081] <Variation 2> In the second embodiment, the internal signal acquisition circuit 210 includes a selective synchronization circuit 292, and outputs an internal signal to the data processing circuit 220 in accordance with the register setting 251 in the first trigger pattern. However, this configuration is not limiting. For example, the selective synchronization circuit 292 may be included in the data processing circuit 220.

[0082] In this case, the data processing circuit 220 starts counting in accordance with the register setting 251 and controls the timing and period for storing the internal signal acquired by the internal signal acquisition circuit 210 in the user-defined area 401 .

[0083] <Variation 3> Furthermore, in the above-described embodiments and modifications, the PLD is described as an FPGA 200, but the PLD is not limited to this. Any large-scale integrated circuit (LSI) may be used as long as its functions can be changed after shipment and it has an area in the output data format where any data can be stored.

[0084] [Hardware configuration] 10(a) is a diagram showing a typical configuration of an FPGA 200. The FPGA 200 has a plurality of logic elements (LEs) 201 arranged in a regular pattern, each including a look-up table (LUT) and a flip-flop (FF), not shown, and a switch matrix called an interconnect 203 that interconnects the LEs 201 with each other and I / O pins 202. Some FPGAs also have built-in dedicated macroblocks such as multipliers and memory blocks.

[0085] Each LUT has multiple SRAM (Static RAM) cells and a multiplexer that selects one of two inputs. The multiple SRAM cells and multiple multiplexers form an address decoder. The input to the LUT is the selection signal for each stage of the multiplexers connected in a tournament configuration, and the output of the final stage multiplexer becomes the output of the LUT. The LUT realizes any logic function (truth table) using the contents stored in the SRAM cells, called the LUT mask.

[0086] The FPGA 200 controls the contents stored in the LUT and the internal wiring state of the interconnect 203 to realize a desired logical operation. That is, the operation of each circuit in the FPGA 200 is realized by logically synthesizing definitions written in a hardware description language, performing placement and wiring, and loading the definitions into the FPGA 200, thereby physically changing the hardware.

[0087] The test opposing device 300 in each of the above embodiments may be realized by, for example, a general-purpose information processing device. The general-purpose information processing device includes, for example, a CPU (Central Processing Unit) 391, a main storage device (memory) 392, an auxiliary storage device 393, a communication I / F 394, and an expansion I / F 395, which are interconnected by an internal bus, as shown in FIG. 10(b).

[0088] The CPU 391 realizes the above functions and comprehensively controls the entire device by, for example, loading a program stored in the auxiliary storage device 393 into the main storage device 392 and executing it. Note that the CPU 391 may be replaced by one or more processors such as an MPU (Micro Processing Unit).

[0089] The main storage device 392 is a memory such as a RAM (Random Access Memory), etc. The main storage device 392 is a work area when the CPU 391 processes programs executed by the installed devices.

[0090] The auxiliary storage device 393 is, for example, a read only memory (ROM), a hard disk drive (HDD), a solid state drive (SSD), etc. The auxiliary storage device 393 stores various programs executed by the installed devices.

[0091] The secondary storage device 393 may include a storage medium such as a flexible disk, a hard disk, an optical disk, a CD-ROM, a CD-R, a magnetic tape, a non-volatile memory card, or a DVD.

[0092] The programs stored in the auxiliary storage device 393 can be provided as program products recorded on a non-transitory computer-readable recording medium. The auxiliary storage device 393 can be used for medium- to long-term storage of various programs recorded on a non-transitory computer-readable recording medium.

[0093] The communication I / F 394 is an interface for inputting and outputting signals and data via wire or wirelessly. In each of the above embodiments and / or modifications, the communication I / F 394 is an interface for receiving, for example, the normal data 420 and the internal signal monitor data 410 from the FPGA 200.

[0094] The expansion I / F 395 is, for example, a USB interface or a memory slot, and is connected to an external storage unit, an input device, an output device, etc. The expansion I / F 395 may be provided with a plurality of different types of interfaces. For example, a display device such as a monitor may be connected to display the internal signal monitor data 410.

[0095] The reception processing unit 310 of the test opposing device 300 is realized by the CPU 391 loading a program stored in the auxiliary storage device 393 into the main storage device 392 and executing the program.

[0096] Note that the hardware configuration of the test opposing device 300 is not limited to this. Furthermore, each function (server) of each device may be implemented, for example, by an integrated circuit (IC) dedicated to each process, an application specific integrated circuit (ASIC), a system on chip (SOC), a field programmable gate array (FPGA), or the like.

[0097] In the process flow used in the above explanation, multiple steps (processes) are described in order, but the order in which each step is performed is not limited to the order described. For example, the order of the steps shown in the figure can be changed to the extent that the content is not affected, such as performing each process in parallel.

[0098] Although the embodiments and modifications of the present disclosure have been described above, the present disclosure is not limited to the above-described embodiments and can be modified in various ways that would be understandable to a person skilled in the art. Each embodiment and modification can be combined with other embodiments as appropriate. Furthermore, for example, the network configurations and element configurations shown in the drawings are examples intended to aid in understanding the present disclosure and are not limited to the configurations shown in these drawings.

[0099] Finally, preferred embodiments of the present disclosure will be summarized. Some or all of the above-described embodiments can be described as, but are not limited to, the following supplementary notes. (Appendix 1) Programmable logic devices an internal signal acquisition circuit for acquiring an internal signal which is a signal of an internal circuit to be evaluated; and a data processing circuit that stores the acquired internal signal in a user-defined area of ​​output data, generates it as internal signal monitor data, and outputs it. (Appendix 2) 10. The programmable logic device of claim 1, It is desirable that the data processing circuit outputs the internal signal monitor data at a timing when there is no normal data communication. (Appendix 3) 3. The programmable logic device of claim 2, It is preferable to further include a buffer area for storing the normal data while the internal signal monitor data is being output. (Appendix 4) 4. The programmable logic device of claim 1, There are a plurality of trigger conditions that trigger the output of the internal signal to the data processing circuit, It is desirable that the data processing circuit divides the user-defined area for each of the trigger conditions and stores the internal signals. (Appendix 5) 5. The programmable logic device of claim 4, The trigger condition is preferably determined by the start count of a counter that is used when acquiring the internal signal from the circuit under evaluation. (Appendix 6) 5. The programmable logic device of claim 4, The trigger condition is preferably a fault notification of the circuit under evaluation. (Appendix 7) 7. The programmable logic device of claim 1, The internal signal acquisition circuit is preferably a branching circuit that is arranged in a subsequent stage of the circuit under evaluation and that branches the internal signal and outputs the branched signal to the data processing circuit. (Appendix 8) The device evaluation system a programmable logic device according to any one of claims 1 to 7; and and a test opposing device having a reception processing unit that receives the internal signal monitor data and presents it to a user. (Appendix 9) The internal signal acquisition method is as follows: Acquire an internal signal, which is a signal of a circuit to be evaluated inside the programmable logic device; storing the acquired internal signal in a user-defined area of ​​output data to generate internal signal monitor data; Output to the test counterpart device. (Appendix 10) The program is Programmable logic devices an internal signal acquisition circuit for acquiring an internal signal which is a signal of an internal circuit to be evaluated; The acquired internal signal is stored in a user-defined area of ​​the output data, and the circuit functions as a data processing circuit that generates and outputs internal signal monitor data. In addition, the form of Supplementary Note 9 or 10 can be expanded into the form of Supplementary Note 2-7, just like Supplementary Note 1.

[0100] The disclosures of the above-mentioned patent documents, etc. are incorporated herein by reference. Modifications and adjustments of the embodiments and variations are possible within the scope of this disclosure (including the claims), and further based on its basic technical concept. Furthermore, various combinations and selections of the various disclosed elements (including each element of each claim, each element of each embodiment or variation, each element of each drawing, etc.) are possible within the scope of this disclosure. In other words, this disclosure naturally includes various modifications and alterations that would be possible by a person skilled in the art in accordance with the entire disclosure, including the claims, and the technical concept. In particular, with regard to the numerical ranges described herein, any numerical value or subrange included within the range should be construed as being specifically described, even if not otherwise specified. [Explanation of symbols]

[0101] 100: Device evaluation system, 200: FPGA, 201: LE, 202: I / O pin, 203: interconnect, 209: board, 210: internal signal acquisition circuit, 220: data processing circuit, 230: setting circuit, 240: selection circuit, 250: trigger setting register, 251: register setting, 252: evaluation target circuit information, 253: reference counter, 254: start count, 255: number of samplings, 260: buffer, 290: evaluation target circuit, 291: branching circuit, 292: selection synchronization circuit, 293: packet transmission circuit, 300: Test opposite device, 310: Reception processing unit, 391: CPU, 392: Main storage device, 393: Auxiliary storage device, 394: Communication I / F, 395: Expansion I / F, 400: IP packet, 401: User-defined area, 410: Internal signal monitor data, 420: Normal data

Claims

1. an internal signal acquisition circuit for acquiring an internal signal which is a signal of an internal circuit to be evaluated; a data processing circuit that stores the acquired internal signal in a user-defined area of ​​output data, and generates and outputs the internal signal monitor data.

2. 10. The programmable logic device of claim 1, The data processing circuit outputs the internal signal monitor data at a timing when there is no normal data communication.

3. 3. The programmable logic device of claim 2, The programmable logic device further comprises a buffer area for storing the normal data while the internal signal monitor data is being output.

4. 10. The programmable logic device of claim 1, There are a plurality of trigger conditions that trigger the output of the internal signal to the data processing circuit, The data processing circuit divides the user-defined area for each trigger condition and stores the internal signal.

5. 5. The programmable logic device of claim 4, The programmable logic device, wherein the trigger condition is determined by a start count of a counter that is used when acquiring the internal signal from the circuit under evaluation.

6. 5. The programmable logic device of claim 4, The programmable logic device, wherein the trigger condition is a fault notification of the circuit under evaluation.

7. 10. The programmable logic device of claim 1, The internal signal acquisition circuit is a branching circuit that is arranged in a subsequent stage of the circuit under evaluation and branches the internal signal and outputs the branched signal to the data processing circuit.

8. a programmable logic device according to claim 1; a test opposing device having a reception processing unit that receives the internal signal monitor data and presents it to a user.

9. Acquire an internal signal, which is a signal of a circuit to be evaluated inside the programmable logic device; storing the acquired internal signal in a user-defined area of ​​output data to generate internal signal monitor data; A method for acquiring an internal signal that is output to the opposing test device.

10. Programmable logic devices an internal signal acquisition circuit for acquiring an internal signal which is a signal of an internal circuit to be evaluated; A program for causing the circuit to function as a data processing circuit that stores the acquired internal signal in a user-defined area of ​​output data, generates it as internal signal monitor data, and outputs it.

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