Method for manufacturing semiconductor light emitting device

Abstract

To improve characteristics of a p-side electrode of a semiconductor light-emitting element.SOLUTION: The method includes forming an active layer 26 made of an AlGaN-based semiconducting material on an n-type semiconductor layer 24 made of an n-type AlGaN-based semiconducting material, forming a p-type semiconductor layer 28 on the active layer 26, forming a first electrode layer 28a that is in contact with an upper surface 30a of the p-type semiconductor layer 28 and contains a first element by vapor deposition, forming a second electrode layer 30a that is in contact with the first electrode layer 30b and contains the first element by sputtering, and forming p-side contact electrodes 30 by annealing the first electrode layer 30a and the second electrode layer 30b.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a semiconductor light-emitting device. [Background technology]

[0002] A semiconductor light-emitting device has an n-type semiconductor layer, an active layer, and a p-type semiconductor layer stacked on a substrate, and a p-side electrode is provided on the p-type semiconductor layer. Light-emitting devices using nitride semiconductors such as GaN and AlGaN use transparent conductive oxides such as indium tin oxide (ITO) or platinum group metals such as rhodium (Rh) as the material for the p-side electrode (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-180241 Summary of the Invention [Problem to be solved by the invention]

[0004] From the viewpoint of improving the characteristics of the semiconductor light emitting device, it is preferable to reduce the contact resistance of the p-side electrode.

[0005] The present invention has been made in view of these problems, and has an object to improve the characteristics of the p-side electrode of a semiconductor light-emitting element. [Means for solving the problem]

[0006] A method for manufacturing a semiconductor light-emitting element according to one embodiment of the present invention includes the steps of forming an active layer made of an AlGaN-based semiconductor material on an n-type semiconductor layer made of an n-type AlGaN-based semiconductor material, forming a p-type semiconductor layer on the active layer, forming a first electrode layer by vapor deposition, the first electrode layer being in contact with an upper surface of the p-type semiconductor layer and containing a first element, forming a second electrode layer by sputtering, the second electrode layer being in contact with the first electrode layer and containing the first element, and annealing the first electrode layer and the second electrode layer to form a p-side contact electrode. [Effects of the Invention]

[0007] According to the present invention, the characteristics of the p-side electrode of a semiconductor light emitting device can be improved. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view schematically illustrating a configuration of a semiconductor light emitting device according to an embodiment. [Figure 2] 1A to 1C are diagrams schematically illustrating a manufacturing process of a semiconductor light emitting device according to an embodiment. [Figure 3] 1A to 1C are diagrams schematically illustrating a manufacturing process of a semiconductor light emitting device according to an embodiment. [Figure 4] 1A to 1C are diagrams schematically illustrating a manufacturing process of a semiconductor light emitting device according to an embodiment. [Figure 5] 1A to 1C are diagrams schematically illustrating a manufacturing process of a semiconductor light emitting device according to an embodiment. [Figure 6] 1A to 1C are diagrams schematically illustrating a manufacturing process of a semiconductor light emitting device according to an embodiment. [Figure 7] 1A to 1C are diagrams schematically illustrating a manufacturing process of a semiconductor light emitting device according to an embodiment. [Figure 8] 1A to 1C are diagrams schematically illustrating a manufacturing process of a semiconductor light emitting device according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments for implementing the present invention will be described in detail with reference to the drawings. In the description, the same elements are denoted by the same reference numerals, and redundant descriptions are omitted as appropriate. Also, for the sake of understanding the description, the dimensional ratios of the respective components in each drawing do not necessarily match the dimensional ratios of the actual light-emitting element.

[0010] The semiconductor light-emitting element according to the present embodiment is configured to emit "deep ultraviolet light" with a central wavelength λ of about 360 nm or less, and is a so-called DUV-LED (Deep UltraViolet-Light Emitting Diode) chip. In order to output deep ultraviolet light of such a wavelength, an aluminum gallium nitride (AlGaN)-based semiconductor material with a bandgap of about 3.4 eV or more is used. In the present embodiment, in particular, the case of emitting deep ultraviolet light with a central wavelength λ of about 240 nm to 320 nm is shown.

[0011] In this specification, the "AlGaN-based semiconductor material" refers to a semiconductor material containing at least aluminum nitride (AlN) and gallium nitride (GaN), and includes semiconductor materials containing other materials such as indium nitride (InN). Therefore, the "AlGaN-based semiconductor material" referred to in this specification can be represented by the composition of In 1-x-y Al x Ga y N (0 < x + y ≤ 1, 0 < x < 1, 0 < y < 1), and includes AlGaN or InAlGaN. The "AlGaN-based semiconductor material" in this specification has, for example, a molar fraction of each of AlN and GaN of 1% or more, preferably 5% or more, 10% or more, or 20% or more.

[0012] Also, in order to distinguish materials that do not contain AlN, they may be referred to as "GaN-based semiconductor materials". "GaN-based semiconductor materials" include GaN and InGaN. Similarly, in order to distinguish materials that do not contain GaN, they may be referred to as "AlN-based semiconductor materials". "AlN-based semiconductor materials" include AlN and InAlN.

[0013] 1 is a cross-sectional view schematically illustrating the configuration of a semiconductor light emitting device 10 according to an embodiment. The semiconductor light emitting device 10 includes a substrate 20, a base layer 22, an n-type semiconductor layer 24, an active layer 26, a p-type semiconductor layer 28, a p-side contact electrode 30, an n-side contact electrode 32, a protective layer 34, a p-side pad electrode 36, and an n-side pad electrode 38.

[0014] 1, the direction indicated by arrow A may be referred to as the "vertical direction" or "thickness direction." Furthermore, when viewed from the substrate 20, the direction away from the substrate 20 may be referred to as the upper side, and the direction toward the substrate 20 may be referred to as the lower side.

[0015] The substrate 20 has a first main surface 20a and a second main surface 20b opposite to the first main surface 20a. The first main surface 20a is a crystal growth surface for growing each layer from the base layer 22 to the p-type semiconductor layer 28. The substrate 20 is made of a material that is transparent to the deep ultraviolet light emitted by the semiconductor light emitting device 10, such as sapphire (Al2O3). A fine uneven pattern with a depth and pitch of submicron (1 μm or less) is formed on the first main surface 20a. Such a substrate 20 is also called a patterned sapphire substrate (PSS). The second main surface 20b is a light extraction surface for extracting the deep ultraviolet light emitted by the active layer 26 to the outside. The substrate 20 may be made of AlN or AlGaN. The substrate 20 may be a normal substrate in which the first main surface 20a is an unpatterned flat surface.

[0016] The base layer 22 is provided on the first main surface 20a of the substrate 20. The base layer 22 is an underlayer (template layer) for forming the n-type semiconductor layer 24. The base layer 22 is, for example, an undoped AlN layer, and more specifically, an AlN layer grown at high temperature (HT-AlN; High Temperature-AlN). The base layer 22 may further include an undoped AlGaN layer formed on the AlN layer. When the substrate 20 is an AlN substrate or an AlGaN substrate, the base layer 22 may be composed of only an undoped AlGaN layer. That is, the base layer 22 includes at least one of an undoped AlN layer and an AlGaN layer.

[0017] The n-type semiconductor layer 24 is provided on the upper surface 22a of the base layer 22. The n-type semiconductor layer 24 is made of an n-type AlGaN-based semiconductor material and is doped with, for example, Si as an n-type impurity. The n-type semiconductor layer 24 has a composition ratio selected so as to transmit the deep ultraviolet light emitted by the active layer 26. For example, the n-type semiconductor layer 24 is configured so that the molar fraction of AlN is 25% or more, preferably 40% or more or 50% or more. The n-type semiconductor layer 24 has a band gap larger than the wavelength of the deep ultraviolet light emitted by the active layer 26, for example, the band gap is 4.3 eV or more. The n-type semiconductor layer 24 is preferably configured so that the molar fraction of AlN is 80% or less, i.e., the band gap is 5.5 eV or less, and more preferably, the molar fraction of AlN is 70% or less (i.e., the band gap is 5.2 eV or less). The n-type semiconductor layer 24 has a thickness of 1 μm or more and 3 μm or less, for example, a thickness of approximately 2 μm.

[0018] The n-type semiconductor layer 24 has an impurity concentration of Si of 1×10 18 / cm 3 5x10 or more 19 / cm 3 The n-type semiconductor layer 24 is configured so that the Si concentration is 5×10 18 / cm 3 3x10 or more 19 / cm 3 It is preferable to configure it so that it is 7×10 18 / cm 3 Over 2×10 19 / cm 3 In one embodiment, the Si concentration of the n-type semiconductor layer 24 is preferably 1×10 19 / cm 3 It is around, specifically 8 x 10 18 / cm 3 Over 1.5 x 10 19 / cm 3 The range is as follows:

[0019] The n-type semiconductor layer 24 has a first upper surface 24a, a second upper surface 24b, and a side surface 24c. The first upper surface 24a is a portion where the active layer 26 is formed, and the second upper surface 24b is a portion where the active layer 26 is not formed. The side surface 24c is inclined at a first angle θ1 with respect to the first upper surface 24a. The first angle θ1 is greater than (i.e., not including) 40 degrees and equal to or less than 70 degrees.

[0020] The active layer 26 is provided on the first upper surface 24a of the n-type semiconductor layer 24. The active layer 26 is made of an AlGaN-based semiconductor material, and is sandwiched between the n-type semiconductor layer 24 and the p-type semiconductor layer 28 to form a double heterostructure. The active layer 26 is configured to have a band gap of 3.4 eV or more in order to output deep ultraviolet light with a wavelength of 355 nm or less, and the AlN composition ratio is selected so that deep ultraviolet light with a wavelength of 320 nm or less can be output, for example.

[0021] The active layer 26 has, for example, a single-layer or multi-layer quantum well structure and includes a barrier layer made of an undoped AlGaN-based semiconductor material and a well layer made of an undoped AlGaN-based semiconductor material. The active layer 26 includes, for example, a first barrier layer in contact with the n-type semiconductor layer 24 and a first well layer provided on the first barrier layer. One or more pairs of a barrier layer and a well layer may be additionally provided between the first well layer and the p-type semiconductor layer 28. Each of the barrier layer and the well layer has a thickness of 1 nm or more and 20 nm or less, for example, a thickness of 2 nm or more and 10 nm or less. The active layer 26 has a side surface (or inclined surface) inclined at a second angle θ2. The second angle θ2 is smaller than the first angle θ1 and is equal to or less than 40 degrees.

[0022] An electron blocking layer may be further provided between the active layer 26 and the p-type semiconductor layer 28. The electron blocking layer is made of an undoped AlGaN-based semiconductor material, for example, configured so that the molar fraction of AlN is 40% or more, preferably 50% or more. The electron blocking layer may be configured so that the molar fraction of AlN is 80% or more, or may be made of an AlN-based semiconductor material that does not contain GaN. The electron blocking layer has a thickness of 1 nm or more and 10 nm or less, for example, a thickness of 2 nm or more and 5 nm or less. The electron blocking layer has a side surface (or an inclined surface) that is inclined at a second angle θ2.

[0023] The p-type semiconductor layer 28 is formed on the active layer 26. The p-type semiconductor layer 28 is a p-type AlGaN-based semiconductor material layer or a p-type GaN-based semiconductor material layer, for example, an AlGaN layer or a GaN layer doped with magnesium (Mg) as a p-type impurity. The p-type semiconductor layer 28 has a thickness of, for example, 20 nm or more and 400 nm or less. The p-type semiconductor layer 28 has a side surface (or an inclined surface) that is inclined at a second angle θ2.

[0024] The p-type semiconductor layer 28 may be composed of multiple layers. The p-type semiconductor layer 28 may have, for example, a p-type cladding layer and a p-type contact layer. The p-type cladding layer is a p-type AlGaN layer with a higher AlN ratio than the p-type contact layer, and is provided so as to be in contact with the active layer 26. The p-type contact layer is a p-type AlGaN layer or p-type GaN layer with a lower AlN ratio than the p-type cladding layer. The p-type contact layer is provided on the p-type cladding layer and is provided so as to be in contact with the p-side contact electrode 30. The p-type cladding layer may have a p-type first cladding layer and a p-side second cladding layer.

[0025] The composition ratio of the p-type first cladding layer is selected so as to transmit deep ultraviolet light emitted by the active layer 26. The p-type first cladding layer is configured, for example, so that the molar fraction of AlN is 25% or more, preferably 40% or more or 50% or more. The AlN ratio of the p-type first cladding layer is, for example, similar to or greater than the AlN ratio of the n-type semiconductor layer 24. The AlN ratio of the p-type cladding layer may be 70% or more, or 80% or more. The p-type first cladding layer has a thickness of 10 nm or more and 100 nm or less, for example, a thickness of 15 nm or more and 70 nm or less.

[0026] The p-type second cladding layer is provided on the p-type first cladding layer. The p-type second cladding layer is a p-type AlGaN layer with a medium AlN ratio, which is lower than that of the p-type first cladding layer and higher than that of the p-type contact layer. The p-type second cladding layer is formed, for example, so that the molar fraction of AlN is 25% or more, preferably 40% or more or 50% or more. The AlN ratio of the p-type second cladding layer is formed, for example, so that it is approximately ±10% of the AlN ratio of the n-type semiconductor layer 24. The p-type second cladding layer has a thickness of 5 nm or more and 250 nm or less, for example, a thickness of 10 nm or more and 150 nm or less. Note that the p-type second cladding layer does not necessarily have to be provided, and the p-type cladding layer may be composed of only the p-type first cladding layer.

[0027] The p-type contact layer is a p-type AlGaN layer or p-type GaN layer with a relatively low AlN ratio. The p-type contact layer is configured to have an AlN ratio of 20% or less to obtain good ohmic contact with the p-side contact electrode 30, and is preferably formed to have an AlN ratio of 10% or less, 5% or less, or 0%. That is, the p-type contact layer can be formed of a p-type GaN-based semiconductor material that is substantially free of AlN. As a result, the p-type contact layer can absorb deep ultraviolet light emitted by the active layer 26. The p-type contact layer is preferably formed thin to minimize the absorption of deep ultraviolet light emitted by the active layer 26. The p-type contact layer has a thickness of 5 nm to 30 nm, for example, a thickness of 10 nm to 20 nm.

[0028] The p-side contact electrode 30 is provided on the upper surface 28a of the p-type semiconductor layer 28. The p-side contact electrode 30 includes a first electrode layer 30a and a second electrode layer 30b. The first electrode layer 30a is in direct contact with the upper surface 28a of the p-type semiconductor layer 28. The second electrode layer 30b is provided on the first electrode layer 30a and in direct contact with the first electrode layer 30a. The thickness of the first electrode layer 30a is smaller than the thickness of the second electrode layer 30b, for example, 20% or less or 10% or less of the thickness of the second electrode layer 30b. The thickness of the first electrode layer 30a is, for example, 1 nm or more, 2 nm or more, or 5 nm or more, and for example, 30 nm or less, 20 nm or less, or 15 nm or less. The thickness of the second electrode layer 30b is, for example, 10 nm or more, 20 nm or more, or 50 nm or more, and for example, 300 nm or less, 200 nm or less, or 150 nm or less.

[0029] The first electrode layer 30a and the second electrode layer 30b may include the same material. The first electrode layer 30a and the second electrode layer 30b may include, for example, a first element. The first element may be a metal element constituting a transparent conductive oxide such as tin oxide (SnO), indium tin oxide (ITO), or zinc oxide (ZnO). That is, the first element may be tin (Sn), indium (In), or zinc (Zn). The first element may be a platinum group element such as ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), or platinum (Pt).

[0030] The first electrode layer 30a may contain only the first element. The first electrode layer 30a may contain, for example, only Sn, In, or Zn, or only Ru, Rh, Pd, Os, Ir, or Pt. The second electrode layer 30b may contain only the first element, or may contain a second element different from the first element. The second electrode layer 30b may contain an oxide of the first element. In this case, the second element may be oxygen (O). As an example, the first electrode layer 30a may contain only In, and the second electrode layer 30b may contain In, Sn, and O.

[0031] The first electrode layer 30a can be formed by vapor deposition. The first electrode layer 30a is formed over a first range W1. The second electrode layer 30b can be formed by sputtering. The second electrode layer 30b can be formed over a second range W2 that is wider than the first range W1. Therefore, the formation range (second range W2) of the second electrode layer 30b is larger than the formation range (first range W1) of the first electrode layer 30a.

[0032] The n-side contact electrode 32 is provided on the second upper surface 24b of the n-type semiconductor layer 24. The n-side contact electrode 32 includes a first Ti layer 32a, an Al layer 32b, a second Ti layer 32c, and a TiN layer 32d, and can have a Ti / Al / Ti / TiN layered structure. The n-side contact electrode 32 does not have to include the second Ti layer 32c, and may have a Ti / Al / TiN layered structure.

[0033] The first Ti layer 32a is in contact with the second upper surface 24b of the n-type semiconductor layer 24 and has a thickness of 1 nm to 10 nm. The thickness of the first Ti layer 32a is, for example, 2 nm to 5 nm. The Al layer 32b is in contact with the first Ti layer 32a and has a thickness of 200 nm to 1000 nm. The thickness of the Al layer 32b is, for example, 300 nm to 400 nm, and for example, 800 nm to 500 nm. The thickness of the second Ti layer 32c is, for example, 1 nm to 5 nm, and for example, 50 nm to 25 nm. The TiN layer 32d covers the Al layer 32b and has a thickness of 100 nm or more. The thickness of the TiN layer 32d is, for example, 105 nm to 120 nm, and for example, 200 nm to 150 nm.

[0034] The first Ti layer 32a, the Al layer 32b, the second Ti layer 32c, and the TiN layer 32d can be formed by sputtering. The first Ti layer 32a, the Al layer 32b, the second Ti layer 32c, and the TiN layer 32d may be formed in the same area.

[0035] The protective layer 34 is made of a dielectric material and covers the entire upper surface of the device. The protective layer 34 covers the n-type semiconductor layer 24, the active layer 26, the p-type semiconductor layer 28, the p-side contact electrode 30, and the n-side contact electrode 32. The protective layer 34 has a p-side opening 34p provided on the p-side contact electrode 30 and an n-side opening 34n provided on the n-side contact electrode 32. The protective layer 34 covers the p-side contact electrode 30 at a location different from the p-side opening 34p and covers the n-side contact electrode 32 at a location different from the n-side opening 34n.

[0036] The protective layer 34 is made of an oxide dielectric material such as silicon oxide (SiO2), aluminum oxide (Al2O3), or hafnium oxide (HfO2). The protective layer 34 may also be made of a nitride dielectric material such as silicon nitride (SiN). The protective layer 34 may have a stacked structure in which multiple dielectric layers are stacked, or the multiple dielectric layers may be made of different dielectric materials. The thickness of the protective layer 34 is, for example, 300 nm or more, 500 nm or more, or 700 nm or more, and, for example, 1500 nm or less, 1000 nm or less, or 800 nm or less.

[0037] The p-side pad electrode 36 and the n-side pad electrode 38 are portions that bond the semiconductor light emitting element 10 to a submount substrate or the like. The p-side pad electrode 36 and the n-side pad electrode 38 include, for example, a stacked structure of Ni / Au, Ti / Au, or Ti / Pt / Au. The thickness of each of the p-side pad electrode 36 and the n-side pad electrode 38 is, for example, 100 nm or more, 200 nm or more, or 400 nm or more, and, for example, 1000 nm or less, 800 nm or less, or 600 nm or less.

[0038] The p-side pad electrode 36 is in contact with the upper surface 30e of the p-side contact electrode 30 at the p-side opening 34p and is electrically connected to the p-side contact electrode 30. The p-side pad electrode 36 overlaps the protective layer 34 outside the p-side opening 34p. The n-side pad electrode 38 is in contact with the upper surface 32e of the n-side contact electrode 32 at the n-side opening 34n and is electrically connected to the n-side contact electrode 32. The n-side pad electrode 38 overlaps the protective layer 34 outside the n-side opening 34n.

[0039] Next, a method for manufacturing the semiconductor light emitting device 10 according to the embodiment will be described. Figures 2 to 8 schematically show the manufacturing process for the semiconductor light emitting device 10 according to the embodiment. First, in Figure 2, a base layer 22, an n-type semiconductor layer 24, an active layer 26, and a p-type semiconductor layer 28 are formed in this order on the first main surface 20a of the substrate 20.

[0040] The substrate 20 is, for example, a patterned sapphire substrate. The base layer 22 includes, for example, an HT-AlN layer and an undoped AlGaN layer. The n-type semiconductor layer 24, the active layer 26, and the p-type semiconductor layer 28 are semiconductor layers made of an AlGaN-based semiconductor material, an AlN-based semiconductor material, or a GaN-based semiconductor material, and can be formed using a well-known epitaxial growth method such as metal organic vapor phase epitaxy (MOVPE) or molecular beam epitaxy (MBE).

[0041] 2, a mask 70 is formed on the upper surface 28a of the p-type semiconductor layer 28 using, for example, known lithography techniques. With the mask 70 formed, the p-type semiconductor layer 28 and the active layer 26 in areas not overlapping with the mask 70 are removed by dry etching or the like to expose the second upper surface 24b of the n-type semiconductor layer 24. This etching process forms the second upper surface 24b of the n-type semiconductor layer 24. Thereafter, the mask 70 is removed.

[0042] 3, a first resist 72 having a first opening 72a located in the upper surface 28a of the p-type semiconductor layer 28 is formed. The first resist 72 can be formed using known lithography techniques. The first resist 72 has an overhang 72b protruding toward the first opening 72a, and an undercut-shaped gap 72c is formed between the upper surface 28a of the p-type semiconductor layer 28 and the overhang 72b. Therefore, a lower opening range W4 in which the upper surface 28a of the p-type semiconductor layer 28 is exposed by the first opening 72a is larger than an upper opening range W3 defined by the overhang 72b.

[0043] Next, a material containing a first element is deposited by vapor deposition on the first resist 72 to form a first electrode layer 30a in contact with the upper surface 28a of the p-type semiconductor layer 28 within the first opening 72a. The first range W1 in which the first electrode layer 30a is formed is equivalent to the upper opening range W3 defined by the overhanging portion 72b. This is because the deposited material passes through the first opening 72a almost vertically and does not flow into the gap 72c at the back of the overhanging portion 72b.

[0044] 4, a material containing the first element is deposited by sputtering on the first resist 72 to form a second electrode layer 30b in contact with the first electrode layer 30a within the first opening 72a. The second area W2 where the second electrode layer 30b is formed is wider than the upper opening area W3 and narrower than the lower opening area W4. This is because the sputtered material contains a component that passes obliquely through the first opening 72a and can therefore wrap around into the gap 72c at the back of the overhanging portion 72b.

[0045] Next, after removing the first resist 72, the first electrode layer 30a and the second electrode layer 30b are annealed to form the p-side contact electrode 30. The annealing temperature for the p-side contact electrode 30 is, for example, 500°C or higher or 550°C or higher, and, for example, 650°C or lower or 625°C or lower. By annealing the p-side contact electrode 30, the contact resistance of the p-side contact electrode 30 is reduced to 1×10 in the first region W1 where the first electrode layer 30a is formed. -2 Ω cm2 or less (e.g., 1×10 -3 Ω cm 2 (See below).

[0046] 5, a second resist 74 is formed having a second opening 74a located on the second upper surface 24b of the n-type semiconductor layer 24. The second resist 74 can be formed using a known lithography technique, similar to the first resist 72. The second resist 74 has an overhanging portion 74b that protrudes toward the second opening 74a, and an undercut-shaped gap 74c is provided between the second upper surface 24b of the n-type semiconductor layer 24 and the overhanging portion 74b.

[0047] Next, an electrode layer is deposited by sputtering on the second resist 74, and the first Ti layer 32a, Al layer 32b, second Ti layer 32c, and TiN layer 32d are formed in this order on the second upper surface 24b of the n-type semiconductor layer 24 in the second opening 74a. Next, after removing the second resist 74, the first Ti layer 32a, Al layer 32b, second Ti layer 32c, and TiN layer 32d are annealed to form the n-side contact electrode 32.

[0048] 6, a mask 76 is formed on the n-type semiconductor layer 24, the active layer 26, the p-type semiconductor layer 28, the p-side contact electrode 30, and the n-side contact electrode 32 using, for example, known lithography techniques. With the mask 76 formed, the outer periphery of the n-type semiconductor layer 24 in an area not overlapping with the mask 76 is removed by dry etching or the like to expose the upper surface 22a of the base layer 22. This etching process forms the side surface 24c of the n-type semiconductor layer 24. Thereafter, the mask 76 is removed.

[0049] 7, a protective layer 34 is formed to cover the entire upper surface of the device. The protective layer 34 can be formed, for example, by using a plasma-enhanced chemical vapor deposition (PECVD) method. The protective layer 34 is formed to be in contact with and cover the upper surface 22a of the base layer 22, the second upper surface 24b and side surface 24c of the n-type semiconductor layer 24, the side surface of the active layer 26, the upper surface 28a and side surface of the p-type semiconductor layer 28, the p-side contact electrode 30, and the n-side contact electrode 32.

[0050] 8, a mask 78 is formed on the protective layer 34 using, for example, a known lithography technique, and the protective layer 34 in the area not overlapping with the mask 78 is removed by dry etching or the like. By removing the protective layer 34 on the p-side contact electrode 30, a p-side opening 34p is formed, exposing the upper surface 30e of the p-side contact electrode 30. By removing the protective layer 34 on the n-side contact electrode 32, an n-side opening 34n is formed, exposing the upper surface 32e of the n-side contact electrode 32. Furthermore, by removing the outer periphery of the protective layer 34, the upper surface 22a of the base layer 22 is exposed. Thereafter, the mask 78 is removed.

[0051] 1, a p-side pad electrode 36 is formed in the p-side opening 34p to connect to the p-side contact electrode 30, and an n-side pad electrode 38 is formed in the n-side opening 34n to connect to the n-side contact electrode 32. The p-side pad electrode 36 and the n-side pad electrode 38 can be formed simultaneously using known lithography techniques, but they may also be formed separately.

[0052] Through the above steps, the semiconductor light emitting device 10 shown in FIG. 1 is completed.

[0053] According to the present embodiment, the characteristics of the p-side contact electrode 30 can be improved by forming the first electrode layer 30a by vapor deposition and the second electrode layer 30b by sputtering. For example, the contact resistance of the p-side contact electrode 30 can be reduced by approximately 80% compared to when the first electrode layer 30a is formed by sputtering. Furthermore, the specific resistance of the p-side contact electrode 30 can be reduced compared to when the second electrode layer 30b is formed by vapor deposition. This improves the characteristics of the p-side contact electrode 30.

[0054] The present invention has been described above based on the embodiments. It will be understood by those skilled in the art that the present invention is not limited to the above-described embodiments, and that various design changes and modifications are possible, and that such modifications are also within the scope of the present invention.

[0055] Several aspects of the present invention will now be described.

[0056] A first aspect of the present invention is a method for manufacturing a semiconductor light-emitting device, comprising the steps of: forming an active layer made of an AlGaN-based semiconductor material on an n-type semiconductor layer made of an n-type AlGaN-based semiconductor material; forming a p-type semiconductor layer on the active layer; forming a first electrode layer by vapor deposition to be in contact with an upper surface of the p-type semiconductor layer and containing a first element; forming a second electrode layer by sputtering to be in contact with the first electrode layer and containing the first element; and annealing the first electrode layer and the second electrode layer to form a p-side contact electrode. According to the first aspect, the first electrode layer and the second electrode layer contain the same first element, and by forming the first electrode layer in contact with the p-type semiconductor layer by vapor deposition and forming the second electrode layer on the first electrode layer by sputtering, the contact resistance and resistivity of the p-side contact electrode can be improved.

[0057] In a second aspect of the present invention, there is provided a method for manufacturing a semiconductor light-emitting device according to the first aspect, wherein the first element is a metal element. According to the second aspect, the contact resistance and resistivity of the p-side contact electrode can be improved by evaporating a metal element that contacts the p-side contact electrode and then sputtering a metal element thereon.

[0058] A third aspect of the present invention is the method for manufacturing a semiconductor light-emitting device according to the first or second aspect, wherein the second electrode layer further contains a second element different from the first element. According to the third aspect, the second electrode layer containing the first element and the second element can be formed by sputtering, and the resistivity of the p-side contact electrode can be improved.

[0059] A fourth aspect of the present invention is the method for manufacturing a semiconductor light-emitting device according to any one of the first to third aspects, wherein the second electrode layer contains an oxide of the first element. According to the fourth aspect, the second electrode layer containing the oxide of the first element can be formed by sputtering, and the resistivity of the p-side contact electrode can be improved.

[0060] A fifth aspect of the present invention is the method for manufacturing a semiconductor light-emitting device according to the second aspect, wherein the first element is a platinum group element. According to the fifth aspect, by using a platinum group element for the p-side contact electrode, the ultraviolet light reflectance of the p-side contact electrode can be improved, and the light extraction efficiency of the semiconductor light-emitting device can be improved.

[0061] A sixth aspect of the present invention is the method for manufacturing a semiconductor light-emitting element according to any one of the first to fifth aspects, wherein the thickness of the first electrode layer is 10% or less of the thickness of the second electrode layer. By reducing the thickness of the first electrode layer, the contact resistance and resistivity of the p-side contact electrode can be improved. [Explanation of symbols]

[0062] 10...semiconductor light-emitting element, 24...n-type semiconductor layer, 26...active layer, 28...p-type semiconductor layer, 28a...upper surface, 30...p-side contact electrode, 30a...first electrode layer, 30b...second electrode layer, 32...n-side contact electrode, 34...protective layer.

Claims

1. forming an active layer made of an AlGaN-based semiconductor material on an n-type semiconductor layer made of an n-type AlGaN-based semiconductor material; forming a p-type semiconductor layer on the active layer; forming a first electrode layer by vapor deposition in contact with an upper surface of the p-type semiconductor layer and including a first element; forming a second electrode layer by sputtering, the second electrode layer being in contact with the first electrode layer and containing the first element; and annealing the first electrode layer and the second electrode layer to form a p-side contact electrode. A method for manufacturing a semiconductor light-emitting device.

2. The first element is a metal element. The method for manufacturing the semiconductor light emitting device according to claim 1 .

3. the second electrode layer further includes a second element different from the first element; The method for manufacturing the semiconductor light emitting device according to claim 1 .

4. the second electrode layer contains an oxide of the first element; The method for manufacturing a semiconductor light emitting device according to claim 2 .

5. The first element is a platinum group element. The method for manufacturing a semiconductor light emitting device according to claim 2 .

6. The thickness of the first electrode layer is 10% or less of the thickness of the second electrode layer. The method for manufacturing the semiconductor light-emitting device according to claim 1 .

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