Light receiving element

Abstract

To provide a light receiving element capable of reducing a dark current and relaxing electric field concentration.SOLUTION: A first semiconductor layer, a light absorbing layer, a second semiconductor layer, and a third semiconductor layer that are sequentially stacked, a first electrode electrically connected to the first semiconductor layer, and a second electrode electrically connected to the third semiconductor layer, the third semiconductor layer forming a first mesa protruding from the second semiconductor layer, the first semiconductor layer having a first conductivity type, the second semiconductor layer and the third semiconductor layer having a second conductivity type, An impurity concentration in the third semiconductor layer is higher than an impurity concentration in the second semiconductor layer, and the impurity concentration in the second semiconductor layer is low in a portion close to the light absorbing layer and is high in a portion close to the third semiconductor layer.SELECTED DRAWING: Figure 2A

Description

[Technical Field]

[0001] The present disclosure relates to a light receiving element. [Background technology]

[0002] In a light receiving element, a pin (positive-intrinsic-negative) junction is formed by stacking an n-type semiconductor layer, an undoped light absorbing layer, and a p-type semiconductor layer (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2008 / 090733 Summary of the Invention [Problem to be solved by the invention]

[0004] Because layers with different impurity concentrations are joined, carriers diffuse between the semiconductor layers due to the concentration difference. Highly doped contact layers are sometimes formed into a mesa shape. The junction interface between the semiconductor layers with different impurity concentrations is exposed on the side of the mesa. Because the concentration difference between the joined semiconductor layers is large, carrier diffusion increases the dark current on the side of the mesa. Furthermore, the built-in potential increases as the carriers diffuse, causing the electric field to concentrate at the junction interface. Edge breakdown is likely to occur. Therefore, the objective is to provide a photodiode that can reduce dark current and mitigate electric field concentration. [Means for solving the problem]

[0005] The light-receiving element according to the present disclosure comprises a first semiconductor layer, a light-absorbing layer, a second semiconductor layer, and a third semiconductor layer stacked in this order, a first electrode electrically connected to the first semiconductor layer, and a second electrode electrically connected to the third semiconductor layer, wherein the third semiconductor layer forms a first mesa protruding from the second semiconductor layer, the first semiconductor layer has a first conductivity type, the second semiconductor layer and the third semiconductor layer have a second conductivity type, the impurity concentration in the third semiconductor layer is higher than the impurity concentration in the second semiconductor layer, and the impurity concentration in the second semiconductor layer is low in a portion close to the light-absorbing layer and high in a portion close to the third semiconductor layer. [Effects of the Invention]

[0006] According to the present disclosure, it is possible to provide a light-receiving element capable of reducing dark current and alleviating electric field concentration. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a plan view illustrating a light receiving element according to the embodiment. [Figure 2A] FIG. 2A is a cross-sectional view illustrating an example of a light receiving element. [Figure 2B] FIG. 2B is a cross-sectional view illustrating an example of a light receiving element. [Figure 3] FIG. 3 is a cross-sectional view illustrating a light-receiving element according to a comparative example. [Figure 4A] FIG. 4A is a schematic view illustrating the impurity concentrations. [Figure 4B] FIG. 4B is a schematic diagram illustrating energy levels. [Figure 5A] FIG. 5A is a schematic view illustrating the impurity concentrations. [Figure 5B] FIG. 5B is a schematic diagram illustrating energy levels. [Figure 6A] FIG. 6A is a cross-sectional view illustrating a light-receiving element according to the second embodiment. [Figure 6B] FIG. 6B is a schematic view illustrating the impurity concentrations. [Figure 7A]FIG. 7A is a cross-sectional view illustrating a light-receiving element according to the third embodiment. [Figure 7B] FIG. 7B is a schematic view illustrating the impurity concentrations. [Figure 8A] FIG. 8A is a cross-sectional view illustrating a light-receiving element according to the fourth embodiment. [Figure 8B] FIG. 8B is a schematic view illustrating the impurity concentrations. DETAILED DESCRIPTION OF THE INVENTION

[0008] [Description of the embodiments of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described.

[0009] One aspect of the present disclosure provides a light-receiving element (1) comprising a first semiconductor layer, a light-absorbing layer, a second semiconductor layer, and a third semiconductor layer stacked in order, a first electrode electrically connected to the first semiconductor layer, and a second electrode electrically connected to the third semiconductor layer, wherein the third semiconductor layer forms a first mesa protruding from the second semiconductor layer, the first semiconductor layer having a first conductivity type, the second semiconductor layer and the third semiconductor layer having a second conductivity type, an impurity concentration in the third semiconductor layer being higher than an impurity concentration in the second semiconductor layer, and an impurity concentration in the second semiconductor layer being lower in a portion closer to the light-absorbing layer and higher in a portion closer to the third semiconductor layer. The impurity concentration difference between the second semiconductor layer and the second semiconductor layer is reduced. The diffusion of carriers between the layers is alleviated. Dark current can be reduced at a junction interface exposed on a side surface of the first mesa. The built-in potential associated with carrier diffusion is reduced. Electric field concentration at the junction interface can be alleviated. (2) In the above (1), the second semiconductor layer may include a plurality of semiconductor layers stacked between the light absorbing layer and the third semiconductor layer, and the impurity concentration of a layer of the plurality of semiconductor layers that is closer to the third semiconductor layer may be higher than the impurity concentration of a layer of the plurality of semiconductor layers that is closer to the light absorbing layer. The difference in impurity concentration between the second semiconductor layers is reduced. Dark current can be reduced. Electric field concentration can be alleviated. (3) In the above (1) or (2), the second semiconductor layer may include a fourth semiconductor layer, a fifth semiconductor layer, and a sixth semiconductor layer, and the light absorption layer, the fourth semiconductor layer, the fifth semiconductor layer, the sixth semiconductor layer, and the third semiconductor layer may be stacked in this order, and the impurity concentration in the fifth semiconductor layer may be higher than the impurity concentration in the fourth semiconductor layer, and the impurity concentration in the sixth semiconductor layer may be higher than the impurity concentration in the fifth semiconductor layer. The impurity concentration decreases between the second semiconductor layer and the sixth semiconductor layer. The impurity concentration also decreases from the sixth semiconductor layer to the fourth semiconductor layer. Dark current can be reduced. Electric field concentration can be alleviated. (4) In the above (2) or (3), the semiconductor layers included in the second semiconductor layer may be formed of the same material, which makes it difficult for distortion of the crystal lattice to occur. (5) In any of the above (1) to (4), the second semiconductor layer may be formed of a material different from that of the third semiconductor layer. The second semiconductor layer and the third semiconductor layer form a heterojunction. This can reduce dark current and alleviate electric field concentration at the heterojunction interface. (6) In any one of the above (1) to (5), the first mesa formed by the second semiconductor layer may have a ring-shaped planar shape. At the ring-shaped junction interface, dark current can be reduced and electric field concentration can be alleviated. (7) In any one of the above (1) to (6), the light absorption layer and the second semiconductor layer may form a second mesa. A depletion region extends to the second mesa. The depletion of the third semiconductor layer reduces the capacitance. (8) In any of the above (1) to (7), the first semiconductor layer may have n-type conductivity, and the second semiconductor layer and the third semiconductor layer may have p-type conductivity. The impurity concentration is reduced between the p-type third semiconductor layer and the second semiconductor layer, thereby mitigating carrier diffusion. (9) In any one of (1) to (8) above, the light-receiving element may be an avalanche photodiode and may include a multiplication layer stacked between the first semiconductor layer and the third semiconductor layer, which can alleviate electric field concentration at the junction interface between the second semiconductor layer and the third semiconductor layer and prevent edge breakdown.

[0010] [Details of the embodiments of the present disclosure] Specific examples of light-receiving elements according to embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0011] First Embodiment Fig. 1 is a plan view illustrating a light receiving element 100 according to an embodiment. Fig. 2A is a cross-sectional view illustrating the light receiving element 100, taken along line AA in Fig. 1. The light receiving element 100 is an avalanche photodiode (APD) and is used, for example, in LiDAR (Light Detection and Ranging).

[0012] As shown in FIG. 1, the light-receiving element 100 has a mesa 10 (first mesa), a mesa 13 (second mesa), an electrode 12 (first electrode), an electrode 14 (second electrode), and a buffer layer 20 (first semiconductor layer). The top surface of the buffer layer 20 is parallel to the XY plane. Two sides of the buffer layer 20 are parallel to the X axis. The other two sides are parallel to the Y axis. The Z axis is the thickness direction of the buffer layer 20. The X axis, Y axis, and Z axis are perpendicular to each other. In FIG. 1, the electrodes 12 and 14 are indicated by diagonal lines.

[0013] In a plan view, mesa 10, electrode 12, and electrode 14 have an annular (ring-shaped) shape. Mesa 13 is circular. In the XY plane, mesa 10 is located inside mesa 13. Electrode 14 is provided on mesa 10. The portion inside electrode 14 functions as light-receiving region 11. The diameter D1 of light-receiving region 11 (inner diameter of mesa 10) is, for example, 200 μm. The diameter D2 of mesa 13 is larger than the inner diameter D1 of mesa 10 and is, for example, 300 μm. Electrode 12 is provided outside mesa 10 and mesa 13 and surrounds mesa 13.

[0014] As shown in FIG. 2A , the photodetector 100 includes a buffer layer 20, a multiplication layer 22, a control layer 24, a light absorption layer 26, a window layer 30 (second semiconductor layer), and a contact layer 32 (third semiconductor layer), and may include other semiconductor layers. A semiconductor substrate (not shown) may be provided below the buffer layer 20. In the XY plane, the central portion of the buffer layer 20 protrudes in the Z-axis direction beyond the outer periphery of the buffer layer 20. The control layer 24, the light absorption layer 26, and the window layer 30 are stacked in this order on the protruding portion of the buffer layer 20. The mesa 13 includes the buffer layer 20, the control layer 24, the light absorption layer 26, and the window layer 30.

[0015] The window layer 30 includes three semiconductor layers: 30-1 (fourth semiconductor layer), 30-2 (fifth semiconductor layer), and 30-3 (sixth semiconductor layer). The semiconductor layers 30-1, 30-2, and 30-3 are stacked in this order between the light absorbing layer 26 and the contact layer 32. The semiconductor layer 30-1 is in contact with the light absorbing layer 26. The semiconductor layer 30-2 is in contact with the semiconductor layer 30-1. The semiconductor layer 30-3 is in contact with the contact layer 32, forming a heterojunction.

[0016] A contact layer 32 is provided on the upper surface of the semiconductor layer 30-3. The contact layer 32 is annular and protrudes in the Z-axis direction beyond the semiconductor layer 30-3 to form a mesa 10. The side and upper surfaces of the mesa 10 are the contact layer 32. The side surfaces of the mesa 13 are formed by layers from the multiplication layer 22 to the semiconductor layer 30-3. The upper surface of the mesa 13 is formed by the semiconductor layer 30-3.

[0017] The upper surface of the buffer layer 20, the side and upper surface of the mesa 13, and the side surface of the mesa 10 are covered with an insulating film 34. The insulating film 34 is provided on the upper surface of the mesa 10. The insulating film 34 has an opening at a position spaced apart from the mesa 13. An electrode 12 is provided in this opening. The insulating film 34 has an opening above the mesa 10. An electrode 14 is provided in this opening. The electrode 14 has a circular ring shape similar to that of the contact layer 32. The insulating film 34 is a passivation film and is made of an insulator such as silicon nitride (SiN). The electrodes 12 and 14 are made of metal.

[0018] The buffer layer 20 has, for example, an n-type (first conductivity type) and is made of n+-type indium phosphide ((n+)-InP). The buffer layer 20 has a thickness of, for example, 1600 nm. The buffer layer 20 is doped with an impurity such as silicon (Si). The impurity concentration is, for example, 1.0×10 18 cm -3 The multiplication layer 22 is, for example, an undoped indium aluminum arsenide (i-In x Al 1-x The multiplication layer 22 has a thickness of, for example, 500 nm. The control layer 24 is made of, for example, p-type (second conductivity type) indium aluminum arsenide (p-In x Al 1-x The control layer 24 is made of As (x=0.52). The thickness of the control layer 24 is, for example, 100 nm. The control layer 24 is doped with an impurity such as zinc (Zn). The impurity concentration is, for example, 3.0×10 17 cm -3 is.

[0019] The light absorption layer 26 is, for example, undoped indium gallium arsenide (i-In x Ga 1-x The light absorbing layer 26 is made of As (x=0.53). The thickness of the light absorbing layer 26 is, for example, 1000 nm. An undoped semiconductor layer such as the light absorbing layer 26 is not intentionally doped with impurities, but may contain 1×10 15 cm -3 It may be doped with impurities of the order of magnitude.

[0020] The semiconductor layers 30-1, 30-2, and 30-3 of the window layer 30 are, for example, p-type In x Al 1-x The window layer 30 is made of As (x=0.52). These three layers are doped with, for example, zinc (Zn) or tellurium (Te). The thickness of each of the three layers is, for example, 200 nm. The band gap of the window layer 30 is wider than the band gap of the light absorption layer 26. The relative dielectric constant of the window layer 30 is lower than the relative dielectric constant of the light absorption layer 26.

[0021] The semiconductor layer 30-1 is p-type. The semiconductor layer 30-2 is p-type. The semiconductor layer 30-3 is p+ type. That is, the impurity concentration of the semiconductor layer 30-3 is higher than the impurity concentrations of the semiconductor layer 30-2 and the semiconductor layer 30-1, and is, for example, 1×10 18 cm -3 The impurity concentration of the semiconductor layer 30-2 is higher than the impurity concentration of the semiconductor layer 30-1, for example, 1×10 17 cm -3 The impurity concentration of the semiconductor layer 30-1 is, for example, 1×10 16 cm -3 is.

[0022] The contact layer 32 is, for example, (p+)-In x Ga 1-x The contact layer 32 is made of As (x=0.53). The thickness of the contact layer 32 is, for example, 200 nm. The concentration of Zn doped into the contact layer 32 is higher than the impurity concentration of the semiconductor layer 30-3, for example, 1×10 19 cm -3 The semiconductor layers of the light-receiving element 100 may be formed of compound semiconductors other than those mentioned above.

[0023] (Manufacturing method) For example, a buffer layer 20 is deposited on one surface of a semi-insulating semiconductor substrate by metal organic chemical vapor deposition (MOCVD). A multiplication layer 22, a control layer 24, a light absorption layer 26, a window layer 30, and a contact layer 32 are epitaxially grown in this order on the surface of the buffer layer 20 opposite the substrate. Impurities are added to the window layer 30 and other layers. The supply rate of the impurities is adjusted to control the impurity concentration.

[0024] The contact layer 32 is shaped into a ring-shaped mesa 10 by etching. The window layer 30, the light absorption layer 26, the control layer 24, the multiplication layer 22, and a portion of the buffer layer 20 are etched to form the mesa 13. The etching may be dry etching or wet etching. An insulating film 34 is formed by plasma CVD (Plasma Enhanced Chemical Vapor Deposition). Openings are formed in the insulating film 34 by etching in the portions covering the top surface of the mesa 10 and the buffer layer 20. The electrodes 12 and 14 are formed by vacuum deposition and lift-off. The photodetector 100 is formed.

[0025] The light receiving element 100 can detect light such as infrared light, for example, light with a wavelength of 1.55 μm. The operating voltage is, for example, 70 V. When using the light receiving element 100, a positive voltage is applied to the electrode 12 and a negative voltage is applied to the electrode 14.

[0026] FIG. 2B is a cross-sectional view illustrating the photodetector 100 when a reverse bias voltage is applied. FIG. 2B shows the light-receiving element 100 from the light-absorbing layer 26 to the contact layer 32. In response to the application of voltage, a depletion region 40 is generated in the mesa 13 and extends in the Z-axis direction, for example, halfway through the semiconductor layer 30-3, but does not reach the junction interface between the semiconductor layer 30-3 and the contact layer 32. The depletion of the window layer 30 reduces the element capacitance. This allows the operating bandwidth of the photodetector 100 to be broadened.

[0027] Light incident from the light-receiving region 11 is absorbed by the light absorption layer 26. By absorbing light, the light absorption layer 26 generates carriers (electron-hole pairs). The electric field applied to the depletion region 40 causes the carriers to move and are output as photocurrent. The control layer 24 functions as an electric field control layer. A high electric field is applied to the multiplication layer 22. As electrons collide with atoms in the multiplication layer 22, more carriers are generated. This improves sensitivity.

[0028] (Comparative Example) 3 is a cross-sectional view illustrating a light-receiving element 110 according to a comparative example. One window layer 30 is provided between the light absorption layer 26 and the contact layer 32. The window layer 30 is made of, for example, i-InAlAs. The impurity concentration is, for example, 1×10 15 cm -3 The thickness of the window layer 30 is, for example, 600 nm. The other configurations are the same as those of the light-receiving element 100. Although not shown, in the comparative example, the depletion region extends to the junction interface between the window layer 30 and the contact layer 32.

[0029] (Impurity concentration) 4A and 5A are schematic diagrams illustrating impurity concentrations. The horizontal axis represents the depth of the light receiving element in the Z-axis direction, from left to right, from the contact layer 32 to the light absorption layer 26. The vertical axis represents the impurity concentration in the layer.

[0030] 4A shows impurity concentrations in the first embodiment. In FIG. 4A, the impurity concentrations of the semiconductor layer 30-1, the semiconductor layer 30-2, the semiconductor layer 30-3, and the contact layer 32 are denoted as C1, C2, C3, and C0, respectively. These concentrations are, for example, the values ​​described above. The impurity concentration of the light absorption layer 26 is denoted as D. The impurity concentration D is, for example, 1×10 15 cm -3 It is on the order of or less.

[0031] Among the layers in FIG. 4A , the contact layer 32 has the highest impurity concentration C0. The impurity concentration in the window layer 30 varies stepwise depending on the position, being higher closer to the contact layer 32 and lower farther away from the contact layer 32. The impurity concentration C1 of the semiconductor layer 30-1 is higher than the impurity concentration of the light absorption layer 26. The impurity concentration C2 of the semiconductor layer 30-2 is higher than the impurity concentration C1 of the semiconductor layer 30-1, for example, about 10 times C1. The impurity concentration C3 of the semiconductor layer 30-3 is higher than the impurity concentration C2 of the semiconductor layer 30-2, for example, about 10 times C2. The impurity concentration C0 of the contact layer 32 is higher than the impurity concentration C3 of the semiconductor layer 30-3, for example, about 10 times C3.

[0032] 5A shows the impurity concentrations in a comparative example. The window layer 30 and the light absorption layer 26 are undoped layers and have similar impurity concentrations D. The impurity concentration C0 of the contact layer 32 is more than 10,000 times higher than the impurity concentration D of the window layer 30 and the light absorption layer 26.

[0033] (Career) 4B and 5B are schematic diagrams illustrating energy levels. Ev represents the energy of the valence band. Ec represents the energy of the conduction band. The contact layer 32 and the window layer 30 are p-type and contain holes as majority carriers. Holes are represented by + symbols in FIGS. 4B and 5B. The number of + symbols does not precisely represent the carrier concentration, but layers with a higher number of + symbols have a higher carrier concentration than layers with a lower number of + symbols.

[0034] 4B shows energy levels in the first embodiment. From left to right in FIG. 4B, the layers from contact layer 32 to semiconductor layer 30-1 are shown. The carrier concentration of contact layer 32 is higher than that of semiconductor layer 30-3. The carrier concentration of semiconductor layer 30-3 is higher than that of semiconductor layer 30-2. The carrier concentration of semiconductor layer 30-2 is higher than that of semiconductor layer 30-1.

[0035] FIG. 5B shows the energy levels in the comparative example. The carrier density of the contact layer 32 is higher than that of the window layer 30. The difference in carrier concentration between the contact layer 32 and the window layer 30 in FIG. 5B is greater than the difference in carrier concentration between the adjacent layers in the example of FIG. 4B. Because of the large change in carrier concentration, carriers diffuse rapidly from the contact layer 32 to the window layer 30. This carrier diffusion increases the dark current. As shown in FIG. 3, in the comparative example, the contact layer 32, which forms the mesa 10, and the window layer 30 are bonded together. The bonded interface is exposed on the side of the mesa 10. The large difference in carrier concentration at the exposed bonded interface increases the dark current.

[0036] As shown in FIG. 5B, carrier diffusion increases the energy difference between the contact layer 32 and the window layer 30, increasing the built-in potential. This generates a high electric field near the junction interface. The depletion region expands into the i-type window layer 30 and reaches the junction interface with the contact layer 32. A high electric field is applied to the junction interface between the contact layer 32 and the window layer 30. The electric field concentration makes it easy for edge breakdown to occur at this interface.

[0037] 4B, according to the first embodiment, the difference in carrier concentration between adjacent layers from the contact layer 32 to the semiconductor layer 30-1 is smaller than in the comparative example. Carrier diffusion between the layers is alleviated. As a result of the alleviated carrier diffusion, the dark current is reduced and the built-in potential is smaller than in the comparative example.

[0038] According to the first embodiment, as shown in FIG. 2A, a light absorption layer 26, a window layer 30, and a contact layer 32 are stacked in this order. The contact layer 32 is a highly doped layer and forms a mesa 10. The window layer 30 includes semiconductor layers 30-1, 30-2, and 30-3. The impurity concentrations of the three semiconductor layers of the window layer 30 are higher the closer to the contact layer 32 and lower the farther from the contact layer 32. That is, the impurity concentration of the semiconductor layer 30-3 is lower than that of the contact layer 32 but higher than that of the semiconductor layer 30-2. The impurity concentration of the semiconductor layer 30-2 is higher than that of the semiconductor layer 30-1. The difference in impurity concentration between the contact layer 32 and the semiconductor layer 30-3 is smaller than that between the contact layer 32 and the window layer 30 in the comparative example. Carrier diffusion is mitigated. Dark current can be reduced at the junction interface between the contact layer 32 and the semiconductor layer 30-3 exposed on the side of the mesa 10.

[0039] Since the concentration difference between the contact layer 32 and the semiconductor layer 30-3 is small, the built-in potential due to carrier diffusion is also small. Electric field concentration at the junction interface between the contact layer 32 and the semiconductor layer 30-3 can be alleviated. Edge breakdown can be prevented.

[0040] The concentration difference between adjacent layers from contact layer 32 to semiconductor layer 30-1 in the first embodiment is also smaller than the concentration difference between contact layer 32 and window layer 30 in the comparative example. Carrier diffusion is also alleviated between semiconductor layer 30-3 and semiconductor layer 30-2, and between semiconductor layer 30-2 and semiconductor layer 30-1. Dark current can be reduced.

[0041] The impurity concentration of the contact layer 32 is, for example, about 10 times the impurity concentration of the semiconductor layer 30-3. The impurity concentration of the semiconductor layer 30-3 is, for example, about 10 times the impurity concentration of the semiconductor layer 30-2. The impurity concentration of the semiconductor layer 30-2 is, for example, about 10 times the impurity concentration of the semiconductor layer 30-1. The target concentration values ​​in the manufacturing process may be set to different values ​​in a ratio of 10 times for each layer, as described above. The ratio of impurity concentrations between adjacent layers may be 10 times or less, for example, 8 times or less, or 5 times or less.

[0042] The buffer layer 20 has n-type conductivity. The window layer 30 and contact layer 32 have p-type conductivity. The light-absorbing layer 26 is i-type. A pin junction is formed between the contact layer 32 and the buffer layer 20, and the light-receiving element 100 functions as a photodiode. The impurity concentration decreases between the p-type window layer 30 and the contact layer 32, mitigating carrier diffusion. The contact layer 32 and window layer 30 may be n-type. An n-type semiconductor layer may be provided on the opposite side of the light-absorbing layer 26 from the window layer 30.

[0043] The semiconductor layers 30-1, 30-2, and 30-3 included in the window layer 30 are made of the same material, for example, InAlAs, which makes it difficult for distortion of the crystal lattice to occur.

[0044] The contact layer 32 is formed of a material different from that of the window layer 30, for example, InGaAs. The junction between the contact layer 32 and the window layer 30 is a heterojunction. The heterojunction interface is exposed on the side surface of the mesa 10. According to the first embodiment, it is possible to reduce dark current at the heterojunction interface. By mitigating the electric field concentration at the heterojunction interface, it is possible to effectively prevent edge breakdown.

[0045] As shown in FIG. 1, the mesa 10 has a ring-shaped planar shape. The junction interface between the contact layer 32 and the window layer 30 is ring-shaped. Dark current can be reduced at the ring-shaped junction interface. Edge breakdown can be prevented by mitigating the electric field concentration at the junction interface. The mesa 10 may include the contact layer 32 and a portion of the window layer 30. The window layer 30 is etched into a ring shape, and the contact layer 32 is stacked on this ring-shaped portion.

[0046] The buffer layer 20, the multiplication layer 22, the control layer 24, the light absorption layer 26, and the window layer 30 form a mesa 13. The mesa 10 is located above the mesa 13 and protrudes from the mesa 13 in the Z-axis direction. As shown in FIG. 2B, a depletion region 40 expands into the mesa 13 upon application of a voltage. Depletion of the window layer 30 and other layers reduces the device capacitance. The impurity concentration of the window layer 30 increases the closer it is to the contact layer 32. As shown in FIG. 2B, the depletion region 40 expands in the Z-axis direction, for example, halfway through the semiconductor layer 30-3, but does not reach the junction interface between the semiconductor layer 30-3 and the contact layer 32. This reduces the electric field applied to the junction interface.

[0047] The light receiving element 100 is an avalanche photodiode, and a voltage of, for example, several tens of volts is applied to it. Since electric field concentration is alleviated, edge breakdown can be prevented. The first embodiment may be applied to photodiodes other than avalanche photodiodes.

[0048] Second Embodiment 6A is a cross-sectional view illustrating a light-receiving element 200 according to the second embodiment. Descriptions of the same components as those in the first embodiment will be omitted. As shown in FIG. 6A, the window layer 30 has two semiconductor layers 30-1 and 30-2. The semiconductor layers 30-1 and 30-2 are stacked in this order between the light absorption layer 26 and the contact layer 32.

[0049] 6B is a schematic diagram illustrating impurity concentrations. The impurity concentration C0 of the contact layer 32 is higher than the impurity concentration C2 of the semiconductor layer 30-2, e.g., 10 times higher than C2. The impurity concentration C2 of the semiconductor layer 30-2 is higher than the impurity concentration C1 of the semiconductor layer 30-1, e.g., 10 times higher than C1.

[0050] According to the second embodiment, the window layer 30 has two semiconductor layers, 30-1 and 30-2. The semiconductor layer 30-1 is stacked on the light absorbing layer 26. The semiconductor layer 30-2 is stacked on the semiconductor layer 30-1 and has a higher impurity concentration than the semiconductor layer 30-1. The concentration difference between the layers from the contact layer 32 to the light absorbing layer 26 is reduced, thereby reducing dark current. Electric field concentration at the heterojunction interface between the semiconductor layer 30-2 and the contact layer 32 can be alleviated.

[0051] Third Embodiment 7A is a cross-sectional view illustrating a light-receiving element 300 according to the third embodiment. Descriptions of the same configurations as those in the first or second embodiment will be omitted. As shown in FIG. 7A, the window layer 30 has N semiconductor layers 30-1 to 30-N, where N is a natural number, for example, 4 or greater. The semiconductor layers 30-1 to 30-N are stacked in this order between the light absorption layer 26 and the contact layer 32.

[0052] 7B is a schematic diagram illustrating impurity concentrations. Among the semiconductor layers included in the window layer 30, the semiconductor layer 30-N has the highest impurity concentration Cn. Among the semiconductor layers included in the window layer 30, the semiconductor layer 30-1 has the lowest impurity concentration C1. The impurity concentrations decrease stepwise from the semiconductor layer 30-N to the semiconductor layer 30-1. That is, the impurity concentration of the semiconductor layer closer to the contact layer 32 is higher than the impurity concentration of the semiconductor layer closer to the light absorption layer 26. The impurity concentration C0 of the contact layer 32 is higher than the impurity concentration Cn of the semiconductor layer 30-N.

[0053] According to the third embodiment, the window layer 30 has N semiconductor layers. Of the N semiconductor layers, the layers closer to the light absorption layer 26 have a low impurity concentration. The layers closer to the contact layer 32 have a high impurity concentration. The concentration difference between the contact layer 32 and the window layer 30 and among the multiple semiconductor layers in the window layer 30 is reduced. This reduces dark current. Electric field concentration at the heterojunction interface between the semiconductor layer 30-N and the contact layer 32 can be alleviated.

[0054] The ratio of impurity concentrations between adjacent semiconductor layers in the window layer 30 is, for example, about 10 times, but may also be 2 times, 5 times, 7 times, 8 times, etc. The N semiconductor layers in the window layer 30 may include semiconductor layers having approximately the same impurity concentration. It is sufficient that the impurity concentration decreases from the semiconductor layer 30-N to the semiconductor layer 30-1.

[0055] <Fourth embodiment> 8A is a cross-sectional view illustrating a light-receiving element 400 according to the fourth embodiment. Descriptions of the same configuration as in any of the first to third embodiments will be omitted. As shown in FIG. 8A, a light absorption layer 26, a window layer 30, and a contact layer 32 are stacked in this order. The window layer 30 has p-type conductivity.

[0056] FIG. 8B is a schematic diagram illustrating the impurity concentration. Although the window layer 30 is a single layer, the impurity concentration in the window layer 30 is not constant. The impurity concentration is high in the portion close to the contact layer 32 and low in the portion close to the light absorption layer 26. For example, the impurity concentration of the window layer 30 varies continuously with the position in the Z-axis direction. The impurity concentration of the window layer 30 has a maximum value at the junction between the window layer 30 and the contact layer 32. The maximum value is, for example, 1×10 18 cm -3 The impurity concentration of the window layer 30 has a minimum value at the interface between the window layer 30 and the light absorption layer 26. The minimum value is, for example, 1×10 16 cm -3 is.

[0057] According to the fourth embodiment, the portion of the window layer 30 close to the light absorption layer 26 has a low impurity concentration. The portion close to the contact layer 32 has a high impurity concentration. Since the concentration difference between the contact layer 32 and the window layer 30 is small, dark current can be reduced. Electric field concentration at the heterojunction interface between the window layer 30 and the contact layer 32 can be alleviated.

[0058] The impurity concentration of the window layer 30 may vary linearly or nonlinearly with respect to position. The third embodiment and the fourth embodiment may be combined. The window layer 30 has a plurality of semiconductor layers 30-1 to 30-N. The impurity concentration of any of the N semiconductor layers may vary continuously.

[0059] Although the embodiments of the present disclosure have been described in detail above, the present disclosure is not limited to such specific embodiments, and various modifications and variations are possible within the scope of the gist of the present disclosure as described in the claims. [Explanation of symbols]

[0060] Mesa 10 and 13 11 Light receiving area 12, 14 electrodes 20 Buffer Layer 22 Multiplication layer 24 Control Layer 26 Light absorption layer 30 Window Layer 30-1, 30-2, 30-3, 30-N Semiconductor layer 32 Contact layer 34 insulating film 40 Depletion region 100, 110, 200, 300 Light receiving element

Claims

1. a first semiconductor layer, a light absorbing layer, a second semiconductor layer, and a third semiconductor layer stacked in this order; a first electrode electrically connected to the first semiconductor layer; a second electrode electrically connected to the third semiconductor layer, the third semiconductor layer forms a first mesa protruding from the second semiconductor layer; the first semiconductor layer has a first conductivity type; the second semiconductor layer and the third semiconductor layer have a second conductivity type; an impurity concentration in the third semiconductor layer is higher than an impurity concentration in the second semiconductor layer; A light-receiving element in which the impurity concentration in the second semiconductor layer is low in a portion close to the light absorption layer and high in a portion close to the third semiconductor layer.

2. the second semiconductor layer includes a plurality of semiconductor layers stacked between the light absorption layer and the third semiconductor layer, The light-receiving element according to claim 1 , wherein a layer of the plurality of semiconductor layers that is closer to the third semiconductor layer has a higher impurity concentration than a layer of the plurality of semiconductor layers that is closer to the light absorption layer.

3. the second semiconductor layer includes a fourth semiconductor layer, a fifth semiconductor layer, and a sixth semiconductor layer, the light absorption layer, the fourth semiconductor layer, the fifth semiconductor layer, the sixth semiconductor layer, and the third semiconductor layer are stacked in this order; an impurity concentration in the fifth semiconductor layer is higher than an impurity concentration in the fourth semiconductor layer; 3. The light-receiving element according to claim 1, wherein the sixth semiconductor layer has a higher impurity concentration than the fifth semiconductor layer.

4. The light-receiving element according to claim 2 , wherein the plurality of semiconductor layers included in the second semiconductor layer are formed of the same material.

5. 3. The light-receiving element according to claim 1, wherein the second semiconductor layer is formed of a material different from that of the third semiconductor layer.

6. 3. The light-receiving element according to claim 1, wherein the first mesa formed by the second semiconductor layer has a ring-shaped planar shape.

7. 3. The light-receiving element according to claim 1, wherein the light absorption layer and the second semiconductor layer form a second mesa.

8. the first semiconductor layer has n-type conductivity; 3. The light-receiving element according to claim 1, wherein the second semiconductor layer and the third semiconductor layer have p-type conductivity.

9. the light receiving element is an avalanche photodiode, 3. The light-receiving element according to claim 1, further comprising a multiplication layer laminated between the first semiconductor layer and the third semiconductor layer.

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