Semiconductor device

Abstract

To provide a semiconductor device capable of improving a breakdown voltage.SOLUTION: The semiconductor device includes an insulating layer 2 provided on a semiconductor substrate 1, a first resistor (R (5)) embedded in the insulating layer 2, and a second resistor (R (6)) embedded in the insulating layer 2 and connected in series to the first resistor (R (5)). And a first capacitor E11 comprising a first upper-electrode E12 electrically connected to one end of the first resistance (R (5)) and a first lower-electrode C1 formed in the insulating layer 2 and electrically connected to one end of the second resistance (R (6)), wherein the first lower-electrode E12 is electrically connected to the second resistance (R (6)) and is electrically connected to a reference electrode EG formed on the insulating layer 2.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a plurality of resistance elements. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2023 / 085026

[0004] [overview]

[0005] The present disclosure provides a semiconductor device capable of improving the breakdown voltage.

[0006] The semiconductor device according to the present disclosure comprises an insulating layer provided on a semiconductor substrate, a first resistor embedded in the insulating layer, a second resistor embedded in the insulating layer and connected in series to the first resistor, a first capacitor having a first upper electrode formed on the insulating layer and electrically connected to one end of the first resistor, and a first lower electrode formed in the insulating layer and electrically connected to one end of the second resistor, wherein the first lower electrode is electrically connected to the second resistor and is electrically connected to a reference electrode formed on the insulating layer. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a plan view of a semiconductor package equipped with a high-voltage detection device. [Figure 2] FIG. 2 is a circuit diagram of the high voltage detection device. [Figure 3] FIG. 3 is a circuit diagram of a resistor of a first example (FIG. 3(A)) and a circuit diagram of a resistor of a second example (FIG. 3(B)). [Figure 4]FIG. 4 is a circuit diagram of a resistor near the reference electrode. [Figure 5] FIG. 5 is a diagram showing an example of the configuration of one resistor. [Figure 6] FIG. 6 is a diagram showing the connection relationship between the resistors and the electrodes. [Figure 7] 7A and 7B are diagrams showing the longitudinal cross-sectional configuration of the resistor taken along the line AA in FIG. 6 (FIG. 7A), and the longitudinal cross-sectional configuration of the resistor taken along the line BB in FIG. 6 (FIG. 7B). [Figure 8] FIG. 8 shows the experimental circuit diagram. [Figure 9] FIG. 9 is a graph showing the relationship between the capacitance (fF) of the first capacitor C1 in the circuit shown in FIG. 8 and the current IR (μA) flowing through one resistance element in various resistors. [Figure 10] FIG. 10 is a diagram showing a planar configuration of a resistor provided with dummy wiring. [Figure 11] FIG. 11 is a diagram showing a vertical cross-sectional configuration of the resistor taken along the arrow line AA in FIG. [Figure 12] FIG. 12 is a diagram showing an example of a planar configuration of a resistor chip.

[0008] [Detailed explanation]

[0009] Various exemplary embodiments will be described in detail below with reference to the drawings. Note that the same or equivalent parts in the drawings will be denoted by the same reference numerals, and redundant explanations will be omitted.

[0010] FIG. 1 is a plan view of a semiconductor package 100 equipped with a high-voltage detection device.

[0011] In addition, the figure shows the state where the upper lid material is removed.

[0012] The semiconductor package 100 includes a case 30 having a recess D1. The case 30 is made of an insulating material such as resin or ceramic. The semiconductor package 100 includes a resistor chip 10 (semiconductor device) disposed on a first die pad 110 within the recess D1 and an amplifier chip 20 (semiconductor device) disposed on a second die pad 120 within the recess D1. The open end of the recess D1 of the semiconductor package 100 is sealed with a lid (not shown), creating an enclosed space within the recess D1. The lid may be made of an insulating material such as resin, and the recess D1 may be filled with a gas or an insulating material. An appropriate potential, such as ground potential, is applied to the first die pad 110 and the second die pad 120 via a lead frame. If necessary, the potential of the first die pad 110 may be set to a high potential, for example.

[0013] The output voltage of the resistor chip 10 is input to the amplifier chip 20. The amplifier chip 20 outputs an output voltage corresponding to the detected voltage.

[0014] The positive terminal of the battery 200 is electrically connected to the first inner lead 10a and is connected via a bonding wire to the first electrode E1 (see FIG. 2) of the resistor chip 10. The negative terminal of the battery 200 is electrically connected to the second inner lead 10b and is connected via a bonding wire to the second electrode E2 (see FIG. 2) of the resistor chip 10.

[0015] Each terminal of the amplifier chip 20 can be connected to the third inner lead 10c, the fourth inner lead 10d, the fifth inner lead 10e, the sixth inner lead 10f, the seventh inner lead 10g, the eighth inner lead 10h, and the ninth inner lead 10i via bonding wires.

[0016] For example, the third inner lead 10c is supplied with a power supply voltage Vcc and input to the amplifier chip 20. The ninth inner lead 10i is supplied with a ground potential GND and input to the amplifier chip 20. The sixth inner lead 10f can output an output voltage Vout. The fourth inner lead 10d can output a monitor signal corresponding to the potential of the first output electrode EP (see Figure 2). The eighth inner lead 10h can output a monitor signal corresponding to the potential of the second output electrode EN (see Figure 2). The fifth inner lead 10e and the seventh inner lead 10g can be used for other purposes as needed.

[0017] 2 is a circuit diagram of a high-voltage detection device. The high-voltage detection device includes a resistor circuit C10 (voltage divider circuit) and a voltage detection circuit C20. The resistor chip 10 described above includes the resistor circuit C10. The amplifier chip 20 includes the voltage detection circuit C20. A first input terminal HV(+) of the resistor circuit C10 is electrically connected to the positive electrode of the battery 200. A second input terminal HV(-) of the resistor circuit C10 is electrically connected to the negative electrode of the battery 200. The first input terminal HV(+) is electrically connected to a first electrode E1 (electrode pad). The second input terminal HV(-) is electrically connected to a second electrode E2 (electrode pad).

[0018] The resistance circuit C10 includes a first high resistance section RP (first resistor), a first low resistance section RPS, a second low resistance section RNS, and a second high resistance section RN (second resistor). The first high resistance section RP, the first low resistance section RPS, the second low resistance section RNS, and the second high resistance section RN are connected in series in this order between the first electrode E1 and the second electrode E2. The first high resistance section RP and the second high resistance section RN have a function of reducing a high voltage and each have a high resistance value. The first low resistance section RPS and the second low resistance section RNS have a function of detecting a voltage and each have a relatively low resistance value compared to the high resistance sections.

[0019] An exemplary resistance value of one high resistance section is 500 MΩ, but it can also be 1 MΩ or more and 1000 MΩ or less. The resistance value of the high resistance section can also be 100 MΩ or more and 800 MΩ or less. The resistance value of the high resistance section can also be 300 MΩ or more and 600 MΩ or less. This resistance value should be a resistance value that can withstand high voltages and allows voltage detection.

[0020] The resistance value of one low resistance section (RPS or RNS) is equal to or less than K% of the resistance value of the high resistance section. Exemplary values ​​of K% are 5%, 3%, 1%, 0.5%, 0.3%, 0.1%, 0.05%, or 0.01%, and the resistance value of the low resistance section can be, for example, 0.01 MΩ to 10 MΩ.

[0021] A first output electrode EP (electrode pad) is electrically connected to the connection point between the first high resistance section RP and the first low resistance section RPS. A second output electrode EN (electrode pad) is electrically connected to the connection point between the second high resistance section RN and the second low resistance section RNS. A reference electrode EG (electrode pad) is electrically connected between the first low resistance section RPS and the second low resistance section RNS.

[0022] The resistor circuit C10 is a voltage divider circuit, which can obtain a voltage corresponding to the resistance value between two selected points within the resistor circuit C10. The first output electrode EP is electrically connected to the first input terminal INP of the voltage detection circuit C20. The second output electrode EN is electrically connected to the second input terminal INN of the voltage detection circuit C20. The reference electrode EG is electrically connected to the reference terminal VC of the voltage detection circuit C20. The potential of the reference terminal VC can be set to, for example, ground potential. The voltage detection circuit C20 can output an output voltage Vout. The output voltage Vout can be the sum of a first potential difference between the first input terminal INP and the reference terminal VC and a second potential difference between the second input terminal INN and the reference terminal VC. The voltage detection circuit C20 can include a source follower (amplifier) ​​that amplifies the voltage input from the input terminals and a differential amplifier circuit that obtains the sum of the input voltages. The voltage detection circuit C20 has an input terminal for a power supply voltage Vcc for operating the internal circuit and an input terminal for setting the ground potential GND.

[0023] Resistor circuit C10 may include a dummy resistor.

[0024] FIG. 3 shows a circuit diagram of a resistor of a first example (FIG. 3(A)) and a circuit diagram of a resistor of a second example (FIG. 3(B)).

[0025] In the resistor circuit C10 of FIG. 3A, one end of a dummy resistor R (Dmy) is electrically connected to the input side of the first high resistance section RP. The dummy resistor R (Dmy) is electrically connected to the input side of the second high resistance section RN. The dummy resistor does not need to be electrically connected to a resistor. For example, resistors at both ends of a resistor chip may have different resistance characteristics compared to resistors near the center. Treating such resistors as dummy resistors may improve detection accuracy.

[0026] The resistor circuit C10 in FIG. 3B has a configuration that is a modification of the circuit of the first example. In this example, the first high resistance section RP is composed of a high resistance section RP1 and a high resistance section RP2 connected in series, and the second high resistance section RN is composed of a high resistance section RN1 and a high resistance section RN2 connected in series. In addition, the reference electrode EG is separated into a first reference electrode EG1 and a second reference electrode EG2, and these electrodes are electrically connectable on the voltage detection circuit side. Furthermore, compared to the circuit of the first example, one or more dummy resistors R (Dmy) are provided between each resistor section.

[0027] The dummy resistor is a resistor through which no current flows, and is provided to maintain electrical equivalence in the resistor circuit C10, maintain electrical stability, or reduce error factors that may occur during resistor manufacturing in the manufacturing process. The circuit configuration of the high voltage detection device is not limited to these, and the shape and arrangement of the resistor may be changed as long as the basic voltage detection function is achieved.

[0028] As described above, the high-voltage detection device can be housed in a single semiconductor package. Alternatively, the functions of each circuit can be separated into a resistor chip and an amplifier chip and mounted in the package. Modifications are also possible in which some of the circuit elements are moved to either chip or integrated into a single chip.

[0029] FIG. 4 is a circuit diagram of a resistor near the reference electrode.

[0030] The first high resistance section RP, to which a positive high potential is applied, includes a first resistor R(1), a second resistor R(2), and a third resistor R(3) connected in series. One resistor is configured by connecting at least two resistance elements (resistors, resistance layers) in series. For example, the first resistor R(1) is configured by connecting two resistance elements (R(1-1) and R(1-2)) in series. Similarly, the k-th resistor R(k) is configured by connecting two resistance elements (R(k-1) and R(k-2)) in series (k is a natural number).

[0031] The second high resistance section RN on the side to which a negative high potential is applied includes a first resistor R(1), a second resistor R(2), and a third resistor R(3) connected in series.

[0032] The first low resistance unit RPS includes a fourth resistor R(4), a fifth resistor R(5), and a sixth resistor R(6) connected in series. Similarly, the second low resistance unit RNS includes a fourth resistor R(4), a fifth resistor R(5), and a sixth resistor R(6) connected in series.

[0033] A first output electrode EP is connected to a node (N11) between the first high resistance section RP and the first low resistance section RPS. One electrode of a first capacitor C1 is connected to a first node N12 between the resistors R(4) and R(5) in the first low resistance section RPS. The other electrode of the first capacitor C1 is electrically connected to the reference electrode EG.

[0034] A second output electrode EN is connected to a node (N21) between the second high resistance section RN and the second low resistance section RNS. One electrode of a second capacitor C2 is connected to a second node N22 between the resistors R(4) and R(5) in the second low resistance section RNS. The other electrode of the second capacitor C2 is electrically connected to the reference electrode EG.

[0035] The reference electrode EG is electrically connected to a node N3 between the resistor R(6) of the first low resistance unit RPS and the resistor R(6) of the second low resistance unit RNS. In other words, the reference electrode EG is electrically connected to one end of the resistor R(6) of the first low resistance unit RPS and one end of the resistor R(6) of the second low resistance unit RNS.

[0036] FIG. 5 is a diagram showing an example of the configuration of one resistor.

[0037] In the first low resistance section RPS and the second low resistance section RNS, one resistor R(k) can be configured by connecting N resistance elements (R(k-1-1) to R(k-1-N)) in a first group in series with N resistance elements (R(k-2-1) to R(k-2-N)) in a second group in series, and connecting a pair of resistance elements (R(k-1-n), R(k-2-n)) in parallel (n is a natural number). The parallel connection can reduce the resistance value of the resistor R(k). This parallel connection configuration is useful in low resistance sections, but can also be used in high resistance sections. Via electrodes are connected to the undersides of both ends of each resistance element, and buried electrodes are disposed below the via electrodes. Adjacent resistance elements are electrically connected by these buried electrodes.

[0038] For example, the resistor (R(5):RPS) has a plurality of resistance elements (resistors) connected in parallel, the resistor (R(6):RPS) has a plurality of resistance elements (resistors) connected in parallel, the resistor (R(5):RNS) has a plurality of resistance elements (resistors) connected in parallel, and the resistor (R(6):RNS) has a plurality of resistance elements (resistors) connected in parallel. In the low resistance section, by connecting a plurality of resistance elements in parallel, the resistance value can be reduced and the voltage detection accuracy can be improved.

[0039] 6 is a diagram showing the connection relationship between the resistor and the electrodes. The figure shows an XYZ three-dimensional Cartesian coordinate system. The depth direction of the semiconductor substrate is the Z-axis direction, the direction perpendicular to the Z-axis and in which the individual resistor elements extend is the Y-axis direction, and the direction perpendicular to both the Z-axis and the Y-axis is the X-axis direction.

[0040] Resistor R(k) includes resistance elements (R(k-1), R(k-2)), and resistor R denotes any resistor R(k). Adjacent resistance elements along the Y-axis direction are connected in series by via electrodes VE arranged directly below their ends and buried electrodes BE to which the via electrodes are connected. Adjacent resistance elements along the X-axis direction are connected by via electrodes VE arranged directly below their respective ends and buried electrodes BE to which these via electrodes VE are connected.

[0041] A first wiring BEP extending along the Y-axis direction is connected to the connection point between the resistive element (resistor R(4-1)) in the first low resistance section RPS and the resistive element (R(3-1)) in the first high resistance section, in other words, to the buried electrode BE that electrically connects one end of these. An end of the first wiring BEP is electrically connected to the first output electrode EP through a via electrode (VE3) formed thereon. The first wiring BEP is formed in the same layer as the buried electrode BE.

[0042] A second wiring BEN extending along the Y-axis direction is connected to the connection point between the resistance element (resistor R(4-1)) in the second low resistance section RNS and the resistance element (R(3-1)) in the second high resistance section, in other words, to the buried electrode BE that electrically connects one end of these. An end of the second wiring BEN is electrically connected to the second output electrode EN through a via electrode (VE3) formed thereon. The second wiring BEN is formed in the same layer as the buried electrode BE.

[0043] The resistive element (resistor R(5-2)) in the first low resistance section RPS is connected to the buried electrode BE through a via electrode (VE), and the first connection wiring WE11, which is continuous with the first upper electrode E11 for the first capacitor, is electrically connected to this buried electrode BE through a second via electrode (VE2).

[0044] The resistive element (resistor R(5-2)) in the second low resistance section RNS is connected to the buried electrode BE through a via electrode (VE), and this buried electrode BE is electrically connected to a second connection wiring WE21 that is continuous with the second upper electrode E21 for the second capacitor through a second via electrode (VE2).

[0045] The reference electrode EG is connected to the third wiring BEG through a via electrode (VE3) located directly below it. The third wiring BEG is connected to the buried electrode BE located directly below one end of the resistive element R(6-2). The third wiring BEG is formed in the same layer as the buried electrode BE. The buried electrode BE to which the third wiring BEG is connected is electrically connected to one end of the resistive element R(6-2) through the via electrode (VE). An end of the third wiring BEG extending in the Y-axis direction is electrically connected to the first lower electrode E12 of the first capacitor C1 through a fourth wiring BEE extending along the X-axis direction. An end of the third wiring BEG is electrically connected to the second lower electrode E22 of the second capacitor C2 through a fourth wiring BEE extending along the X-axis direction.

[0046] 7A and 7B are diagrams showing the longitudinal cross-sectional configuration of the resistor taken along the line AA in FIG. 6 (FIG. 7A), and the longitudinal cross-sectional configuration of the resistor taken along the line BB in FIG. 6 (FIG. 7B).

[0047] 7(A), the semiconductor device includes an insulating layer 2 provided on a semiconductor substrate 1, and a plurality of resistors R (resistive elements, resistive layers) embedded in the insulating layer 2. All of the resistors R are embedded in the insulating layer 2.

[0048] The insulating layer 2 includes a plurality of laminated dielectric layers (first dielectric layer 2A, second dielectric layer 2B). At least one of the plurality of dielectric layers (first dielectric layer 2A) is made of a material containing silicon oxide. At least one of the plurality of dielectric layers (second dielectric layer 2B) is made of a material containing silicon nitride. In this example, the first dielectric layer 2A and the second dielectric layer 2B are alternately laminated. The silicon oxide in this example is SiO2, but the elemental composition ratio may be changed or other elements may be included as necessary. The silicon nitride in this example is Si3N4, but the elemental composition ratio may be changed or other elements may be included as necessary. The thickness of the insulating layer 2 may be, for example, 5 μm or more and 50 μm or less.

[0049] The insulating layer 2 is a lower dielectric layer 2A formed on a second dielectric layer 2B located at the top. L and the lower dielectric layer 2A L Upper dielectric layer 2A formed on H The lower dielectric layer 2A L and upper dielectric layer 2A H The exemplary material is the same as the material of the first dielectric layer 2A.

[0050] The protective film 4 includes a first protective film 4A, a second protective film 4B, and a third protective film 4C, which are sequentially stacked on the insulating layer 2. The first protective film 4A may be made of an inorganic insulator such as silicon oxide or silicon nitride, for example, SiO2. The second protective film 4B is formed on the first protective film 4A. The second protective film 4B is made of an inorganic insulator such as silicon oxide or silicon nitride, and may be the same as or different from the material of the first protective film 4A, for example, silicon nitride. The third protective film 4C is made of a resin (insulator) such as polyimide.

[0051] A buried electrode BE is disposed directly below the resistor R, and the resistor R and buried electrode BE are connected via a via electrode (VE). A via electrode (VE2) is provided on the buried electrode BE, and the upper end of the via electrode (VE2) is physically and electrically connected to a first connection wiring WE11 disposed on the insulating layer 2. Note that, since the physical connection of conductive elements involves an electrical connection, in the explanation, the term "connection" may be used simply when the connection state is clear. A first upper electrode E11 is continuous with the first connection wiring WE11. That is, the first upper electrode E11 constituting the first capacitor C1 is electrically connected to one end of the resistor R.

[0052] An upper dielectric layer 2A is provided directly below the first upper electrode E11. H The first capacitor C1 is composed of a first upper electrode E11, a first lower electrode E12, and an upper dielectric layer 2A interposed therebetween. H It consists of:

[0053] The second capacitor C2 shown in FIG. 6 has the same configuration as the first capacitor C1, and is composed of a second upper electrode E21, a second lower electrode E22, and an upper dielectric layer interposed therebetween. The structure on the second low resistance section RNS side to which the second capacitor C2 is connected includes a resistor R(5) (see FIG. 6) embedded in the insulating layer 2 and a resistor R(6) embedded in the insulating layer 2 and connected in series to the resistor R(5). The second capacitor C2 on the second low resistance section RNS side includes a second upper electrode E21 (FIG. 6) formed on the insulating layer 2 and electrically connected to one end of the resistor R(5), and a second lower electrode E22 (FIG. 6) formed in the insulating layer 2 and electrically connected to one end of the resistor R(6). The second lower electrode E22 is electrically connected to the resistor R(6) on the second low resistance section RNS side and is also electrically connected to a reference electrode EG formed on the insulating layer 2.

[0054] 7(B), a reference electrode EG is disposed on the insulating layer 2. The upper end of a via electrode (VE3) is connected to the lower surface of the reference electrode EG, and the lower end of the via electrode (VE3) is connected to the third wiring BEG. The third wiring BEG also functions as a buried electrode at a position directly below the resistor R, and the resistor R and the buried electrode (third wiring BEG) are electrically connected via the via electrode VE.

[0055] As described above, the resistor chip 10 includes a first electrode E1 formed on the insulating layer 2 (FIG. 7), a second electrode E2 formed on the insulating layer 2, a first output electrode EP formed on the insulating layer 2, and a second output electrode EN formed on the insulating layer 2. As shown in FIG. 2, the resistor chip 10 includes a first high resistance section RP connected between the first electrode E1 and the first output electrode EP, a first low resistance section RPS connected between the first output electrode EP and the reference electrode EG, a second high resistance section RN connected between the second electrode E2 and the second output electrode EN, and a second low resistance section RNS connected between the second output electrode EN and the reference electrode EG. The resistance value of the first high resistance section RP is relatively higher than the resistance value of the first low resistance section RPS, and the resistance value of the second high resistance section RN is relatively higher than the resistance value of the second low resistance section RNS. The first low resistance unit RPS includes a resistor (R(5):RPS) and a resistor (R(6):RPS), and the second low resistance unit RNS includes a resistor (R(5):RNS) and a resistor (R(6):RNS). The above configuration makes it possible to measure the input voltage.

[0056] FIG. 8 shows the experimental circuit diagram.

[0057] The resistors R(1) to R(6) are connected in series, and a first output electrode EP is connected to a node (N11) between the third resistor R(3) and the fourth resistor R(4). Since the number of resistors in the high resistance section is actually three or more, the figure illustrates that resistors such as resistor R(n) and resistor R(n+1) are interposed between the first resistor R(1) and the first electrode E1. The first node N12 between the fourth resistor R(4) and the fifth resistor R(5) is connected to the reference electrode EG via a first capacitor C1. An impedance RZ (e.g., 100 kΩ) is interposed between the first output electrode EP and the reference electrode EG. The size of the electrode of the first capacitor C1 is, for example, a square with sides of 72 μm, and the capacitance in this case is 200 fF.

[0058] Resistor R is made of CrSi, and a parasitic capacitance CP exists between it and the semiconductor substrate. The back surface of the semiconductor substrate is fixed to a frame. Assume that high-frequency noise, such as static electricity or surge voltage, is input to the semiconductor substrate via the frame. The voltage of the high-frequency source SRC is, for example, 2000 V. In this case, current flows through each resistor R via the parasitic capacitance CP. The resistance values ​​of the first resistor R(1) through the third resistor R(3) are each 400 kΩ. The resistance values ​​of the fourth resistor R(4) through the sixth resistor R(6) are each 14.8 kΩ. Each of the fourth resistor R(4) through the sixth resistor R(6) is made up of 27 resistors (400 kΩ) connected in parallel.

[0059] FIG. 9 shows the relationship between the capacitance (fF) of the first capacitor C1 in the circuit shown in FIG. 8 and the current I flowing through one resistance element in various resistors. R 10 is a graph showing the relationship between the temperature and the flow rate (μA).

[0060] If the first capacitor C1 does not exist, the capacitance of the first capacitor C1 (assumed to be C1) is zero. Then, the sixth resistor R(6) will have the largest current I RThis tendency is the same even when dummy wiring, which will be described later, is arranged, when the dummy wiring is electrically connected to the buried electrode, or when the dummy wiring and the buried electrode are capacitively coupled. When the capacitance of the first capacitor C1 is increased, the current I R decreases, and the current I R When the capacitance is Cx (fF), the current I in the sixth resistor R(6) R and the current I in the third resistor R(3) R When the capacitance exceeds Cx(fF), for example, the capacitance becomes 200(fF), the current I in the sixth resistor R(6) R is the current I in the third resistor R(3). R For example, assume that Cx(fF) is 165(fF).

[0061] From the viewpoint of increasing the breakdown voltage, the current I R It is preferable to set the capacitance so that the maximum value of the current I is small. That is, if the capacitance (C1) of the first capacitor C1 is 60 (fF)≦C1≦500 (fF), R The maximum value of the current I can be made smaller than 3000 (μA). If 100 (fF) ≦ C1 ≦ 300 (fF), the current I R The maximum value of can be further reduced.

[0062] The above-described structure may further include dummy wiring.

[0063] FIG. 10 is a diagram showing a planar configuration of a resistor provided with dummy wiring.

[0064] The first resistor R(1) is formed by connecting a pair of resistive elements R(1-1) and R(1-2) in series via a buried electrode BE. The resistive elements and the buried electrode BE are connected by a via electrode VE. If the resistance value of one resistive element is 200 kΩ, the series resistance value of the pair of resistive elements is 400 kΩ. The resistance value of 27 400 kΩ resistors connected in parallel is approximately 14.8 kΩ. This figure is a schematic diagram, and the 27 resistive elements are not shown. The number of resistive elements is arbitrary and can be determined according to the design. The fourth resistor R(4), fifth resistor R(5), and sixth resistor R(6), which constitute the low resistance section, are each resistors formed by connecting resistive elements in parallel. The dummy wiring DMW can be connected to the buried electrode BE located directly below the gap between the parallel-connected resistive elements via a via electrode (VE4). The dummy wiring DMW may be capacitively coupled to the buried electrode BE.

[0065] The dummy wiring DMW is provided to increase the breakdown voltage. When the dummy wiring DMW is present, it is possible to make the change in voltage per unit distance gentler. The dummy wiring DMW is electrically connected to the buried electrode BE that connects the resistance element through a via electrode (VE4). The dummy wiring DMW, the first output electrode EP, the reference electrode EG, the second output electrode EN, the first upper electrode E11, and the second upper electrode E21 can be formed at the same height position (in the same layer).

[0066] The dummy wiring DMW extends in the direction along which the individual resistance elements (resistance layers) extend, but can be curved. The length of the dummy wiring DMW is short in the vicinity of the first output electrode EP, the reference electrode EG, and the second output electrode EN. As it approaches the region where high voltage is applied, the length of the dummy wiring DMW becomes relatively long, and it can extend so as to surround the first electrode E1 (second electrode E2) to which high voltage is applied (see the arrows in FIG. 12).

[0067] FIG. 11 is a diagram showing a vertical cross-sectional configuration of the resistor taken along the arrow line AA in FIG.

[0068] The resistors constituting the second resistor R(2) include a first resistive element (R) and a second resistive element (R), which are connected via a central buried electrode BE and a via electrode VE. The right-hand buried electrode BE is connected to the right-hand resistive element (R) via a via electrode, and the right-hand buried electrode BE is connected to a dummy wiring DMW via a via electrode (VE4). The connection structure of the dummy wiring DMW is the same even within a cross section including other resistors.

[0069] For example, in a fifth resistor R(5) formed by connecting multiple resistance elements in parallel, one end of each of the multiple resistance elements is connected to the same buried electrode BE, and a dummy wiring DMW is connected to this buried electrode BE through a via electrode (VE4). The dummy wiring DMW is formed on an insulating layer 2 and is covered with a protective film 4. Note that the structure including the dummy wiring, the first capacitor, and the second capacitor can be applied not only to the circuit of FIG. 3(A) but also to the circuit of FIG. 3(B).

[0070] FIG. 12 is a diagram showing an example of the planar configuration of the resistor chip 10. As shown in FIG.

[0071] This resistor chip corresponds to the circuit diagram in Figure 3(A). The resistor chip 10 is constructed by forming an insulating layer on a semiconductor substrate and embedding a resistor in the insulating layer. The resistor chip 10 has a rectangular planar shape with four side faces. An annular conductor 1R can be embedded in the insulating layer along these side faces. The annular conductor 1R can be constructed of a metal material (such as copper), but if necessary, an annular body made of another material (e.g., a resistive material CrSi) electrically connected to the top or bottom of the metal material by a via electrode (such as tungsten) can also be provided. The annular body can contribute to improving waterproofness and electrical stability.

[0072] Resistors are arranged between the first electrode E1 and the second electrode E2. The resistor group on the left side can be designated R(k-1), and the resistor group on the right side can be designated R(k-2). The left and right resistor groups are electrically connected by a bridge structure consisting of the above-mentioned via electrodes and buried electrodes BE. The detailed structure of the resistor groups is as described above.

[0073] In the region where the dummy wiring DMW is formed, the arrows indicate the direction in which the dummy wiring extends. In the region near the first output electrode EP or the second output electrode EN, the length of the dummy wiring is relatively short. In the region relatively close to the first electrode E1 or the second electrode E2, the length of the dummy wiring is longer and is arranged to surround the first electrode E1 and the second electrode E2. The dummy wiring extending from the resistor closest to the first electrode E1 has a large absolute value of potential, so it is positioned to pass close to the first electrode E1. The dummy wiring extending from the resistor positioned slightly away from the first electrode E1 has a small absolute value of potential, so it is positioned to pass a position slightly away from the first electrode E1. In other words, the presence of the dummy wiring allows the potential to change gradually in the direction from the first electrode E1 toward the chip edge. This further increases the withstand voltage of the resistor chip. Dummy wiring is also similarly arranged around the second electrode E2.

[0074] It should be noted that the resistor chip 10 can also be incorporated into the amplifier chip 20 (FIG. 1).

[0075] The materials of each element will be explained.

[0076] The semiconductor substrate 1 (FIGS. 7 and 11) may have conductivity. For example, the impurity concentration of the semiconductor substrate 1 may be 5×10 13 (cm -3 ) or more 5 x 10 14 (cm -3 The thickness of the semiconductor substrate 1 may be 50 μm or more and 800 μm or less. The material of the semiconductor substrate 1 may be silicon (Si), but it is also possible to use a compound semiconductor such as SiC or SiGe.

[0077] The material of the resistive layer (wire resistor) constituting the resistor R is a resistive material with a higher resistivity than polysilicon. Specifically, the material of the resistor (resistive layer) is a material containing chromium (Cr) and silicon (Si), such as CrSi, CrSiC, or CrSiN. Other materials can also be used. Specifically, the material of the resistive layer constituting the resistor can include at least one metal compound selected from the group consisting of CrSi, CrSiN, CrSiO, TaN, and TiN. The resistive layer constituting the resistor can be formed using a sputtering method using a target containing a resistive material. Depending on the type of material of the resistor R, a plating method can also be used. The material of the resistor R may be composed of a single resistive material or a combination of multiple resistive materials. The thickness Rd of each resistive layer constituting the resistor R can be 1 nm≦Rd≦5 nm. When the thickness Rd is equal to or less than the upper limit, the resistance value can be sufficiently high, and when the thickness Rd is equal to or greater than the lower limit, the durability and strength of the resistive layer can be maintained.

[0078] The first electrode E1, the second electrode E2, and the buried electrodes (buried wiring) can be made of metal materials such as Al (aluminum) or Cu (copper).The various via electrodes can be made of high-melting-point metals such as tungsten (W), but other electrode materials can also be used.

[0079] In addition, in the range of various parameters, the range of an arbitrary parameter P is P min ≦P≦P max If given by (P min +ΔP)≦P≦(P max -ΔP), ΔP=(P max -P min )×R%, R may be set to 10, or R may be set to 20, R may be set to 30, or R may be set to 40.

[0080] (Supplementary Note) As described above, various embodiments of the present disclosure can be defined as the following supplementary notes.

[0081] [A1] A semiconductor device comprising: an insulating layer 2 provided on a semiconductor substrate 1; a first resistor (R(5):RPS) embedded in the insulating layer 2; a second resistor (R(6):RPS) embedded in the insulating layer 2 and connected in series to the first resistor (R(5):RPS); a first capacitor C1 having a first upper electrode E11 formed on the insulating layer 2 and electrically connected to one end of the first resistor (R(5):RPS); and a first lower electrode E12 formed in the insulating layer 2 and electrically connected to one end of the second resistor (R(6):RPS), wherein the first lower electrode E12 is electrically connected to the second resistor (R(6):RPS) and is electrically connected to a reference electrode EG formed on the insulating layer 2.

[0082] [A2] The semiconductor device according to [A1], further comprising: a third resistor (R(5):RNS) embedded in the insulating layer 2; a fourth resistor (R(6):RNS) embedded in the insulating layer 2 and connected in series to the third resistor (R(5):RNS); a second capacitor C2 having a second upper electrode E21 formed on the insulating layer 2 and electrically connected to one end of the third resistor (R(5):RNS); and a second lower electrode E22 formed in the insulating layer 2 and electrically connected to one end of the fourth resistor (R(6):RNS), wherein the second lower electrode E22 is electrically connected to the fourth resistor (R(6):RNS) and is electrically connected to a reference electrode EG formed on the insulating layer 2.

[0083] [A3] A first electrode E1 formed on the insulating layer 2, a second electrode E2 formed on the insulating layer 2, a first output electrode EP formed on the insulating layer 2, a second output electrode EN formed on the insulating layer 2, a first high resistance portion RP connected between the first electrode E1 and the first output electrode EP, a first low resistance portion RPS connected between the first output electrode EP and the reference electrode EG, a second high resistance portion RN connected between the second electrode E2 and the second output electrode EN, and a second low resistance portion RPS connected between the second output electrode EN and the reference electrode EG. and a second low resistance section RNS connected therebetween, wherein the resistance value of the first high resistance section RP is relatively higher than the resistance value of the first low resistance section RPS, the resistance value of the second high resistance section RN is relatively higher than the resistance value of the second low resistance section RNS, the first low resistance section RPS includes a first resistor (R(5):RPS) and a second resistor (R(6):RPS), and the second low resistance section RNS includes a third resistor (R(5):RNS) and a fourth resistor (R(6):RNS).

[0084] [A4] The semiconductor device according to [A3], wherein the first resistor (R(5):RPS) has a plurality of resistive elements connected in parallel, the second resistor (R(6):RPS) has a plurality of resistive elements connected in parallel, the third resistor (R(5):RNS) has a plurality of resistive elements connected in parallel, and the fourth resistor (R(6):RNS) has a plurality of resistive elements connected in parallel.

[0085] [A5] The semiconductor device according to [A1], wherein the capacitance of the first capacitor C1 is equal to or greater than 60 (fF) and equal to or less than 500 (fF).

[0086] [A6] A semiconductor device according to [A1], comprising: a buried electrode BE to which the first resistor (R(5):RPS) is connected via a first via electrode (VE); and a dummy wiring DMW formed on an insulating layer 2 and connected to the buried electrode BE via a second via electrode (VE4).

[0087] Although various exemplary embodiments have been described above, various omissions, substitutions, and modifications may be made without being limited to the above-described exemplary embodiments. Furthermore, elements from different embodiments may be combined to form other embodiments. It will be understood from the above description that various embodiments of the present disclosure have been described herein for illustrative purposes, and that various modifications may be made without departing from the scope and spirit of the present disclosure. Accordingly, the various embodiments disclosed herein are not intended to be limiting, with the true scope and spirit being indicated by the appended claims. [Explanation of symbols]

[0088] 1...Semiconductor substrate 1R...Ring conductor 2...Insulating layer 2A...First dielectric layer 2A H ,2A L ...dielectric layer 2B: Second dielectric layer 4...Protective film 4A…First protective film 4B…Second protective film 4C…Third protective film 10...Resistor chip 10a…1st inner lead 10b…Second inner lead 10c…3rd inner lead 10d…4th inner lead 10e…5th Inner Lead 10f...6th inner lead 10g...7th inner lead 10h…8th inner lead 10i…9th inner lead 20...Amplifier chip 30…cases 100...Semiconductor package 110...First die pad 120...Second die pad 200...battery BE...buried electrode BEP…1st wiring BEN: Second wiring BEG…Third wiring BEE…4th wiring C1: First capacitor C2: Second capacitor DMW...Dummy wiring E1…1st electrode E2…Second electrode E11,E12…Top electrode E21,E22…lower electrode EG…Reference electrode EP…1st output electrode EN: Second output electrode R…Resistor (resistance element) RP…1st high resistance part RN…Second high resistance section RPS...1st low resistance section RNS…Second low resistance section C10…Resistance circuit C20: Voltage detection circuit CP...parasitic capacitance D1...Concave EG1...1st reference electrode EG2…Second reference electrode GND: Ground potential HV(+)...First input terminal HV(-)...Second input terminal INP...First input terminal INN: Second input terminal N3...node N12...1st node N22: 2nd node R(Dmy)...Dummy resistor RN1,RN2,RP1,RP2…High resistance part RZ…Impedance SRC: High frequency source VE: Via electrode WE11...1st connection wiring WE21...Second connection wiring

Claims

1. an insulating layer provided on a semiconductor substrate; a first resistor embedded within the insulating layer; a second resistor embedded within the insulating layer and connected in series with the first resistor; a first capacitor including a first upper electrode formed on the insulating layer and electrically connected to one end of the first resistor, and a first lower electrode formed within the insulating layer and electrically connected to one end of the second resistor; Preparation, the first lower electrode is electrically connected to the second resistor and is electrically connected to a reference electrode formed on the insulating layer; Semiconductor device.

2. a third resistor embedded within the insulating layer; a fourth resistor embedded in the insulating layer and connected in series with the third resistor; a second capacitor including a second upper electrode formed on the insulating layer and electrically connected to one end of the third resistor, and a second lower electrode formed within the insulating layer and electrically connected to one end of the fourth resistor; Preparation, the second lower electrode is electrically connected to the fourth resistor and to the reference electrode formed on the insulating layer; The semiconductor device according to claim 1 .

3. a first electrode formed on the insulating layer; a second electrode formed on the insulating layer; a first output electrode formed on the insulating layer; a second output electrode formed on the insulating layer; a first high resistance section connected between the first electrode and the first output electrode; a first low resistance portion connected between the first output electrode and the reference electrode; a second high resistance section connected between the second electrode and the second output electrode; a second low resistance section connected between the second output electrode and the reference electrode; Equipped with a resistance value of the first high resistance portion is relatively higher than a resistance value of the first low resistance portion; a resistance value of the second high resistance portion is relatively higher than a resistance value of the second low resistance portion; the first low resistance unit includes the first resistor and the second resistor, the second low resistance unit includes the third resistor and the fourth resistor; The semiconductor device according to claim 2 .

4. the first resistor comprises a plurality of resistive elements connected in parallel; the second resistor comprises a plurality of resistive elements connected in parallel; the third resistor comprises a plurality of resistive elements connected in parallel; the fourth resistor comprises a plurality of resistive elements connected in parallel; The semiconductor device according to claim 3 .

5. The capacitance of the first capacitor is equal to or greater than 60 (fF) and equal to or less than 500 (fF). The semiconductor device according to claim 1 .

6. a buried electrode to which the first resistor is connected through a first via electrode; a dummy wiring formed on the insulating layer and connected to the buried electrode through a second via electrode; Equipped with The semiconductor device according to claim 1 .

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