Semiconductor element and semiconductor device

Abstract

To provide a semiconductor element capable of improving reliability.SOLUTION: The electrode terminal 60 of the semiconductor element 30 includes a terminal portion 64 and a base portion 66. Each of the terminals 64 is provided across both the exposed portion 40A and the peripheral edge 52 of the opening 51 in the insulating layer 50. The terminal portion 64 includes a terminal portion reverse surface 642 and a terminal portion side surface 643. The reverse surface 642 is in contact with the exposed portion 40A and the peripheral portion 52. The terminal portion side surface 643 intersects the terminal portion back surface 642. The pedestal portion 66 protrudes outward from a portion 645 of the terminal portion side surface 643 of the terminal portion 64, which is close to the terminal portion back surface 642. The base portion 66 includes a base portion reverse surface 662, a base portion side surface 663, and a curved surface 664. The base-portion back surface 662 is in contact with the insulating layer 50. The base-portion side surface 663 intersects the base-portion back surface 662 and is located outward of the terminal-portion side surface 643. The curved surface 664 is provided between the base-portion back surface 662 and the base-portion side surface 663.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor element and a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a semiconductor package including a conductive member, a semiconductor device flip-bonded to the conductive member using Cu pillars on a Cu conductive layer, and a sealing resin covering a portion of the conductive member and the semiconductor device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-167330

[0004] [overview] Incidentally, improved reliability is desired for semiconductor devices.

[0005] A semiconductor element according to one aspect of the present disclosure includes an electrode provided on a surface of the element facing a thickness direction, an insulating layer covering the electrode and including an opening that exposes a portion of the electrode, and an electrode terminal that contacts the exposed portion of the electrode exposed by the opening and partially overlaps the insulating layer when viewed from the thickness direction, the electrode terminal being provided across both the exposed portion and a peripheral portion of the opening in the insulating layer, and including a terminal portion electrically connected to the electrode and a base portion connected to the terminal portion. , wherein the terminal portion includes a terminal portion back surface facing the exposed portion and the peripheral portion, and a terminal portion side surface intersecting the terminal portion back surface, and the base portion protrudes outward from a portion of the terminal portion side surface of the terminal portion closer to the terminal portion back surface, and the base portion includes a base portion back surface facing the insulating layer, a base portion side surface intersecting the base portion back surface and positioned outward of the terminal portion side surface, and a curved surface provided between the base portion back surface and the base portion side surface.

[0006] A semiconductor device according to one aspect of the present disclosure includes a semiconductor element including electrode terminals, a plurality of connection terminals electrically connected to the electrode terminals of the semiconductor element, and a sealing resin that seals the semiconductor element and the plurality of connection terminals, wherein the semiconductor element includes an electrode provided on a surface of the element facing a thickness direction, an insulating layer that covers the electrode and includes an opening that exposes a portion of the electrode, and the electrode terminal that contacts the exposed portion of the electrode exposed by the opening and partially overlaps the insulating layer when viewed from the thickness direction, and the electrode terminal is provided across both the exposed portion and a peripheral portion of the opening in the insulating layer, and is electrically connected to the electrode. the terminal portion includes a terminal portion back surface facing the exposed portion and the peripheral edge portion, and a terminal portion side surface intersecting the terminal portion back surface, the pedestal portion protruding outward from a portion of the terminal portion side surface of the terminal portion closer to the terminal portion back surface, the pedestal portion includes a pedestal portion back surface facing the insulating layer, a pedestal portion side surface intersecting the pedestal portion back surface and positioned outward of the terminal portion side surface, and a curved surface provided between the pedestal portion back surface and the pedestal portion side surface, and the sealing resin enters between the curved surface of the pedestal portion and the insulating layer. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic perspective view showing an example of a semiconductor device. [Figure 2] FIG. 2 is a schematic plan view of the semiconductor device of FIG. 1 as viewed from the rear surface. [Figure 3] FIG. 3 is a schematic plan view showing the internal structure of the semiconductor device of FIG. [Figure 4] FIG. 4 is a schematic cross-sectional view of the semiconductor device taken along line F4-F4 in FIG. [Figure 5] FIG. 5 is a schematic cross-sectional view showing an enlarged view of the electrode terminal and its peripheral members in the F5 region of FIG. [Figure 6] FIG. 6 is a schematic cross-sectional view showing the electrode terminal and its peripheral members taken along line F6-F6 in FIG. [Figure 7]FIG. 7 is a schematic cross-sectional view showing the configuration of an electrode terminal of the semiconductor element shown in FIG. [Figure 8] FIG. 8 is a schematic cross-sectional view showing an enlarged view of the electrode terminal of FIG. [Figure 9] 9A to 9C are schematic cross-sectional views illustrating exemplary manufacturing steps for the semiconductor device shown in FIG. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 11] FIG. 11 is a schematic cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 12] FIG. 12 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 13] FIG. 13 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 14] FIG. 14 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 15] FIG. 15 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 16] FIG. 16 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 17] FIG. 17 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 18] FIG. 18 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 19] FIG. 19 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 20] FIG. 20 is a schematic cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 21] FIG. 21 is a schematic cross-sectional view showing an enlarged view of an electrode terminal and its peripheral members of a semiconductor device according to a modified example. [Figure 22] FIG. 22 is a schematic cross-sectional view showing an enlarged view of an electrode terminal and its peripheral members of a semiconductor device according to a modified example. [Figure 23] FIG. 23 is a schematic cross-sectional view showing an electrode terminal and its peripheral members of a semiconductor device according to a modified example.

[0008] [Detailed explanation] Hereinafter, several embodiments of the semiconductor device of the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of description, components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered to limit the present disclosure. Terms such as "first," "second," and "third" in the present disclosure are used merely to distinguish between objects and do not rank the objects.

[0009] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0010] (Embodiment) A semiconductor device 10 according to an embodiment will be described with reference to FIGS. FIG. 1 is a schematic perspective view showing an example of a semiconductor device 10. FIG. 2 is a schematic plan view of the semiconductor device 10 of FIG. 1 as viewed from the back. FIG. 3 is a schematic plan view showing the internal structure of the semiconductor device 10 of FIG. 1. In FIG. 3, the sealing resin 70 is indicated by a two-dot chain line to show the state of the semiconductor element 30 and the connection terminal 20. FIG. 4 is a schematic cross-sectional view of the semiconductor device 10 taken along line F4-F4 in FIG. 3. FIG. 5 is a schematic cross-sectional view showing an enlarged view of the electrode terminal in region F5 of FIG. 4 and its surrounding components. FIGS. 4 and 5 show the semiconductor element 30 with its element surface 301 facing downward. FIG. 6 is a schematic cross-sectional view of the electrode terminal 60 and its surrounding components taken along line F6-F6 in FIG. 5. FIG. 7 is a schematic cross-sectional view showing the configuration of the electrode terminal 60 of the semiconductor element 30 shown in FIG. 5. FIG. 7 shows the semiconductor element 30 with its element surface 301 facing upward. FIG. 7 also shows the state of the bonding layer 68 before being bonded to the connection terminal 20. Fig. 8 is a schematic cross-sectional view showing an enlarged portion of the electrode terminal 60 shown in Fig. 7. The term "plan view" used in the present disclosure refers to viewing the semiconductor device 10 in the Z-axis direction of the X, Y and Z axes that are orthogonal to each other and shown in Fig. 1.

[0011] (Schematic configuration of semiconductor device) As shown in FIG. 1, the semiconductor device 10 has a rectangular flat plate shape with its thickness direction in the Z-axis direction. The semiconductor device 10 includes a surface 11 facing the Z-axis direction and a back surface 12 opposite the surface 11. The semiconductor device 10 includes four side surfaces 13 to 16 connecting the surface 11 and the back surface 12 in the Z-axis direction. The side surfaces 13 and 14 form both end surfaces of the semiconductor device 10 in the X-axis direction, and the side surfaces 15 and 16 form both end surfaces of the semiconductor device 10 in the Y-axis direction. In the example shown in FIG. 1, the semiconductor device 10 has a square shape in a plan view. The semiconductor device 10 is a surface-mount package in which the back surface 12 serves as the mounting surface when mounted on, for example, a circuit board (not shown). In the example shown in FIG. 1, the package format of the semiconductor device 10 is a QFN (Quad Flat Non-leaded Package) type. Note that the shape of the semiconductor device 10 in a plan view is not limited to a square shape and can be arbitrarily changed. The dimensions of the semiconductor device 10 in the X-axis direction, Y-axis direction, and Z-axis direction can be arbitrarily changed. Furthermore, the package format of the semiconductor device 10 is not limited to QFN, and can be changed arbitrarily.

[0012] 1 to 4, the semiconductor device 10 includes a connection terminal 20. The semiconductor device 10 may include a plurality of connection terminals 20. The connection terminal 20 includes a connection terminal front surface 201, a connection terminal front surface 201 facing the Z-axis direction, and a connection terminal back surface 202 opposite the connection terminal front surface 201. In one example, the connection terminal back surface 202 is exposed from the device back surface 12.

[0013] The connection terminal 20 may include a lead portion 21, a pad portion 22, and a finger portion 23. In one example, the semiconductor device 10 includes a plurality of lead portions 21. The number of lead portions 21 can be changed as desired. In one example, the semiconductor device 10 includes one pad portion 22. The number of pad portions 22 can be changed as desired. In one example, the semiconductor device 10 includes a plurality of finger portions 23. The number of finger portions 23 can be changed as desired. The semiconductor device 10 may not include the pad portion 22. The semiconductor device 10 may not include the finger portion 23.

[0014] The plurality of leads 21 are arranged on the periphery of the semiconductor device 10. The plurality of leads 21 are exposed from the back surface 12 of the device. The plurality of leads 21 may be arranged along at least one of the device side surfaces 13 to 16. In one example, the plurality of leads 21 are arranged along each of the device side surfaces 13 to 16. The plurality of leads 21 may be exposed from the corresponding device side surface 13 to 16.

[0015] In one example, each of the plurality of lead portions 21 has a strip shape extending in a direction perpendicular to the corresponding device side surface 13 to 16 in a plan view. The planar shape of the plurality of lead portions 21 can be changed as desired. In one example, each of the plurality of lead portions 21 includes a protruding portion 211 that protrudes toward the center of the semiconductor device 10 on the connection terminal surface 201 side.

[0016] The pad portion 22 is arranged so as to be exposed from the device back surface 12 of the semiconductor device 10. In one example, the pad portion 22 is arranged in the center of the device back surface 12. In one example, the pad portion 22 has a rectangular flat plate shape in a plan view. In one example, the pad portion 22 has four sides parallel to the device side surfaces 13 to 16 in a plan view. In one example, the pad portion 22 includes a protruding portion 221 that protrudes toward the device side surfaces 13 to 16 at the peripheral edge on the connection terminal surface 201 side.

[0017] The multiple finger portions 23 extend from the pad portion 22 toward the device side surfaces 13 to 16 of the semiconductor device 10 in a plan view. In one example, the multiple finger portions 23 extend from the four corners of the rectangular pad portion 22 toward the four corners of the semiconductor device 10. The multiple finger portions 23 may be exposed from the device side surfaces 13 to 16.

[0018] The connection terminal 20 is made of a conductive material. For example, the conductive material may be one or more appropriately selected from Ti (titanium), TiN (titanium nitride), Au (gold), Ag (silver), Cu (copper), Al (aluminum), and W (tungsten). The connection terminal 20 is formed, for example, by etching a plate material made of a conductive material. The method for forming the connection terminal 20 can be changed as desired. For example, the connection terminal 20 may be formed by punching, bending, or the like, a plate material.

[0019] The semiconductor device 10 includes a semiconductor element 30. The semiconductor element 30 is disposed inside the semiconductor device 10. In a plan view, the semiconductor element 30 is disposed in the center of the semiconductor device 10. In a plan view, the semiconductor element 30 is disposed inside the semiconductor device 10 so as to overlap the entire pad portion 22 and the inner ends of the multiple lead portions 21.

[0020] The semiconductor element 30 has a rectangular flat plate shape with its thickness direction in the Z-axis direction. The semiconductor element 30 includes an element front surface 301 facing the Z-axis direction and an element back surface 302 opposite the element front surface 301. The semiconductor element 30 also includes element side surfaces 303 to 306 that connect the element front surface 301 and the element back surface 302 in the Z-axis direction. The element side surfaces 303 and 304 form both end surfaces of the semiconductor element 30 in the X-axis direction, and the element side surfaces 305 and 306 form both end surfaces of the semiconductor element 30 in the Y-axis direction.

[0021] The semiconductor element 30 includes a plurality of electrode terminals 60 on an element surface 301. The semiconductor element 30 is arranged with the plurality of electrode terminals 60 facing the connection terminals 20. It can be said that the semiconductor element 30 is arranged with the element surface 301 facing the connection terminals 20. The plurality of connection terminals 20 are mechanically and electrically connected to the connection terminals 20 by a bonding layer 68. It can be said that the semiconductor element 30 is flip-chip mounted to the connection terminals 20.

[0022] The semiconductor device 10 includes a sealing resin 70. The sealing resin 70 constitutes the external structure of the semiconductor device 10. More specifically, the sealing resin 70 has a rectangular flat plate shape with its thickness direction in the Z-axis direction. The sealing resin 70 has a sealing surface 701, a sealing back surface 702 opposite the sealing surface 701 in the Z-axis direction, and four sealing side surfaces 703 to 706 connecting the sealing surface 701 and the sealing back surface 702 in the Z-axis direction. The sealing surface 701 constitutes the device surface 11, and the sealing back surface 702 constitutes the device back surface 12. The sealing side surface 703 constitutes the device side surface 13, the sealing side surface 704 constitutes the device side surface 14, the sealing side surface 705 constitutes the device side surface 15, and the sealing side surface 706 constitutes the device side surface 16.

[0023] As shown in FIG. 4 , the sealing resin 70 covers the semiconductor element 30. The sealing resin 70 is made of an insulating material such as epoxy resin. The sealing resin 70 may be colored black or the like. The sealing resin 70 covers the entire semiconductor element 30 and some of the connection terminals 20. It can be said that the sealing resin 70 seals the semiconductor element 30 and some of the connection terminals 20. It can be said that the sealing resin 70 supports the connection terminals 20.

[0024] A conductive film 75, shown by a two-dot chain line in FIG. 4, may be provided on the surface of the connection terminal 20 exposed from the sealing resin 70. The conductive film 75 may be a plating film containing Sn (tin), for example. The conductive film 75 may include a plurality of plating films. For example, the conductive film 75 may include a plurality of plating films stacked in this order of Ni (nickel), Pd (palladium), and Au.

[0025] (Schematic configuration of semiconductor element) As shown in FIG. 4, the semiconductor device 30 includes a substrate 31. The substrate 31 is, for example, a semiconductor substrate. In one example, the substrate 31 is a semiconductor substrate made of a material containing Si (silicon). The substrate 31 may be made of a wide bandgap semiconductor. A wide bandgap semiconductor is a semiconductor having a bandgap greater than the bandgap of Si. Examples of wide bandgap semiconductors include GaN (gallium nitride) and SiC (silicon carbide). In this embodiment, the substrate 31 is made of a Si silicon chip. The substrate 31 may have a layered structure including a semiconductor substrate and an epitaxial layer. The substrate 31 may be made of an epitaxial layer.

[0026] The substrate 31 has a rectangular flat plate shape with its thickness direction in the Z-axis direction. The substrate 31 includes a substrate front surface 311 and a substrate back surface 312 opposite to the substrate front surface 311. The substrate 31 is disposed such that the substrate front surface 311 faces the connection terminal surface 201 of the connection terminal 20. In one example, the substrate back surface 312 constitutes the element back surface 302.

[0027] The semiconductor device 30 includes one or more device regions 32 defined in a substrate surface 311 of a substrate 31. In Figure 4, the multiple device regions 32 are indicated by dashed lines. The substrate surface 311 of the substrate 31 can be referred to as a device surface. In one example, the substrate 31 has multiple device regions 32 defined therein.

[0028] The number and arrangement of device regions 32 may be changed arbitrarily. Device regions 32 may include functional devices arranged in regions inside and outside substrate 31. The functional devices may include, for example, at least one of semiconductor switching devices, semiconductor rectifying devices, and passive devices. The functional devices may also include circuitry that combines at least two of semiconductor switching devices, semiconductor rectifying devices, and passive devices.

[0029] The semiconductor switching device may include at least one of a metal insulator semiconductor field effect transistor (MISFET), a bipolar junction transistor (BJT), an insulated gate bipolar junction transistor (IGBT), and a junction field effect transistor (JFET). The semiconductor rectifying device may include at least one of a pn junction diode, a pin junction diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The passive device may include at least one of a resistor, a capacitor, an inductor, and a fuse.

[0030] The semiconductor element 30 includes an insulating film 33 disposed on the substrate surface 311. The insulating film 33 is interposed between the connection terminal 20 and the substrate 31. In one example, the insulating film 33 covers the entire substrate surface 311 in a plan view and is in contact with the substrate surface 311.

[0031] The insulating film 33 may include a plurality of interlayer insulating films 34 and a top insulating film 35 . The number of layers in the multiple interlayer insulating films 34 is arbitrary. For example, the number of layers in the interlayer insulating films 34 may be 2 or more and 25 or less. Each of the multiple interlayer insulating films 34 may have a single-layer structure or a multilayer structure including at least one of an SiO2 (silicon oxide) film and an SiN (silicon nitride) film. For example, each of the multiple interlayer insulating films 34 has a single-layer structure made of an SiO2 film.

[0032] The top insulating film 35 forms a termination insulating film of the insulating film 33 and covers the uppermost interlayer insulating film 34. The top insulating film 35 may also be referred to as an "inorganic insulating film" or a "passivation film." The top insulating film 35 may have a single-layer structure including at least one of an SiO2 film and an SiN film.

[0033] The top insulating film 35 may be made of an insulating material different from at least the uppermost interlayer insulating film 34. In one example, the top insulating film 35 has a single-layer structure made of a SiN film. The top insulating film 35 has a flat surface extending along the substrate surface 311. In one example, the top insulating film 35 may have a thickness less than that of the uppermost interlayer insulating film 34. The top insulating film 35 may be made of a stacked structure of a SiO2 film and a SiN film. In one example, the surface of the top insulating film 35 opposite the substrate 31 may constitute the device surface 301 of the semiconductor device 30.

[0034] The semiconductor element 30 may include a plurality of interlayer wirings 36 arranged in the insulating film 33. The plurality of interlayer wirings 36 are wiring films arranged on any of the interlayer insulating films 34 below the top insulating film 35. The plurality of interlayer wirings 36 may be routed in any manner. The semiconductor element 30 may include a plurality of via wirings 37 connected to the plurality of interlayer wirings 36. The plurality of via wirings 37 penetrate the interlayer insulating film 34. The plurality of interlayer wirings 36 and the plurality of via wirings 37, together with the plurality of interlayer insulating films 34, form a multilayer wiring structure 38. The plurality of interlayer wirings 36 are made of a material containing at least one of Al, Cu, Ti, and W.

[0035] The semiconductor element 30 includes a plurality of electrodes 40 arranged on the element surface 301. The element surface 301 is formed by the insulating film 33, more specifically the surface of the top insulating film 35. Therefore, it can be said that the semiconductor element 30 includes a plurality of electrodes 40 arranged on the surface of the insulating film 33. The plurality of electrodes 40 each constitutes a terminal wiring of the multilayer wiring structure 38. The plurality of electrodes 40 may be routed in any manner. The plurality of electrodes 40 may be routed in a line shape in a planar view, or may have an island shape. Of course, the plurality of electrodes 40 may have a relatively wide island portion in a planar view, and a relatively narrow line portion that is drawn out in a line shape from the island portion.

[0036] Each of the electrodes 40 has a thickness that exceeds the thickness of the top insulating film 35. Each of the electrodes 40 may have a thickness that exceeds the thickness of each interlayer wiring 36. The multiple wiring layers have the same configuration except for their locations and routing patterns.

[0037] The semiconductor element 30 includes an insulating layer 50 disposed on the element surface 301. The insulating layer 50 covers a surface 351 of the top insulating film 35 and a portion of the electrode 40. The insulating layer 50 may be made of an insulating material such as an epoxy resin, a phenolic resin, or a polyimide resin. The insulating layer 50 includes an opening 51 that exposes a portion of the electrode 40. For example, the opening 51 may have a circular shape in a plan view.

[0038] The semiconductor element 30 includes a plurality of electrode terminals 60. The plurality of electrode terminals 60 are provided corresponding to the plurality of electrodes 40. The electrode terminals 60 are in contact with exposed portions of the electrodes 40. Furthermore, the electrode terminals 60 partially overlap the insulating layer 50 in a planar view. It can be said that the semiconductor element 30 includes electrode terminals 60 that are in contact with exposed portions of the electrodes 40 and that partially overlap the insulating layer 50 in a planar view. The electrode terminals 60 are electrically connected to the electrodes 40. It can be said that the semiconductor element 30 includes electrode terminals 60 that are electrically connected to the electrodes 40.

[0039] The plurality of electrode terminals 60 protrude in the Z-axis direction from the electrode upper surface 401 of the electrode 40. The plurality of electrode terminals 60 have a columnar shape. In one example, the electrode terminal 60 has a cylindrical shape. The plurality of electrode terminals 60 are interposed between the electrode 40 and the connection terminal 20.

[0040] The semiconductor element 30 includes a bonding layer 68 provided on a terminal surface 601 of the electrode terminal 60. The bonding layer 68 is interposed between the electrode terminal 60 and the connection terminal 20. The electrode terminal 60 is mechanically and electrically connected to the connection terminal 20 by the bonding layer 68.

[0041] (Details of the electrode terminal and its surrounding structure) The electrode terminal 60 and its surrounding structure will be described in detail with reference to FIGS.

[0042] (electrode) An example of the electrode 40 shown in Figures 5 to 8 will be described below. The shape, configuration, and material of the electrode 40 can each be changed as desired.

[0043] The electrode 40 includes an electrode upper surface 401 and an electrode lower surface 402 opposite to the electrode upper surface 401. The electrode lower surface 402 is in contact with the surface 351 of the top insulating film 35. As shown in FIG. 6 , the electrode 40 may have a rectangular shape in a plan view, for example.

[0044] The electrode 40 includes a wiring barrier film 41 disposed on a surface 351 of the top insulating film 35. The wiring barrier film 41 selectively covers the top insulating film 35. The wiring barrier film 41 may be made of a material containing at least one of Ti, TiN, Ta (tantalum), W, Mo (molybdenum), and Cr (chromium). The wiring barrier film 41 may have a multilayer structure or a single-layer structure containing at least one of a Ti film and a TiN film. In one example, the wiring barrier film 41 has a single-layer structure made of a material containing Ti.

[0045] The electrode 40 includes a wiring electrode 42 that covers the wiring barrier film 41. The wiring electrode 42 constitutes the main body of the electrode 40. The wiring electrode 42 may cover the entire area of ​​the wiring barrier film 41 in cross-sectional and plan views. The wiring electrode 42 may be made of a material containing at least one of Al and Cu.

[0046] The wiring electrode 42 includes a wiring upper surface 421, a wiring lower surface 422 opposite to the wiring upper surface 421, and a wiring side surface 423 connecting the wiring upper surface 421 and the wiring lower surface 422. The wiring lower surface 422 faces the surface of the top insulating film 35. In one example, the wiring electrode 42 has a wiring upper end corner 424 that is formed into a rounded shape. The wiring upper end corner 424 slopes obliquely downward in an arc shape from the wiring upper surface 421 toward the wiring side surface 423 at the periphery of the wiring upper surface 421.

[0047] The electrode 40 includes a cover electrode 43 that covers the wiring electrode 42. The cover electrode 43 has a film-like shape that covers the entire wiring electrode 42. The cover electrode 43 includes a cover upper surface 431 and a cover lower surface 432 opposite the cover upper surface 431. The cover lower surface 432 contacts the wiring upper surface 421 of the wiring electrode 42. The cover electrode 43 includes a rounded portion 434 that covers the wiring upper end corner 424 in a film-like shape so as to curve along the wiring upper end corner 424.

[0048] In this embodiment, the cover electrode 43 may have a laminated structure in which multiple metal films are stacked. The cover electrode 43 may include a first metal film 441 and a second metal film 442 stacked in this order from the wiring electrode 42 side. The first metal film 441 covers the entire wiring upper surface 421 in a film-like manner. The first metal film 441 constitutes the cover lower surface 432 of the cover electrode 43. In one example, the first metal film 441 is made of a material containing Ni. The second metal film 442 covers the entire first metal film 441 in a film-like manner. The second metal film 442 constitutes the cover upper surface 431 of the cover electrode 43. In one example, the second metal film 442 is made of a material containing Pd.

[0049] The electrode 40 is electrically connected to the interlayer wiring 36 by a via wiring 37. The via wiring 37 is embedded in a via hole 375 arranged in the insulating film 33. In FIGS. 5 and 7, the via hole 375 penetrates the top insulating film 35 and the interlayer insulating film 34. The via wiring 37 has a layered structure including a barrier film 371 and a via body 372. The barrier film 371 covers the inner surface of the via hole 375 in a film-like manner. In one example, the barrier film 371 is made of a material containing Ti. The via body 372 is embedded in the via hole 375 with the barrier film 371 sandwiched therebetween. In one example, the via body 372 is made of a material containing W.

[0050] (insulating layer) As shown in FIGS. 5 and 7, the insulating layer 50 covers the surface 351 of the top insulating film 35 and a part of the electrode 40 .

[0051] The insulating layer 50 includes an opening 51 that exposes a portion of the electrode 40. In one example, the opening 51 has a circular shape in a plan view. The electrode 40 includes an exposed portion 40A that is exposed by the opening 51 in the insulating layer 50, and an unexposed portion 40B that is covered by the insulating layer 50.

[0052] The insulating layer 50 includes a peripheral edge portion 52 outside the opening 51. The peripheral edge portion 52 overlaps with the electrode 40 in a plan view. The peripheral edge portion 52 may be a portion that covers the electrode 40. The surface 53 of the peripheral edge portion 52 includes a first surface 531 and a second surface 532. The second surface 532 is a surface outside the first surface 531.

[0053] Peripheral edge portion 52 includes an open end 541 that constitutes opening 51 that exposes a portion of electrode 40. Open end 541 is an annular region that surrounds exposed portion 40A of electrode 40 with circular opening 51 in plan view.

[0054] Peripheral portion 52 includes flat portion 542 that is outward from opening end 541 and has a flat surface. In one example, second surface 532 includes the surface of flat portion 542. First surface 531 includes a surface that slopes obliquely downward in an arc from second surface 532 toward opening 51. First surface 531 can be said to be the surface of opening end 541. In other words, the surface of opening end 541 can be said to be a surface that slopes obliquely downward in an arc from the surface of flat portion 542 toward opening 51. Surface 53 of peripheral portion 52 can be said to include flat second surface 532 and first surface 531 that is inward from second surface 532 and slopes toward exposed portion 40A of electrode 40.

[0055] (electrode terminal) 5 to 8 , the electrode terminal 60 is electrically connected to the electrode 40 exposed from the opening 51 of the insulating layer 50. The electrode 40 includes an exposed portion 40A exposed by the opening 51 of the insulating layer 50. The electrode terminal 60 is electrically connected to the exposed portion 40A of the electrode 40.

[0056] The electrode terminal 60 protrudes in the Z-axis direction from the electrode upper surface 401 of the electrode 40. The electrode terminal 60 protrudes in the Z-direction from the surface 53 of the peripheral portion 52 of the insulating layer 50. The electrode terminal 60 has a columnar shape. In one example, the electrode terminal 60 has a cylindrical shape.

[0057] The electrode terminal 60 is in contact with the exposed portion 40A of the electrode 40 exposed by the opening 51 in the insulating layer 50. When viewed from the thickness direction, the electrode terminal 60 partially overlaps the insulating layer 50. The electrode terminal 60 is provided across both the exposed portion 40A of the electrode 40 and the peripheral portion 52 of the opening 51 in the insulating layer 50.

[0058] The electrode terminal 60 includes a terminal back surface 602 facing the electrode 40, and a terminal front surface 601 opposite the terminal back surface 602. The electrode terminal 60 includes a terminal side surface 603 connecting the terminal back surface 602 and the terminal front surface 601. The terminal back surface 602 includes a first portion 602A in contact with the exposed portion 40A of the electrode 40, and a second portion 602B in contact with the peripheral edge portion 52 of the insulating layer 50. The second portion 602B of the terminal back surface 602 surrounds the first portion 602A of the terminal back surface 602.

[0059] (base layer) The electrode terminal 60 may include a base layer 61. The base layer 61 is provided across both the exposed portion 40A of the electrode 40 and the peripheral edge 52 of the opening 51 in the insulating layer 50. The base layer 61 is in contact with both the exposed portion 40A of the electrode 40 and the peripheral edge 52 of the insulating layer 50. The base layer 61 includes an upper surface 611 and a lower surface 612 opposite to the upper surface 611. The lower surface 612 of the base layer 61 is in contact with both the exposed portion 40A of the electrode 40 and the surface 53 of the peripheral edge 52 of the insulating layer 50. In one example, the lower surface 612 of the base layer 61 forms the terminal back surface 602 of the electrode terminal 60. The base layer 61 includes an outer circumferential edge 613.

[0060] The upper surface 611 of the base layer 61 includes a first region 611A and a second region 611B. It can be said that the base layer 61 has an upper surface 611 that includes the first region 611A and the second region 611B. The first region 611A overlaps the exposed portion 40A of the electrode 40 in a plan view. The first region 611A also overlaps a portion of the periphery 52 of the opening 51 in the insulating layer 50. In one example, the first region 611A overlaps the first surface 531 of the insulating layer 50. The first region 611A overlaps the exposed portion 40A of the electrode 40 and the first surface 531 of the insulating layer 50 in a plan view. The second region 611B is disposed outward from the first region 611A. The second region 611B is an annular region that surrounds the first region 611A. In a plan view, the second region 611B overlaps with the flat portion 542 of the insulating layer 50. That is, in a plan view, the second region 611B overlaps with the second surface 532 of the insulating layer 50. The second region 611B can be said to be a flat surface. In a plan view, the area of ​​the first region 611A is larger than the area of ​​the second region 611B.

[0061] The base layer 61 may have a laminated structure or a single layer structure. For example, the base layer 61 has a laminated structure including a barrier layer 62 and a seed layer 63. The layer configuration of the base layer 61 can be changed as desired.

[0062] The barrier layer 62 contacts both the exposed portion 40A of the electrode 40 and the surface 53 of the peripheral portion 52 of the insulating layer 50. In one example, the barrier layer 62 forms the lower surface 612 of the base layer 61. The barrier layer 62 may be made of a material containing at least one of Ti, TiN, Ta, W, Mo, Cr, and Ru (ruthenium). In one example, the barrier layer 62 is made of a material containing Ti. The barrier layer 62 may have a single-layer structure or a multilayer structure. In one example, the thickness of the barrier layer 62 may be 0.15 μm.

[0063] The seed layer 63 covers the barrier layer 62. The seed layer 63 covers the entire barrier layer 62. For example, the seed layer 63 forms the upper surface 611 of the base layer 61. The seed layer 63 is made of a material containing Cu. The seed layer 63 may have a single-layer structure or a multilayer structure. For example, the thickness of the seed layer 63 may be 0.25 μm.

[0064] In one example, the barrier layer 62 and the seed layer 63 are sputtered layers. The barrier layer 62 and the seed layer 63 are formed using sputtering. That is, in one example, the base layer 61 is a sputtered layer. The base layer 61 is formed using sputtering. In one example, the size of the barrier layer 62 and the size of the seed layer 63 are equal in plan view. Therefore, the side surfaces of the barrier layer 62 and the seed layer 63 are flush with each other. In plan view, the barrier layer 62 may be larger than the seed layer 63. In plan view, the barrier layer 62 may be smaller than the seed layer 63. The outer peripheral edge 613 of the base layer 61 may be referred to as the outer peripheral edge of the barrier layer 62. The outer peripheral edge 613 of the base layer 61 may be referred to as the outer peripheral edge of the seed layer 63.

[0065] (Terminals, base) The electrode terminal 60 includes a terminal portion 64 and a pedestal portion 66. In one example, the terminal portion 64 and the pedestal portion 66 are bonded to the upper surface 611 of the base layer 61. The electrode terminal 60 can be said to include the terminal portion 64 and the pedestal portion 66 bonded to the upper surface of the base layer 61. The terminal portion 64 is bonded to a first region 611A of the upper surface 611 of the base layer 61. The pedestal portion 66 is bonded to a second region 611B of the upper surface 611 of the base layer 61. The electrode terminal 60 can be said to include the terminal portion 64 bonded to the first region 611A of the upper surface 611 of the base layer 61, and the pedestal portion 66 bonded to the second region 611B of the upper surface 611 of the base layer 61. The second region 611B is disposed outward from the first region 611A. The pedestal portion 66 can be said to be disposed outward from the terminal portion 64.

[0066] The terminal portion 64 stands upright from the first region 611A. The terminal portion 64 has a columnar shape. In one example, the terminal portion 64 may have a cylindrical shape. The shape of the terminal portion 64 may be changed as desired.

[0067] The terminal portion 64 includes a terminal portion front surface 641 and a terminal portion back surface 642 opposite the terminal portion front surface 641. The terminal portion back surface 642 faces the electrode 40. It can be said that the terminal portion 64 includes the terminal portion back surface 642 facing the electrode 40. The terminal portion 64 includes a terminal portion side surface 643 that intersects with the terminal portion back surface 642. The terminal portion 64 may include a surface recess 644. The surface recess 644 is recessed from the terminal portion front surface 641.

[0068] A portion of the terminal portion back surface 642 faces the exposed portion 40A of the electrode 40. A portion of the terminal portion back surface 642 faces the peripheral edge portion 52 of the insulating layer 50. It can be said that the terminal portion 64 includes the terminal portion back surface 642 that faces the exposed portion 40A of the electrode 40 and the peripheral edge portion 52 of the insulating layer 50. The terminal portion back surface 642 is in contact with the upper surface 611 of the base layer 61. The terminal portion 64 is electrically connected to the base layer 61. The base layer 61 is electrically connected to the exposed portion 40A of the electrode 40. Therefore, the terminal portion 64 is electrically connected to the electrode 40.

[0069] The pedestal portion 66 is connected to the terminal portion 64. The pedestal portion 66 protrudes outward from a terminal portion side surface 643 of the terminal portion 64. The pedestal portion 66 protrudes outward from a portion 645 of the terminal portion side surface 643 of the terminal portion 64 that is closer to a terminal portion back surface 642 of the terminal portion 64. As shown in FIG. 6 , the pedestal portion 66 is provided along the terminal portion side surface 643 of the terminal portion 64, over the entire terminal portion 64. It can be said that the pedestal portion 66 has a ring shape in a plan view.

[0070] The pedestal portion 66 includes a pedestal portion back surface 662. The pedestal portion back surface 662 faces the surface 53 of the peripheral portion 52 of the insulating layer 50. It can be said that the pedestal portion 66 includes the pedestal portion back surface 662 that faces the insulating layer 50. The pedestal portion back surface 662 is in contact with the upper surface 611 of the base layer 61. The pedestal portion back surface 662 is in contact with the second region 611B of the upper surface 611 of the base layer 61. It can be said that the pedestal portion 66 is joined to the upper surface 611 of the base layer 61 by the pedestal portion back surface 662.

[0071] The base 66 includes a base front surface 661 opposite to a base back surface 662. The base front surface 661 intersects with a terminal side surface 643 of the terminal 64. The base 66 includes a base side surface 663. The base side surface 663 intersects with the base back surface 662. It can be said that the base 66 includes the base side surface 663 that intersects with the base back surface 662. The base side surface 663 intersects with the base surface 661. It can be said that the base 66 includes the base side surface 663 that intersects with the base surface 661.

[0072] The base portion 66 includes a curved surface 664. The curved surface 664 is provided between the base portion back surface 662 and the base portion side surface 663. The curved surface 664 can be said to be a surface that connects the base portion back surface 662 and the base portion side surface 663. The curved surface 664 is curved so as to be convex outward from the base portion 66. The curved surface 664 may be a surface that protrudes outward in an arc shape. The sealing resin 70 penetrates between the curved surface 664 of the base portion 66 and the insulating layer 50. Furthermore, the sealing resin 70 penetrates between the curved surface 664 of the base portion 66 and the base layer 61.

[0073] As shown in FIG. 8 , the base portion back surface 662 includes an outer peripheral edge 665. The outer peripheral edge 665 is an end of the base portion back surface 662 that contacts the upper surface 611 of the base layer 61 and is closer to the base portion side surface 663. The base portion back surface 662 is connected to the base portion side surface 663 by a curved surface 664. The curved surface 664 is located more inward of the electrode terminal 60 than the base portion side surface 663. The base portion 66 protrudes outward from the terminal portion side surface 643 of the terminal portion 64. Therefore, the outer peripheral edge 665 of the base portion back surface 662 is located between the terminal portion side surface 643 of the terminal portion 64 and the base portion side surface 663 of the base portion 66 in a plan view.

[0074] The outer peripheral edge 613 of the base layer 61 may be located outward from a terminal portion side surface 643 of the terminal portion 64 in a plan view. The outer peripheral edge 613 of the base layer 61 may be located outward from a outer peripheral edge 665 of a base portion back surface 662 of the base portion 66 in a plan view. In one example, the outer peripheral edge 613 of the base layer 61 may be located between the outer peripheral edge 665 of the base portion back surface 662 and the base portion side surface 663 in a plan view.

[0075] A base back surface 662 of the base portion 66 is connected to a curved surface 664 of the base portion 66. An outer peripheral edge 665 of the base back surface 662 can be said to be an inner peripheral edge 666 of the curved surface 664. The inner peripheral edge 666 of the curved surface 664 can be said to be located between a terminal portion side surface 643 of the terminal portion 64 and the base portion side surface 663 of the base portion 66 in a plan view. The inner peripheral edge 666 of the curved surface 664 can be said to be located inside the outer peripheral edge 613 of the base layer 61. The inner peripheral edge 666 of the curved surface 664 can be said to be located between the outer peripheral edge 613 of the base layer 61 and the terminal portion side surface 643 of the terminal portion 64 in a plan view.

[0076] The terminal portion 64 and the base portion 66 are made of the same material. In one example, the terminal portion 64 and the base portion 66 are made of a material containing Cu. The terminal portion 64 and the base portion 66 may be a single body that is physically connected to each other. In one example, the terminal portion 64 and the base portion 66 are plated layers. The terminal portion 64 and the base portion 66 are formed using a plating method.

[0077] (Joining layer) The semiconductor element 30 may include a bonding layer 68 provided on the terminal surface 601. The bonding layer 68 may be used for external connection. In one example, the bonding layer 68 is used to mount the semiconductor element 30 to the connection terminal 20.

[0078] The bonding layer 68 may include a first layer 681 and a second layer 682. The first layer 681 is provided on the terminal surface 601 of the electrode terminal 60. The first layer 681 of the bonding layer 68 covers the terminal surface 601 of the electrode terminal 60. The first layer 681 of the bonding layer 68 is in contact with the terminal surface 601 of the electrode terminal 60. For example, the first layer 681 of the bonding layer 68 may be made of a material containing Ni and Fe. The first layer 681 may be a barrier layer.

[0079] The second layer 682 is provided on the first layer 681. The second layer 682 is in contact with the first layer 681. The bonding layer 68 can be said to have a laminated structure including the first layer 681 and the second layer 682 disposed on the first layer 681. The second layer 682 may be made of solder containing Sn. In one example, the second layer 682 may contain SnAg. As shown in FIG. 7 , before the electrode terminal 60 is bonded to the connection terminal 20, the second layer 682 has an arc-shaped surface.

[0080] The first layer 681 of the bonding layer 68 is interposed between the second layer 682 of the bonding layer 68 and the terminal portion 64 of the electrode terminal 60. The second layer 682 may be made of solder. The first layer 681 of the bonding layer 68 may be made of a metal material that suppresses a chemical reaction between the second layer 682 of the bonding layer 68 and the terminal portion 64 of the electrode terminal 60. In one example, the terminal portion 64 contains Cu and the second layer 682 contains Sn, while the first layer 681 may be made of a material containing Ni.

[0081] 6, the size of the electrode terminal 60, ie, the diameter D1 of the electrode terminal 60, may be indicated as the diameter of the terminal portion 64 at the terminal portion side surface 643, i.e., the size of the terminal portion 64. The diameter D1 of the electrode terminal 60 may be 10 μm or more and 150 μm or less.

[0082] 8, the thickness T11 of the terminal portion 64 may be expressed as the distance in the thickness direction from the upper surface 611 of the base layer 61 above the peripheral edge portion 52 of the insulating layer 50 to the upper end of the terminal portion side surface 643. As an example, the thickness T11 of the terminal portion 64 may be not less than 10 μm and not more than 100 μm.

[0083] The thickness T12 of the pedestal 66 may be expressed as the distance from the pedestal back surface 662 to the pedestal front surface 661 in the thickness direction. The thickness T12 of the pedestal 66 may be 5 μm or more and 20 μm or less. In one example, the thickness T12 of the pedestal 66 may be 10 μm.

[0084] The width W1 of the pedestal portion 66 may be expressed as the length of the pedestal portion 66 extending outward. The width W1 of the pedestal portion 66 may be expressed as the distance from the terminal portion side surface 643 of the terminal portion 64 to the pedestal portion side surface 663 of the pedestal portion 66 in a direction perpendicular to the thickness direction, for example, in the X-axis direction. The width W1 of the pedestal portion 66 may be 10 μm or more and 40 μm or less.

[0085] The width W11 of the pedestal back surface 662 of the pedestal 66 may be expressed as the distance from the terminal portion side surface 643 of the terminal portion 64 to the outer peripheral edge 665 of the pedestal back surface 662 of the pedestal 66 in a direction perpendicular to the thickness direction, for example, the X-axis direction, in a plan view. The width W11 of the pedestal back surface 662 may be 8 μm or more and 35 μm or less. For example, the width W11 of the pedestal back surface 662 may be 8 μm.

[0086] The width W11 of the base back surface 662 may be larger than the width W12 of the curved surface 664 in a plan view. The width W12 of the curved surface 664 may be the distance from the inner peripheral end 666 of the curved surface 664 to the base side surface 663 of the base 66. The width W12 of the curved surface 664 may be the distance from the outer peripheral end 665 of the base back surface 662 to the base side surface 663 of the base 66. In a plan view, the width W12 of the curved surface 664 may be, for example, 1 μm or more and 4 μm or less. In a plan view, the width W11 of the base back surface 662 may be larger than the distance L1 between the inner peripheral end 666 of the curved surface 664 and the outer peripheral end 613 of the base layer 61. In plan view, the distance L1 between the inner peripheral edge 666 of the curved surface 664 of the pedestal portion 66 and the outer peripheral edge 613 of the base layer 61 may be, for example, 2 μm or less.

[0087] The bonding layer 68 includes a first layer 681 covering the terminal surface 641 of the terminal 64 and a second layer 682 on the first layer 681. The thickness T21 of the first layer 681 is smaller than the thickness T22 of the second layer 682. The thickness T22 of the second layer 682 may be shown in a state before bonding to the connection terminal 20 shown in FIG. 5. The thickness T22 of the second layer 682 may be shown as the distance from the surface at the outer circumferential edge of the first layer 681 to the apex of the second layer 682 in the Z-axis direction on the surface of the second layer 682. For example, the thickness T21 of the first layer 681 may be 1 μm or more and 5 μm or less. For example, the thickness T22 of the second layer 682 may be 10 μm or more and 50 μm or less. For example, the thickness T21 of the first layer 681 may be 3 μm. For example, the thickness T22 of the second layer 682 may be 30 μm.

[0088] (Method of manufacturing a semiconductor device) Next, an example of a method for manufacturing the semiconductor device 10 will be described. 9 to 18, an example of a method for manufacturing the semiconductor element 30 will be described, mainly the electrode terminals 60. An example of a method for manufacturing the semiconductor device 10 including the semiconductor element 30 will be described with reference to FIGS.

[0089] 9 to 18 are cross-sectional views showing an example of a manufacturing process for the semiconductor element 30 shown in FIGS. 5 to 8. In FIGS. 9 to 18, an example of a manufacturing method for the portion relating mainly to the electrode terminals 60 will be described. FIGS. 9 to 18 are cross-sectional views corresponding to the cut surfaces of FIGS. 5 and 7. FIG. 19 is a cross-sectional view showing the bonding of the semiconductor element 30 to the connection terminals 20. FIG. 20 is a cross-sectional view showing the formation of the sealing resin 70. For ease of understanding, in FIGS. 9 to 20, components similar to those in FIGS. 5 and 7 are denoted by the same reference numerals.

[0090] 9, a wafer 801 including a multilayer wiring structure 38 is prepared. The outermost surface of the multilayer wiring structure 38 is composed of the top insulating film 35 with a plurality of via wirings 37 exposed.

[0091] 9, the method for manufacturing the semiconductor device 30 includes forming an electrode 40. The electrode 40 is formed on the top insulating film 35. In one example, the electrode 40 includes a wiring barrier film 41, a wiring electrode 42, and a cover electrode 43. The cover electrode 43 includes a first metal film 441 and a second metal film 442.

[0092] First, a wiring barrier film 41 and a seed layer are formed on the top surface of the top insulating film 35. For example, the wiring barrier film 41 and the seed layer may each be formed by sputtering. A mask is formed on the seed layer. The mask includes openings in areas where the electrodes 40 are to be formed. The mask is obtained by forming a photosensitive resist film and forming openings in the resist film by photolithography. The resist film is obtained by attaching a sheet-like photosensitive resin or applying a liquid photosensitive resin. Next, the wiring electrode 42 and the cover electrode 43 (first metal film 441 and second metal film 442) are formed in the openings of the mask. For example, the wiring electrode 42 and the cover electrode 43 may be formed by a plating method (electrolytic plating method or electroless plating method). After removing the mask, the seed layer and the wiring barrier film 41 exposed from the wiring electrode 42 are removed. The seed layer and the wiring barrier film 41 may be removed by an etching method (e.g., wet etching method).

[0093] 10, the method for manufacturing the semiconductor device 30 includes forming an insulating layer 50. The insulating layer 50 includes an opening 51. A photosensitive resin that serves as the base of the insulating layer 50 is formed on the top insulating film 35. The photosensitive resin may be in liquid or film form. The photosensitive resin is formed so as to cover the electrode 40. The photosensitive resin is subjected to photolithography and curing to form the insulating layer 50 that includes an opening 51 that exposes a portion of the electrode 40. The electrode 40 includes an exposed portion 40A that is exposed by the opening 51 in the insulating layer 50.

[0094] 11, the method for manufacturing the semiconductor device 30 includes forming a base layer 61. In one example, the base layer 61 includes a barrier layer 62 and a seed layer 63. A base layer 61 is formed on the exposed portion 40A of the electrode 40 and the insulating layer 50. A barrier layer 62 is formed on the exposed portion 40A of the electrode 40 and the insulating layer 50. The barrier layer 62 is made of a material containing Ti, for example. The barrier layer 62 may be formed by sputtering, for example. A seed layer 63 is formed on the barrier layer 62. The seed layer 63 is made of a material containing Cu, for example. The seed layer 63 may be formed by sputtering, for example.

[0095] 12, the method for manufacturing the semiconductor element 30 includes forming a first mask 802. The first mask 802 is formed on the base layer 61. The first mask 802 includes a first opening 803 that exposes a region of the base layer 61 where the pedestal portion 66 of the electrode terminal 60 is to be formed.

[0096] The first mask 802 is obtained, for example, by forming a photosensitive resist film on the base layer 61 and forming first openings 803 in the resist film by photolithography. The resist film is obtained, for example, by applying a liquid photosensitive resin. The resist film may be a positive type. The first openings 803 in the first mask 802 are formed to expose regions of the base layer 61 that are to become the first region 611A and the second region 611B. The thickness of the first mask 802 may be set according to the thickness T12 of the pedestal portion 66 shown in FIG. 8.

[0097] The first mask 802 includes an inner wall surface 804 that defines the first opening 803. The first mask 802 includes a protrusion 805 that protrudes from the inner wall surface 804 toward the inside of the first opening 803 at a lower end of the inner wall surface 804 that is closer to the seed layer 63. The protrusion 805 has a curved surface 806 that is recessed toward the inside of the protrusion 805. This protrusion 805 may be called a skirt of the first mask 802. The curved surface 806 of the protrusion 805 may be formed by the photolithography conditions for the resist film. The curved surface 806 of the protrusion 805 forms the curved surface 664 of the pedestal 66 shown in FIGS. 5, 7, and 8.

[0098] 13, the method for manufacturing the semiconductor element 30 includes forming a second mask 810. The second mask 810 is formed on the first mask 802. The second mask 810 is formed so as to cover the entire upper surface 807 of the first mask 802. The second mask 810 includes second openings 811 corresponding to the terminal portions 64 of the electrode terminals 60. The second openings 811 of the second mask 810 are formed so as to overlap with the first openings 803 of the first mask 802 in the Z direction. Furthermore, the second openings 811 of the second mask 810 are smaller than the first openings 803 of the first mask 802 in a plan view.

[0099] The second mask 810 is obtained, for example, by forming a photosensitive resist film on the first mask 802 and forming the second openings 811 in the resist film by photolithography. The resist film is obtained, for example, by attaching a sheet-like photosensitive resin. The resist film may be a positive type, for example. The second openings 811 in the second mask 810 are formed according to the shape of the terminal portions 64.

[0100] 14 , the method for manufacturing the semiconductor element 30 includes forming the terminal portions 64 and the pedestal portion 66. In one example, the terminal portions 64 and the pedestal portion 66 are formed by depositing a material that forms the terminal portions 64 and the pedestal portion 66 by plating (for example, electrolytic plating) on ​​the surface of the base layer 61 that is exposed from the first mask 802. The terminal portions 64 and the pedestal portion 66 are formed in the first openings 803 of the first mask 802 and the second openings 811 of the second mask 810.

[0101] 15, the method for manufacturing semiconductor element 30 includes forming bonding layer 68. Bonding layer 68 includes a first layer 681 and a second layer 682. First layer 681 is formed on terminal portion 64, and second layer 682 is formed on first layer 681. In one example, first layer 681 and second layer 682 of bonding layer 68 are formed by depositing a material constituting first layer 681 and a material constituting second layer 682 in this order in second opening 811 of second mask 810 using a plating method (e.g., electrolytic plating).

[0102] 16, the method for manufacturing the semiconductor device 30 includes removing the first mask 802 and the second mask 810 shown in FIG. 15. In one example, the first mask 802 and the second mask 810 are removed using a stripping solution.

[0103] 17, the manufacturing method of the semiconductor device 30 includes forming a base layer 61. The base layer 61 shown in Fig. 17 is formed by removing the portions of the base layer 61 shown in Fig. 16 that are exposed from the electrode terminals 60. The unnecessary portions of the base layer 61 are removed by etching (e.g., wet etching).

[0104] In this step, the terminal portion 64 and the pedestal portion 66 are removed from their respective surfaces together with unnecessary portions of the base layer 61. Therefore, the terminal portion surface 641 of the terminal portion 64 is located inward from the outer peripheral edge of the first layer 681 of the bonding layer 68 into the terminal portion 64. In addition, the outer peripheral edge 613 of the base layer 61 is located inward from the terminal portion 64 with respect to the pedestal portion side surface 663 of the pedestal portion 66 in a plan view.

[0105] 18, the method for manufacturing the semiconductor device 30 includes forming the second layer 682 of the bonding layer 68. In one example, the second layer 682 of the bonding layer 68 is formed into a hemispherical shape by a reflow process. The reflow process may be performed before removing unnecessary portions of the base layer 61. The wafer 801 is then selectively cut. In this way, the semiconductor device 30 is manufactured.

[0106] 19, the method for manufacturing the semiconductor device 10 includes preparing the connection terminals 20. The connection terminals 20 are formed as parts of a lead frame, for example. The manufacturing method of the semiconductor device 10 includes mounting the semiconductor element 30 on the connection terminal 20. The semiconductor element 30 is placed on the connection terminal 20 with the electrode terminal 60 and the bonding layer 68 facing the connection terminal 20, and the electrode terminal 60 of the semiconductor element 30 is electrically connected to the connection terminal 20 by the second layer 682 of the bonding layer 68.

[0107] 20, the method for manufacturing the semiconductor device 10 includes forming a sealing resin 70. The semiconductor element 30 and the connection terminals 20 are sealed with the sealing resin 70. In this way, the semiconductor device 10 is manufactured.

[0108] (Operation of the embodiment) Next, the operation of the semiconductor element 30 and the semiconductor device 10 of the embodiment will be described. The semiconductor element 30 includes an electrode 40, an insulating layer 50, and an electrode terminal 60. The electrode 40 is provided on an element surface 301 facing the Z direction. The insulating layer 50 covers the electrode 40 and includes an opening 51 that exposes a portion of the electrode 40. The electrode terminal 60 contacts the exposed portion 40A of the electrode 40 exposed by the opening 51, and partially overlaps the insulating layer 50 when viewed from the thickness direction.

[0109] The electrode terminal 60 includes a terminal portion 64 and a pedestal portion 66. The terminal portion 64 is provided across both the exposed portion 40A of the electrode 40 and the peripheral portion 52 of the opening 51 in the insulating layer 50. The terminal portion 64 is in contact with the exposed portion 40A. The terminal portion 64 includes a terminal portion back surface 642 and a terminal portion side surface 643. The terminal portion back surface 642 is in contact with the exposed portion 40A and the peripheral portion 52. The terminal portion side surface 643 intersects with the terminal portion back surface 642. The pedestal portion 66 protrudes outward from a portion 645 of the terminal portion side surface 643 of the terminal portion 64 that is closer to the terminal portion back surface 642. The pedestal portion 66 includes a pedestal portion back surface 662, a pedestal portion side surface 663, and a curved surface 664. The pedestal portion back surface 662 is in contact with the insulating layer 50. Base side surface 663 intersects with base back surface 662 and is positioned outward of terminal side surface 643. Curved surface 664 is provided between base back surface 662 and base side surface 663.

[0110] The semiconductor device 10 includes a semiconductor element 30 , connection terminals 20 connected to electrode terminals 60 of the semiconductor element 30 , and a sealing resin 70 that seals the semiconductor element 30 and the connection terminals 20 . Here, a semiconductor device and a semiconductor element of a comparative example will be described in comparison with the semiconductor device 10 and the semiconductor element 30 of the embodiment. Note that the same components of the semiconductor device and the semiconductor element of the comparative example will be described using the same reference numerals as those of the semiconductor device 10 and the semiconductor element 30 of the embodiment. The semiconductor element of the comparative example does not include the pedestal 66 of the embodiment. That is, the electrode terminals of the semiconductor element of the comparative example include corner portions between the terminal portion side surface 643 and the terminal portion back surface 642. In the semiconductor device of the comparative example, stress due to temperature changes in the sealing resin 70 or stress remaining during the manufacturing process may concentrate near the corner portions of the electrode terminals of the semiconductor element of the comparative example. Such stress concentration can cause cracks in the insulating layer 50, peeling of the sealing resin 70, and the like.

[0111] In the semiconductor element 30 of this embodiment, the electrode terminal 60 includes a terminal portion 64 and a pedestal portion 66 protruding outward from a terminal portion side surface 643 of the terminal portion 64. The pedestal portion 66 includes a pedestal portion back surface 662 facing the front surface 53 of the insulating layer 50, a pedestal portion side surface 663 intersecting with the pedestal portion back surface 662, and a curved surface 664 provided between the pedestal portion back surface 662 and the pedestal portion side surface 663. The sealing resin 70 is inserted between the curved surface 664 of the pedestal portion 66 and the insulating layer 50. This curved surface 664 can reduce stress concentration at the end of the pedestal portion 66 closer to the insulating layer 50. This can suppress cracking of the insulating layer 50, peeling of the sealing resin 70, and the like. This improves the reliability of the semiconductor device 10.

[0112] The electrode terminal 60 of the semiconductor element 30 of the embodiment includes a terminal portion 64 and a pedestal portion 66 that protrudes outward from a terminal portion side surface 643 of the terminal portion 64. The electrode terminal 60 also includes a base layer 61 that contacts both the exposed portion 40A of the electrode 40 and the peripheral edge portion 52 of the insulating layer 50. The terminal portion 64 and the pedestal portion 66 are in contact with the base layer 61.

[0113] In a test on the semiconductor element 30, such as a shear strength test, a force is applied to the electrode terminal 60 in a direction intersecting the Z-axis direction, e.g., the X-axis direction. For example, when forming the sealing resin 70 that seals the semiconductor element 30, a force is applied to the electrode terminal 60 in a direction intersecting the Z-axis direction. In the case of an electrode terminal that does not include the pedestal portion 66 of the embodiment, the force in the X-axis direction is applied directly to the terminal portion 64, which may result in the terminal portion 64 peeling off from the base layer 61. In contrast, in the electrode terminal 60 of the embodiment, when a force in the X-axis direction is applied to the terminal portion 64, the pedestal portion 66 limits the inclination of the terminal portion 64. This prevents the terminal portion 64 and the pedestal portion 66 from peeling off from the base layer 61. This improves the shear strength of the electrode terminal 60. As a result, the reliability of the semiconductor element 30 is improved. Furthermore, the reliability of the semiconductor device 10 including this semiconductor element 30 is improved.

[0114] The base portion 66 is in a frame shape so as to surround the opening, which can prevent the terminal portion 64 from peeling off due to a force in a direction intersecting the Z-axis direction, thereby further improving the reliability of the semiconductor element 30.

[0115] The electrode terminals 60 have a circular shape when viewed from the thickness direction. If the electrode terminals 60 were prismatic, stress due to temperature changes in the sealing resin 70 or stress remaining during the manufacturing process could be concentrated at the corners. Stress concentration at the corners could cause cracks to occur in the sealing resin 70. In contrast, in the semiconductor device 10 of the embodiment, the electrode terminals 60 of the semiconductor element 30 have a circular shape when viewed from the Z-axis direction, so that stress concentration at the electrode terminals 60 can be suppressed.

[0116] The base layer 61 includes a barrier layer 62 in contact with both the exposed portion 40A and the peripheral edge portion 52 of the insulating layer 50, and a seed layer 63 having a lower surface 632 in contact with the barrier layer 62 and an upper surface 611 including a first region 611A and a second region 611B. The barrier layer 62 can relieve stress applied to the insulating layer 50 from the electrode terminal 60.

[0117] The bonding layer 68 includes a first layer 681 on the terminal surface 601 and a second layer 682 on the first layer 681. In one example, the first layer 681 is made of a material containing Ni. In one example, the second layer 682 is a solder layer made of a material containing Sn. Therefore, by melting the second layer 682, the electrode terminal 60 and the connection terminal 20 can be easily bonded. In addition, since the first layer 681 is interposed between the terminal portion 64 of the electrode terminal 60 and the second layer 682 of the bonding layer 68, a chemical reaction between the terminal portion 64 containing Cu and the second layer 682 containing Sn can be suppressed.

[0118] (Effects of the embodiment) As described above, the semiconductor device 10 of this embodiment provides the following advantages. (1) The semiconductor element 30 includes an electrode 40, an insulating layer 50, and an electrode terminal 60. The electrode 40 is provided on an element surface 301 facing the Z direction. The insulating layer 50 covers the electrode 40 and includes an opening 51 that exposes a portion of the electrode 40. The electrode terminal 60 contacts the exposed portion 40A of the electrode 40 exposed by the opening 51, and partially overlaps the insulating layer 50 when viewed from the thickness direction.

[0119] The electrode terminal 60 includes a terminal portion 64 and a pedestal portion 66. The terminal portion 64 is provided across both the exposed portion 40A and the peripheral portion 52 of the opening 51 in the insulating layer 50. The terminal portion 64 is in contact with the exposed portion 40A. The terminal portion 64 includes a terminal portion back surface 642 and a terminal portion side surface 643. The terminal portion back surface 642 is in contact with the exposed portion 40A and the peripheral portion 52. The terminal portion side surface 643 intersects with the terminal portion back surface 642. The pedestal portion 66 protrudes outward from a portion 645 of the terminal portion side surface 643 of the terminal portion 64 that is closer to the terminal portion back surface 642. The pedestal portion 66 includes a pedestal portion back surface 662, a pedestal portion side surface 663, and a curved surface 664. The pedestal portion back surface 662 is in contact with the insulating layer 50. Base side surface 663 intersects with base back surface 662 and is positioned outward of terminal side surface 643. Curved surface 664 is provided between base back surface 662 and base side surface 663.

[0120] The semiconductor device 10 includes a semiconductor element 30 , connection terminals 20 connected to electrode terminals 60 of the semiconductor element 30 , and a sealing resin 70 that seals the semiconductor element 30 and the connection terminals 20 . The electrode terminal 60 includes a terminal portion 64 and a pedestal portion 66 protruding outward from a terminal portion side surface 643 of the terminal portion 64. The pedestal portion 66 includes a pedestal portion back surface 662 facing the front surface 53 of the insulating layer 50, a pedestal portion side surface 663 intersecting with the pedestal portion back surface 662, and a curved surface 664 provided between the pedestal portion back surface 662 and the pedestal portion side surface 663. This curved surface 664 can reduce stress concentration at the end of the pedestal portion 66 closer to the insulating layer 50. This can suppress the occurrence of cracks in the insulating layer 50, peeling of the sealing resin 70, and the like. This can improve the reliability of the semiconductor device 10.

[0121] (2) The electrode terminal 60 of the semiconductor element 30 according to the embodiment includes a terminal portion 64 and a pedestal portion 66 that protrudes outward from a terminal portion side surface 643 of the terminal portion 64. The electrode terminal 60 also includes a base layer 61 that contacts both the exposed portion 40A of the electrode 40 and the peripheral edge portion 52 of the insulating layer 50. The terminal portion 64 and the pedestal portion 66 contact the base layer 61.

[0122] In a test on the semiconductor element 30, such as a shear strength test, a force is applied to the electrode terminal 60 in a direction intersecting the Z-axis direction, e.g., the X-axis direction. For example, when forming the sealing resin 70 that seals the semiconductor element 30, a force is applied to the electrode terminal 60 in a direction intersecting the Z-axis direction. In the case of an electrode terminal that does not include the pedestal portion 66 of the embodiment, the force in the X-axis direction is applied directly to the terminal portion 64, which may result in the terminal portion 64 peeling off from the base layer 61. In contrast, in the electrode terminal 60 of the embodiment, when a force in the X-axis direction is applied to the terminal portion 64, the pedestal portion 66 limits the inclination of the terminal portion 64. This prevents the terminal portion 64 and the pedestal portion 66 from peeling off from the base layer 61. This improves the shear strength of the electrode terminal 60. As a result, the reliability of the semiconductor element 30 is improved. Furthermore, the reliability of the semiconductor device 10 including this semiconductor element 30 is improved.

[0123] (3) The base portion 66 is frame-shaped so as to surround the opening. This prevents the terminal portion 64 from peeling off due to a force acting in a direction intersecting the Z-axis direction. This further improves the reliability of the semiconductor element 30.

[0124] (4) The electrode terminals 60 are circular when viewed from the thickness direction. If the electrode terminals 60 are prismatic, stress due to temperature changes in the sealing resin 70 or stress remaining during the manufacturing process may concentrate at the corners. Stress concentration at the corners can cause cracks to occur in the sealing resin 70. In contrast, in the semiconductor device 10 of the embodiment, the electrode terminals 60 of the semiconductor element 30 are circular when viewed from the Z-axis direction, so stress concentration on the electrode terminals 60 can be suppressed.

[0125] (5) The base layer 61 includes a barrier layer 62 in contact with both the exposed portion 40A and the peripheral edge portion 52 of the insulating layer 50, and a seed layer 63 having a lower surface 632 in contact with the barrier layer 62 and an upper surface 611 including a first region 611A and a second region 611B. The barrier layer 62 can relieve stress applied to the insulating layer 50 from the electrode terminal 60.

[0126] (6) The bonding layer 68 includes a first layer 681 on the terminal surface 601 and a second layer 682 on the first layer 681. The first layer 681 is, for example, made of a material containing Ni. The second layer 682 is, for example, a solder layer made of a material containing Sn. Therefore, by melting the second layer 682, the electrode terminal 60 and the connection terminal 20 can be easily bonded. Furthermore, since the first layer 681 is interposed between the terminal portion 64 of the electrode terminal 60 and the second layer 682 of the bonding layer 68, a chemical reaction between the terminal portion 64 containing Cu and the second layer 682 containing Sn can be suppressed.

[0127] (Example of change) The above embodiment can be modified, for example, as follows: The above embodiment and each of the following modified examples can be combined with each other as long as no technical contradiction occurs. In the following modified examples, parts common to the above embodiment will be assigned the same reference numerals as in the above embodiment, and their description will be omitted.

[0128] The configuration of the semiconductor device 10 may be changed as appropriate. The terminal portion 64 may have any shape, such as an ellipse, an oval, or a polygon, in a plan view.

[0129] As shown in FIG. 21 , the semiconductor device 10A includes a semiconductor element 30A. In this semiconductor element 30A, a base layer 61A of an electrode terminal 60A has a single-layer structure. The base layer 61A may be a seed layer, for example. The base layer 61A may be made of a material containing at least one of Ti and Cu. In this semiconductor device 10A, the curved surface 664 of the pedestal portion 66 of the electrode terminal 60 can reduce stress concentration. Furthermore, in this semiconductor device 10A, the pedestal portion 66 in contact with the base layer 61 can prevent the electrode terminal 60A from peeling off.

[0130] As shown in FIG. 22, the semiconductor device 10B includes a semiconductor element 30B. In this semiconductor element 30B, an electrode terminal 60B does not include the base layer 61 shown in FIG. 5 or the base layer 61A shown in FIG. 21. That is, in the electrode terminal 60B, a terminal portion 64 contacts an exposed portion 40A of an electrode 40 and a surface 53 of a peripheral portion 52 of an insulating layer 50. A pedestal portion 66 contacts the surface 53 of a peripheral portion 52 of an insulating layer 50. In this semiconductor device 10B, a curved surface 664 of the pedestal portion 66 can reduce stress concentration. In addition, in this semiconductor device 10B, the pedestal portion 66 in contact with the insulating layer 50 can prevent the electrode terminal 60B from peeling off.

[0131] The positional relationship between the outer circumferential edge 613 of the base layer 61 of the electrode terminal 60 and the base side surface 663 can be changed as appropriate. In one example, the outer circumferential edge 613 of the base layer 61 may be located at the same position as the base side surface 663 when viewed from the thickness direction. The outer circumferential edge 613 of the base layer 61 may be located outward from the base side surface 663.

[0132] The base layer 61 includes a barrier layer 62 and a seed layer 63. In one example, the side surfaces of the barrier layer 62 and the seed layer 63 may be flush with each other. The side surfaces of the barrier layer 62 may be located outward from the side surfaces of the seed layer 63. The side surfaces of the barrier layer 62 may be located inward from the side surfaces of the seed layer 63.

[0133] As shown in FIG. 23, a plurality of pedestals 66 may be provided at intervals along the terminal side surface 643 of the terminal 64. The term "on" as used in this disclosure includes both "on" and "above" unless the context clearly indicates otherwise. Thus, the phrase "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer may be disposed directly on the second layer in contact with the second layer, while in other embodiments, the first layer may be disposed above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which another layer is formed between the first and second layers.

[0134] The Z-axis direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure (for example, the structure shown in FIG. 1 ) are not limited to the "up" and "down" in the Z-axis direction described in this disclosure being "up" and "down" in the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0135] (Addendum) The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the embodiments. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0136] (Appendix 1) an electrode (40) provided on the element surface (301) facing the thickness direction (Z); an insulating layer (50) covering the electrode (40) and including an opening (51) exposing a portion of the electrode (40); an electrode terminal (60) that contacts the exposed portion (40A) of the electrode (40) exposed by the opening (51) and partially overlaps the insulating layer (50) when viewed from the thickness direction (Z); Including, The electrode terminal (60) is a terminal portion (64) that is provided across both the exposed portion (40A) and a peripheral portion (52) of the opening (51) in the insulating layer (50) and is electrically connected to the electrode (40); a base portion (66) connected to the terminal portion (64); Including, The terminal portion (64) is a rear surface (642) of the terminal portion facing the exposed portion (40A) and the peripheral edge portion (52); a terminal portion side surface (643) intersecting the terminal portion back surface (642); Including, The base portion (66) protrudes outward from a portion (645) of the terminal portion side surface (643) of the terminal portion (64) that is closer to the terminal portion back surface (642), The base portion (66) is a base back surface (662) facing the insulating layer (50); a base portion side surface (643) that intersects with the base portion rear surface (662) and is positioned outward of the terminal portion side surface (643); a curved surface (664) provided between the base back surface (662) and the base side surface (643); Including, Semiconductor element.

[0137] (Appendix 2) The curved surface (664) is curved so as to be convex outward from the base portion (66). 2. The semiconductor device of claim 1.

[0138] (Appendix 3) The outer peripheral edge of the base rear surface (662) is located between the terminal portion side surface (643) and the base portion side surface (643) when viewed from the thickness direction (Z). 10. The semiconductor device according to claim 1 or 2.

[0139] (Appendix 4) When viewed from the thickness direction (Z), a width (W11) of the base rear surface (662) is longer than a distance (W12) from the base side surface (643) to an outer peripheral edge (665) of the base rear surface (662). 4. The semiconductor device of claim 3.

[0140] (Appendix 5) The base portion (66) is provided over the entire terminal portion (64) along the terminal portion side surface (643) when viewed from the thickness direction (Z). 5. A semiconductor device according to any one of claims 1 to 4.

[0141] (Appendix 6) The base portion (66) is provided at intervals along the terminal portion side surface (643) when viewed from the thickness direction (Z). 6. A semiconductor device according to any one of claims 1 to 5.

[0142] (Appendix 7) The electrode terminal (60) includes a base layer (61) in contact with both the exposed portion (40A) of the electrode (40) and the peripheral edge portion (52) of the insulating layer (50); Both the terminal portion (64) and the base portion (66) are in contact with the base layer (61). 7. A semiconductor device according to any one of claims 1 to 6.

[0143] (Appendix 8) The outer peripheral edge (613) of the base layer (61) is located between the terminal portion side surface (643) and the base portion side surface (643) when viewed from the thickness direction (Z). 8. The semiconductor device of claim 7.

[0144] (Appendix 9) The outer peripheral edge (613) of the base layer (61) is located outward from the outer peripheral edge (665) of the back surface (662) of the base portion. 9. The semiconductor device of claim 8.

[0145] (Appendix 10) The base layer (61) a barrier layer (62) in contact with both the exposed portion (40A) of the electrode (40) and the peripheral edge portion (52) of the insulating layer (50); a seed layer (63) in contact with the barrier layer; Including, Both the terminal portion (64) and the base portion (66) are in contact with the seed layer (63). 10. The semiconductor device according to claim 8 or 9.

[0146] (Appendix 11) The inner peripheral edge of the curved surface (664) is located inside the outer peripheral edge (613) of the seed layer (63). 11. The semiconductor device of claim 10.

[0147] (Appendix 12) The distance between the inner peripheral edge of the curved surface (664) and the outer peripheral edge (613) of the seed layer (63) is 2 μm. 12. The semiconductor device according to claim 10 or 11.

[0148] (Appendix 13) a width (W11) of the back surface (662) of the base portion is greater than a distance (W12) between an inner peripheral edge of the curved surface (664) and an outer peripheral edge (613) of the seed layer (63); 13. The semiconductor device according to any one of claims 10 to 12.

[0149] (Appendix 14) The terminal portion (64) has a circular shape when viewed from the thickness direction (Z). 14. The semiconductor device according to any one of claims 1 to 13.

[0150] (Appendix 15) The terminal portion (64) includes a terminal portion surface (641) opposite to the terminal portion back surface (642), 15. The semiconductor device of any one of claims 1 to 14.

[0151] (Appendix 16) The terminal portion (64) includes a surface recess (644) extending from the terminal portion surface (641) toward the electrode (40). 16. The semiconductor device of claim 15.

[0152] (Appendix 17) The size (D1) of the terminal portion (64) is 10 μm or more and 150 μm or less. 17. The semiconductor device of any one of claims 1 to 16.

[0153] (Appendix 18) The distance between the terminal portion side surface (643) and the base portion side surface (643) in a direction perpendicular to the thickness direction (Z) is 10 μm or more and 40 μm or less. 18. The semiconductor device of any one of claims 1 to 17.

[0154] (Appendix 19) The thickness of the base portion (66) is 5 μm or more and 20 μm or less. 19. The semiconductor device of any one of claims 1 to 18.

[0155] (Appendix 20) The electrode terminal (60) includes a bonding layer (68) provided on the terminal portion surface (641). 17. The semiconductor device according to claim 15 or 16.

[0156] (Appendix 21) The bonding layer (68) includes a first layer (681) on the terminal portion surface (641) and a second layer (682) on the first layer (681). 21. The semiconductor device of claim 20.

[0157] (Appendix 22) The thickness (T21) of the first layer (681) is smaller than the thickness (T22) of the second layer (682). 22. The semiconductor device of claim 21.

[0158] (Appendix 23) a semiconductor element (30) including electrode terminals (60); a plurality of connection terminals (20) electrically connected to the electrode terminals (60) of the semiconductor element (30); a sealing resin (70) that seals the semiconductor element (30) and the plurality of connection terminals (20); Including, The semiconductor element (30) is an electrode (40) provided on the element surface (301) facing the thickness direction (Z); an insulating layer (50) covering the electrode (40) and including an opening (51) exposing a portion of the electrode (40); the electrode terminal (60) contacting an exposed portion (40A) of the electrode (40) exposed by the opening (51) and partially overlapping the insulating layer (50) when viewed from the thickness direction (Z); Including, The electrode terminal (60) is a terminal portion (64) that is provided across both the exposed portion (40A) and a peripheral portion (52) of the opening (51) in the insulating layer (50) and is electrically connected to the electrode (40); a base portion (66) connected to the terminal portion (64); Including, The terminal portion (64) is a rear surface (642) of the terminal portion facing the exposed portion (40A) and the peripheral edge portion (52); a terminal portion side surface (643) intersecting the terminal portion back surface (642); Including, The base portion (66) protrudes outward from a portion of the terminal portion side surface (643) of the terminal portion (64) that is closer to the terminal portion back surface (642), The base portion (66) is a base back surface (662) facing the insulating layer (50); a base portion side surface (643) that intersects with the base portion rear surface (662) and is positioned outward of the terminal portion side surface (643); a curved surface (664) provided between the base back surface (662) and the base side surface (643); Including, The sealing resin (70) penetrates between the curved surface (664) of the base portion (66) and the insulating layer (50). Semiconductor device.

[0159] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims. [Explanation of symbols]

[0160] 10, 10A, 10B Semiconductor device 11 Device surface 12 Back of the device 13~16 Side of device 20 Connection terminal 201 Connection terminal surface 202 Connection terminal back side 21 Lead section 211 Overhang 22 Pad section 221 Overhang 23 Finger section 30, 30A, 30B Semiconductor elements 301 Element surface 302 Back side of element 303~306 Side of element 31 PCB 311 Substrate surface 312 Back of the board 32 Device Area 33 Insulating film 34 Interlayer insulating film 35 Top insulating film 351 Surface 36 Interlayer wiring 37 Via wiring 371 Barrier membrane 372 via body 375 Beer Hall 38 Multilayer wiring structure 40 electrodes 40A exposed part 40B Non-exposed part 401 Electrode top surface 402 Bottom surface of electrode 41 Wiring barrier film 42 Wiring electrode 421 Wiring top surface 422 Bottom side of wiring 423 Wiring side 424 Upper corner of wiring 43 Cover electrode 431 Top of cover 432 Underside of cover 434 Round Section 441 First metal film 442 Second metal film 50 insulating layer 51 Opening 52 Periphery 53 Surface 531 1st surface 532 2nd surface 541 Open end 542 Flat area 60,60A,60B electrode terminal 601 Terminal surface 602 Terminal back side 602A Part 1 602B 2nd part 603 Terminal side 61,61A Base layer 611 Top surface 611A 1st area 611B 2nd area 612 Bottom surface 613 Outer edge 62 Barrier Layer 63 Seed Layer 632 Bottom surface 64 Terminal section 641 Terminal surface 642 Back side of terminal 643 Terminal side side 644 Surface recess 645 parts 66 Base 661 Base surface 662 Back of base 663 Side of base 664 curved surface 665 Outer edge 666 Inner edge 68 Bonding layer 681 1st layer 682 2nd layer 70 Sealing resin 701 Sealing surface 702 Sealing back side 703 Sealing side 704 Sealing side 705 Sealing side 706 Sealing side 75 Conductive Film D1 diameter L1 distance T11, T12 thickness T21, T22 thickness W1, W11, W12 width

Claims

1. an electrode provided on the surface of the element facing in the thickness direction; an insulating layer covering the electrode and including an opening exposing a portion of the electrode; an electrode terminal that contacts the exposed portion of the electrode exposed by the opening and that partially overlaps the insulating layer when viewed from the thickness direction; Including, The electrode terminal is a terminal portion provided across both the exposed portion and a peripheral portion of the opening in the insulating layer, the terminal portion being electrically connected to the electrode; a base portion connected to the terminal portion; Including, The terminal portion is a rear surface of the terminal portion facing the exposed portion and the peripheral edge portion; a terminal portion side surface intersecting the terminal portion back surface; Including, the base portion protrudes outward from a portion of the terminal portion side surface that is closer to the rear surface of the terminal portion, The base portion is a back surface of a base portion facing the insulating layer; a base portion side surface that intersects with the base portion rear surface and is positioned outward from the terminal portion side surface; a curved surface provided between the back surface of the base portion and the side surface of the base portion; Including, Semiconductor element.

2. The curved surface is curved so as to be convex outward from the base portion. The semiconductor device according to claim 1 .

3. an outer peripheral edge of the back surface of the base portion is located between the terminal portion side surface and the base portion side surface when viewed from the thickness direction; The semiconductor device according to claim 1 .

4. When viewed from the thickness direction, the width of the back surface of the base portion is longer than the distance from the side surface of the base portion to the outer circumferential edge of the back surface of the base portion. The semiconductor device according to claim 3 .

5. The base portion is provided over the entire terminal portion along a side surface of the terminal portion when viewed from the thickness direction. The semiconductor device according to claim 1 .

6. When viewed from the thickness direction, the base portion is provided at a distance from a side surface of the terminal portion. The semiconductor device according to claim 1 .

7. the electrode terminal includes a base layer in contact with both the exposed portion of the electrode and the peripheral edge of the insulating layer; Both the terminal portion and the base portion are in contact with the base layer. The semiconductor device according to claim 1 .

8. an outer peripheral edge of the base layer is located between the terminal portion side surface and the base portion side surface when viewed from the thickness direction; The semiconductor device according to claim 7 .

9. The outer peripheral edge of the base layer is located outward from the outer peripheral edge of the back surface of the base portion. The semiconductor device according to claim 8 .

10. The base layer is a barrier layer in contact with both the exposed portion of the electrode and the peripheral edge of the insulating layer; a seed layer in contact with the barrier layer; Including, both the terminal portion and the pedestal portion are in contact with the seed layer; The semiconductor device according to claim 8 .

11. an inner peripheral edge of the curved surface is located inside an outer peripheral edge of the seed layer; The semiconductor device according to claim 10.

12. the distance between the inner peripheral edge of the curved surface and the outer peripheral edge of the seed layer is 2 μm; The semiconductor device according to claim 10.

13. a width of the rear surface of the pedestal portion is greater than a distance between an inner peripheral edge of the curved surface and an outer peripheral edge of the seed layer; The semiconductor device according to claim 10.

14. The terminal portion has a circular shape when viewed from the thickness direction. The semiconductor device according to claim 1 .

15. The terminal portion includes a terminal portion surface opposite to the terminal portion back surface, The semiconductor device according to claim 1 .

16. The terminal portion includes a surface recess extending from a surface of the terminal portion toward the electrode. The semiconductor device of claim 15.

17. The size of the terminal portion is 10 μm or more and 150 μm or less. The semiconductor device according to claim 1 .

18. a distance between the side surface of the terminal portion and the side surface of the base portion in a direction perpendicular to the thickness direction is 10 μm or more and 40 μm or less; The semiconductor device according to claim 1 .

19. The electrode terminal includes a bonding layer provided on a surface of the terminal portion. The semiconductor device of claim 15.

20. a semiconductor element including electrode terminals; a plurality of connection terminals electrically connected to the electrode terminals of the semiconductor element; a sealing resin that seals the semiconductor element and the plurality of connection terminals; Including, The semiconductor element is an electrode provided on the surface of the element facing in the thickness direction; an insulating layer covering the electrode and including an opening exposing a portion of the electrode; the electrode terminal contacting the exposed portion of the electrode exposed by the opening and partially overlapping the insulating layer when viewed from the thickness direction; Including, The electrode terminal is a terminal portion provided across both the exposed portion and a peripheral portion of the opening in the insulating layer, the terminal portion being electrically connected to the electrode; a base portion connected to the terminal portion; Including, The terminal portion is a rear surface of the terminal portion facing the exposed portion and the peripheral edge portion; a terminal portion side surface intersecting the terminal portion back surface; Including, the base portion protrudes outward from a portion of the terminal portion side surface that is closer to the rear surface of the terminal portion, The base portion is a back surface of a base portion facing the insulating layer; a base portion side surface that intersects with the base portion rear surface and is positioned outward from the terminal portion side surface; a curved surface provided between the back surface of the base portion and the side surface of the base portion; Including, the sealing resin penetrates between the curved surface of the base and the insulating layer. Semiconductor device.

Images