Semiconductor device and method of manufacturing the same

Abstract

To provide a semiconductor device capable of suitably forming a contact plug.SOLUTION: According to one embodiment, a semiconductor device includes first and second insulating films, a first stacked film including a first electrode layer and a plurality of second electrode layers on the second insulating film, third and fourth insulating films provided on the first stacked film, and a second stacked film including a third electrode layer and a plurality of fourth electrode layers on the fourth insulating film. One fourth plug for the fourth electrode layer includes a first portion in the second insulating film, the first stacked film, and the third insulating film, and a second portion in the fourth insulating film and the second stacked film, and a diameter of the fourth plug discontinuously changes at a boundary between the first portion and the second portion. A third plug for the third electrode layer includes a third portion in the second insulating film, the first stacked film, and the third insulating film, and a fourth portion in the fourth insulating film, and a diameter of the third plug continuously changes at a boundary between the third portion and the fourth portion.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] In a three-dimensional semiconductor memory, contact plugs for word lines may be formed so as to penetrate other word lines. In this case, when manufacturing a three-dimensional semiconductor memory, it may be difficult to properly form the contact plugs due to the insulating film on the top word line or between adjacent word lines. For example, if the insulating film on the top word line is thicker than the insulating film between adjacent word lines, the difference in the thickness of these insulating films may complicate the process of forming the contact plugs. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-139973 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor device capable of suitably forming a contact plug and a method for manufacturing the same are provided. [Means for solving the problem]

[0005] According to one embodiment, a semiconductor device includes a first insulating film and a second insulating film provided on the first insulating film. The device further includes a first stacked film including a first electrode layer provided on the second insulating film and a plurality of second electrode layers provided above the first electrode layer and spaced apart from each other in a first direction. The device further includes a third insulating film provided on the first stacked film and a fourth insulating film provided on the third insulating film. The device further includes a second stacked film including a third electrode layer provided on the fourth insulating film and a plurality of fourth electrode layers provided above the third electrode layer and spaced apart from each other in the first direction. The device further includes a first plug electrically connected to the first electrode layer, a second plug electrically connected to one of the plurality of second electrode layers, a third plug electrically connected to the third electrode layer, and a fourth plug electrically connected to one of the plurality of fourth electrode layers. Furthermore, the fourth plug includes a first portion provided in the second insulating film, the first stacked film, and the third insulating film, and a second portion provided on the first portion in the fourth insulating film and the second stacked film, the diameter of the fourth plug varying discontinuously along the first direction at a boundary between the first portion and the second portion. Further, the third plug includes a third portion provided in the second insulating film, the first stacked film, and the third insulating film, and a fourth portion provided on the third portion in the fourth insulating film, and the diameter of the third plug varying continuously along the first direction at a boundary between the third portion and the fourth portion. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a cross-sectional view showing the structure of a semiconductor device according to a first embodiment. [Figure 2] 1 is an enlarged cross-sectional view showing the structure of a semiconductor device according to a first embodiment. [Figure 3] 4 is a cross-sectional view (1 / 2) illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 4] 4 is a cross-sectional view (2 / 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 5]FIG. 4 is a cross-sectional view showing the structure of a semiconductor device of a comparative example of the first embodiment. [Figure 6] 1 is a cross-sectional view showing the structure of a semiconductor device according to a first embodiment. [Figure 7] 10 is a cross-sectional view (1 / 16) showing a method for manufacturing a semiconductor device of a comparative example of the first embodiment. [Figure 8] 16 is a cross-sectional view (2 / 16) illustrating a method for manufacturing a semiconductor device according to a comparative example of the first embodiment. [Figure 9] 16 is a cross-sectional view (3 / 16) illustrating a method for manufacturing a semiconductor device according to a comparative example of the first embodiment. [Figure 10] 16 is a cross-sectional view (4 / 16) showing a method for manufacturing a semiconductor device of a comparative example of the first embodiment. [Figure 11] 16 is a cross-sectional view (5 / 16) showing a method for manufacturing a semiconductor device of a comparative example of the first embodiment. FIG. [Figure 12] 6 is a cross-sectional view (6 / 16) illustrating a method for manufacturing a semiconductor device according to a comparative example of the first embodiment. [Figure 13] 7 is a cross-sectional view (7 / 16) showing a method for manufacturing a semiconductor device of a comparative example of the first embodiment. [Figure 14] 8 is a cross-sectional view (8 / 16) illustrating a method for manufacturing a semiconductor device according to a comparative example of the first embodiment. [Figure 15] 9 is a cross-sectional view (9 / 16) illustrating a method for manufacturing a semiconductor device according to a comparative example of the first embodiment. [Figure 16] 10 is a cross-sectional view (10 / 16) illustrating a method for manufacturing a semiconductor device according to a comparative example of the first embodiment. [Figure 17] 11 is a cross-sectional view (11 / 16) illustrating a method for manufacturing a semiconductor device according to a comparative example of the first embodiment. [Figure 18] 12 is a cross-sectional view (12 / 16) illustrating a method for manufacturing a semiconductor device according to a comparative example of the first embodiment. [Figure 19] 13 is a cross-sectional view (13 / 16) illustrating a method for manufacturing a semiconductor device according to a comparative example of the first embodiment. [Figure 20] 14 is a cross-sectional view (14 / 16) illustrating a method for manufacturing a semiconductor device according to a comparative example of the first embodiment. [Figure 21]15A and 15B are cross-sectional views (15 / 16) illustrating a method for manufacturing a semiconductor device according to a comparative example of the first embodiment. [Figure 22] 16 is a cross-sectional view (16 / 16) showing a method for manufacturing a semiconductor device of a comparative example of the first embodiment. [Figure 23] 1A and 1B are cross-sectional views (1 / 18) illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 24] 1A and 1B are cross-sectional views (2 / 18) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 25] 3 is a cross-sectional view (3 / 18) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 26] 4 is a cross-sectional view (4 / 18) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 27] 5 is a cross-sectional view (5 / 18) showing the method for manufacturing the semiconductor device according to the first embodiment. [Figure 28] 6 is a cross-sectional view (6 / 18) illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 29] 7 is a cross-sectional view (7 / 18) showing the method for manufacturing the semiconductor device according to the first embodiment. [Figure 30] 8 is a cross-sectional view (8 / 18) showing the method for manufacturing the semiconductor device according to the first embodiment. [Figure 31] 9 is a cross-sectional view (9 / 18) showing the method for manufacturing the semiconductor device according to the first embodiment. [Figure 32] 10 is a cross-sectional view (10 / 18) showing the method for manufacturing the semiconductor device according to the first embodiment. [Figure 33] 11 is a cross-sectional view (11 / 18) showing the method for manufacturing the semiconductor device according to the first embodiment. [Figure 34] 12 is a cross-sectional view (12 / 18) showing the method for manufacturing the semiconductor device according to the first embodiment. [Figure 35] 13A and 13B are cross-sectional views (13 / 18) illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 36] 14 is a cross-sectional view (14 / 18) showing the method for manufacturing the semiconductor device according to the first embodiment. [Figure 37] 15A and 15B are cross-sectional views (15 / 18) illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 38] 16A to 18C are cross-sectional views (16 / 18) illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 39] 17A and 17B are cross-sectional views (17 / 18) illustrating a method for manufacturing the semiconductor device according to the first embodiment. [Figure 40] 18 is a cross-sectional view (18 / 18) showing the method for manufacturing the semiconductor device according to the first embodiment. [Figure 41] 10 is a cross-sectional view (1 / 4) showing a method for manufacturing a semiconductor device according to a second embodiment. [Figure 42] 10 is a cross-sectional view (2 / 4) illustrating a method for manufacturing a semiconductor device according to a second embodiment. [Figure 43] 10 is a cross-sectional view (3 / 4) illustrating a method for manufacturing a semiconductor device according to a second embodiment. [Figure 44] 10 is a cross-sectional view (4 / 4) illustrating the method for manufacturing the semiconductor device according to the second embodiment. [Figure 45] FIG. 10 is a cross-sectional view showing the structure of a semiconductor device according to a third embodiment. [Figure 46] FIG. 10 is a cross-sectional view showing the structure of a semiconductor device according to a fourth embodiment. [Figure 47] FIG. 10 is a cross-sectional view showing the structure of a semiconductor device according to a fifth embodiment. [Figure 48] 10 is a cross-sectional view (1 / 2) showing a method for manufacturing a semiconductor device according to a fifth embodiment. [Figure 49] 10 is a cross-sectional view (2 / 2) showing the method for manufacturing the semiconductor device according to the fifth embodiment. [Figure 50] FIG. 13 is a cross-sectional view showing the structure of a semiconductor device according to a modification of the fifth embodiment. [Figure 51] FIG. 10 is a cross-sectional view showing the structure of a semiconductor device according to a sixth embodiment. [Figure 52] 13 is a cross-sectional view (1 / 2) showing a method for manufacturing a semiconductor device according to a sixth embodiment. [Figure 53] 13 is a cross-sectional view (2 / 2) showing the method for manufacturing the semiconductor device according to the sixth embodiment. [Figure 54] FIG. 13 is a cross-sectional view showing the structure of a semiconductor device according to a modification of the sixth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings. In Figures 1 to 54, the same components are denoted by the same reference numerals, and duplicated descriptions will be omitted.

[0008] (First embodiment) FIG. 1 is a cross-sectional view showing the structure of a semiconductor device according to a first embodiment.

[0009] As shown in Fig. 1, the semiconductor device of this embodiment includes an array chip 1 and a circuit chip 2 bonded together. In Fig. 1, the array chip 1 is disposed on the circuit chip 2. The symbol S indicates the bonding surface between the array chip 1 and the circuit chip 2. The semiconductor device of this embodiment is, for example, a three-dimensional semiconductor memory.

[0010] The array chip 1 includes a laminated film 11 including a plurality of electrode layers, and an interlayer insulating film 12 provided below the laminated film 11. The interlayer insulating film 12 is, for example, a laminated insulating film including an SiO2 film (silicon oxide film) and other insulating films. In this embodiment, the interlayer insulating film 12 is provided not only below the laminated film 11 but also above the laminated film 11.

[0011] The circuit chip 2 includes an interlayer insulating film 13 disposed under the interlayer insulating film 12, and a substrate 14 disposed under the interlayer insulating film 13. The interlayer insulating film 13 is, for example, a stacked insulating film including an SiO2 film and other insulating films. The substrate 14 is, for example, a semiconductor substrate such as a Si (silicon) substrate.

[0012] The X direction, Y direction, and Z direction shown in Fig. 1 intersect with each other. Specifically, Fig. 1 shows the X direction and Y direction, which are parallel to the surface of the substrate 14 and perpendicular to each other, and the Z direction, which is perpendicular to the surface of the substrate 14. In this specification, the +Z direction is treated as the upward direction, and the -Z direction is treated as the downward direction. Note that the -Z direction may or may not coincide with the direction of gravity. The Z direction is an example of a first direction.

[0013] As shown in FIG. 1, the laminated film 11 includes a laminated film 11a including multiple electrode layers 21a and multiple insulating films 22a alternately arranged in the Z direction, and a laminated film 11b including multiple electrode layers 21b and multiple insulating films 22b alternately arranged in the Z direction. The electrode layers 21a and 21b in the laminated films 11a and 11b are spaced apart from each other in the Z direction. In FIG. 1, the laminated film 11a is provided above the laminated film 11b. The laminated film 11b is an example of a first laminated film, and the laminated film 11a is an example of a second laminated film. The array chip 1 further includes a wiring layer 23 provided in the interlayer insulating film 12 above the laminated films 11a and 11b.

[0014] 1, the stacked film 11 includes regions R1, R2, and R3. The electrode layers 21a and 21b and the insulating films 22a and 22b of this embodiment are provided across the regions R1, R2, and R3, and the wiring layer 23 of this embodiment is provided above the regions R1, R2, and R3.

[0015] Region R1, together with wiring layer 23 and the like, forms a memory cell array 31. In memory cell array 31, electrode layers 21a and 21b function as word lines WLa and WLb, respectively, and wiring layer 23 functions as a source line SL. Memory cell array 31 further includes source-side selection lines and drain-side selection lines (not shown) within stacked film 11. FIG. 1 also shows multiple pillars 32 penetrating region R1 in the Z direction. These pillars 32, together with electrode layers 21a and 21b, form multiple memory cells. Each pillar 32 is electrically connected to a source line SL and, via a contact plug 33, to a bit line BL.

[0016] In region R2, the array chip 1 includes multiple beams 34, multiple contact plugs 36, and the like. Each beam 34 penetrates region R2 in the Z direction. Each contact plug 36 is provided in region R2 via a spacer insulating film 35 and is electrically connected to either one of the electrode layers 21a in the laminated film 11a or one of the electrode layers 21b in the laminated film 11b. As shown in FIG. 1 , the contact plug 36 electrically connected to the electrode layer 21a includes a plug 36a provided in the laminated film 11a and a plug 36b provided in the laminated film 11b below the plug 36a. The contact plug 36 electrically connected to the electrode layer 21b includes a plug 36b provided in the laminated film 11b. The side surfaces of each plug 36a are surrounded by an insulating film 35a in the spacer insulating film 35, and the side surfaces of each plug 36b are surrounded by an insulating film 35b in the spacer insulating film 35. The array chip 1 further includes multiple contact plugs 37 and the like below region R2. Each contact plug 37 is provided below a corresponding contact plug 36 and electrically connects the contact plug 36 to a word wiring layer 38 .

[0017] In the region R3, the array chip 1 includes a plurality of via plugs 56. Details of these via plugs 56 will be described later.

[0018] The circuit chip 2 further includes a plurality of transistors 41 , a plurality of contact plugs 42 , a wiring layer 43 , a wiring layer 44 , a wiring layer 45 , a plurality of via plugs 46 , and a plurality of metal pads 47 .

[0019] Each transistor 41 includes a gate insulating film 41a and a gate electrode 41b provided in this order on the substrate 14, and a source region and a drain region (not shown) provided within the substrate 14. Each contact plug 42 is provided on the gate electrode 41b, the source region, or the drain region of the corresponding transistor 41. The wiring layer 43 includes a plurality of wirings and is provided on the contact plug 42. The wiring layer 44 includes a plurality of wirings and is provided on the wiring layer 43. The wiring layer 45 includes a plurality of wirings and is provided on the wiring layer 44. The via plug 46 is provided on the wiring layer 45. The metal pad 47 is provided on the via plug 46. Each metal pad 47 is, for example, a metal layer including a Cu (copper) layer. The circuit chip 2 includes a logic circuit that controls the operation of the array chip 1. This logic circuit is composed of the transistor 41 and the like and is electrically connected to the metal pad 47.

[0020] The array chip 1 further includes a plurality of metal pads 51, a plurality of via plugs 52, a wiring layer 53, a wiring layer 54, a plurality of spacer insulating films 55, and the above-mentioned plurality of via plugs 56.

[0021] The metal pads 51 are provided on the metal pads 47. Each metal pad 51 is, for example, a metal layer including a Cu layer. The logic circuit is electrically connected to the memory cell array 31 via the metal pads 47, 51, etc., and controls the operation of the memory cell array 31 via the metal pads 47, 51, etc. The via plugs 52 are provided on the metal pads 51. The wiring layer 53 includes a plurality of wirings and is provided on the via plugs 52. The wiring layer 54 includes a plurality of wirings and is provided on the wiring layer 53. The bit lines BL are included in the wiring layer 54. Each via plug 56 is disposed on the wiring layer 54, is provided in the region R3 via a spacer insulating film 55, and penetrates the region R3 in the Z direction. Each via plug 56 includes a plug 56a provided in the stacked film 11a, and a plug 56b provided in the stacked film 11b below the plug 56a. The side surfaces of each plug 56 a are surrounded by the insulating film 55 a in the spacer insulating film 55 , and the side surfaces of each plug 56 b are surrounded by the insulating film 55 b in the spacer insulating film 55 .

[0022] The array chip 1 further includes an insulating film 61 , a metal pad 62 , and a passivation insulating film 63 .

[0023] The insulating film 61 is provided in a recess formed in the interlayer insulating film 12 and on the side surfaces of the interlayer insulating film 12 and the wiring layer 23. The metal pad 62 is provided in the recess formed in the interlayer insulating film 12 on the upper surfaces of the interlayer insulating film 12 and the via plug 56 and on the side surfaces of the insulating film 61, and is provided outside the recess formed in the interlayer insulating film 12 on the upper surfaces of the interlayer insulating film 12 and the insulating film 61. The metal pad 62 is, for example, a metal layer including a Cu layer, and functions as an external connection pad (bonding pad) of the semiconductor device of this embodiment. The passivation insulating film 63 is provided on the metal pad 62 and the interlayer insulating film 12 and has an opening P that exposes the upper surface of the metal pad 62. The metal pad 62 can be electrically connected to a mounting substrate or another device via a bonding wire, a solder ball, a metal bump, or the like through this opening P.

[0024] FIG. 2 is an enlarged cross-sectional view showing the structure of the semiconductor device of the first embodiment.

[0025] FIG. 2 shows a region R1 of the laminated film 11 shown in FIG. 1. The laminated film 11 includes a laminated film 11a including multiple electrode layers 21a and multiple insulating films 22a alternately arranged in the Z direction, and a laminated film 11b including multiple electrode layers 21b and multiple insulating films 22b alternately arranged in the Z direction. As described above, the electrode layers 21a and 21b function as word lines WLa and WLb, respectively. Each of the electrode layers 21a and 21b is, for example, a metal layer including a W layer. Each of the insulating films 22a and 22b is, for example, a SiO2 film.

[0026] 2 further shows one of the plurality of columnar portions 32 shown in FIG. 1. As shown in FIG. 2, each columnar portion 32 includes a block insulating film 71, a charge storage layer 72, a tunnel insulating film 73, a channel semiconductor layer 74, and a core insulating film 75, which are provided in this order in the stacked film 11. The block insulating film 71 is, for example, a SiO2 film. The charge storage layer 72 is, for example, a SiN film (silicon nitride film). The tunnel insulating film 73 is, for example, a SiO2 film. The channel semiconductor layer 74 is, for example, a polysilicon layer. The core insulating film 75 is, for example, a SiO2 film.

[0027] 3 and 4 are cross-sectional views showing the method for manufacturing the semiconductor device of the first embodiment.

[0028] 3 shows an array wafer W1 including a plurality of array chips 1 and a circuit wafer W2 including a plurality of circuit chips 2. The orientation of the array wafer W1 in FIG. 3 is opposite to the orientation of the array chip 1 in FIG. 1. In this embodiment, a semiconductor device is manufactured by bonding the array wafer W1 and the circuit wafer W2 together. FIG. 3 shows the array wafer W1 before its orientation is reversed for bonding, and FIG. 1 shows the array chip 1 after its orientation is reversed for bonding, bonding, and dicing.

[0029] 3 further shows the top surface S1 of the array wafer W1 and the top surface S2 of the circuit wafer W2. The array wafer W1 includes a substrate 15 disposed under an interlayer insulating film 12. The substrate 15 is, for example, a semiconductor substrate such as a Si substrate.

[0030] In this embodiment, as shown in FIG. 3, first, the stacked film 11, interlayer insulating film 12, wiring layer 23, memory cell array 31, columnar portion 32, contact plugs 36, contact plugs 37, metal pads 51, via plugs 56, etc. are formed on the substrate 15 of the array wafer W1, and then the interlayer insulating film 13, transistors 41, contact plugs 42, metal pads 47, etc. are formed on the substrate 14 of the circuit wafer W2. Next, as shown in FIG. 4, the array wafer W1 and the circuit wafer W2 are bonded together by mechanical pressure so that the upper surfaces S1 and S2 face each other. This bonds the interlayer insulating film 12 and the interlayer insulating film 13. Next, the array wafer W1 and the circuit wafer W2 are annealed. This bonds the metal pads 51 and 47. In this manner, the substrate 15 and the substrate 14 are bonded together with the interlayer insulating films 12 and 13 sandwiched between them.

[0031] Thereafter, the substrate 14 is thinned by CMP (Chemical Mechanical Polishing), the substrate 15 is removed by CMP, and then the array wafer W1 and the circuit wafer W2 are cut into a plurality of chips. In this manner, the semiconductor device of this embodiment is manufactured (FIG. 1). Note that the insulating film 61, metal pad 62, and passivation insulating film 63 shown in FIG. 1 are formed above the stacked film 11 and the wiring layer 23 after the substrate 14 is thinned and the substrate 15 is removed.

[0032] 1 shows the boundary surface between interlayer insulating film 12 and interlayer insulating film 13 and the boundary surface between metal pad 51 and metal pad 47, but these boundaries generally become invisible after the above-mentioned annealing. However, the positions of these boundaries can be estimated by detecting, for example, the inclination of the side surface of metal pad 51 or the side surface of metal pad 47, or the positional deviation between the side surface of metal pad 51 and the side surface of metal pad 47.

[0033] Next, with reference to FIGS. 5 and 6, the structure of the semiconductor device of this embodiment will be described in comparison with a comparative example of this embodiment.

[0034] FIG. 5 is a cross-sectional view showing the structure of a semiconductor device as a comparative example of the first embodiment.

[0035] The semiconductor device of this comparative example (FIG. 5) has roughly the same structure as the semiconductor device of the first embodiment (FIG. 1). Therefore, the semiconductor device of this comparative example will be described as a continuation of the above description of the semiconductor device of the first embodiment, except for the differences between the first embodiment and this comparative example. For example, this comparative example will be described using the same reference numerals as the first embodiment. The differences between the first embodiment and this comparative example will be described later.

[0036] FIG. 5 shows region R2 of the laminated film 11. FIG. 5 also shows an insulating film 12a, which is part of the interlayer insulating film 12, and a wiring layer 23 (source line SL). The laminated film 11 of this comparative example includes an insulating film 11e, a laminated film 11b, an insulating film 11d, an insulating film 11c, and a laminated film 11a, which are sequentially disposed on the insulating film 12a. As described above, the laminated film 11b includes multiple electrode layers 21b (word lines WLb) and multiple insulating films 22b alternately arranged in the Z direction, and the laminated film 11a includes multiple electrode layers 21a (word lines WLa) and multiple insulating films 22a alternately arranged in the Z direction. The insulating films 11c and 11d disposed between the laminated film 11a and the laminated film 11b are called joint insulating films, and the insulating film 11e disposed under the laminated films 11a and 11b is called an external insulating film. The insulating films 11c, 11d, 11e, 12a, 22a, and 22b of this comparative example are, for example, SiO2 films.

[0037] In this comparative example, the film thicknesses of the electrode layers 21a and 21b in the laminated film 11 are set to the same value, and the film thicknesses of the insulating films 22a and 22b in the laminated film 11 are set to the same value. Furthermore, in this comparative example, the total film thickness of the insulating films 11c and 11d (the film thickness of the joint insulating film) is set to be thicker than the film thicknesses of the insulating films 22a and 22b. Furthermore, in this comparative example, the film thickness of the insulating film 11c and the film thickness of the insulating film 11e are set to be thicker than the film thicknesses of the insulating films 22a and 22b.

[0038] 5 further shows electrode layer 21ax and electrode layer 21bx. Electrode layer 21ax is the lowermost electrode layer 21a among the multiple electrode layers 21a included in stacked film 11a. Electrode layer 21bx is the lowermost electrode layer 21b among the multiple electrode layers 21b included in stacked film 11b. Further details of electrode layers 21ax and 21bx will be described later.

[0039] 5 further shows a plurality of contact plugs 37 provided in the insulating film 12a and a plurality of contact plugs 36 provided in the stacked film 11. Each contact plug 36 includes a plug 36a and a plug 36b, or includes only a plug 36b. In FIG. 5, each plug 36b is provided in the insulating film 11e, or in the insulating film 11e and the stacked film 11b, or in the insulating film 11e, the stacked film 11b, and the insulating film 11d, and each plug 36a is provided in the insulating film 11c, or in the insulating film 11c and the stacked film 11a.

[0040] In the following description, a plug including one contact plug 36 and one contact plug 37 provided below this contact plug 36 will be referred to as plug C. Fig. 5 shows six plugs C1 to C6 as examples of plugs C. Note that plug C may include not only contact plugs 36 and 37, but also only contact plug 37, as will be described later.

[0041] The plug C1 includes plugs 36a, 36b, and a contact plug 37, and is electrically connected to one electrode layer 21a other than the electrode layer 21ax. The same applies to the plug C2. The plug C3 includes plugs 36a, 36b, and a contact plug 37, and is electrically connected to the electrode layer 21ax.

[0042] The plug C4 includes a plug 36b and a contact plug 37, and is electrically connected to one of the electrode layers 21b other than the electrode layer 21bx. The same applies to the plug C5. The plug C6 includes a plug 36b and a contact plug 37, and is electrically connected to the electrode layer 21bx.

[0043] The symbols Pa, Pb, and Pc in FIG. 5 represent portions within each plug C. The symbol Pa represents a portion within the laminate film 11a and insulating film 11c of each plug C. The symbol Pb represents a portion within the laminate film 11b, insulating film 11d, and insulating film 11e of each plug C. The symbol Pc represents a portion within the insulating film 12a of each plug C. Thus, the portions Pa, Pb, and Pc of each plug C in this comparative example correspond to the plug 36a, plug 36b, and contact plug 37 of each plug C, respectively. Each of the plugs C1 to C3 includes the portions Pa, Pb, and Pc and is electrically connected to one of the electrode layers 21a in the laminate film 11a. Each of the plugs C4 to C6 includes only the portions Pb and Pc and is electrically connected to one of the electrode layers 21b in the laminate film 11b. The portions Pa, Pb, and Pc will be described in further detail below.

[0044] In this comparative example, when manufacturing a semiconductor device, it is difficult to properly form plugs C1 to C6 due to insulating films 11c, 11d, 11e, 12a, 22a, 22b, etc. Specifically, it is difficult to properly form contact holes for contact plugs 36. This problem will be described in more detail later.

[0045] FIG. 6 is a cross-sectional view showing the structure of the semiconductor device of the first embodiment.

[0046] The semiconductor device of this embodiment shown in Fig. 6 has roughly the same structure as the semiconductor device of the comparative example shown in Fig. 5. In the following explanation of Fig. 6, the explanation of the commonalities between Fig. 5 and Fig. 6 will be omitted to some extent, and the explanation will focus on the differences between Fig. 5 and Fig. 6.

[0047] 6, like FIG. 5, illustrates region R2 and the like of the laminated film 11. The laminated film 11 of this embodiment also includes an insulating film 11e, a laminated film 11b, an insulating film 11d, an insulating film 11c, and a laminated film 11a, which are sequentially disposed on an insulating film 12a. The laminated film 11b includes multiple electrode layers 21b (word lines WLb) and multiple insulating films 22b alternately arranged in the Z direction, and the laminated film 11a includes multiple electrode layers 21a (word lines WLa) and multiple insulating films 22a alternately arranged in the Z direction. The insulating films 11c, 11d, 11e, 12a, 22a, and 22b of this embodiment are, for example, SiO2 films. The insulating films 12a and 11e are examples of the first and second insulating films, respectively. The insulating films 11d and 11c are examples of the third and fourth insulating films, respectively. The insulating films 22b and 22a are examples of the fifth and sixth insulating films, respectively.

[0048] In this embodiment, the electrode layers 21a and 21b in the laminated film 11 are all set to have the same film thickness, and the insulating films 22a and 22b in the laminated film 11 are all set to have the same film thickness. Furthermore, in this embodiment, the total film thickness (the film thickness of the joint insulating film) of the insulating films 11c and 11d is set to be thicker than the insulating films 22a and 22b. Furthermore, in this embodiment, the film thickness of the insulating film 11c and the film thickness of the insulating film 11e are set to be thicker than the insulating films 22a and 22b. The above is similar to the comparative example. The laminated film 11 may include an electrode layer 21a or an electrode layer 21b having a film thickness different from that of the other electrode layers 21a and 21b. Furthermore, the laminated film 11 may include an insulating film 22a or an insulating film 22b having a film thickness different from that of the other insulating films 22a and 22b.

[0049] FIG. 6 further illustrates electrode layer 21ax and electrode layer 21bx, similar to FIG. 5. Electrode layer 21ax is the lowest electrode layer 21a among the multiple electrode layers 21a in stacked film 11a. Electrode layer 21bx is the lowest electrode layer 21b among the multiple electrode layers 21b in stacked film 11b. Electrode layer 21bx is an example of a first electrode layer, and each electrode layer 21b other than electrode layer 21bx is an example of a second electrode layer. Electrode layer 21ax is an example of a third electrode layer, and each electrode layer 21a other than electrode layer 21ax is an example of a fourth electrode layer.

[0050] 6 further illustrates, as in FIG. 5, a plurality of contact plugs 37 in the insulating film 12a and a plurality of contact plugs 36 in the stacked film 11. Each contact plug 36 includes plugs 36a and 36b, or includes only plug 36b. In FIG. 6, each plug 36b is provided in the insulating film 11e and stacked film 11b, or in the insulating film 11e, stacked film 11b, and insulating film 11d, or in the insulating film 11e, stacked film 11b, insulating film 11d, and insulating film 11c, and each plug 36a is provided in the insulating film 11c and stacked film 11a. As described above, the semiconductor device of this embodiment does not include plugs 36b provided only in the insulating film 11e or plugs 36a provided only in the insulating film 11c, but instead includes plugs 36b provided in the insulating film 11e, stacked film 11b, insulating film 11d, and insulating film 11c. The semiconductor device of this embodiment also includes contact plugs 37 provided in the insulating film 12a and insulating film 11e. Further details of these contact plugs 36 and 37 will be described later.

[0051] FIG. 6 further shows a spacer insulating film 35 provided on the side surface of each contact plug 36. The side surface of each plug 36a is surrounded by an insulating film 35a within the spacer insulating film 35, and the side surface of each plug 36b is surrounded by an insulating film 35b within the spacer insulating film 35. Each of the plugs 36a and 36b has a solid columnar shape extending in the Z direction, and each of the insulating films 35a and 35b has a hollow columnar shape (i.e., a tubular shape) extending in the Z direction. In this embodiment, the insulating films 35a and 35b are, for example, SiO2 films. Note that the side surface of each contact plug 37 in this embodiment is not surrounded by a spacer insulating film, but is instead surrounded by an insulating film 12a or an insulating film 11e.

[0052] Each plug 36a of this embodiment is provided on the lower surface of one of the electrode layers 21a in the laminated film 11a and penetrates one or more of the electrode layers 21a in the laminated film 11a via the insulating film 35a. As a result, each plug 36a of this embodiment is electrically connected to the former electrode layer 21a and electrically insulated from the latter electrode layer 21a. On the other hand, each plug 36b of this embodiment is provided on the lower surface of one of the plugs 36a in the laminated film 11a, the electrode layer 21ax in the laminated film 11a, or one of the electrode layers 21b in the laminated film 11b and penetrates one or more of the electrode layers 21b in the laminated film 11b via the insulating film 35b. As a result, each plug 36b of this embodiment is electrically connected to the plug 36a, the electrode layer 21ax, or the former electrode layer 21b and electrically insulated from the latter electrode layer 21b.

[0053] The plugs 36a, 36b of this embodiment are formed by forming a plurality of holes in the stacked films 11a, 11b and then forming the plugs 36a, 36b in these holes via the insulating films 35a, 35b when performing the process shown in Fig. 3. Thus, each of the plugs 36a, 36b of this embodiment has a diameter that decreases along the +Z direction in Fig. 6, i.e., a tapered shape toward the +Z direction.

[0054] Similarly, the plurality of contact plugs 37 of this embodiment are formed by forming a plurality of contact holes in the insulating film 12 and then forming the contact plugs 37 in these contact holes when performing the process shown in FIG. 3. Therefore, each contact plug 37 of this embodiment has a diameter that decreases along the +Z direction in FIG. 6, that is, a tapered shape toward the +Z direction. The shape of the XY cross section of each contact plug 37 of this embodiment is, for example, circular. This also applies to each plug 36a and each plug 36b of this embodiment.

[0055] Similarly to FIG. 5, FIG. 6 further shows six plugs C1 to C6 as examples of the plug C (see the description of FIG. 5).

[0056] The plug C1 of this embodiment, like the comparative example, includes plugs 36a, 36b, and a contact plug 37, and is electrically connected to one electrode layer 21a other than the electrode layer 21ax, like the comparative example. The same applies to the plug C2 of this embodiment. On the other hand, the plug C3 of this embodiment, like the comparative example, is electrically connected to the electrode layer 21ax, but unlike the comparative example, includes only the plug 36b and the contact plug 37. In the plug C3 of this embodiment, the plug 36b is provided in the stacked film 11b, the insulating film 11d, and the insulating film 11c. The plugs C1 and C2 are examples of fourth plugs, and the plug C3 is an example of a third plug.

[0057] Like the comparative example, plug C4 of this embodiment includes plug 36b and contact plug 37, and like the comparative example, is electrically connected to one electrode layer 21b other than electrode layer 21bx. The same applies to plug C5 of this embodiment. Meanwhile, plug C6 of this embodiment is electrically connected to electrode layer 21bx like the comparative example, but unlike the comparative example, includes only contact plug 37. In plug C6 of this embodiment, contact plug 37 is provided in insulating film 12a and insulating film 11e. Plugs C4 and C5 are examples of second plugs, and plug C6 is an example of a first plug.

[0058] 5, the symbols Pa, Pb, and Pc shown in FIG. 6 represent portions within each plug C. Symbol Pa represents portions within the stacked film 11a and insulating film 11c of each plug C. Symbol Pb represents portions within the stacked film 11b, insulating film 11d, and insulating film 11e of each plug C. Symbol Pc represents a portion within the insulating film 12a of each plug C. In each plug C, portion Pa is located on portion Pb, and portion Pb is located on portion Pc.

[0059] Each of the plugs C1 and C2 of this embodiment includes portions Pa, Pb, and Pc, and is electrically connected to any of the electrode layers 21a (excluding the electrode layer 21ax) in the laminated film 11a. The portions Pa, Pb, and Pc of the plug C1 of this embodiment correspond to the plug 36a, plug 36b, and contact plug 37 of the plug C1, respectively. The portions Pa, Pb, and Pc of the plug C2 of this embodiment correspond to the plug 36a, plug 36b, and contact plug 37 of the plug C2, respectively. The above is the same as in the comparative example. The portions Pa, Pb, and Pc of the plugs C1 and C2 are examples of the second portion, the first portion, and the ninth portion, respectively.

[0060] The plug C3 of this embodiment includes portions Pa, Pb, and Pc, and is electrically connected to the electrode layer 21ax in the laminated film 11a. The above is the same as in the comparative example. Meanwhile, the portions Pa and Pb of the plug C3 of this embodiment correspond to the plug 36b of the plug C3, and the portion Pc of the plug C3 of this embodiment corresponds to the contact plug 37 of the plug C3. The portion Pa of the plug C3 is formed by the plug 36a in the comparative example, but is formed by the plug 36b in this embodiment. The portions Pa, Pb, and Pc of the plug C3 are examples of the fourth portion, the third portion, and the tenth portion, respectively.

[0061] Each of the plugs C4 and C5 of this embodiment includes only portions Pb and Pc, and is electrically connected to one of the electrode layers 21b (excluding the electrode layer 21bx) in the laminated film 11b. The portions Pb and Pc of the plug C4 of this embodiment correspond to the plug 36b and the contact plug 37 of the plug C4, respectively. The portions Pb and Pc of the plug C5 of this embodiment correspond to the plug 36b and the contact plug 37 of the plug C5, respectively. The above is the same as in the comparative example. The portions Pb and Pc of the plugs C4 and C5 are examples of the sixth and fifth portions, respectively.

[0062] The plug C6 of this embodiment includes only the portions Pb and Pc, and is electrically connected to the electrode layer 21bx in the laminated film 11b. The above is the same as in the comparative example. Meanwhile, the portions Pb and Pc of the plug C6 of this embodiment correspond to the contact plug 37 of the plug C6. The portion Pb of the plug C6 is formed of the plug 36b in the comparative example, but is formed of the contact plug 37 in this embodiment. The portions Pb and Pc of the plug C6 are examples of the eighth and seventh portions, respectively. In this embodiment, the portion Pb of the plug C6 is formed of the contact plug 37 rather than the plug 36b, and therefore the side surface of the portion Pb of the plug C6 is not surrounded by the insulating film 35b.

[0063] In this embodiment, the boundary between the portion Pa and the portion Pb of the plug C1 is located at the boundary between the plug 36a and the plug 36b. As a result, the diameter of the plug C1 changes discontinuously along the Z direction at the boundary between the portion Pa and the portion Pb. In FIG. 6, the diameter of the lower end of the portion Pa of the plug C1 is larger than the diameter of the upper end of the portion Pb of the plug C1. In this embodiment, such discontinuity is also observed in the taper angle of the side surface of the plug C1. In the plug C1 shown in FIG. 6, the taper angle of the side surface of the portion Pa at the lower end of the portion Pa is different from the taper angle of the side surface of the portion Pb at the upper end of the portion Pb. The same applies to the plug C2.

[0064] On the other hand, in this embodiment, the boundary between the portion Pa and the portion Pb of the plug C3 is located between the upper and lower ends of the plug 36b. As a result, the diameter of the plug C3 changes continuously along the Z direction at the boundary between the portion Pa and the portion Pb. In FIG. 6, the diameter of the plug C3 near the boundary between the portion Pa and the portion Pb gradually decreases along the +Z direction. This continuity is also observed in the taper angle of the side surface of the plug C3 in this embodiment. In the plug C3 shown in FIG. 6, the taper angle of the side surface of the portion Pa at the lower end of the portion Pa is the same as the taper angle of the side surface of the portion Pb at the upper end of the portion Pb.

[0065] Furthermore, in this embodiment, the boundary between the portion Pb and the portion Pc of the plug C4 is located at the boundary between the plug 36b and the contact plug 37. As a result, the diameter of the plug C4 changes discontinuously at the boundary between the portion Pb and the portion Pc along the Z direction. In FIG. 6, the diameter of the lower end of the portion Pb of the plug C4 is larger than the diameter of the upper end of the portion Pc of the plug C4. In this embodiment, such discontinuity is also observed in the taper angle of the side surface of the plug C4. In the plug C4 shown in FIG. 6, the taper angle of the side surface of the portion Pb at the lower end of the portion Pb is different from the taper angle of the side surface of the portion Pc at the upper end of the portion Pc. The same applies to the plug C5 and the plugs C1 to C3.

[0066] On the other hand, in this embodiment, the boundary between the portion Pb and the portion Pc of the plug C6 is located between the upper and lower ends of the contact plug 37. As a result, the diameter of the plug C6 changes continuously along the Z direction at the boundary between the portion Pb and the portion Pc. In FIG. 6, the diameter of the plug C6 near the boundary between the portion Pb and the portion Pc gradually decreases along the +Z direction. This continuity is also observed in the taper angle of the side surface of the plug C6 in this embodiment. In the plug C6 shown in FIG. 6, the taper angle of the side surface of the portion Pb at the lower end of the portion Pb is the same as the taper angle of the side surface of the portion Pc at the upper end of the portion Pc.

[0067] As described above, in the comparative example, when manufacturing a semiconductor device, it is difficult to properly form the plugs C1 to C6 due to the insulating films 11c, 11d, 11e, 12a, 22a, 22b, etc. Specifically, it is difficult to properly form the contact hole for the contact plug 36. On the other hand, according to this embodiment, this problem can be addressed by setting the shapes of the plugs C3 and C6 as described above. Further details of this effect will be described later.

[0068] The semiconductor device of this embodiment further includes a plurality of plugs C (not shown) other than the plugs C1 to C6. Each of the electrode layers 21a, 21b of this embodiment is electrically connected to one of the plugs C. The plugs C electrically connected to each of the electrode layers 21a other than the electrode layer 21ax can be formed in the same manner as the plugs C1 and C2. Furthermore, the plugs C electrically connected to each of the electrode layers 21b other than the electrode layer 21bx can be formed in the same manner as the plugs C4 and C5. Although the plugs C1 to C6 of this embodiment are aligned in the X direction in FIG. 6, they may be arranged in other layouts within the region R2. This also applies to the plurality of plugs C (not shown) other than the plugs C1 to C6.

[0069] Furthermore, the stacked film 11 of this embodiment may further include one or more stacked films between the stacked film 11a and the stacked film 11b. In this case, each stacked film between the stacked film 11a and the stacked film 11b may have a structure similar to that of the stacked films 11a and 11b. Furthermore, the plug C for each stacked film between the stacked film 11a and the stacked film 11b may have a shape similar to that of the plugs C1 to C3 of this embodiment, for example.

[0070] Furthermore, with regard to plugs C1 to C3 of this embodiment, the plugs 36a, 36b, and contact plugs 37 in each plug C may be formed from the same material layer or different material layers. Similarly, with regard to plugs C4 to C6 of this embodiment, the plugs 36b and contact plugs 37 in each plug C may be formed from the same material layer or different material layers. In the following description, an example will be described in which the plugs 36a, 36b, and contact plugs 37 in plugs C1 to C6 are formed from the same material layer. The material layer is, for example, a metal layer including a W layer.

[0071] Next, with reference to FIGS. 7 to 40, the method for manufacturing the semiconductor device of this embodiment will be described in comparison with a comparative example of this embodiment.

[0072] 7 to 22 are cross-sectional views showing a method for manufacturing a semiconductor device of a comparative example of the first embodiment.

[0073] 7 to 22 show steps for forming the structure shown in Fig. 5. The steps shown in Fig. 7 to 22 correspond to a part of the steps shown in Fig. 3.

[0074] First, a wiring layer 23, a stacked film 11a, an insulating film 11c, a hard mask layer 81, and a resist layer 82 are formed in this order above the substrate 15 (not shown) of the array wafer W1 (FIG. 7). The hard mask layer 81 is, for example, a polysilicon layer. The stacked film 11a shown in FIG. 7 is formed to include multiple sacrificial layers 21a' and multiple insulating films 22a alternately. These sacrificial layers 21a' in the stacked film 11a are spaced apart from each other in the Z direction. Each sacrificial layer 21a' is, for example, a SiN film. The sacrificial layer 21ax' shown in FIG. 7 is the uppermost sacrificial layer 21a' among the multiple sacrificial layers 21a' included in the stacked film 11a.

[0075] Next, the resist layer 82, the hard mask layer 81, and the insulating film 11c are etched by lithography and RIE (Reactive Ion Etching) (FIG. 7). As a result, a plurality of recesses 92 are formed in the resist layer 82, and these recesses 92 are transferred to the hard mask layer 81 and the insulating film 11c, thereby forming a plurality of recesses 91 in the hard mask layer 81 and the insulating film 11c. These recesses 91 are formed to serve as holes into which the plugs 36a of the plugs C1 to C3 are buried. Each recess 91 shown in FIG. 7 is formed so that the insulating film 11c, having approximately the same thickness as the insulating film 22a, remains below each recess 91. The planar shape of each recess 92 in the resist layer 82 is, for example, circular.

[0076] Next, after removing the resist layer 82, a resist layer 83 is formed on the hard mask layer 81 (FIG. 8). As a result, the recesses 91 for the plugs C1 to C3 are filled with the resist layer 83.

[0077] Next, the resist layer 83, the insulating film 11c, and the stacked film 11a are etched by lithography and RIE (FIG. 8). As a result, a plurality of recesses 93 are formed in the resist layer 83, the resist layer 83 is removed from the recesses 91 for the plugs C1 and C2, and the stacked film 11a in these recesses 91 is further etched. Meanwhile, the resist layer 83 is left in the recess 91 for the plug C3. The stacked film 11a in FIG. 8 is etched so that the bottom surfaces of the recesses 91 for the plugs C1 and C2 reach the upper surfaces of the predetermined insulating films 22a. The planar shape of each recess 93 in the resist layer 83 is, for example, circular.

[0078] 8, the etching for processing the recess 91 for the plug C1 and the etching for processing the recess 91 for the plug C2 may be performed simultaneously or sequentially. In the latter case, the etching for processing the recess 91 for the plug C1 and the etching for processing the recess 91 for the plug C2 are performed using, for example, separate resist layers 83.

[0079] Next, after removing the resist layer 83 and the hard mask layer 81, the insulating film 35a of the spacer insulating film 35 is formed in each recess 91 (FIG. 9). As a result, the insulating film 35a is formed on the side surface and bottom surface of each recess 91.

[0080] Next, the insulating film 35a is removed from the bottom surface of each recess 91 by lithography and RIE (FIG. 10). At this time, one insulating film 22a is further removed from the bottom surface of the recess 91 for the plug C1, one insulating film 22a is further removed from the bottom surface of the recess 91 for the plug C2, and another insulating film 11c is removed from the bottom surface of the recess 91 for the plug C3. As a result, the bottom surfaces of the recesses 91 for the plugs C1 to C3 reach the upper surface of a predetermined sacrificial layer 21a'. Note that the reason why the insulating film 11c having approximately the same thickness as the insulating film 22a is left under each recess 91 in the step shown in FIG. 7 is to facilitate simultaneous etching of the insulating film 22a under the recesses 91 for the plugs C1 and C2 and the insulating film 11c under the recess 91 for the plug C3 in the step shown in FIG.

[0081] Next, a sacrificial layer 36a' is embedded in each recess 91 (FIG. 11). As a result, a sacrificial layer 36a' is formed on a predetermined sacrificial layer 21a' in each recess 91. The sacrificial layer 36a' is, for example, a polysilicon layer.

[0082] Next, an insulating film 11d, a stacked film 11b, an insulating film 11e, a hard mask layer 84, and a resist layer 85 are sequentially formed on the insulating film 11c, the insulating film 35a, and the sacrificial layer 36a' (FIG. 12). The hard mask layer 84 is, for example, a polysilicon layer. The stacked film 11b shown in FIG. 12 is formed to include multiple sacrificial layers 21b' and multiple insulating films 22b alternately. These sacrificial layers 21b' in the stacked film 11b are spaced apart from each other in the Z direction. Each sacrificial layer 21b' is, for example, a SiN film. The sacrificial layer 21bx' shown in FIG. 12 is the uppermost sacrificial layer 21b' among the multiple sacrificial layers 21b' included in the stacked film 11b.

[0083] Next, the resist layer 85, the hard mask layer 84, and the insulating film 11e are etched by lithography and RIE (FIG. 12). As a result, a plurality of recesses 95 are formed in the resist layer 85, and these recesses 95 are transferred to the hard mask layer 84 and the insulating film 11e, thereby forming a plurality of recesses 94 in the hard mask layer 84 and the insulating film 11e. These recesses 94 are formed to serve as holes in which the plugs 36b of the plugs C1 to C6 are buried. Each recess 94 shown in FIG. 12 is formed so that the insulating film 11e, having approximately the same thickness as the insulating film 22b, remains below each recess 94. The planar shape of each recess 95 in the resist layer 85 is, for example, circular.

[0084] Next, after removing the resist layer 85, a resist layer 86 is formed on the hard mask layer 84 (FIG. 13). As a result, the recesses 94 for the plugs C1 to C6 are filled with the resist layer 86.

[0085] Next, the resist layer 86, the insulating film 11e, and the stacked film 11b are etched by lithography and RIE (FIG. 13). As a result, a plurality of recesses 96 are formed in the resist layer 86, the resist layer 86 is removed from the recesses 94 for the plugs C1 to C5, and the stacked film 11b in these recesses 94 is further etched. Meanwhile, the resist layer 86 is left in the recess 94 for the plug C6. The stacked film 11b in FIG. 13 is etched so that the bottom surfaces of the recesses 94 for the plugs C1 to C5 reach the upper surfaces of the predetermined insulating films 22b. The planar shape of each recess 96 in the resist layer 86 is, for example, circular.

[0086] 13, the etching for processing the recesses 94 for the plugs C1 to C5 may be performed simultaneously or sequentially. For example, the etching for processing the recesses 94 for the plugs C1 to C4 may be performed simultaneously, and the etching for processing the recesses 94 for the plugs C1 to C4 and the etching for processing the recess 94 for the plug C5 may be performed sequentially. In this case, the etching for processing the recesses 94 for the plugs C1 to C4 and the etching for processing the recess 94 for the plug C5 are performed using, for example, separate resist layers 86.

[0087] Next, after removing the resist layer 86, a resist layer 87 is formed on the hard mask layer 84 (FIG. 14). As a result, the recesses 94 for the plugs C1 to C6 are filled with the resist layer 87.

[0088] Next, the resist layer 87, the stacked film 11b, and the insulating film 11d are etched by lithography and RIE (FIG. 14). As a result, a plurality of recesses 97 are formed in the resist layer 87, the resist layer 87 is removed from the recesses 94 for the plugs C1 to C3, and the stacked film 11b and the insulating film 11d in these recesses 94 are further etched. Meanwhile, the resist layer 87 is left in the recesses 94 for the plugs C4 to C6. The etching of the stacked film 11b and the insulating film 11d in FIG. 14 is performed so that the bottom surface of each recess 94 for the plugs C1 to C3 reaches the upper surface of the corresponding sacrificial layer 36a'. The planar shape of each recess 97 in the resist layer 87 is, for example, circular.

[0089] Next, after removing the resist layer 87 and the hard mask layer 84, the insulating film 35b of the spacer insulating film 35 is formed in each recess 94 (FIG. 15). As a result, the insulating film 35b is formed on the side surface and bottom surface of each recess 94.

[0090] Next, the insulating film 35b is removed from the bottom surface of each recess 94 by lithography and RIE (FIG. 16). At this time, one more insulating film 22b is removed from the bottom surface of the recess 94 for the plug C4, one more insulating film 22b is removed from the bottom surface of the recess 94 for the plug C5, and another insulating film 11e is removed from the bottom surface of the recess 94 for the plug C6. As a result, the bottom surfaces of the recesses 94 for the plugs C4 to C6 reach the upper surface of a predetermined sacrificial layer 21b'. Note that the reason why the insulating film 11e having approximately the same thickness as the insulating film 22b is left under each recess 94 in the step shown in FIG. 12 is to facilitate simultaneous etching of the insulating film 22b under the recesses 94 for the plugs C4 and C5 and the insulating film 11e under the recess 94 for the plug C6 in the step shown in FIG.

[0091] Next, a sacrificial layer 36b' is embedded in each recess 94 (FIG. 17). As a result, a sacrificial layer 36b' is formed on a predetermined sacrificial layer 21a' or sacrificial layer 36a' in each recess 94. The sacrificial layer 36b' is, for example, a polysilicon layer.

[0092] Next, an insulating film 12a for the interlayer insulating film 12 is formed on the insulating film 11e, the insulating film 35b, and the sacrificial layer 36b' (FIG. 18). Next, a plurality of slits (not shown) penetrating the insulating film 12a, the insulating film 11e, the stacked film 11b, the insulating film 11d, the insulating film 11c, and the stacked film 11a are formed, and the sacrificial layers 21a', 21b' are removed from the stacked films 11a, 11b by wet etching through these slits (FIG. 18). As a result, a plurality of recesses Ha are formed in the stacked film 11a, and a plurality of recesses Hb are formed in the stacked film 11b. The recess Hax shown in FIG. 18 is the uppermost recess Ha of the plurality of recesses Ha included in the stacked film 11a. The recess Hbx shown in FIG. 18 is the uppermost recess Hb of the plurality of recesses Hb included in the stacked film 11b.

[0093] Next, electrode layers 21a and 21b (word lines WLa and WLb) are formed in the recesses Ha and Hb through the slits, respectively (FIG. 19). In this way, the sacrificial layers 21a' and 21b' are replaced with the electrode layers 21a and 21b, respectively, to form a laminated film 11 including the electrode layers 21a and 21b. The electrode layer 21ax shown in FIG. 19 is the uppermost electrode layer 21a of the multiple electrode layers 21a included in the laminated film 11a. The electrode layer 21bx shown in FIG. 19 is the uppermost electrode layer 21b of the multiple electrode layers 21b included in the laminated film 11b. The electrode layers 21a and 21b are formed, for example, by sequentially burying a barrier metal layer (e.g., a TiN film (titanium nitride film)) and an electrode material layer (e.g., a W layer) in the recesses Ha and Hb.

[0094] Next, the insulating film 12a is etched by RIE (FIG. 20). As a result, a plurality of recesses 98 are formed in the insulating film 12a. These recesses 98 are formed to be used as contact holes in which the contact plugs 37 of the plugs C1 to C6 are buried. The etching of the insulating film 12a in FIG. 20 is performed so that the bottom surface of each recess 98 for the plugs C1 to C6 reaches the upper surface of the corresponding sacrificial layer 36b'.

[0095] Next, the sacrificial layers 36a', 36b' for the plugs C1 to C6 are removed from the laminated film 11 by etching from the recesses 98 (FIG. 21). As a result, recesses 99 for the plugs C1 to C6 are formed in the laminated film 11. These recesses 99 are formed to be used as contact holes in which the contact plugs 36 of the plugs C1 to C6 are embedded. Each recess 99 for the plugs C1 to C3 includes a recess 99a corresponding to the recess 91 and a recess 99b corresponding to the recess 94. On the other hand, each recess 99 for the plugs C4 to C6 includes only the recess 99b corresponding to the recess 94.

[0096] Next, a material layer for the contact plugs 36, 37 is buried in the recesses 98, 99 for the plugs C1 to C6 (FIG. 22). As a result, the contact plugs 37, 36 are formed in the recesses 98, 99, respectively. Specifically, the plugs 36a, 36b are formed in the recesses 99a, 99b, respectively. Each of the plugs C1 to C3 is formed on the corresponding electrode layer 21a, and each of the plugs C4 to C6 is formed on the corresponding electrode layer 21b. The above material layer is formed to include, for example, a barrier metal layer (e.g., a TiN film) and a plug material layer (e.g., a W layer) in that order. In this manner, the structure shown in FIG. 7 is formed.

[0097] In this comparative example, when manufacturing a semiconductor device, it is difficult to properly form plugs C1 to C6 due to insulating films 11c, 11d, 11e, 12a, 22a, and 22b. For example, it is difficult to leave insulating film 11c having a thickness substantially equal to that of insulating film 22a under each recess 91 in the process shown in FIG. 7, and it is difficult to leave insulating film 11e having a thickness substantially equal to that of insulating film 22b under each recess 94 in the process shown in FIG. 12. This makes it difficult to properly form recesses 91 and 94 for plugs C1 to C6. This problem will be described in more detail later.

[0098] 23 to 40 are cross-sectional views showing the method for manufacturing the semiconductor device of the first embodiment.

[0099] Figures 23 to 40 show steps for forming the structure shown in Figure 6. The steps shown in Figures 23 to 40 correspond to some of the steps shown in Figure 3. In the following explanation of Figures 23 to 40, the explanation of commonalities with Figures 7 to 22 will be omitted to some extent, and the explanation will focus on differences from Figures 7 to 22.

[0100] First, a wiring layer 23, a stacked film 11a, an insulating film 11c, a hard mask layer 81, and a resist layer 82 are formed in this order above a substrate 15 (not shown) of the array wafer W1 (FIG. 23). The stacked film 11a shown in FIG. 23 is formed to include a plurality of sacrificial layers 21a' and a plurality of insulating films 22a, alternating with each other. The sacrificial layer 21ax' shown in FIG. 23 is the uppermost sacrificial layer 21a' among the plurality of sacrificial layers 21a' included in the stacked film 11a. The sacrificial layer 21ax' is an example of a third layer, and each of the sacrificial layers 21a' other than the sacrificial layer 21ax' is an example of a fourth layer.

[0101] Next, the resist layer 82, the hard mask layer 81, the insulating film 11c, and the sacrificial layer 21ax′ are etched by lithography and RIE (FIG. 23). As a result, a plurality of recesses 92 are formed in the resist layer 82, and these recesses 92 are transferred to the hard mask layer 81, the insulating film 11c, and the sacrificial layer 21ax′, thereby forming a plurality of recesses 91 in the hard mask layer 81, the insulating film 11c, and the sacrificial layer 21ax′. These recesses 91 are formed to serve as holes into which the plugs 36a of the plugs C1 and C2 are embedded. Each recess 91 shown in FIG. 7 (comparative example) is formed so that the insulating film 11c, which has a thickness substantially the same as that of the insulating film 22a, remains below each recess 91, whereas each recess 91 shown in FIG. 23 (present embodiment) is formed so as to penetrate the sacrificial layer 21ax′.

[0102] Next, after removing the resist layer 82, a resist layer 83 is formed on the hard mask layer 81 (FIG. 24). As a result, the recesses 91 for the plugs C1 and C2 are filled with the resist layer 83.

[0103] Next, the resist layer 83 and the laminated film 11a are etched by lithography and RIE (FIG. 24). As a result, a recess 93 is formed in the resist layer 83, the resist layer 83 is removed from the recess 91 for the plug C1, and the laminated film 11a in this recess 91 is further etched. Meanwhile, the resist layer 83 is left in the recess 91 for the plug C2. The etching of the laminated film 11a in FIG. 24 is performed so that the bottom surface of the recess 91 for the plug C1 reaches the upper surface of the predetermined insulating film 22a. Note that, because the bottom surface of the recess 91 for the plug C2 reaches the upper surface of the predetermined insulating film 22a in the step shown in FIG. 23, the recess 91 for the plug C2 is not etched in the step shown in FIG. 24.

[0104] 24, the etching for processing the recess 91 for the plug C1 and the etching for processing the recess 91 for the plug C2 may be performed simultaneously or sequentially. In the latter case, the etching for processing the recess 91 for the plug C1 and the etching for processing the recess 91 for the plug C2 are performed using, for example, separate resist layers 83.

[0105] Next, after removing the resist layer 83 and the hard mask layer 81, the insulating film 35a of the spacer insulating film 35 is formed in each recess 91 (FIG. 25). As a result, the insulating film 35a is formed on the side surface and bottom surface of each recess 91.

[0106] Next, the insulating film 35a is removed from the bottom surface of each recess 91 by lithography and RIE (FIG. 26). At this time, one more insulating film 22a is removed from the bottom surface of the recess 91 for the plug C1, and one more insulating film 22a is removed from the bottom surface of the recess 91 for the plug C2. As a result, the bottom surfaces of the recesses 91 for the plugs C1 and C2 reach the upper surface of a predetermined sacrificial layer 21a'.

[0107] Next, a sacrificial layer 36a' is embedded in each recess 91 (FIG. 27). As a result, a sacrificial layer 36a' is formed on a predetermined sacrificial layer 21a' in each recess 91. The sacrificial layer 36a' is an example of a first film.

[0108] Next, an insulating film 11d, a stacked film 11b, an insulating film 11e, a hard mask layer 84, and a resist layer 85 are formed in this order on the insulating film 11c, the insulating film 35a, and the sacrificial layer 36a' (FIG. 28). The stacked film 11b shown in FIG. 28 is formed to include a plurality of sacrificial layers 21b' and a plurality of insulating films 22b alternately. The sacrificial layer 21bx' shown in FIG. 28 is the uppermost sacrificial layer 21b' of the plurality of sacrificial layers 21b' included in the stacked film 11b. The sacrificial layer 21bx' is an example of a first layer, and each of the sacrificial layers 21b' other than the sacrificial layer 21bx' is an example of a second layer.

[0109] Next, the resist layer 85, the hard mask layer 84, the insulating film 11e, and the sacrificial layer 21bx′ are etched by lithography and RIE (FIG. 28). As a result, a plurality of recesses 95 are formed in the resist layer 85, and these recesses 95 are transferred to the hard mask layer 84, the insulating film 11e, and the sacrificial layer 21bx′, thereby forming a plurality of recesses 94 in the hard mask layer 84, the insulating film 11e, and the sacrificial layer 21bx′. These recesses 94 are formed to serve as holes into which the plugs 36b of the plugs C1 to C5 are buried. Each recess 94 shown in FIG. 12 (comparative example) is formed so that the insulating film 11e, which has approximately the same thickness as the insulating film 22b, remains below each recess 94, whereas each recess 94 shown in FIG. 28 (present embodiment) is formed so as to penetrate the sacrificial layer 21bx′.

[0110] Next, after removing the resist layer 85, a resist layer 86 is formed on the hard mask layer 84 (FIG. 29). As a result, the recesses 94 for the plugs C1 to C5 are filled with the resist layer 86.

[0111] Next, the resist layer 86 and the laminated film 11b are etched by lithography and RIE (FIG. 29). As a result, a plurality of recesses 96 are formed in the resist layer 86, the resist layer 86 is removed from the recesses 94 for the plugs C1 to C4, and the laminated film 11b in these recesses 94 is further etched. On the other hand, the resist layer 86 is left in the recess 94 for the plug C5. The etching of the laminated film 11b in FIG. 29 is performed so that the bottom surfaces of the recesses 94 for the plugs C1 to C4 reach the upper surface of the predetermined insulating film 22b. Note that, because the bottom surface of the recess 94 for the plug C5 reaches the upper surface of the predetermined insulating film 22b in the step shown in FIG. 28, the recess 94 for the plug C5 is not etched in the step shown in FIG.

[0112] 29, etching for processing the recesses 94 for the plugs C1 to C4 may be performed simultaneously or sequentially. Furthermore, when etching for processing the recesses 94 for the plugs C1 to C5 is performed in the step shown in FIG. 29, etching for processing the recesses 94 for the plugs C1 to C5 may be performed simultaneously or sequentially in the step shown in FIG. 29. For example, etching for processing the recesses 94 for the plugs C1 to C4 may be performed simultaneously, and etching for processing the recesses 94 for the plugs C1 to C4 and etching for processing the recess 94 for the plug C5 may be performed sequentially. In this case, the etching for processing the recesses 94 for the plugs C1 to C4 and the etching for processing the recess 94 for the plug C5 are performed using, for example, separate resist layers 86.

[0113] Next, after removing the resist layer 86, a resist layer 87 is formed on the hard mask layer 84 (FIG. 30). As a result, the recesses 94 for the plugs C1 to C5 are filled with the resist layer 87.

[0114] Next, the resist layer 87, the stacked film 11b, the insulating film 11d, and the insulating film 11c are etched by lithography and RIE (FIG. 30). As a result, a plurality of recesses 97 are formed in the resist layer 87. The resist layer 87 is removed from the recesses 94 for the plugs C1 to C3, and the stacked film 11b and the insulating film 11d in the recesses 94 for the plugs C1 and C2 and the stacked film 11b, the insulating film 11d, and the insulating film 11c in the recess 94 for the plug C3 are further etched. Meanwhile, the resist layer 87 is left in the recesses 94 for the plugs C4 and C5. The etching of the stacked film 11b, the insulating film 11d, and the insulating film 11c in FIG. 30 is performed so that the bottom surfaces of the recesses 94 for the plugs C1 and C2 reach the upper surfaces of the corresponding sacrificial layers 36a′ and the bottom surface of the recess 94 for the plug C3 reaches the upper surface of the sacrificial layer 21ax′.

[0115] Next, after removing the resist layer 87 and the hard mask layer 84, the insulating film 35b of the spacer insulating film 35 is formed in each recess 94 (FIG. 31). As a result, the insulating film 35b is formed on the side surface and bottom surface of each recess 94.

[0116] Next, the insulating film 35b is removed from the bottom surface of each recess 94 by lithography and RIE (FIG. 32). At this time, one more insulating film 22b is removed from the bottom surface of the recess 94 for the plug C4, and one more insulating film 22b is removed from the bottom surface of the recess 94 for the plug C5. As a result, the bottom surfaces of the recesses 94 for the plugs C4 and C5 reach the upper surface of a predetermined sacrificial layer 21b'.

[0117] Next, a sacrificial layer 36b' is embedded in each recess 94 (FIG. 33). As a result, in each recess 94, a sacrificial layer 36b' is formed on a predetermined sacrificial layer 36a', sacrificial layer 21a', or sacrificial layer 21b'. The sacrificial layer 36b' for the plugs C1 and C2 is an example of a second film. The sacrificial layer 36b' for the plug C3 is an example of a third film. The sacrificial layer 36b' for the plugs C4 and C5 is an example of a fourth film.

[0118] Next, an insulating film 12a for the interlayer insulating film 12 is formed on the insulating film 11e, the insulating film 35b, and the sacrificial layer 36b' (FIG. 34). Next, a plurality of slits (not shown) penetrating the insulating film 12a, the insulating film 11e, the stacked film 11b, the insulating film 11d, the insulating film 11c, and the stacked film 11a are formed, and the sacrificial layers 21a', 21b' are removed from the stacked films 11a, 11b by wet etching through these slits (FIG. 34). As a result, a plurality of recesses Ha are formed in the stacked film 11a, and a plurality of recesses Hb are formed in the stacked film 11b. The recess Hax shown in FIG. 34 is the uppermost recess Ha of the plurality of recesses Ha included in the stacked film 11a. The recess Hbx shown in FIG. 34 is the uppermost recess Hb of the plurality of recesses Hb included in the stacked film 11b.

[0119] Next, electrode layers 21a and 21b (word lines WLa and WLb) are formed in the recesses Ha and Hb from the slits, respectively (FIG. 35). In this manner, the sacrificial layers 21a' and 21b' are replaced with the electrode layers 21a and 21b, respectively, to form a laminated film 11 including the electrode layers 21a and 21b. The electrode layer 21ax shown in FIG. 35 is the uppermost electrode layer 21a of the multiple electrode layers 21a included in the laminated film 11a. The electrode layer 21bx shown in FIG. 35 is the uppermost electrode layer 21b of the multiple electrode layers 21b included in the laminated film 11b.

[0120] Next, the insulating film 12a is etched by RIE (FIG. 36). As a result, a plurality of recesses 98 are formed in the insulating film 12a. These recesses 98 are formed to be used as contact holes in which the contact plugs 37 of the plugs C1 to C5 are buried. The etching of the insulating film 12a in FIG. 36 is performed so that the bottom surface of each recess 98 for the plugs C1 to C5 reaches the upper surface of the corresponding sacrificial layer 36b'.

[0121] Next, the sacrificial layers 36a', 36b' for the plugs C1 to C5 are removed from the stacked film 11 by etching from the recesses 98 (FIG. 37). As a result, recesses 99 for the plugs C1 to C5 are formed in the stacked film 11. These recesses 99 are formed to be used as contact holes in which the contact plugs 36 of the plugs C1 to C5 are embedded. Each recess 99 for the plugs C1 and C2 includes a recess 99a corresponding to the recess 91 and a recess 99b corresponding to the recess 94. On the other hand, each recess 99 for the plugs C3 to C5 includes only the recess 99b corresponding to the recess 94. The recesses 98, 99 for the plugs C1 and C2 are an example of a fourth recess. The recesses 98, 99 for the plug C3 are an example of a third recess. The recesses 98, 99 for the plugs C4 and C5 are an example of a second recess.

[0122] Next, a material layer for contact plugs 36, 37 is buried in the recesses 98, 99 for plugs C1 to C5 (FIG. 38). As a result, contact plugs 37, 36 are formed in the recesses 98, 99, respectively. Specifically, plugs 36a, 36b are formed in the recesses 99a, 99b, respectively. Each of the plugs C1 to C3 is formed on the corresponding electrode layer 21a, and each of the plugs C4 to C6 is formed on the corresponding electrode layer 21b.

[0123] Next, the insulating film 12a and the insulating film 11e are etched by RIE (FIG. 39). As a result, a recess 98 is formed in the insulating film 12a and the insulating film 11e. This recess 98 is formed to be used as a contact hole in which the contact plug 37 of the plug C6 is embedded. The etching of the insulating film 12a and the insulating film 11e in FIG. 39 is performed so that the bottom surface of this recess 98 reaches the upper surface of the electrode layer 21bx. This recess 98 for the plug C6 is an example of a first recess.

[0124] 39 may be performed simultaneously with the RIE in the step shown in Fig. 36. This makes it possible to form the recess 98 for the plug C6 simultaneously with the recesses 98 for the plugs C1 to C5.

[0125] Next, a material layer for the contact plug 37 is buried in the recess 98 for the plug C6 (FIG. 40). As a result, the plug C6 (contact plug 37) is formed in the recess 98 for the plug C6. The plug C6 is formed on the electrode layer 21bx. The material layer used in the step shown in FIG. 40 is the same as the material layer used in the step shown in FIG. 38, for example. In this manner, the structure shown in FIG. 8 is formed.

[0126] 40 may be performed simultaneously with the filling step shown in Fig. 38. For example, the step (RIE) shown in Fig. 36 and Fig. 39 may be performed simultaneously, then the step (etching) shown in Fig. 37 may be performed, and then the step (filling) shown in Fig. 38 and Fig. 40 may be performed simultaneously. This makes it possible to form the plug C6 simultaneously with the plugs C1 to C5.

[0127] As described above, in the comparative example, when manufacturing a semiconductor device, it is difficult to properly form plugs C1 to C6 due to the insulating films 11c, 11d, 11e, 12a, 22a, and 22b. For example, it is difficult to leave insulating film 11c having a thickness substantially equal to that of insulating film 22a under each recess 91 in the process shown in FIG. 7, or to leave insulating film 11e having a thickness substantially equal to that of insulating film 22b under each recess 94 in the process shown in FIG. 12. On the other hand, according to this embodiment, by forming plug C3 without using the recess 91 and by forming plug C6 without using the recess 94, it is possible to avoid leaving insulating films 11c and 11e under the recesses 91 and 94. This addresses the problem in the comparative example and enables proper formation of recesses 91 and 94 for plugs C1 to C6 through simple processing.

[0128] As described above, according to this embodiment, plugs C1 to C6 can be preferably formed by forming plug C3 without using plug 36a and by forming plug C6 without using plug 36b. In this embodiment, by forming plug C3 without using plug 36a, the diameter of plug C3 changes continuously between portion Pa and portion Pb as shown in FIG. 6. Similarly, in this embodiment, by forming plug C6 without using plug 36b, the diameter of plug C6 changes continuously between portion Pb and portion Pc as shown in FIG. 6.

[0129] The hard mask layers 81 and 84 of this embodiment (see FIGS. 23, 28, etc.) are, for example, polysilicon layers. According to this embodiment, by using polysilicon layers for the hard mask layers 81 and 84, it is possible to prevent exposure light from passing through the hard mask layers 81 and 84, for example, when the resist layers 82, 83, 85, 86, and 87 are exposed for lithography. The resist layers 82, 83, 85, 86, and 87 are formed of, for example, a negative resist material.

[0130] (Second embodiment) 41 to 44 are cross-sectional views showing a method for manufacturing a semiconductor device according to the second embodiment. The method for manufacturing a semiconductor device according to the present embodiment is generally similar to the method for manufacturing a semiconductor device according to the first embodiment, except for the following points.

[0131] FIG. 41 shows a process corresponding to the process shown in FIG. 27. The sacrificial layer 36a' in this embodiment is formed by sequentially filling each recess 91 with sacrificial layers L1 and L2. The sacrificial layer L2 is, for example, a SiN film. The sacrificial layer L1 is, for example, a protective film for protecting this SiN film. The sacrificial layer L2 may be a polysilicon layer, similar to the sacrificial layer 36a' in the first embodiment.

[0132] FIG. 42 shows a process corresponding to the process shown in FIG. 33. The sacrificial layer 36b' in this embodiment is formed by sequentially filling the recesses 94 with sacrificial layers L3 and L4. The sacrificial layer L4 is, for example, a SiN film. The sacrificial layer L3 is, for example, a protective film for protecting this SiN film. The sacrificial layer L4 may be a polysilicon layer, similar to the sacrificial layer 36b' in the first embodiment.

[0133] According to this embodiment, during the wet etching shown in FIG. 34, the sacrificial layers L2 and L4 can be protected from the etching solution by the sacrificial layers L1 and L3.

[0134] Figures 43 and 44 show steps corresponding to the steps shown in Figures 36 and 37. The sacrificial layers 36a', 36b' (L1 to L4) of this embodiment are removed by etching from the recesses 98, similar to the sacrificial layers 36a', 36b' of the first embodiment.

[0135] According to this embodiment, by using the sacrificial layers L1 and L3 that function as protective films, it becomes possible to use various materials for the sacrificial layers L2 and L4.

[0136] (Third embodiment) FIG. 45 is a cross-sectional view showing the structure of the semiconductor device of the third embodiment.

[0137] The semiconductor device of this embodiment (FIG. 45) has the same structure as the semiconductor device of the first embodiment (FIG. 6). Therefore, the semiconductor device of this embodiment can be manufactured by, for example, the method for manufacturing the semiconductor device of the first embodiment shown in FIGS.

[0138] However, the thickness of the insulating film 11c in this embodiment is set thinner than the thickness of the insulating film 11c in the first embodiment. The insulating film 11c in this embodiment can be obtained, for example, by thinning the insulating film 11c between the step of FIG. 27 and the step of FIG. 28. The thinning of the insulating film 11c can be performed, for example, by CMP or dry etch-back. The thickness of the insulating film 11c shown in FIG. 45 is the same as the thickness of the insulating films 22a and 22b, for example. Meanwhile, in this embodiment, the total thickness (thickness of the joint insulating film) of the insulating films 11c and 11d shown in FIG. 45 may be the same as the thickness of the insulating films 22a and 22b.

[0139] Similarly, the thickness of the insulating film 11e of this embodiment is set thinner than the thickness of the insulating film 11e of the first embodiment. The insulating film 11e of this embodiment can be obtained, for example, by thinning the insulating film 11e between the steps of FIG. 33 and FIG. 34. The thinning of the insulating film 11e can be performed, for example, by CMP or dry etch-back. The thickness of the insulating film 11e shown in FIG. 45 is the same as the thickness of the insulating films 22a and 22b, for example.

[0140] 45 has an advantage that, for example, the thickness of the laminated film 11 can be reduced. On the other hand, when the thickness of the insulating films 11c and 11e shown in FIG. 45 is increased, an advantage is that, for example, the breakdown voltage of the semiconductor device of this embodiment can be increased.

[0141] (Fourth embodiment) FIG. 46 is a cross-sectional view showing the structure of the semiconductor device of the fourth embodiment.

[0142] The semiconductor device of the first embodiment is manufactured by bonding an array wafer W1 and a circuit wafer W2 together, as shown in Figures 3 and 4. On the other hand, the semiconductor device of this embodiment is manufactured without such bonding.

[0143] Therefore, as shown in Fig. 46, the semiconductor device of this embodiment includes a substrate 15 that is removed during the manufacture of the semiconductor device in the first embodiment. The orientation of the laminated film 11 shown in Fig. 46 is opposite to the orientation of the laminated film 11 shown in Figs. 1 and 6. This is because the laminated film 11 shown in Fig. 46 is drawn so that the substrate 15 is located below the laminated film 11, whereas the laminated film 11 shown in Figs. 1 and 6 is drawn so that the substrate 14 is located below the laminated film 11. The laminated film 11 of this embodiment has the same structure as the laminated film 11 of the first embodiment if the orientation shown in Fig. 46 is reversed.

[0144] (Fifth embodiment) FIG. 47 is a cross-sectional view showing the structure of the semiconductor device of the fifth embodiment.

[0145] The semiconductor device of this embodiment (FIG. 47) has the same structure as the semiconductor device of the first embodiment (FIG. 6). However, the plug C3 of this embodiment has the same structure as the plug C3 shown in FIG. 6, whereas the plug C6 of this embodiment has the same structure as the plug C6 shown in FIG.

[0146] 48 and 49 are cross-sectional views showing a method for manufacturing the semiconductor device of the fifth embodiment.

[0147] The semiconductor device of this embodiment is manufactured by the semiconductor device manufacturing method of the first embodiment shown in Figures 23 to 40. However, in this embodiment, the steps of Figures 48 and 49 are performed between the step of Figure 33 and the step of Figure 34. In the steps of Figures 48 and 49, an insulating film 35b and a sacrificial layer 36b' for plug C6 are formed in the same flow as the steps of Figures 12 to 17. Furthermore, in this embodiment, the steps of Figures 36 to 38 are performed not only on plugs C1 to C5 but also on plug C6, and the steps of Figures 39 and 40 are omitted.

[0148] FIG. 50 is a cross-sectional view showing the structure of a semiconductor device according to a modification of the fifth embodiment.

[0149] The semiconductor device of this modification (FIG. 50) has a structure similar to that of the semiconductor device of the fifth embodiment (FIG. 47). However, the side surface of the plug 36b in the plug C6 of this modification is not surrounded by the insulating film 35b. Because the plug 36b is not formed in the stacked film 11b, the step of forming the insulating film 35b for the plug 36b can be omitted.

[0150] As described above, according to this embodiment, of the plugs C3 and C6, only the plug C3 can have the same structure as that of the first embodiment.

[0151] (Sixth embodiment) FIG. 51 is a cross-sectional view showing the structure of the semiconductor device of the sixth embodiment.

[0152] The semiconductor device of this embodiment (FIG. 51) has the same structure as the semiconductor device of the first embodiment (FIG. 6). However, the plug C6 of this embodiment has the same structure as the plug C6 shown in FIG. 6, whereas the plug C3 of this embodiment has the same structure as the plug C3 shown in FIG.

[0153] 52 and 53 are cross-sectional views showing a method for manufacturing the semiconductor device of the sixth embodiment.

[0154] The semiconductor device of this embodiment is manufactured by the semiconductor device manufacturing method of the first embodiment shown in Figures 23 to 40. However, in this embodiment, the steps of Figures 52 and 53 are performed between the step of Figure 27 and the step of Figure 28. In the steps of Figures 52 and 53, an insulating film 35a and a sacrificial layer 36a' for plug C3 are formed in the same flow as the steps of Figures 7 to 11. Furthermore, in this embodiment, in the step of Figure 30, a recess 94 for plug C3 is processed in the same way as the recesses 94 for plugs C1 and C2.

[0155] FIG. 54 is a cross-sectional view showing the structure of a semiconductor device according to a modification of the sixth embodiment.

[0156] The semiconductor device of this modification (FIG. 54) has a structure similar to that of the semiconductor device of the sixth embodiment (FIG. 51). However, the side surface of the plug 36a in the plug C3 of this modification is not surrounded by the insulating film 35a. Because the plug 36a is not formed in the stacked film 11a, the step of forming the insulating film 35a for the plug 36a can be omitted.

[0157] As described above, according to this embodiment, the same structure as in the first embodiment can be adopted for only the plug C6 out of the plugs C3 and C6.

[0158] Although several embodiments have been described above, these embodiments are presented only as examples and are not intended to limit the scope of the invention. The novel apparatus and method described herein may be embodied in various other forms. Furthermore, various omissions, substitutions, and modifications may be made to the forms of the apparatus and method described herein without departing from the spirit of the invention. The appended claims and their equivalents are intended to cover such forms and modifications that fall within the scope and spirit of the invention. [Explanation of symbols]

[0159] 1: Array chip, 2: Circuit chip, 11: laminated film, 11a: laminated film, 11b: laminated film, 11c: insulating film, 11d: insulating film, 11e: insulating film, 12: interlayer insulating film, 12a: insulating film, 13: interlayer insulating film, 14: substrate, 15: substrate, 21a: electrode layer, 21a': sacrificial layer, 21ax: electrode layer, 21ax': sacrificial layer, 21b: electrode layer, 21b': sacrificial layer, 21bx: electrode layer, 21bx': sacrificial layer, 22a: insulating film, 22b: insulating film, 23: wiring layer, 31: memory cell array, 32: columnar portion, 33: contact plug, 34: beam portion, 35: spacer insulating film, 35a: insulating film, 35b: insulating film, 36: contact plug, 36a: plug, 36a': sacrificial layer, 36b: plug, 36b': sacrificial layer, 37: contact plug, 38: word wiring layer, 41: transistor, 41a: gate insulating film, 41b: gate electrode, 42: contact plug, 43: wiring layer, 44: wiring layer, 45: wiring layer, 46: via plug, 47: metal pad, 51: metal pad, 52: via plug, 53: wiring layer, 54: wiring layer, 55: spacer insulating film, 55a: insulating film, 55b: insulating film, 56: via plug, 56a: plug, 56b: plug, 61: insulating film, 62: metal pad, 63: passivation insulating film, 71: Block insulating film, 72: Charge storage layer, 73: Tunnel insulating film, 74: channel semiconductor layer, 75: core insulating film, 81: hard mask layer, 82: resist layer, 83: resist layer, 84: hard mask layer, 85: resist layer, 86: resist layer, 87: resist layer, 91: recess, 92: recess, 93: recess, 94: recess, 95: recess, 96: recess, 97: recess, 98: recess, 99: recess, 99a: recess, 99b: recess

Claims

1. a first insulating film; a second insulating film provided on the first insulating film; a first stacked film including a first electrode layer provided on the second insulating film and a plurality of second electrode layers provided above the first electrode layer and spaced apart from each other in a first direction; a third insulating film provided on the first stacked film; a fourth insulating film provided on the third insulating film; a second stacked film including a third electrode layer provided on the fourth insulating film and a plurality of fourth electrode layers provided above the third electrode layer and spaced apart from each other in the first direction; a first plug electrically connected to the first electrode layer; a second plug electrically connected to any one of the plurality of second electrode layers; a third plug electrically connected to the third electrode layer; a fourth plug electrically connected to any one of the plurality of fourth electrode layers; the fourth plug includes a first portion provided in the second insulating film, the first stacked film, and the third insulating film, and a second portion provided on the first portion in the fourth insulating film and the second stacked film, and a diameter of the fourth plug discontinuously changes at a boundary between the first portion and the second portion along the first direction; the third plug includes a third portion provided in the second insulating film, the first stacked film, and the third insulating film, and a fourth portion provided in the fourth insulating film on the third portion, and a diameter of the third plug changes continuously along the first direction at a boundary between the third portion and the fourth portion. Semiconductor device.

2. the second plug includes a fifth portion provided in the first insulating film and a sixth portion provided on the fifth portion in the second insulating film and the first stacked film, and a diameter of the second plug varies discontinuously at a boundary between the fifth portion and the sixth portion along the first direction; the first plug includes a seventh portion provided in the first insulating film and an eighth portion provided on the seventh portion in the second insulating film, and a diameter of the first plug continuously changes at a boundary between the seventh portion and the eighth portion along the first direction. The semiconductor device according to claim 1 .

3. the fourth plug further includes a ninth portion provided in the first insulating film below the first portion, and a diameter of the fourth plug discontinuously changes at a boundary between the first portion and the ninth portion along the first direction; the third plug further includes a tenth portion provided in the first insulating film below the third portion, and a diameter of the third plug discontinuously changes at a boundary between the third portion and the tenth portion along the first direction. The semiconductor device according to claim 1 .

4. 2. The semiconductor device according to claim 1, wherein each of said first to fourth portions is surrounded by an insulating film having a tubular shape extending in said first direction.

5. 3. The semiconductor device according to claim 2, wherein only said fifth portion of said fifth to eighth portions is surrounded by an insulating film having a tubular shape extending in said first direction.

6. the first direction is a direction from the first stacked film to the second stacked film, 2. The semiconductor device according to claim 1, wherein each of said first to fourth portions has a diameter that decreases along said first direction.

7. the first direction is a direction from the first stacked film to the second stacked film, 3. The semiconductor device according to claim 2, wherein each of said fifth to eighth portions has a diameter that decreases along said first direction.

8. the first stacked film further includes a plurality of fifth insulating films provided on the first electrode layer alternately with the plurality of second electrode layers in the first direction, 2. The semiconductor device according to claim 1, wherein a total thickness of said third insulating film and said fourth insulating film is greater than a thickness of at least one of said plurality of fifth insulating films.

9. the second stacked film further includes a plurality of sixth insulating films provided on the third electrode layer alternately with the plurality of fourth electrode layers in the first direction, 2. The semiconductor device according to claim 1, wherein a total thickness of said third insulating film and said fourth insulating film is greater than a thickness of at least one of said plurality of sixth insulating films.

10. a first insulating film; a second insulating film provided on the first insulating film; a first stacked film including a first electrode layer provided on the second insulating film and a plurality of second electrode layers provided above the first electrode layer and spaced apart from each other in a first direction; a third insulating film provided on the first stacked film; a fourth insulating film provided on the third insulating film; a second stacked film including a third electrode layer provided on the fourth insulating film and a plurality of fourth electrode layers provided above the third electrode layer and spaced apart from each other in the first direction; a first plug electrically connected to the first electrode layer; a second plug electrically connected to any one of the plurality of second electrode layers; a third plug electrically connected to the third electrode layer; a fourth plug electrically connected to any one of the plurality of fourth electrode layers; the second plug includes a fifth portion provided in the first insulating film and a sixth portion provided on the fifth portion in the second insulating film and the first stacked film, and a diameter of the second plug varies discontinuously at a boundary between the fifth portion and the sixth portion along the first direction; the first plug includes a seventh portion provided in the first insulating film and an eighth portion provided on the seventh portion in the second insulating film, and a diameter of the first plug varies discontinuously at a boundary between the seventh portion and the eighth portion along the first direction. Semiconductor device.

11. the fourth plug includes a first portion provided in the second insulating film, the first stacked film, and the third insulating film, and a second portion provided on the first portion in the fourth insulating film and the second stacked film, and a diameter of the fourth plug discontinuously changes at a boundary between the first portion and the second portion along the first direction; the third plug includes a third portion provided in the second insulating film, the first stacked film, and the third insulating film, and a fourth portion provided in the fourth insulating film on the third portion, and a diameter of the third plug changes continuously along the first direction at a boundary between the third portion and the fourth portion. The semiconductor device according to claim 10.

12. 12. The semiconductor device according to claim 11, wherein each of said first to fourth portions is surrounded by an insulating film having a tubular shape extending in said first direction.

13. 11. The semiconductor device according to claim 10, wherein only the fifth portion of the fifth to eighth portions is surrounded by an insulating film having a tubular shape extending in the first direction.

14. the first direction is a direction from the first stacked film to the second stacked film, 12. The semiconductor device according to claim 11, wherein each of the first to fourth portions has a diameter that decreases along the first direction.

15. the first direction is a direction from the first stacked film to the second stacked film, 11. The semiconductor device according to claim 10, wherein each of the fifth to eighth portions has a diameter that decreases along the first direction.

16. the first stacked film further includes a plurality of fifth insulating films provided on the first electrode layer alternately with the plurality of second electrode layers in the first direction, 11. The semiconductor device according to claim 10, wherein a total thickness of said third insulating film and said fourth insulating film is thicker than a thickness of at least one of said plurality of fifth insulating films.

17. the second stacked film further includes a plurality of sixth insulating films provided on the third electrode layer alternately with the plurality of fourth electrode layers in the first direction, 11. The semiconductor device according to claim 10, wherein a total thickness of said third insulating film and said fourth insulating film is thicker than a thickness of at least one of said plurality of sixth insulating films.

18. forming a plurality of fourth layers spaced apart from each other in a first direction, and forming a third layer above the plurality of fourth layers, thereby forming a second stacked film including the plurality of fourth layers and the third layer; forming a fourth insulating film on the second stacked film; forming a first film on any one of the plurality of fourth layers in the fourth insulating film and the second stacked film; forming a third insulating film on the fourth insulating film after forming the first film; forming a plurality of second layers spaced apart from each other in the first direction on the third insulating film, and forming a first layer above the plurality of second layers to form a first stacked film including the plurality of second layers and the first layer; forming a second insulating film on the first stacked film; forming a second film on the first film within the second insulating film, the first stacked film, and the third insulating film; forming a third film on the third layer within the second insulating film, the first stacked film, the third insulating film, and the fourth insulating film; The first to fourth layers are replaced with first to fourth electrode layers, respectively; removing the first film and the second film to form a fourth recess; forming a fourth plug on any one of the plurality of fourth electrode layers in the fourth recess; removing the third film to form a third recess; forming a third plug on the third electrode layer within the third recess; A method for manufacturing a semiconductor device, comprising:

19. After forming the second film and the third film, the method further includes forming a first insulating film on the second insulating film; the fourth recess is formed by etching the first insulating film and removing the first film and the second film; the third recess is formed by etching the first insulating film and removing the third film. The method for manufacturing a semiconductor device according to claim 18.

20. forming a plurality of fourth layers spaced apart from each other in a first direction, and forming a third layer above the plurality of fourth layers, thereby forming a second stacked film including the plurality of fourth layers and the third layer; forming a fourth insulating film on the second stacked film; forming a third insulating film on the fourth insulating film; forming a plurality of second layers spaced apart from each other in the first direction on the third insulating film, and forming a first layer above the plurality of second layers to form a first stacked film including the plurality of second layers and the first layer; forming a second insulating film on the first stacked film; forming a fourth film on any one of the plurality of second layers in the second insulating film and the first stacked film; The first to fourth layers are replaced with first to fourth electrode layers, respectively; After forming the fourth film, a first insulating film is formed on the second insulating film; forming a second recess by etching the first insulating film and removing the fourth film; forming a second plug in the second recess on any one of the plurality of second electrode layers; forming a first recess by etching the first insulating film and the second insulating film; forming a first plug on the first electrode layer within the first recess; A method for manufacturing a semiconductor device, comprising:

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