Image sensor and method of manufacturing the same

Abstract

To provide an image sensor in which occurrence of cracks due to a stress difference in the image sensor is minimized, and to provide a method of manufacturing the same.SOLUTION: An image sensor includes a photoelectric conversion device provided in a pixel array region, a peripheral region provided on at least one side of the pixel array region, and a nanostructure layer provided on the pixel array region and the peripheral region, wherein the nanostructure layer includes a meta-microlens configured to collect light incident on the pixel array on the pixel array region, and a dummy nanopattern on the peripheral region.SELECTED DRAWING: Figure 3B

Description

[Technical Field]

[0001] The present invention relates to an image sensor and a method for manufacturing the same. [Background technology]

[0002] The image sensor is a semiconductor-based sensor that is used in optical sensors or imaging modules to convert optical images into electrical signals, and includes a pixel array having a plurality of pixels.

[0003] Image sensors are manufactured using a variety of materials, each with a different thermal expansion coefficient. Therefore, stress cracks often occur during the manufacturing process or post-manufacturing evaluation process of the image sensor due to the difference in thermal expansion coefficient. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent No. 11,978,748 Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention has been made in view of the above-mentioned conventional problems, and an object of the present invention is to provide an image sensor and a manufacturing method thereof that minimizes the occurrence of cracks due to stress differences within the image sensor. [Means for solving the problem]

[0006] In order to achieve the above object, an image sensor according to one aspect of the present invention comprises a photoelectric conversion element provided within a pixel array region, a peripheral region provided on at least one side of the pixel array region, and a nanostructure layer provided on the pixel array region and the peripheral region, wherein the nanostructure layer includes a meta-microlens configured to collect light incident on the pixel array on the pixel array region, and includes a dummy nanopattern on the peripheral region.

[0007] To achieve the above object, one aspect of the present invention provides a method for manufacturing an image sensor, comprising the steps of: providing a first substrate including a pixel array region and a peripheral region; forming an etching prevention film on the pixel array region and the peripheral region; forming an initial nanostructure layer on the pixel array region and the peripheral region using a material having a first refractive index; patterning the initial nanostructure layer to form a plurality of holes; forming nanoposts in the plurality of holes by depositing a material having a second refractive index different from the first refractive index; forming a meta-microlens on the pixel array region using the nanoposts; and forming a dummy nanopattern on the peripheral region using the nanoposts. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide an image sensor and a manufacturing method thereof that minimizes the occurrence of cracks due to stress by providing a structure that can alleviate or buffer stress differences within the image sensor. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a block diagram of an image sensor according to an embodiment of the present invention; [Figure 2] 2 is a circuit diagram of a pixel included in a pixel array of an image sensor according to an embodiment of the present invention. [Figure 3A]1 is a plan view illustrating an image sensor according to an embodiment of the present invention; [Figure 3B] FIG. 3B is an enlarged plan view of a first example showing a portion P1 of FIG. 3A. [Figure 4] FIG. 3C is a cross-sectional view of the first example taken along line AA' in FIG. 3B. [Figure 5] This is an enlarged view of the pixel array region corresponding to R1 in Figure 3B, and also shows a plan view of a meta-microlens corresponding to the pixel and a cross-sectional view of the plan view cut along line B-B'. [Figure 6] This is an enlarged view of the peripheral area corresponding to R2 in Figure 3B, showing a plan view of the peripheral area where dummy nanopatterns are provided, and a cross-sectional view of the plan view cut along line CC'. [Figure 7] 10 is a perspective view illustrating an example of the shape of a second nanopost according to an embodiment of the present invention. FIG. [Figure 8] FIG. 3B is an enlarged plan view of a second example showing a portion P1 of FIG. 3A. [Figure 9] 9 is an enlarged view of the surrounding area corresponding to R3 in FIG. 8. FIG. [Figure 10] 3B is a diagram showing a third example of an image sensor according to an embodiment of the present invention, illustrating a region corresponding to part P1 of FIG. 3A. [Figure 11] 3B is a diagram showing a fourth example of an image sensor according to an embodiment of the present invention, illustrating a region corresponding to part P1 of FIG. 3A. [Figure 12A] FIG. 3B is an enlarged plan view of a fifth example showing a portion P2 of FIG. 3A. [Figure 12B] FIG. 3B is an enlarged plan view of a sixth example showing a portion P2 of FIG. 3A. [Figure 12C] FIG. 3B is an enlarged plan view of a seventh example showing a portion P2 of FIG. 3A. [Figure 13] FIG. 10 is a cross-sectional view of an eighth example of an image sensor according to an embodiment of the present invention. [Figure 14]13. FIG. 14 is a cross-sectional view of a ninth example of an image sensor according to an embodiment of the present invention, illustrating the image sensor shown in FIG. 13 on which an anti-reflection film is further formed. [Figure 15] FIG. 19 is a cross-sectional view of a tenth example of an image sensor according to an embodiment of the present invention, in which a portion of the nanostructure layer is used as a color separation lens array. [Figure 16] FIG. 16 is a cross-sectional view showing an eleventh example of an image sensor according to an embodiment of the present invention. [Figure 17A] 1A to 1C are cross-sectional views sequentially illustrating a method for manufacturing an image sensor according to an embodiment of the present invention. [Figure 17B] 1A to 1C are cross-sectional views sequentially illustrating a method for manufacturing an image sensor according to an embodiment of the present invention. [Figure 17C] 1A to 1C are cross-sectional views sequentially illustrating a method for manufacturing an image sensor according to an embodiment of the present invention. [Figure 17D] 1A to 1C are cross-sectional views sequentially illustrating a method for manufacturing an image sensor according to an embodiment of the present invention. [Figure 17E] 1A to 1C are cross-sectional views sequentially illustrating a method for manufacturing an image sensor according to an embodiment of the present invention. [Figure 17F] 1A to 1C are cross-sectional views sequentially illustrating a method for manufacturing an image sensor according to an embodiment of the present invention. [Figure 17G] 1A to 1C are cross-sectional views sequentially illustrating a method for manufacturing an image sensor according to an embodiment of the present invention. [Figure 17H] 1A to 1C are cross-sectional views sequentially illustrating a method for manufacturing an image sensor according to an embodiment of the present invention. [Figure 17I] 1A to 1C are cross-sectional views sequentially illustrating a method for manufacturing an image sensor according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0010] Since the present invention can be modified in various ways and can have various forms, specific embodiments are illustrated in the drawings and described in detail herein, but it should be understood that this is not intended to limit the present invention to the specific embodiments, and that the present invention includes all modifications, equivalents, and alternatives within the spirit and technical scope of the present invention.

[0011] Hereinafter, specific examples of embodiments of the present invention will be described in detail with reference to the drawings.

[0012] FIG. 1 is a block diagram of an image sensor according to one embodiment of the present invention.

[0013] Referring to FIG. 1 , an image sensor according to an embodiment of the present invention includes a pixel array 1, a row decoder 2, a row driver 3, a column decoder 4, a timing generator 5, a correlated double sampler (CDS) 6, an analog to digital converter (ADC) 7, and an input / output buffer 8.

[0014] The pixel array 1 includes a plurality of pixels arranged two-dimensionally, and the pixels convert optical signals into electrical signals. The pixel array 1 is driven by a plurality of drive signals (e.g., pixel select signals, reset signals, and / or charge transfer signals) transmitted from a row driver 3. The converted electrical signals are provided to a correlated double sampler 6.

[0015] The row driver 3 provides a plurality of driving signals to the pixel array 1 for driving a plurality of pixels according to the result of decoding by the row decoder 2. When the pixels are arranged in a matrix, the driving signals are provided row by row.

[0016] A timing generator 5 provides timing and control signals to the row decoder 2 and the column decoder 4 .

[0017] The correlated double sampler 6 receives the electrical signal generated by the pixel array 11 and holds and samples the received signal. The correlated double sampler 6 double samples a specific noise level and a signal level based on the electrical signal, and outputs a difference level corresponding to the difference between the noise level and the signal level.

[0018] The analog-to-digital converter 7 converts the analog signal corresponding to the difference level output from the correlated double sampler 6 into a digital signal and outputs the digital signal.

[0019] The input / output buffer 8 latches the digital signals and sequentially outputs the latched signals to an image signal processor (not shown) according to the decoding results of the column decoder 4.

[0020] FIG. 2 is a circuit diagram of a pixel included in a pixel array of an image sensor according to an embodiment of the present invention.

[0021] 2, the pixel array includes a plurality of pixels PXL, which are arranged in a matrix. Each pixel PXL includes a pixel transistor, which includes a transfer transistor TX and logic transistors (RX, SX, SFX). The logic transistors (RX, SX, SFX) include a reset transistor RX, a selection transistor SX, and a source follower transistor SFX. Each pixel PXL also includes a photoelectric conversion element PD and a floating diffusion region FD.

[0022] The photoelectric conversion element PD generates and accumulates photocharges in proportion to the amount of externally incident light. The photoelectric conversion element PD may include a photodiode, a phototransistor, a photogate, a pinned photodiode, or a combination thereof. The transfer transistor TX transfers the photocharges generated in the photoelectric conversion element PD to the floating diffusion region FD. The transfer gate of the transfer transistor TX is connected to a transfer gate line TGL. The floating diffusion region FD receives and cumulatively stores the photocharges generated in the photoelectric conversion element PD.

[0023] The gate of the source follower transistor SFX is connected to the floating diffusion region FD, and the drain terminal of the source follower transistor SFX is connected to a power supply terminal VDD to which a power supply voltage is supplied. The source follower transistor SFX is controlled according to the amount of photocharge accumulated in the floating diffusion region FD.

[0024] The reset transistor RX periodically resets the charge stored in the floating diffusion region FD. The gate of the reset transistor RX is connected to a reset gate line RGL. The source terminal of the reset transistor RX is connected to the floating diffusion region FD, and the drain terminal of the reset transistor RX is connected to a power supply terminal V. DD When the reset transistor RX is turned on, the power supply terminal V DD The power supply voltage is applied to the floating diffusion region FD through the reset transistor RX. In other words, when the reset transistor RX is turned on, the charge stored in the floating diffusion region FD is discharged by the power supply voltage, and the floating diffusion region FD is reset.

[0025] The source follower transistor SFX acts as a source follower buffer amplifier, amplifying the potential change in the floating diffusion region FD and outputting the amplified potential change to the output line VOUT.

[0026] The gate of the select transistor SX is connected to a select gate line SGL, the drain terminal of the select transistor SX is connected to the source terminal of the source follower transistor SFX, and the source terminal of the select transistor SX is connected to an output line V OUT The selection transistor SX of the pixel PXL to be read out row by row is selected by a selection signal applied through the corresponding selection gate line SGL. When the selection transistor SX is turned on, the potential change amplified by the source follower transistor SFX is transmitted to the output line V through the selection transistor SX. OUT will be output.

[0027] Although each pixel PXL has a single photoelectric conversion element PD in FIG. 2, embodiments of the present invention are not limited thereto. In one embodiment, each pixel PXL may include a plurality of photoelectric conversion elements PD. In this case, a plurality of transfer transistors TX are provided in each pixel PXL to correspond to the plurality of photoelectric conversion elements PD, respectively. The plurality of photoelectric conversion elements PD and the plurality of transfer transistors TX each constitute a plurality of sub-pixels, and the sub-pixels share the floating diffusion region FD and logic transistors (RX, SX, SFX) of each pixel PXL.

[0028] Fig. 3A is a plan view showing an image sensor according to an embodiment of the present invention, Fig. 3B is a plan view of a first example showing an enlarged view of part P1 of Fig. 3A, and Fig. 4 is a cross-sectional view of the first example taken along line A-A' of Fig. 3B.

[0029] 3A, 3B, and 4, an image sensor according to an embodiment of the present invention includes a first structure S1 and a second structure S2. The first structure S1 is stacked on the second structure S2. That is, the image sensor has a stack structure. The first structure S1 is a sensor chip provided with a photoelectric conversion region 110. The second structure S2 is a logic chip provided with a logic circuit. The first structure S1 and the second structure S2 are bonded to each other by at least one of various bonding methods and electrically connected to each other by at least one of various connection methods.

[0030] The first structure S1 includes a photoelectric conversion layer 10, a light-transmitting layer 20, and a first wiring layer 30. The photoelectric conversion layer 10 is disposed between the light-transmitting layer 20 and the first wiring layer 30. The photoelectric conversion layer 10 includes a first substrate 100, which includes a pixel array region AR, a peripheral region PP, and a pad region PR. The pixel array region AR has a rectangular shape in a plan view. However, the shape of the pixel array region AR is not limited to this and may be a shape other than a rectangle, for example, a circle.

[0031] The first substrate 100 has a first surface 100a and a second surface 100b facing each other. In one embodiment, the first substrate 100 is a semiconductor substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, or a silicon germanium (SiGe) substrate).

[0032] The peripheral region PP is disposed between the pixel array region AR and the pad region PR in a plan view. In one embodiment, the peripheral region PP surrounds at least a portion of the pixel array region AR in a plan view, and the pad region PR surrounds at least a portion of the pixel array region AR and the peripheral region PP in a plan view. However, embodiments of the present invention are not limited thereto. In one embodiment, the peripheral region PP and the pad region PR may be provided on one or some of the four sides of the pixel array region AR in a plan view. For example, as shown in FIG. 3A , the peripheral region PP and the pad region PR may be provided on one or some of the three sides of the pixel array region AR in a plan view. In one embodiment, the peripheral region PP and the pad region PR may be provided on all four sides of the pixel array region AR in a plan view. In this case, the pixel array region AR corresponds to the center of the first substrate 100, and the peripheral region PP and the pad region PR correspond to the edges of the first substrate 100 in a plan view.

[0033] A deep isolation pattern DTI is provided in the first substrate 100 to define a plurality of pixel regions PXR. A shallow isolation pattern STI is provided in the first substrate 100 to define at least one active region in each of the pixel regions PXR. The shallow isolation pattern STI is adjacent to a first surface 100a of the first substrate 100.

[0034] A photoelectric conversion region 110 is provided in each pixel region PXR. The first substrate 100 is doped with a dopant having a first conductivity type, and the photoelectric conversion region 110 is doped with a dopant having a second conductivity type different from the first conductivity type. For example, the first conductivity type is P-type, and the second conductivity type is N-type.

[0035] A floating diffusion region FD is provided in each corresponding active region of the pixel region PXR. The floating diffusion region FD is doped with a dopant having a second conductivity type. A transmission gate TG is provided on one side of the floating diffusion region FD on the corresponding active region. A gate dielectric layer is disposed between the transmission gate TG and the corresponding active region. In one embodiment, the transmission gate TG fills a gate recess formed in the corresponding active region. In this case, the gate dielectric layer extends and is disposed between the transmission gate TG and the inner surface of the gate recess.

[0036] In one embodiment, other gates (not shown) are provided on the corresponding active regions via a gate dielectric film. The other gates include a reset gate, a source follower gate, and a select gate. In one embodiment, the other gates further include gates performing other functions (e.g., a dual conversion gain gate). Source / drain regions are provided in the corresponding active regions on both sides of each of the other gates. The other gates are provided on the corresponding active regions of each of the pixel regions PXR. Alternatively, the other gates may be provided on the corresponding active regions of the pixel regions PXR of pixels that share the other gate.

[0037] As described above, the transmission gate TG and other gates are provided on the first surface 100a of the first substrate 100. However, embodiments of the present invention are not limited thereto. In one embodiment, the transmission gate TG is provided on the first surface 100a of the first substrate 100, and other gates are provided on an additional substrate (not shown). The additional substrate has a third surface facing the first surface 100a and a fourth surface opposite the third surface. The other gates are provided on the third or fourth surface of the additional substrate via an additional gate insulating film. An intermediate structure (not shown) including the additional substrate and other gates is provided between the first structure S1 and the second structure S2, and the intermediate structure is bonded to the first and second structures S1 and S2 by at least one of various bonding methods. For ease of explanation, the following description will be given taking as an example an embodiment in which the transmission gate TG and other gates are provided on the first surface 100a of the first substrate 100.

[0038] The deep isolation pattern DTI, the shallow isolation pattern STI, the photoelectric conversion region 110, the floating diffusion region FD, and the transfer gate TG are included in the photoelectric conversion layer 10.

[0039] The pixels, each including a photoelectric conversion region 110 in the pixel array region AR, convert incident light into an electrical signal (ie, a pixel signal).

[0040] The light-transmitting layer 20 is provided on the second surface 100b of the first substrate 100. The light-transmitting layer 20 transmits light traveling from the outside to the photoelectric conversion region 110, and the second surface 100b of the first substrate 100 is a light-incident surface into which the light is incident. The light-transmitting layer 20 includes a transparent insulating film 310, a grid pattern 320, a protective film 330, a color filter CF, and a nanostructure layer NS.

[0041] The transmissive insulating layer 310 covers the second surface 100b of the first substrate 100. The transmissive insulating layer 310 may have a single-layered structure or a multi-layered structure. In one embodiment, the transmissive insulating layer 310 includes a fixed charge layer and / or an anti-reflection layer.

[0042] The fixed charge film has negative fixed charges. Therefore, holes are accumulated adjacent to the fixed charge film, for example, at the interface between the fixed charge film and the first substrate 100 and / or at a portion of the first substrate 100 adjacent to the second surface 100b. As a result, the fixed charge film can effectively reduce dark current and / or white spots. In one embodiment, the fixed charge film is formed of a metal oxide or metal fluoride containing at least one of hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium (Y), or a lanthanide. For example, the fixed charge film is formed of hafnium oxide or aluminum oxide.

[0043] The anti-reflection coating reduces or minimizes reflection of light incident on the second surface 100b. For example, the anti-reflection coating may include at least one of titanium oxide, silicon nitride, silicon oxide, or hafnium oxide. When the transmissive insulating layer 310 includes a fixed charge layer and an anti-reflection layer, the fixed charge layer contacts the second surface 100b of the first substrate 100, and the anti-reflection layer is disposed on the fixed charge layer. However, embodiments of the present invention are not limited thereto. In one embodiment, the transmissive insulating layer 310 may include either a fixed charge layer or an anti-reflection layer, or may further include an additional insulating layer.

[0044] The grid pattern 320 has a grid shape with openings in a plan view.

[0045] In one embodiment, the openings of the grid pattern 320 vertically overlap the pixel regions PXR. The grid pattern 320 guides incident light so that it enters the photoelectric conversion region 110. In one embodiment, the grid pattern 320 includes a light-shielding pattern and / or a low-refractive index pattern. For example, the light-shielding pattern includes at least one of titanium, titanium nitride, tantalum, tantalum nitride, and tungsten. The low-refractive index pattern has a refractive index lower than that of the color filter CF. For example, the low-refractive index pattern has a refractive index of about 1.1 to about 1.3. For example, the low-refractive index pattern includes an organic material.

[0046] The protective layer 330 conformally covers the surface (e.g., top and side surfaces) of the lattice pattern 320 and the transparent insulating layer 310 exposed by the openings of the lattice pattern 320. In one embodiment, the protective layer 330 is formed of an insulating material having a high dielectric constant. For example, the protective layer 330 includes aluminum oxide or hafnium oxide.

[0047] The color filter CF fills the openings of the grid pattern 320. The color filter CF is disposed on the protective film 330. The color filter CF vertically overlaps the photoelectric conversion region 110. In one embodiment, the color filter CF includes a first color filter having a first color, a second color filter having a second color, and a third color filter having a third color. In one embodiment, the first color is one of red, green, and blue, the second color is another of red, green, and blue, and the third color is the other of red, green, and blue. Alternatively, the first color may be one of magenta, cyan, and yellow, the second color may be another of magenta, cyan, and yellow, and the third color may be the other of magenta, cyan, and yellow. However, embodiments of the present invention are not limited thereto. The first to third colors may be various other colors.

[0048] Each of the color filters CF vertically overlaps a corresponding one of the photoelectric conversion regions 110. However, embodiments of the present invention are not limited thereto. In one embodiment, each of the color filters CF vertically overlaps a plurality of adjacent photoelectric conversion regions 110. In one embodiment, each of the color filters CF overlaps a portion of a corresponding one of the photoelectric conversion regions 110. Also, in one embodiment, depending on the positions of the color filters CF, some of the color filters CF overlap a corresponding one of the photoelectric conversion regions 110, and other some of the color filters CF overlap only a portion of a corresponding one of the photoelectric conversion regions 110.

[0049] The photoelectric conversion regions 110 corresponding to each color filter CF are arranged in a matrix shape, for example, a 2x2 matrix shape, a 3x3 matrix shape, or a 4x4 matrix shape.

[0050] A nanostructured layer NS is provided on the color filter CF.

[0051] A planarization film PL, a spacer SP, and a first etching prevention film 95 are provided between the nanostructure layer NS and the color filter CF.

[0052] The first etch stop layer 95 is provided to prevent components (e.g., spacers SP and planarization layer PL) disposed below the first etch stop layer 95 from being over-etched when the nanostructure layer NS is formed using an etching process. The first etch stop layer 95 includes HfO, SiO, and / or AlO.

[0053] The planarization layer PL covers the upper surface of the color filter CF between the first etching prevention layer 95 and the color filter CF. The planarization layer PL includes at least one of various organic materials, for example, an organic polymer. Examples of organic polymers include, but are not limited to, epoxy resin, polyimide, polycarbonate, polyacrylic, and PMMA (polymethyl methacrylate). The planarization layer PL is optional and may be omitted if the spacer SP, described below, is sufficiently thick.

[0054] The spacer SP secures the gap between the color filter CF and the nanostructure layer NS. That is, the focal length of the meta-microlens MML (described later) can be secured by adjusting the thickness of the spacer SP. The spacer SP is optionally provided in addition to the planarization layer PL, and can be omitted if the planarization layer PL is sufficiently thick.

[0055] The nanostructure layer NS includes a plurality of meta-microlenses MML in the pixel array region AR and a dummy nanopattern DNP in the peripheral region PP. The nanostructure NS will be described later.

[0056] 4, the grating pattern 320 is aligned vertically to the deep isolation pattern DTI, and the meta-microlenses MML and color filters CF are aligned vertically to the corresponding photoelectric conversion regions 110. However, the embodiment of the present invention is not limited thereto.

[0057] In one embodiment, light is radially incident on the entire second surface 100b of the first substrate 100 from an objective lens (not shown) overlapping the center of the pixel array region AR. In other words, the incident light is substantially perpendicular to the photoelectric conversion regions 110 in the center of the pixel array region AR, but obliquely incident on the photoelectric conversion regions 110 in the edge portions of the pixel array region AR. In this case, the grid pattern 320 on the center of the pixel array region AR is aligned perpendicular to the deep isolation pattern DTI, and the meta-microlenses MML and color filters CF on the center of the pixel array region AR are aligned perpendicular to the corresponding photoelectric conversion regions 110. In contrast, the grid pattern 320 on the edge portions of the pixel array region AR is laterally shifted from the deep isolation pattern DTI, and the meta-microlenses MML and color filters CF on the edge portions of the pixel array region AR are laterally shifted from the corresponding photoelectric conversion regions 110. The grid pattern 320, the meta-microlenses MML, and the color filters CF on the edge portions of the pixel array region AR are laterally shifted in a direction from the edge toward the center of the pixel array region AR. In one embodiment, the degree of shift of the grid pattern 320, the meta-microlenses MML, and the color filters CF on the edge portions of the pixel array region AR gradually decreases in a direction from the edge toward the center of the pixel array region AR.

[0058] The first wiring layer 30 is provided on the first surface 100a of the first substrate 100. The first wiring layer 30 covers the first surface 100a of the first substrate 100 and includes a first interlayer insulating film ILD1 and a first wiring line ICL1. The first wiring line ICL1 is provided between the first interlayer insulating films ILD1. The first wiring line ICL1 is electrically connected to and / or electrically connects pixel transistors (e.g., transfer transistor, reset transistor, source follow transistor, and select transistor) through first contact plugs.

[0059] The second structure S2 includes a second substrate 200, a peripheral transistor PTR formed on the upper surface of the second substrate 200, and a second wiring layer 40 provided on the upper surface of the second substrate 200 and covering the peripheral transistor PTR. The second substrate 200 is a semiconductor substrate such as a silicon substrate, a germanium substrate, or a silicon germanium substrate. The second wiring layer 40 includes a second interlayer insulating film ILD2 and a second wiring line ICL2 between the second interlayer insulating film ILD2. The second wiring line ICL2 is electrically connected to the peripheral transistor PTR through a second contact plug and / or electrically connects the peripheral transistor PTR. The second wiring line ICL2 and the peripheral transistor PTR constitute peripheral circuits of the image sensor (e.g., the row decoder, row driver, column decoder, timing generator, correlated double sampler, analog-to-digital converter, and / or input / output buffer of FIG. 1).

[0060] The first structure S1 is stacked on the second structure S2, and the first and second structures (S1, S2) are bonded to each other. The second wiring layer 40 is disposed between the first wiring layer 30 and the second substrate 200. In one embodiment, a portion of the bottom of the first interlayer insulating film ILD1 is bonded to a portion of the top of the second interlayer insulating film ILD2.

[0061] In one embodiment, the first structure S1 is electrically connected to the second structure S2 through one or more connection structures (50, 60). In one embodiment, the connection structures (50, 60) include a first connection structure 50 and a second connection structure 60.

[0062] The first connecting structure 50 includes a first through electrode 51, a first filling insulation pattern 52, and a first capping pattern 53. The first through electrode 51 is provided in a first through hole TH1 that penetrates the first substrate 100, the first wiring layer 30, and a portion of the second wiring layer 40 in the peripheral region PP. In one embodiment, the first through hole TH1 also penetrates the transparent insulating film 310. The first through electrode 51 conformally covers the inner surface of the first through hole TH1. The first through hole TH1 exposes a corresponding portion of the first wiring line ICL1 and a corresponding portion of the second wiring line ICL2. Therefore, the first through electrode 51 is electrically connected to the corresponding portion of the first wiring line ICL1 and the corresponding portion of the second wiring line ICL2. The first filling insulation pattern 52 is provided on the first through electrode 51 and fills the first through hole TH1. The first capping pattern 53 covers an upper surface of the first filling insulation pattern 52.

[0063] According to one embodiment, a first recess RS1 is recessed into the first substrate 100 from the second surface 100b of the first substrate 100 in the peripheral region PP. The first recess RS1 exposes the buried conductive pattern of the deep device isolation pattern DTI. In one embodiment, the first recess RS1 penetrates the transparent insulating film 310. The first recess RS1 is disposed on one side of the first through hole TH1. The first through electrode 51 extends onto the second surface 100b of the first substrate 100 and the inner surface of the first recess RS1. Thus, the first through electrode 51 is electrically connected to the buried conductive pattern of the deep device isolation pattern DTI. During operation of the image sensor, a negative bias voltage is applied to the buried conductive pattern of the deep device isolation pattern DTI through the first through electrode 51. In one embodiment, the first through electrode 51 extends further toward the pixel array region AR to cover most of the peripheral region PP. The portion of the first through electrode 51 covering the peripheral region PP functions as a light-shielding pattern. In one embodiment, unlike FIG. 4, the portion of the first through electrode 51 that functions as a light-shielding pattern may be separated from the portion of the first through electrode 51 that covers the inner surfaces of the first recess RS1 and the first through hole TH1.

[0064] A conductive plug 70 fills the remaining area of ​​the first recess RS1. The conductive plug 70 contacts the first through-hole electrode 51 provided in the first recess RS1. In one embodiment, the conductive plug 70 is formed of a conductive material having a resistance lower than that of the first through-hole electrode 51.

[0065] 4, the protective film 330 covers the first through electrode 51 and the conductive plug 70. In the first through hole TH1, the protective film 330 is provided between the first through electrode 51 and the first buried insulating pattern 52. Alternatively, the protective film 330 may be disposed between the first through electrode 51 and the transparent insulating film 310. In this case, the protective film 330 is not present in the first through hole TH1 and the first recess RS1. For example, in this case, the first through hole TH1 and the first recess RS1 penetrate the protective film 330 and the transparent insulating film 310.

[0066] The filtering pattern 80 covers the first through-electrodes 51 and the first capping pattern 53. The filtering pattern 80 blocks light of a specific wavelength band. For example, the filtering pattern 80 blocks ultraviolet light. For example, the filtering pattern 80 may include, but is not limited to, a blue color filter.

[0067] The second connecting structure 60 includes a second through electrode 61, a second buried insulating pattern 62, and a second capping pattern 63. The second through electrode 61 is provided in a second through hole TH2 that penetrates at least a portion of the first substrate 100, the first wiring layer 30, and the second wiring layer 40 in the pad region PR. In one embodiment, the second through hole TH2 also penetrates the transparent insulating film 310. The second through electrode 61 conformally covers the inner surface of the second through hole TH2. The second through hole TH2 exposes a corresponding portion of the second wiring line ICL2, and thus the second through electrode 61 is electrically connected to the corresponding portion of the second wiring line ICL2. The second buried insulating pattern 62 is provided on the second through electrode 61 and fills the second through hole TH2. The second capping pattern 63 covers the upper surface of the second buried insulating pattern 62. Similarly to the first connecting structure 50, a protective film 330 is disposed between the second through electrode 61 and the second buried insulating pattern 62. Alternatively, the protective film 330 may be disposed below the second through-electrode 61, so that the second through-hole TH2 may also penetrate the protective film 330.

[0068] According to an embodiment, a second recess RS2 is recessed into the first substrate 100 from the second surface 100b of the first substrate 100 in the pad region PR. The second recess RS2 is disposed on one side of the second through hole TH2. In an embodiment, the second recess RS2 further penetrates the transmissive insulating film 310. In an embodiment, the second through electrode 61 extends onto the second surface 100b of the first substrate 100 and the inner surface of the second recess RS2.

[0069] The connection pads CP fill the remaining area of ​​the second recesses RS2. The connection pads CP contact the second through-hole electrodes 61. Therefore, the connection pads CP are electrically connected to the second structure S2 through the second through-hole electrodes 61. The connection pads CP are used for electrical connection with an external device. In one embodiment, the connection pads CP receive various signals (e.g., command signals and / or control signals) transmitted from an external device, and various electrical signals generated in the image sensor are transmitted to the external device through the connection pads CP. For example, connectors such as bonding wires are connected to the connection pads CP, and the connection pads CP are electrically connected to the external device through the connectors. In one embodiment, the connection pads CP are formed of a conductive material having a resistance value lower than that of the second through-hole electrodes 61.

[0070] Each of the first and second through electrodes (51, 61) is formed of a conductive material. For example, the first and second through electrodes (51, 61) are formed of a metal (e.g., tungsten (W), titanium (Ti), tantalum (Ta), etc.) and / or a conductive metal nitride (e.g., titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), etc.). In one embodiment, the first and second through electrodes (51, 61) are formed of the same material. Each of the first and second buried insulating patterns (52, 62) is formed of an insulating material. In one embodiment, the first and second buried insulating patterns (52, 62) are formed of the same insulating material. Each of the first and second capping patterns (53, 63) is formed of an insulating material. In one embodiment, the first and second capping patterns (53, 63) are formed of the same insulating material. As described above, the resistance value of the conductive plug 70 is lower than the resistance value of the first through-hole electrode 51, and the resistance value of the connection pad CP is lower than the resistance value of the second through-hole electrode 61. In one embodiment, the conductive plug 70 and the connection pad CP are formed of the same conductive material. For example, the conductive plug 70 and the connection pad CP include aluminum (Al).

[0071] A passivation film 90 is provided on the nanostructure layer NS provided on the second surface 100b of the first substrate 100. The passivation film 90 covers the pixel array region AR, the peripheral region PP, and the pad region PR. An opening OPN penetrates the passivation film 90, the nanostructure layer NS, the first etching prevention film 95, the spacer SP, and the planarization film PL on the pad region PR to expose the connection pad CP.

[0072] In the above-described embodiment, the connection pads CP are disposed in the second recesses RS2 formed in the first substrate 100. However, the present invention is not limited to this embodiment. In an embodiment, the connection pads CP may be disposed in other portions.

[0073] In one embodiment of the present invention, the nanostructure layer NS provided on the color filter CF has different shapes on the pixel array region AR and the peripheral region PP. Hereinafter, the nanostructure layer NS on the pixel array region AR will be described first, and the nanostructure layer NS on the peripheral region PP will be described later.

[0074] Figure 5 shows an enlarged view of the area corresponding to R1 in Figure 3B, including a plan view of the meta-microlens provided in the pixel area and a cross-sectional view of the plan view cut along line B-B'.

[0075] 3A, 3B, 4, and 5, one photoelectric conversion region 110, one color filter CF, and one meta-microlens MML are provided for each pixel region PXR. However, at least one of the photoelectric conversion region 110, color filter CF, and meta-microlens MML corresponding to one pixel region PXR may be provided in plural. For example, two photoelectric conversion regions 110 may correspond to one color filter CF and one meta-microlens MML, or four photoelectric conversion regions 110 and four color filters CF may correspond to one meta-microlens MML. For simplicity of explanation, the following description will mainly focus on a case where one photoelectric conversion region 110, one color filter CF, and one meta-microlens MML correspond to one pixel region PXR.

[0076] The color filters CF and meta-microlenses MML provided for each pixel region PXR are arranged in a matrix. In one embodiment, a number of pixel regions PXR constitute one unit pixel region, and the unit pixel regions are also arranged in a matrix. One unit pixel region may include various numbers of pixel regions PXR, for example, two pixel regions PXR, four pixel regions PXR, nine pixel regions PXR, or sixteen pixel regions PXR. FIG. 5 illustrates, as an example, four pixel regions PXR arranged in a 2×2 configuration constituting one unit pixel region.

[0077] 5, when one unit pixel region includes pixel regions in a 2x2 matrix, i.e., first to fourth pixel regions (PXR1, PXR2, PXR3, PXR4), the unit pixel region has a Bayer pattern. In this case, one red pixel region and one blue pixel region are arranged in one diagonal direction within the unit pixel region, and two green pixel regions are arranged in the other diagonal direction. That is, the first pixel P region PXR1 is the red pixel region, the second pixel P region PXR2 and the third pixel region PXR3 are green pixel regions, and the fourth pixel region PXR4 is the blue pixel region.

[0078] The meta-microlenses MML are disposed on the color filter CF as planar microlenses. Each meta-microlens MML includes nanostructures with subwavelength periods for locally adjusting the refractive index of incident light. The nanostructures can control the polarization, phase, and size of light by locally adjusting the refractive index of incident light. In one embodiment of the present invention, the phase delay of transmitted light is adjusted by adjusting the ratio of materials with locally different refractive indices in the portion through which light passes.

[0079] More specifically, the meta-microlens MML includes a first nano-refractive pattern RF1 and a second nano-refractive pattern RF2 made of two or more materials having different refractive indices. The second nano-refractive pattern RF2 is filled between the first nano-refractive patterns RF1. In one embodiment, the first nano-refractive pattern RF1 includes a material having a relatively high refractive index, and the second nano-refractive pattern RF2 includes a material having a relatively low refractive index. For example, the first nano-refractive pattern RF1 includes a dielectric material having a relatively high refractive index and low absorption in the visible light range, such as TiO2, GaN, ZnS, ZnSe, SiNx (e.g., Si3N4), etc. The second nano-refractive pattern RF2 includes a dielectric material having a relatively low refractive index and low absorption in the visible light range, such as SiO2, SiCOH, siloxane-based spin-on glass (SOG), air, etc. The meta-microlens MML includes a plurality of first nanoposts NP1 as the first nano-refractive pattern RF1.

[0080] The meta-microlens MML is disposed so that at least a portion thereof overlaps vertically (for example, in the third direction) with the photoelectric conversion region 110. The meta-microlens MML is provided at a position corresponding to the photoelectric conversion region 110.

[0081] Just as each meta-microlens MML acts as a convex lens that converges light, the effective refractive index of the meta-microlens MML is highest in any one region of the meta-microlens MML and gradually decreases toward the periphery of that region. In other words, the ratio of the first nano-refractive pattern RF1 to the second nano-refractive pattern RF2 is highest in any one region of the meta-microlens MML and gradually decreases toward the periphery of that region.

[0082] The diameter and arrangement of the first nanoposts NP1 vary depending on the position of the first nanoposts NP1 in the region AR of the pixel array. If the four pixel regions PXR constituting the unit pixel region are designated as first to fourth pixel regions (PXR1, PXR2, PXR3, and PXR4), the diameters and arrangements of the first nanoposts NP1 in the first to fourth pixel regions (PXR1, PXR2, PXR3, and PXR4) are set differently.

[0083] When light passes through a certain material, phase modulation occurs due to the refractive index of the material. As described above, the meta-microlens MML according to one embodiment of the present invention is manufactured using two materials with different effective refractive indices, and the phase of light passing through the meta-microlens MML changes as the diameter of the first nanopost NP1 with a high refractive index changes.

[0084] In one embodiment of the present invention, the color filter CF, the grid pattern 320, and / or the meta-microlens MML are provided overlapping at positions corresponding to each pixel, but this is not limiting. At least one of the color filter CF, the grid pattern 320, and the meta-microlens MML may be shifted by a predetermined amount at positions corresponding to each pixel.

[0085] The shift degree of at least one of the color filter CF, the grating pattern 320, and the meta-microlens MML is intentionally selected to optimize the light path in consideration of the angle of light traveling from the outside to the pixel.

[0086] A passivation film 90 is provided on the meta-microlens MML. The passivation film 90 may be formed of a single film or multiple films. The passivation film 90 functions not only as a protective film for protecting the meta-microlens MML but also as an anti-reflection pattern that prevents external light from being reflected by the upper surface of the meta-microlens MML while transmitting light. The passivation film 90 may be made of various materials, such as hafnium oxide, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide oxide, silicon carbide oxynitride, zirconium oxide, titanium oxide, or aluminum oxide (Al2O3, alumina). In this case, the passivation film 90 prevents light reflection so that light traveling through the meta-microlens MML toward the second surface 100b can smoothly reach the photoelectric conversion region 110.

[0087] Figure 6 is an enlarged view of the peripheral area corresponding to R2 in Figure 3B, showing a plan view of the peripheral area where dummy nanopatterns are provided, and a cross-sectional view of the plan view cut along line CC'.

[0088] 6, the dummy nanopattern DNP is disposed on the peripheral region PP. The dummy nanopattern DNP is intended to relieve stress generated between the pixel array region AR, the peripheral region PP, and / or the pad region PR. The dummy nanopattern DNP is formed of nanostructures made of different materials, such as the meta-microlens MML.

[0089] To fabricate an image sensor, different materials with different thermal expansion coefficients are used in the pixel array region AR, peripheral region PP, and pad region PR. Components formed in the pixel array region AR, peripheral region PP, and pad region PR include organic and inorganic materials with large differences in thermal expansion coefficients. Materials with different thermal expansion coefficients expand to different degrees during the manufacturing process, causing stress to be applied to adjacent components. The stress may cause cracks to form in at least one of the pixel array region AR, peripheral region PP, and / or pad region PR, particularly in the peripheral region PP and pad region PR. The cracks propagate to adjacent regions along the stress-vulnerable portions. In one embodiment of the present invention, dummy nanopatterns DNP made of different materials are formed on the peripheral region PP, thereby mitigating or buffering stress applied to the peripheral region PP and regions adjacent to the peripheral region PP.

[0090] The dummy nanopattern DNP includes a first nanorefraction pattern RF1 and a second nanorefraction pattern RF2. The dummy nanopattern DNP includes a plurality of second nanoposts NP2 as the first nanorefraction pattern RF1. A plurality of first nanorefraction patterns RF1 are arranged on a plane in the form of nanoposts NP, and the second nanorefraction pattern RF2 is provided in a form filling the remaining area excluding the nanoposts NP.

[0091] The first nano-refractive pattern RF1 and the second nano-refractive pattern RF2 include different materials, for example, materials having different thermal expansion coefficients.

[0092] In one embodiment, the first nano-refractive pattern RF1 and the second nano-refractive pattern RF2 of the dummy nano-pattern DNP include the same material as the first nano-refractive pattern RF1 and the second nano-refractive pattern RF2 of the meta-microlens MML, respectively. Furthermore, the first nano-refractive pattern RF1 and the second nano-refractive pattern RF2 of the dummy nano-pattern DNP are manufactured in the same step as the manufacturing process of the first nano-refractive pattern RF1 and the second nano-refractive pattern RF2 of the meta-microlens MML, respectively. In this case, the dummy nano-pattern DNP can be manufactured in the same step as the manufacturing process of the meta-microlens MML without an additional process for forming the dummy nano-pattern DNP.

[0093] In one embodiment, each second nanopost NP2 has a bar shape that extends long in one direction in plan view and penetrates the nanostructure layer NS in cross section. In one embodiment, each second nanopost NP2 has a rectangular pillar shape.

[0094] In a planar view, the extension direction of the second nanoposts NP2 intersects (e.g., is substantially perpendicular to) the direction of crack generation due to the difference in thermal expansion coefficients. Two components containing materials with different thermal expansion coefficients cause thermal stress in the peripheral region PP during the manufacturing process or during a post-manufacturing evaluation stage. For example, the planarization film PL and the nanostructure layer NS are formed of organic and inorganic materials, respectively, with different thermal expansion coefficients. When heat is applied during the manufacturing process and / or during a post-manufacturing evaluation stage, they expand to different degrees. For example, heat is applied to an image sensor during the manufacturing process and / or during post-manufacturing evaluation. The difference in thermal expansion between the planarization film PL and the nanostructure layer NS causes significant thermal stress in the regions where the planarization film PL and the nanostructure layer NS are formed and in other adjacent regions. Thermal stress can cause cracks in structurally vulnerable portions of the first substrate 100. In this case, the cracks propagate primarily along the stress-vulnerable portions from the pad region PR toward the peripheral region PP and from the peripheral region PP toward the pixel array region AR.

[0095] In a plan view, the second nanoposts NP2 extend substantially perpendicular to the direction in which stress is applied so that the stress is relaxed or buffered. For example, the second nanoposts NP2 are provided along a direction parallel to the boundary between the pixel array region AR and the peripheral region PP. Alternatively, the second nanoposts NP2 are provided along a direction parallel to the boundary between the peripheral region PP and the pad region PR.

[0096] In one embodiment, each of the second nanoposts NP2 has a variety of sizes and shapes. For example, in a plan view, the second nanoposts NP2 have a bar shape that extends vertically. In this case, the ratio of the width W of the second nanoposts NP2 to the length L of the second nanoposts NP2 is 1:2 to 1:7.

[0097] The ratio of the horizontal distance Dx between two adjacent second nanoposts NP2 to the vertical distance Dy between them is 1:0.8 to 1:1.2. The ratio of the vertical distance Dy between two adjacent second nanoposts NP2 to the width W of the second nanopost NP2 is 1:1 to 1:2. Furthermore, the horizontal distance Ds from one second nanopost NP2 to the farthest second nanopost NP2 at a specific point is 0.6 to 1.1 times the length L of the second nanopost NP2. However, the size of the second nanoposts NP2 is not limited to this and may have various other values.

[0098] In this embodiment, when a plurality of second nanoposts NP2 are arranged in the horizontal direction, the second nanoposts NP2 are arranged in a zigzag pattern so that the horizontal positions of one end of the second nanoposts NP2 do not coincide with each other.

[0099] In one embodiment, the second nanoposts NP2 are provided at a density similar to or substantially the same as that of the first nanoposts NP1. In particular, the density of the second nanoposts NP2 per unit area in a plan view is about 70% to about 130%, about 80% to about 120%, about 90% to about 110%, or 100% of the density of the first nanoposts NP1 per unit area. When the densities of the first nanoposts NP1 and the second nanoposts NP2 are similar or substantially the same, process variations in the pixel array region AR, peripheral region PP, and pad region PR during the process of forming the nanostructure layer NS can be reduced. For example, when chemically and mechanically polishing the top surface of the nanostructure layer NS, if the densities of the pixel array region AR and the peripheral region PP are different, the polishing degree of the pixel array region AR and the peripheral region PP may differ. According to one embodiment of the present invention, the density of the first nanoposts NP1 on the pixel array region AR is similar to or substantially the same as the density of the second nanoposts NP2 on the peripheral region PP, thereby making it possible to substantially match the polishing degree of the pixel array region AR and the peripheral region PP.

[0100] Thus, in one embodiment of the present invention, a dummy nanopattern DNP, i.e., a second nanopost NP2, is provided on the peripheral region PP, thereby alleviating the stress applied to the peripheral region PP and the region adjacent to the peripheral region PP (the pixel array region AR and / or the pad region PR).

[0101] In one embodiment of the present invention, the second nanoposts NP2 can have various shapes.

[0102] FIG. 7 is a perspective view illustrating an example of the shape of the second nanopost according to an embodiment of the present invention.

[0103] 7, the second nanoposts NP2 according to an embodiment of the present invention may have various pillar shapes. For example, the upper and lower surfaces of the second nanoposts NP2 may be polygonal, such as square or cross-shaped. Alternatively, the upper and lower surfaces of the second nanoposts NP2 may be circular. Alternatively, the upper and lower surfaces of the second nanoposts NP2 may be closed shapes formed by straight and curved lines. Alternatively, although not shown, the second nanoposts NP2 may be polygonal in plan view, with the corners of the upper and lower surfaces treated with curved surfaces. Alternatively, the shape of the second nanoposts NP2 may be changed depending on the manufacturing process margins during manufacturing, so the upper and lower surfaces of the second nanoposts NP2 may have different sizes.

[0104] In one embodiment of the present invention, the second nanoposts NP2 in the peripheral region PP have the same shape overall, but this is not limited thereto and they may have different shapes depending on their positions. For example, the second nanoposts NP2 may have a rectangular prism shape with a relatively large top surface area in one region of the peripheral region PP and a rectangular prism shape with a relatively small top surface area in another region of the peripheral region PP. Alternatively, the second nanoposts NP2 may have a rectangular prism shape in one region of the peripheral region PP and a cross prism shape in another region of the peripheral region PP.

[0105] As described above, the second nanoposts NP2 may have various shapes, and therefore, for ease of explanation, the following description will be directed to a square pillar-shaped second nanopost NP2. For ease of explanation, the following embodiment will mainly focus on differences from the above embodiment.

[0106] FIG. 8 is a plan view of the second example showing an enlarged view of the P1 portion of FIG. 3A, and FIG. 9 is a view showing an enlarged view of the peripheral region corresponding to R3 of FIG.

[0107] Referring to FIGS. 8 and 9, each of the second nanoposts NP2 has a square pillar shape.

[0108] In one second nanopost NP2 according to this embodiment, the ratio of the width W of the second nanopost NP2 to the length L of the second nanopost NP2 is 1:0.9 to 1:1.1, or 1:1. In plan view, the second nanoposts NP2 are arranged in a zigzag pattern along the horizontal and / or vertical directions.

[0109] The ratio of the horizontal distance Dx between two adjacent second nanoposts NP2 to the vertical distance Dy between them is 1:0.9 to 1:1.1, or 1:1. The ratio of the vertical distance Dy between two adjacent second nanoposts NP2 to the length L of the second nanoposts is 1:0.9 to 1:1.1, or 1:1. Furthermore, the horizontal distance Ds from one second nanopost NP2 to the farthest second nanopost NP2 at a specific point is 1.8 to 2.2 times the length L of the second nanopost. However, the shape and size of each second nanopost NP2 are not limited thereto and may be changed to various other shapes and sizes.

[0110] In one embodiment, the second nanoposts NP2 are arranged at similar densities in the horizontal and vertical directions on a unit area, so that stress can be relieved in both the horizontal and vertical directions.

[0111] In one embodiment of the present invention, the shape and density of the second nanoposts NP2 on the peripheral region PP are uniform regardless of position, but are not limited thereto and may be varied depending on the position in consideration of the degree of thermal stress and the type of cracks. For example, the number of second nanoposts NP2 per unit area increases closer to the pixel array region AR and / or the pad region PR.

[0112] In one embodiment of the present invention, second nanoposts NP2 for relieving thermal stress due to thermal expansion are also provided on the pad region PR.

[0113] Figures 10 and 11 are plan views of a third and fourth example showing an image sensor according to one embodiment of the present invention in which a second nanopost provision position has been added, and are views showing the area corresponding to portion P1 of Figure 3A.

[0114] 10 and 11, second nanoposts NP2 are also provided in the pad region PR. The second nanoposts NP2 are disposed between two adjacent connection pads CP. In one embodiment, the second nanoposts NP2 do not need to be disposed between every connection pad CP, and may be disposed in positions where cracks frequently occur.

[0115] In one embodiment, the second nanoposts NP2 arranged on the pad region PR are provided with substantially the same shape and density as the second nanoposts NP2 arranged on the peripheral region PP.

[0116] 10, the extension direction of the second nanoposts NP2 arranged on the pad region PR is substantially perpendicular to the extension direction of the second nanoposts NP2 arranged on the peripheral region PP. Alternatively, although not shown, the extension direction of the second nanoposts NP2 arranged on the pad region PR may be parallel to the extension direction of the second nanoposts NP2 arranged on the peripheral region PP or may intersect at an angle other than perpendicular.

[0117] In one embodiment of the present invention, the second nanoposts NP2 are arranged in a different arrangement from the above-described arrangement depending on their positions on the peripheral region PP. For example, the second nanoposts NP2 are arranged in various arrangements at the vertices and corners (sides) of the peripheral region PP.

[0118] 12A to 12C are enlarged plan views of the fifth to seventh examples of the P2 portion of FIG. 3A.

[0119] 12A to 12C, the second nanoposts NP2 in the peripheral region PP corresponding to the vertices and corners of the image sensor in a plan view have different arrangements depending on the position. For example, as shown in FIG. 12A, at the vertex where the horizontal side HL and the vertical side VL of the image sensor meet, the second nanoposts NP2 are arranged in different directions in the peripheral region PP arranged on the horizontal side HL side and the peripheral region PP arranged on the vertical side VL side.

[0120] In one embodiment, the peripheral region PP in which second nanoposts NP2 are arranged, extending in a certain direction corresponding to the horizontal side HL, is defined as the first peripheral region A1, and the peripheral region PP in which second nanoposts NP2 are arranged, extending in a direction different from that of the first peripheral region A1, corresponding to the vertical side VL, is defined as the second peripheral region A2.The second nanoposts NP2 on the first peripheral region A1 extend horizontally along the extension direction of the horizontal side HL, and the second nanoposts NP2 on the second peripheral region A2 extend vertically along the extension direction of the vertical side VL.

[0121] In an embodiment, the boundary between the first peripheral region A1 and the second peripheral region A2 may have various shapes, and the arrangement of the second nanoposts NP2 may vary depending on the shape.

[0122] 12A, the boundary between the first peripheral region A1 and the second peripheral region A2 is defined by a straight line connecting the vertex of the pixel array region AR and the vertex of the peripheral region PP. Second nanoposts NP2 are alternately arranged based on the boundary between the first peripheral region A1 and the second peripheral region A2.

[0123] 12B, the boundary between the first peripheral region A1 and the second peripheral region A2 is defined by a straight line extending parallel to the horizontal side HL from the vertex of the pixel array region AR to the vertical side VL of the peripheral region PP. Alternatively, although not shown, the boundary between the first peripheral region A1 and the second peripheral region A2 is defined by a straight line extending parallel to the vertical side VL from the vertex of the pixel array region AR to the horizontal side HL of the peripheral region PP. In the first peripheral region A1, the second nanoposts NP2 extend horizontally along the extension direction of the horizontal side HL, and in the second peripheral region A2, the second nanoposts NP2 extend vertically along the extension direction of the vertical side VL.

[0124] 12C, the boundary between the first peripheral region A1 and the second peripheral region A2 is defined by a line extending parallel to the horizontal side HL from the vertex of the pixel array region AR to a specific point in the peripheral region PP and a line connecting the specific point to the vertex of the peripheral region PP. Therefore, the second nanoposts NP2 extend horizontally from the first peripheral region A1 to the specific point along the extension direction of the horizontal side HL, and the second nanoposts NP2 on the first peripheral region A1 and the second nanoposts NP2 on the second peripheral region A2 are alternately arranged adjacent to the line connecting the specific point to the vertex of the peripheral region PP.

[0125] In one embodiment of the present invention, the boundary between the first peripheral area A1 and the second peripheral area A2 is not limited to this, and may be set differently from the above-described form.

[0126] In one embodiment of the present invention, the nanostructure layer NS may be provided in multiple layers.

[0127] FIG. 13 is a cross-sectional view of an eighth example of an image sensor according to an embodiment of the present invention.

[0128] Referring to FIG. 13, the nanostructure layer NS includes a first nanostructure layer NS1 and a second nanostructure layer NS2 stacked on the first nanostructure layer NS1.

[0129] The first nanostructure layer NS1 includes a first meta-microlens MML1 on the pixel array region AR and a first dummy nanopattern DNP1 on the peripheral region PP, where the first meta-microlens MML1 and the first dummy nanopattern DNP1 include first and second nanoposts (NP1, NP2), respectively.

[0130] The second nanostructure layer NS2 includes a second meta-microlens MML2 on the pixel array region AR and a second dummy nanopattern DNP2 on the peripheral region PP, where the second meta-microlens MML2 and the second dummy nanopattern DNP2 include first and second nanoposts (NP1, NP2), respectively.

[0131] The first nanoposts NP1 of the first nanostructure layer NS1 are aligned with the first nanoposts NP1 of the second nanostructure layer NS2 along the stacking direction of the first nanostructure layer NS1 and the second nanostructure layer NS2 and overlap each other. The first nanoposts NP1 of the first nanostructure layer NS1 have substantially the same shape as the first nanoposts NP1 of the second nanostructure layer NS2. For example, if the first nanoposts NP1 of the first nanostructure layer NS1 have a cylindrical shape, the first nanoposts NP1 of the second nanostructure layer NS2 will also have a cylindrical shape but will have the same area as the first nanoposts NP1 of the first nanostructure layer NS1.

[0132] Furthermore, the second nanoposts NP2 of the first nanostructure layer NS1 overlap the second nanoposts NP2 of the second nanostructure layer NS2 in an aligned manner along the stacking direction of the first nanostructure layer NS1 and the second nanostructure layer NS2. The second nanoposts NP2 of the first nanostructure layer NS1 have substantially the same shape as the second nanoposts NP2 of the second nanostructure layer NS2. For example, if the second nanoposts NP2 of the first nanostructure layer NS1 have a rectangular pillar shape, the second nanoposts NP2 of the second nanostructure layer NS2 will also have a rectangular pillar shape but have the same area as the second nanoposts NP2 of the first nanostructure layer NS1.

[0133] An etching prevention layer is provided between the first nanostructure layer NS1 and the second nanostructure layer NS2. The etching prevention layer provided under the first nanostructure layer NS1 is referred to as a first etching prevention layer 95, and the etching prevention layer provided between the first nanostructure layer NS1 and the second nanostructure layer NS2 is referred to as a second etching prevention layer 97.

[0134] When the nanostructure layer NS is formed in multiple layers, the height of the first nanopost NP1 and the second nanopost NP2 can be sufficiently ensured. When forming the meta-microlens MML, it is difficult to simultaneously satisfy the height and width of the nanoposts due to process limitations, but when the nanostructure layer NS is formed in multiple layers, the height and width of the nanoposts can be adjusted to an appropriate level.

[0135] In one embodiment of the present invention, the nanoposts of the first nanostructure layer NS1 and the second nanostructure layer NS2 are aligned in substantially the same shape, but this is not limited to this. Similar to controlling the path of light by overlapping physical optical lenses of different shapes, the first nanostructure layer NS1 and the second nanostructure layer NS2 can be designed to have different first nanoposts NP1, and by stacking the first nanostructure layer NS1 and the second nanostructure layer NS2 having different first nanoposts NP1, the path of light can be efficiently controlled.

[0136] Although not shown, the nanostructure layer NS can of course be formed not only of two layers but also of more layers, for example, first to third nanostructure layers.

[0137] In one embodiment of the present invention, an additional functional film, for example, an anti-reflection pattern ARL, may be further formed on the nanostructure layer NS.

[0138] FIG. 14 is a cross-sectional view of a ninth example of an image sensor according to an embodiment of the present invention, in which an anti-reflection pattern ARL is further formed on the image sensor shown in FIG.

[0139] Referring to FIG. 14, a third anti-etching layer 99 is provided on the second nanostructure layer NS2, and an anti-reflection pattern ARL is provided on the third anti-etching layer 99.

[0140] The antireflection pattern ARL includes a protrusion pattern on the third anti-etching film 99. The protrusion pattern of the antireflection pattern ARL may or may not overlap the nanoposts NP of the second nanostructure layer NS2, i.e., the first and second nanoposts (NP1, NP2). For example, the protrusion pattern of the antireflection pattern ARL is aligned with and overlaps the nanoposts NP of the second nanostructure layer NS2, i.e., the first and second nanoposts (NP1, NP2). In other words, the protrusion pattern has substantially the same shape as the nanoposts of the second nanostructure layer NS2, i.e., the first and second nanoposts (NP1, NP2). When the protrusion pattern of the antireflection pattern ARL and the nanoposts of the second nanostructure layer NS2 have the same shape, the protrusion pattern of the antireflection pattern ARL can be formed using the etching mask used to form the nanoposts of the second nanostructure layer NS2. In this case, a separate etching mask is not required for forming the antireflection pattern ARL, thereby reducing process costs.

[0141] In one embodiment of the present invention, a portion of the nanostructure layer NS is used as a color separation lens array.

[0142] FIG. 15 is a cross-sectional view showing a tenth example of an image sensor according to an embodiment of the present invention, in which a part of the nanostructure layer NS is used as a color separation lens array.

[0143] Referring to FIG. 15, the nanostructure layer NS includes a first nanostructure layer NS1 and a second nanostructure layer NS2 stacked on the first nanostructure layer NS1.

[0144] In this embodiment, in the pixel array region AR, the first nanostructure layer NS1 includes a color separation lens array, and the second nanostructure layer NS2 includes a meta-microlens MML. In the peripheral region PP, the first and second nanostructure layers (NS1, NS2) include dummy nanopatterns DNP.

[0145] The color separating lens array (CSLA) is a component configured to focus light of a corresponding color onto each pixel region PXR. The color separating lens array includes a plurality of first nanoposts NP1 that change the phase of incident light differently depending on the incident position. In this case, at least a portion of the first nanoposts NP1 of the first nanostructure layer NS1 does not overlap at least a portion of the first nanoposts NP1 of the second nanostructure layer NS2 along the stacking direction of the first nanostructure layer NS1 and the second nanostructure layer NS2.

[0146] A color separation lens array forms a different phase profile for each different wavelength of light contained in incident light, focusing each different wavelength of light on a pixel area. For example, a color separation lens array focuses light of one wavelength on one pixel area and light of a second wavelength on another pixel area. Because the refractive index of a material varies depending on the wavelength of light it reacts to, a color separation lens array provides a different phase profile for each different wavelength of light. Again, even the same material has a different refractive index depending on the wavelength of light it reacts to, and the phase delay experienced by light when passing through the material also varies depending on the wavelength, resulting in a different phase profile for each wavelength.

[0147] The first nanostructure layer NS1 includes first nanoposts NP1 arranged in a specific order so that the color separation lens array can have phases for different wavelengths of light (e.g., blue, green, and red wavelengths). The specific order refers to parameters such as the shape, size (width, height), spacing, and arrangement of the nanoposts NP, and these parameters are determined according to the phase profile to be realized through the color separation lens array. To realize different phase distributions for each pixel region PXR, the size, shape, spacing, and / or arrangement of the first nanoposts NP1 in each pixel region PXR is different from the size, shape, spacing, and / or arrangement of the nanoposts NPs provided in other regions.

[0148] In this embodiment, the color filter CF is optionally omitted. In one embodiment, the first nanostructure layer NS1 is used as a color separation lens array, thereby eliminating the need for a separate component for displaying color at each pixel. However, in one embodiment, the first nanostructure layer NS1 can display color, but the color filter CF does not need to be omitted to complement additional colors. In this case, the color separation lens array performs color separation, and the additional color filter array serves to complement some of the errors that occur when the color separation is performed by the color separation lens array, thereby enhancing color purity.

[0149] In one embodiment of the present invention, an image sensor is provided with a different structure than the above-described embodiments.

[0150] FIG. 16 is a cross-sectional view illustrating an eleventh example of an image sensor according to an embodiment of the present invention, in which the first structure and the second structure are formed differently from those in the above-described embodiments.

[0151] 16 is a cross-sectional view of an image sensor according to an embodiment of the present invention, taken along line AA' of FIG. 3B.

[0152] 16, in this embodiment, the connection pad CP is disposed in the second wiring layer 40 of the second structure S2. More specifically, the connection pad CP is disposed in the second wiring layer 40 below the pad region PR of the first substrate 100. The connection pad overlaps the pad region PR in a plan view. In one embodiment, the side and top surfaces of the connection pad CP are covered by a portion of the top of the second interlayer insulating film ILD2. A pad through-hole PTH penetrates the first substrate 100, the first wiring layer 30, and a portion of the second wiring layer 40 in the pad region PR (e.g., the top second interlayer insulating film ILD2) to expose the top surface of the connection pad CP.

[0153] A through electrode TE is disposed in the pad through hole PTH. In one embodiment, the through electrode TE contacts at least a portion of the exposed upper surface of the connection pad CP. The through electrode TE extends upward along at least a portion of the inner surface of the pad through hole PTH. The through electrode TE also extends along the second surface 100b of the first substrate 100. Therefore, the through electrode TE electrically connects the connection pad CP to at least one of various terminals adjacent to the second surface 100b of the first substrate 100. For example, the through electrode TE extends onto the inner surface of the first recess RS1 and is connected to the buried conductive pattern of the deep device isolation pattern DTI.

[0154] In one embodiment, the first structure S1 further includes a first bonding pad provided within a bottom portion of the first interlayer dielectric film ILD1, and the second structure S2 further includes a second bonding pad provided within a top portion of the second interlayer dielectric film ILD2. The first bonding pad is bonded to the second bonding pad, respectively. In one embodiment, the first and second bonding pads are formed of copper and are bonded to each other using a copper-to-copper bonding method. In this case, the interface between the bonded first and second bonding pads is not visible.

[0155] As shown, in this embodiment, the second recess RS2 and the first and second connecting structures 50 and 60 of FIG. 4 are omitted. However, embodiments of the present invention are not limited thereto. In one embodiment, at least one of the first and second connecting structures 50 and 60 may be applied to the image sensor according to this embodiment. In other words, the first and second structures S1 and S2 are electrically connected to each other through at least one of the first and second connecting structures 50 and 60 and / or the first and second bonding pads.

[0156] The image sensor having the above-described structure has been described by way of example only, and various modifications may be made without departing from the spirit and scope of the present invention. For example, the above-described embodiments may be combined in various forms except where incompatible with each other. The image sensor having the above-described structure may reduce or prevent defects such as cracks occurring in the image sensor by alleviating or buffering stress applied to the peripheral region PP and regions adjacent to the peripheral region PP.

[0157] In the following description, the ninth example of the method for manufacturing an image sensor shown in Fig. 14 will be described as an example to avoid redundancy. However, the method for manufacturing an image sensor according to an embodiment of the present invention may be modified in various ways within the concept of the present invention.

[0158] 17A to 17I are cross-sectional views sequentially illustrating a method for manufacturing an image sensor according to an embodiment of the present invention.

[0159] Referring to FIG. 17A, a portion of a first structure S1 and a second structure S2 are prepared, the first structure S1 is inverted and placed on the second structure S2, and then they are bonded together.

[0160] To form the first structure S1, a first substrate 100 is prepared, and some components of a pixel are formed on a first surface 100a of the first substrate 100. At this stage, a first wiring layer 30 is formed on the first surface 100a of the first substrate 100. The second structure S2 is prepared separately from the first structure S1. The second structure S2 is manufactured by a method of preparing a second substrate 200 and forming a peripheral transistor PTR and a second wiring layer 40 on the second substrate 200.

[0161] 17B, ​​after bonding the first structure S1 and the second structure S2, a portion of the first substrate 100 on the rear surface of the first structure S1, i.e., the second surface side, is removed. The portion of the first substrate 100 is removed through a chemical mechanical polishing process. The polishing is performed until the deep isolation pattern DTI is exposed. Next, a transmissive insulating film 310 is formed on the second surface 100b of the first substrate 100, and first and second recesses RS1 and RS2, first and second through holes TH1 and TH2, etc. are formed.

[0162] Referring to FIG. 17C, a lattice pattern 320, connecting structures 50 and 60, connecting pads CP, color filters CF, a protective film 330, color filters CF, and a filtering pattern 80 are formed on the first substrate 100.

[0163] Referring to FIG. 17D, a planarization film PL, a spacer SP, a first etching prevention film 95, and a first initial nanostructure layer NS1i are sequentially formed on a first substrate 100.

[0164] The planarization film PL is coated using an organic polymer and then cured, and the spacer SP, the first etching prevention film 95, and the first initial nanostructure layer NS1i are deposited. The first initial nanostructure layer NS1i is made of a material having a relatively low refractive index.

[0165] Referring to FIG. 17E, the first initial nanostructure layer NS1i is patterned using photolithography and etching processes to form a first nanostructure layer pattern, and then a first nanostructure layer NS1 is formed by depositing a first nanorefractive index material having a relatively high refractive index. In other words, the first initial nanostructure layer NS1i is formed on the first substrate 100 using a low refractive index material, and the low refractive index material layer is etched to form a first nanostructure layer pattern having a plurality of holes, which are then filled with a high refractive index material. The first etch stop layer 95 prevents the spacer SP below the first etch stop layer 95 from being etched when the low refractive index material layer is etched. The plurality of holes are formed corresponding to the areas where the first and second nanoposts (NP1, NP2) will be formed. The first nanorefractive index material (i.e., a high refractive index material) is deposited in the holes of the first nanostructure layer pattern to form the first nanoposts NP1 and second nanoposts NP2. The top surface of the first nanostructure layer NS1 is polished using chemical mechanical polishing.

[0166] As described above, the first nanostructure layer NS1 includes the meta-microlenses MML and the dummy nanopatterns DNP. In one embodiment of the present invention, the meta-microlenses MML on the pixel array region AR and the dummy nanopatterns DNP on the peripheral region PP are individually formed using separate photolithography processes. However, the meta-microlenses MML and the dummy nanopatterns DNP can be formed using a single mask in a single photolithography process, which simplifies the process and reduces costs.

[0167] 17F, a second etching prevention film 97 is formed on the first nanostructure layer NS1, and a second initial nanostructure layer NS2i is formed on the second etching prevention film 97. The second initial nanostructure layer NS2i is formed of the material of the second nanorefractive index pattern having a relatively low refractive index.

[0168] 17G, the second initial nanostructure layer NS2i is patterned using photolithography and etching processes to form a second nanostructure layer pattern, and then a second nanostructure layer NS2 is formed by depositing a material of the first nanorefractive index pattern having a relatively high refractive index. Here, the material of the first nanorefractive index pattern is deposited into the holes of the second nanostructure layer pattern to form first nanoposts NP1 and second nanoposts NP2. The top surface of the second nanostructure layer NS2 is polished using chemical mechanical polishing.

[0169] 17H, a third anti-etching film 99 and an initial anti-reflection film ARLi are formed on the substrate on which the second nanostructure layer NS2 is formed. The initial anti-reflection film ARLi is formed of a material having a relatively low refractive index.

[0170] Referring to FIG. 17I, the initial anti-reflection layer ARLi is etched through a photolithography process to form an anti-reflection pattern ARL.

[0171] 14, the third etch stop film 99, the second nanostructure layer NS2, the second etch stop film 97, the first nanostructure layer NS1, the first etch stop film 95, the spacer SP, and the planarization layer PL are patterned using a photolithography process and an etching process to form an opening OPN, which exposes the top surface of the connection pad CP.

[0172] An embodiment of the present invention provides an image sensor and a method for manufacturing the same that minimizes the occurrence of cracks due to stress by providing a structure that can alleviate or buffer stress differences within the image sensor.

[0173] Although the embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the technical concept of the present invention. [Explanation of symbols]

[0174] 1 pixel array Two-line decoder 3-row driver 4-row decoder 5 Timing Generator 6. Correlated Double Sampler (CDS) 7 Analog-to-Digital Converter (ADC) 8 Input / Output Buffers 10 Photoelectric conversion layer 20 Light transmission layer 30, 40 1st, 2nd wiring layer 50, 60 1st and 2nd connected structure 51, 61 1st and 2nd through electrode 52, 62 First and second buried insulating patterns 53, 63 1st and 2nd capping patterns 70 Conductive plug 80 Filtering Patterns 90 Passivation Film 95, 97, 99 First to third etching prevention films 100, 200 First and second boards 100a, 100b 1st and 2nd pages 110 Photoelectric conversion region 310 Transparent insulating film 320 grid pattern 330 Protective film AR pixel array area ARL Anti-Reflection Pattern ARLi early anti-reflection coating CF color filter CP Connecting Pad DNP dummy nanopattern DNP1, DNP2 First and second dummy nanopatterns DTI Deep Isolation Pattern FD Floating diffusion region HL horizontal edge ICL1, ICL2 1st and 2nd wiring lines ILD1, ILD2 First and second interlayer insulating films MML Meta Micro Lens MML1, MML2 1st and 2nd meta-microlenses NP nanopost NP1, NP2 First and second nanoposts NS nanostructure layer NS1, NS2: First and second nanostructure layers NS1i, NS2i First and second initial nanostructure layers OPN opening PD photoelectric conversion element PL planarization film PP peripheral area PR pad area PTH Pad through hole PTR peripheral transistor PXL Pixel PXR Pixel Area PXR1, PXR2, PXR3, PXR4 1st to 4th pixel areas RGL Reset gate line RF1, RF2 First and second nano-refractive patterns RS1, RS2 1st and 2nd recesses RX reset transistor S1, S2 1st, 2nd structure SGL Select Gate Line SP spacer STI shallow isolation pattern SX select transistor SXF Source Follower Transistor TE through electrode TG Transmission Gate TGL Transmission Gate Line TH1, TH2 1st and 2nd through holes TX Transistor V DD power terminal VL vertical edge V OUT Output Line

Claims

1. a photoelectric conversion element provided within the pixel array region; a peripheral region provided on at least one side of the pixel array region; a nanostructure layer provided on the pixel array region and the peripheral region; The nanostructure layer includes a meta-microlens configured to focus light incident on the pixel array over the pixel array region, and a dummy nanopattern over the peripheral region.

2. each of the meta-microlens and the dummy nanopattern includes a first nano-refractive pattern having a first refractive index and a second nano-refractive pattern having a second refractive index; the first refractive index and the second refractive index are different from each other, The image sensor of claim 1 , wherein the first nano-refractive pattern comprises nano-posts.

3. 3. The image sensor of claim 2, wherein the nanostructure layer comprises a first nanostructure layer and a second nanostructure layer disposed on the first nanostructure layer.

4. The image sensor of claim 3 , wherein the first nanostructure layer includes a color separation lens array.

5. the nanoposts include first layer nanoposts in the first nanostructure layer and second layer nanoposts in the second nanostructure layer; 4. The image sensor according to claim 3, wherein the first layer nanoposts overlap the second layer nanoposts in a plan view.

6. the nanoposts include first layer nanoposts in the first nanostructure layer and second layer nanoposts in the second nanostructure layer; 4. The image sensor according to claim 3, wherein one of the first layer nanoposts does not overlap the second layer nanopost in a plan view.

7. The image sensor of claim 2 , further comprising a color filter disposed on the pixel array region.

8. each of the meta-microlenses includes a plurality of first nanoposts; The image sensor of claim 2 , wherein the dummy nanopattern includes a plurality of second nanoposts.

9. The image sensor of claim 8 , wherein the plurality of second nanoposts include bar-shaped second nanoposts extending in a first direction in a plan view.

10. The image sensor of claim 9 , wherein the first direction extends along a direction parallel to a boundary between the pixel array region and the peripheral region.

11. The image sensor of claim 8 , wherein each of the second nanoposts is a polygonal pillar, a circular pillar, or an elliptical pillar.

12. The image sensor of claim 8, characterized in that the density of the plurality of second nanoposts per unit area in the peripheral region is 80% to 120% of the density of the plurality of first nanoposts per unit area in the pixel array region in a planar view.

13. a pad region provided on one side of the peripheral region; a connecting pad on the pad area, The image sensor of claim 8 , wherein the connection pad provides an electrical connection to an external device.

14. the image sensor includes a first structure and a second structure provided below the first structure and bonded to the first structure; The image sensor of claim 13 , wherein the connection pad is included in the first structure.

15. The image sensor of claim 13 , wherein the second nanoposts are provided in the pad region.

16. the plurality of second nanoposts of the first group on the peripheral region have a bar shape extending in a first direction; 16. The image sensor of claim 15, wherein the second nanoposts of the second group provided on the pad region have a bar shape extending in a second direction different from the first direction.

17. the image sensor includes a first structure and a second structure provided below the first structure and bonded to the first structure; The image sensor of claim 13 , wherein the connection pad is included in the second structure.

18. 18. The image sensor of claim 17, wherein the first structure and the second structure are bonded to each other using a copper-to-copper bonding method.

19. providing a first substrate including a pixel array region and a peripheral region; forming an etch stop layer on the pixel array region and the peripheral region; forming an initial nanostructure layer on the pixel array region and the peripheral region using a material having a first refractive index; patterning the initial nanostructure layer to form a plurality of holes; forming nanoposts by depositing a material having a second refractive index different from the first refractive index in the plurality of holes; forming a meta-microlens on the pixel array region using the nanoposts; and forming a dummy nanopattern on the peripheral region using the nanoposts.

20. 20. The method of claim 19, wherein forming the meta-microlenses on the pixel array region and forming the dummy nanopatterns on the peripheral region are performed using a single mask.

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