Fetching and reusing flushed instructions after an instruction pipeline flush in response to hazards in a processor to reduce instruction re-fetching

Abstract

To reuse flushed instructions after an instruction pipeline flush in response to a hazard.SOLUTION: The instruction processing circuit detects a performance-degrading instruction (PDI) that could cause a precise interrupt that would cause a flush of the instruction pipeline at a preliminary execution stage in the instruction pipeline, and in response to the PDI detection, captures the fetched PDI and / or younger fetched instructions that follow the PDI in the pipeline refill circuit. The instruction processing circuit also injects the fetched PDI and / or its younger instructions, previously captured from the pipeline refill circuit, into the instruction pipeline to be processed without being re-fetched if execution after the PDI in the instruction pipeline causes a flush of the instruction pipeline.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The techniques of this disclosure relate to computer processors ("processors"), and more particularly to fetching computer program instructions executing in the processor. [Background technology]

[0002] Microprocessors, also known as "processors," perform computational tasks for a wide variety of applications. A traditional microprocessor includes a central processing unit (CPU), which contains one or more processor cores, also known as "CPU cores." A CPU executes computer program instructions ("instructions"), also known as "software instructions," to perform operations on data and produce results, which are generated values. The processing of each instruction within a processor is divided into a series of distinct stages or steps known as instruction pipelining. This allows multiple instructions to be processed simultaneously in different stages, increasing instruction processing throughput, as opposed to sequentially processing each instruction completely before processing the next. The instruction pipelining steps are performed within one or more instruction pipelines within the processor, each consisting of multiple processing stages.

[0003] Optimal processor performance can be achieved when all pipeline stages in an instruction pipeline can process instructions simultaneously within that instruction pipeline. However, hazards can occur in an instruction pipeline that prevent an instruction from executing without leading to incorrect computational results. One example of a hazard that can flush an instruction pipeline is a structural hazard. An example of a structural hazard is a load instruction that fails to load an entry into a load queue that may be full. If the load instruction cannot execute, a deadlock can occur in the instruction pipeline. Another example of a hazard that can flush an instruction pipeline is a control hazard resulting from the execution of a control flow instruction that causes a precise interrupt within the processor. One example of a control flow instruction that can cause a control hazard is a conditional branch instruction. A conditional branch instruction contains a predicate condition that is not fully evaluated in a later execution stage in the instruction pipeline to determine whether the instruction flow will take or not take the branch. A control flow prediction circuit can be provided within the processor that speculatively predicts the branch target address of a conditional branch instruction so that it is not necessary to stall the fetching of subsequent instructions, i.e., younger instructions behind the conditional branch instruction, into the instruction pipeline before the conditional branch instruction is executed. The processor may then speculatively fetch subsequent instructions in the fetch stages of the instruction pipeline following the fetch of the conditional branch instruction based on the prediction of the branch target address.

[0004] If the actual resolved branch target address is determined to match the predicted branch address during execution, no stall occurs in the instruction pipeline. This is because when the conditional branch instruction reaches its execution stage in the instruction pipeline, the subsequent instructions beginning at the predicted branch target address have been correctly fetched and are already present in the instruction pipeline. However, if the predicted branch target address and the resolved branch target address do not match, a mispredicted branch hazard occurs in the instruction pipeline, causing a precise interrupt. As a result, the instruction pipeline is flushed of existing, previously fetched instructions in various stages of the instruction pipeline. The fetch stage of the instruction pipeline is instructed to fetch new instructions beginning at the correct resolved branch target. Thus, stages of the instruction pipeline remain stalled until the newly fetched instructions advance through the instruction pipeline and are processed and executed, thereby reducing instruction throughput performance.

[0005] There are also other situations that can be encountered when processing instructions beyond a branch instruction that can cause architectural hazards and thus flush the instruction pipeline. Examples include deadlocks and instructions that cannot be executed due to a lack of resources such as available space in a queue. Summary of the Invention [Means for solving the problem]

[0006] An example aspect disclosed herein includes reusing fetched and flushed instructions after an instruction pipeline flush in response to a hazard in a processor to reduce instruction refetching. The processor includes an instruction processing circuit configured to fetch instructions into the instruction pipeline to be processed and executed in an execution stage as part of instruction pipelining. Execution circuitry within the instruction processing circuitry is configured to generate a precise interrupt in response to encountering a hazard (e.g., a structural or control flow hazard) when executing the instructions. For example, a precise interrupt may be generated as a result of a mispredicted conditional branch instruction whose subsequent control-dependent instructions to the conditional branch instruction from an incorrect instruction flow path are already fetched in the instruction pipeline. In response to the precise interrupt, the instruction processing circuitry is configured to flush the instruction that caused the precise interrupt and any subsequent younger instructions in the instruction pipeline to overcome the hazard. This reduces instruction throughput in the instruction pipeline. If these already fetched instructions can be reused in the instruction pipelining after flushing without having to be refetched, these already fetched instructions can be injected into the instruction pipeline without having to refetch these instructions, thus mitigating the reduced instructions from the flushing.

[0007] In this regard, in an exemplary aspect disclosed herein, an instruction processing circuit in a processor is configured to detect a fetched instruction in a pre-execution stage in the instruction pipeline that may cause a precise interrupt that will cause a flush of the instruction pipeline. These instructions may be referred to as performance degrading instructions (PDIs). For example, the instruction processing circuit may be configured to detect the PDI after being decoded in a decode stage of the instruction pipeline. In response to detecting the PDI in the instruction pipeline, the instruction processing circuit is configured to capture the fetched PDI (if not already present) and any subsequent, younger fetched instructions that are processed behind the PDI in the instruction pipeline in a pipeline fetch refill circuit. Thus, if execution of the PDI in the instruction pipeline causes a precise interrupt that causes a flush of the instruction pipeline (a flush event), the instruction processing circuit can determine whether the detected instruction (i.e., the PDI and / or the subsequent instruction) is present in the pipeline fetch refill circuit as previously captured. If the detected instruction is present in the pipeline fetch refill circuitry, the instruction processing circuitry can inject the detected instruction and any subsequent younger instructions previously captured in the pipeline fetch refill circuitry into the instruction pipeline to be processed without having to refetch such instructions. In this way, the instruction throughput of the instruction pipeline does not incur any latency associated with refetching these instructions. The instruction processing circuitry provides a "fall-through" program counter (PC) in the fetch stage of the instruction pipeline so that it knows where to begin refetching instructions that need to be fetched in response to a flush event, since they cannot be injected from the pipeline fetch refill circuitry. The fall-through PC is the PC of the next instruction following the last captured younger instruction in the pipeline fetch refill circuitry.The instruction processing circuitry can be configured to capture a fall-through PC in a pipeline fetch refill circuitry associated with the captured PDI.

[0008] In another exemplary aspect, the instruction pipeline circuitry may also be configured to capture instruction flow path information within the instruction processing circuitry for a PDI having a variable instruction flow path. For example, the instruction flow path taken after a conditional branch instruction or an indirect branch instruction varies based on the resolution of the branching behavior of such an instruction. In this manner, the specific instruction flow path of a captured subsequent, younger instruction from the captured PDI is known. In response to detecting and determining the presence of a PDI in the pipeline fetch refill circuitry responsive to a flush event, the instruction processing circuitry may also determine whether the captured younger control-dependent instruction from the PDI should be injected into the instruction pipeline as being from the correct instruction flow path. If the captured younger control-dependent instruction is from the correct resolved instruction flow path from the PDI, the younger control-dependent instruction can be injected into the instruction pipeline as being known to be from the correct instruction flow path of the PDI without needing to be refetched. If the captured younger control-dependent instruction is determined not to be from the correct instruction flow path from the PDI, the younger control-dependent instruction can be ignored and refetched. Instruction flow path information does not need to be recorded for younger instructions that are control-independent to the PDI, because control-independent instructions do not depend on resolved instruction flow paths from the PDI.

[0009] In this regard, in one exemplary aspect, a processor is provided. The processor has an instruction processing circuit including an instruction fetch circuit configured to fetch a plurality of instructions from program code as a plurality of fetched instructions into an instruction pipeline for execution. The instruction processing circuit also has an execution circuit coupled to the instruction fetch circuit, the execution circuit configured to execute a fetched instruction of the plurality of fetched instructions in the instruction pipeline and generate a pipeline flush event to flush the instruction pipeline in response to execution of a fetched instruction of the plurality of instructions that includes a hazard-generating PDI. The processor also has an instruction fetch refill circuit coupled to the instruction pipeline. In response to the pipeline flush event, the instruction fetch refill circuit determines whether a source identification information of the fetched instruction matches a source identification information in a refill tag in a fetch refill entry as a matching fetch refill entry among a plurality of fetch refill entries of the pipeline fetch refill circuit. In response to the source identification information of the fetched instruction matching the source identification information in the refill tag in the fetch refill entry, the instruction fetch reclamation circuit is configured to insert one or more captured instructions in the matching fetch refill entry into the instruction pipeline after the instruction fetch circuit for processing.

[0010] In another exemplary aspect, a method for reclaiming fetched and flushed instructions in an instruction pipeline in a processor is provided. The method includes fetching a plurality of instructions from program code as a plurality of fetched instructions into the instruction pipeline for execution. The method also includes executing a fetched instruction of the plurality of fetched instructions in the instruction pipeline. The method also includes generating a pipeline flush event to flush the instruction pipeline in response to execution of a fetched instruction of the plurality of instructions generating a hazard as a PDI. In response to the pipeline flush event, the method also includes determining whether source identification information of the detected instruction matches source identification information in a refill tag in a fetch refill entry as a matching fetch refill entry among a plurality of fetch refill entries of a pipeline fetch refill circuit. In response to the source identification information of the detected instruction matching source identification information in the refill tag in the fetch refill entry, the method also includes inserting one or more captured instructions in the matching fetch refill entry into the instruction pipeline as fetched instructions to be executed.

[0011] Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects of the present disclosure after reading the following detailed description of the preferred embodiments in connection with the accompanying drawings. [Brief explanation of the drawings]

[0012] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate several aspects of the present disclosure and, together with the description, serve to explain the principles of the disclosure.

[0013] [Figure 1]1 is a diagram of an exemplary processor-based system including a processor having instruction processing circuitry including one or more instruction pipelines for processing computer instructions, the instruction processing circuitry being configured to, in response to a pipeline flush caused by execution of a captured PDI, reuse a captured fetched instruction (i.e., the fetched PDI and / or its captured, fetched, subsequent, younger instruction) in the instruction pipeline to be processed, thereby avoiding the need to refetch the PDI to be processed and its younger instruction.

[0014] [Figure 2A] 10 is a flowchart illustrating an exemplary process of the instruction processing circuit of FIG. 1 detecting and capturing fetched instructions in the instruction pipeline to the pipeline fetch refill circuit.

[0015] [Figure 2B] 10 is a flowchart illustrating an exemplary process of the instruction processing circuit of FIG. 1 reclaiming captured fetched instructions from the pipeline fetch refill circuit in the instruction pipeline in response to a flush event caused by execution of a PDI.

[0016] [Figure 3] 1 is a diagram of another exemplary processor-based system including a processor having instruction processing circuitry including one or more instruction pipelines for processing computer instructions, the instruction processing circuitry being configured to, in response to a pipeline flush caused by execution of the captured PDI, reuse a captured fetched instruction in the instruction pipeline to be processed, thereby avoiding the need to refetch the PDI to be processed and its younger instructions.

[0017] [Figure 4]FIG. 4 is a diagram of the example pipeline fetch fill circuit of FIG. 3 configured to store captured and fetched instructions present in the instruction pipeline, and configured to provide the captured and fetched PDIs and / or their fetched younger instructions for reuse in response to a flush event caused by execution of the PDIs.

[0018] [Figure 5] 1 and 3, and in accordance with the exemplary process of FIGS. 2A and 2B, a processor having instruction processing circuitry configured to reuse captured fetched instructions in an instruction pipeline to be processed in response to a pipeline flush caused by execution of a captured PDI, and avoid the need to refetch the captured fetched instructions to be processed. DETAILED DESCRIPTION OF THE INVENTION

[0019] An example aspect disclosed herein includes reusing fetched and flushed instructions after an instruction pipeline flush in response to a hazard in a processor to reduce instruction refetching. The processor includes an instruction processing circuit configured to fetch instructions into the instruction pipeline to be processed and executed in an execution stage as part of instruction pipelining. Execution circuitry within the instruction processing circuitry is configured to generate a precise interrupt in response to encountering a hazard (e.g., a structural or control flow hazard) when executing the instructions. For example, the precise interrupt may be generated as a result of a mispredicted conditional branch instruction whose subsequent control-dependent instructions to the conditional branch instruction from an incorrect instruction flow path are already fetched in the instruction pipeline. In response to the precise interrupt, the instruction processing circuitry is configured to flush the instruction that caused the precise interrupt and any subsequent younger instructions in the instruction pipeline to overcome the hazard. This reduces instruction throughput in the instruction pipeline. If these already fetched instructions can be reused in the instruction pipelining after flushing without having to be refetched, these already fetched instructions can be injected into the instruction pipeline without having to refetch these instructions, thus mitigating the reduced instructions from the flushing.

[0020] In this regard, in an exemplary aspect disclosed herein, an instruction processing circuit in a processor is configured to detect a fetched instruction in a pre-execution stage in the instruction pipeline that may cause a precise interrupt that will cause a flush of the instruction pipeline. These instructions may be referred to as performance degrading instructions (PDIs). For example, the instruction processing circuit may be configured to detect the PDI after being decoded in a decode stage of the instruction pipeline. In response to detecting the PDI in the instruction pipeline, the instruction processing circuit is configured to capture the fetched PDI (if not already present) and any subsequent, younger fetched instructions that are processed behind the PDI in the instruction pipeline in a pipeline fetch refill circuit. Thus, if execution of the PDI in the instruction pipeline causes a precise interrupt that causes a flush of the instruction pipeline (a flush event), the instruction processing circuit can determine whether the detected instruction (i.e., the PDI and / or the subsequent instruction) is present in the pipeline fetch refill circuit as previously captured. If the detected instruction is present in the pipeline fetch refill circuitry, the instruction processing circuitry can inject the detected instruction and any subsequent younger instructions previously captured in the pipeline fetch refill circuitry into the instruction pipeline to be processed without having to refetch such instructions. In this way, the instruction throughput of the instruction pipeline does not incur any latency associated with refetching these instructions. The instruction processing circuitry provides a "fall-through" program counter (PC) in the fetch stage of the instruction pipeline so that it knows where to begin refetching instructions that need to be fetched in response to a flush event, since they cannot be injected from the pipeline fetch refill circuitry. The fall-through PC is the PC of the next instruction following the last captured younger instruction in the pipeline fetch refill circuitry.The instruction processing circuitry can be configured to capture a fall-through PC in a pipeline fetch refill circuitry associated with the captured PDI.

[0021] In this regard, Figure 1 is a schematic diagram of an exemplary processor-based system 100 including a processor 102. As discussed in more detail below, processor 102 is configured to recycle fetched instructions that were fetched and present in the instruction pipeline and were subsequently flushed in response to an encountered hazard in order to reduce instruction re-fetching. Before discussing the recycle of fetched instructions in response to a pipeline flush that occurs in response to an encountered hazard, other components of processor 102 are first discussed below.

[0022] Referring to FIG. 1, processor 102 includes one or more instruction pipelines I0-I1 for processing computer instructions for execution. N The processor 102 includes an instruction processing circuit 104 including an instruction pipeline 108. The processor 102 is an out-of-order processor (OoP) as shown in FIG. 1, but may also be an in-order processor. The instruction processing circuit 104 includes an instruction fetch circuit 106 configured to fetch instructions 108 from an instruction memory 110. The instruction memory 110 may be provided in or as part of a system memory within the processor-based system 100, as an example. To reduce timing delays within the instruction fetch circuit 106, an instruction cache 112 may be provided within the processor 102 for caching instructions 108 fetched from the instruction memory 110. The instruction fetch circuit 106 in this example transmits instructions 108 as fetched instructions 108F to one or more of the instruction pipelines I0-I1 as an instruction stream 114 within the instruction processing circuit 104 to be preprocessed. N The fetched instruction 108F then reaches the execution circuit 116 for execution as the executed instruction 108E. Nare provided across different processing circuits or stages of the instruction processing circuitry 104 to pre-process and process the fetched instructions 112F in a series of steps that can be performed in parallel to increase throughput, prior to execution of the fetched instructions 108F by the execution circuitry 116.

[0023] A control flow prediction circuit 118 (e.g., a control flow prediction circuit) is also provided in the instruction processing circuit 104 in the processor 102 of FIG. 1, and is used to predict the flow of instruction pipelines I0-I1. N The control flow prediction circuit 118 predicts or guesses the outcome of a predicate in a fetched conditional control instruction 108F, such as a conditional branch instruction, that affects the instruction control flow path of the instruction stream 114 being processed in the instruction processing circuit 104. The predictions of the control flow prediction circuit 118 can be used by the instruction fetch circuit 106 to determine the next fetched instruction 108F to fetch based on the predicted branch target address. The instruction processing circuit 104 also includes an instruction decode circuit 120 configured to decode the fetched instructions 108F fetched by the instruction fetch circuit 106 into decoded instructions 108D to determine the required instruction type and action. The required instruction type and action encoded in the decoded instruction 108D also determine which instruction pipeline 108D the decoded instruction 108D will be routed to. N This may be used to determine what should be placed in

[0024] In this example, the decoded instructions 108D are sent to the instruction pipeline I0-I1. N, P0, P1, ..., P2, ..., P3, ... in a physical register file (PRF) 126. The physical register file (PRF) 126 stores the physical registers P0, P1, ..., P4, ... in a physical register file (PRF) 126. The physical registers P0, P1, ..., P2, ... in a physical register file (PRF) 126 are used to store the physical registers P0, P1, ..., P3, ... in a physical register file (PRF) 126. The physical registers P0, P1, ..., P4, ... in a physical register file (PRF) 126 are used to store the physical registers P0, P1, ..., P2, ... in a physical register file (PRF) 126. The physical registers P0, P1, ..., P3, ... in a physical register file (PRF) 126 are used to store the physical registers P0, P1, ..., P4, ... in a physical register file (PRF) 126. The physical registers P0, P1, ..., P2, ... in a physical register file (PRF) 126 are used to store the physical registers P0, P1, ..., P3, ... in a physical register file (PRF) 126. The physical registers P0, P1, ..., P4, ... in a physical register file (PRF) 126 are used to store the physical registers P0, P1, ..., P4, ... in a physical register file (PRF) 126. The physical registers P0, P1, ..., P2, ... in a physical register file (PRF) 126 are used to store the physical registers P0, P1, ..., P2, ... in a physical register file (PRF) 126. The physical registers P0, P1, ..., P3, ... in a physical register file (PRF) 126 are used to store the physical registers P0, P1, ..., P4, ... in a physical register file (PRF X The rename access table circuit 124 is configured to write to each of the logical registers R0-R1. P The register mapping entries 128(0) through 128(P) are mapped to (i.e., associated with) physical registers P0 through P1 in the PRF 126, respectively. X Logical registers R0 to R P Each physical register P0 to P1 stores mapping information corresponding to the physical registers P0 to P1. X is configured to store data entries 130(0) through 130(X) for source and / or destination register operands of the decoded instruction 108D.

[0025] The instruction processing circuitry 104 in the processor 102 of FIG. 1 also includes an instruction pipeline I0-I1 before the issue circuitry 134. N The register access circuit 132 is located within the rename access table circuit 124. The register access circuit 132 accesses the logical registers R0 to R1 within the rename access table circuit 124. P Physical registers P0 through P1 in the PRF 126 are mapped to the register mapping entries 128(0) through 128(P). X, and are configured to use them as input values ​​for the designated source register operands of the decoded instructions 108D executed within the execution circuitry 116. The issue circuitry 134 passes the decoded instructions 108D through the instruction pipeline I0 through I1 until all of their respective source register operands are available for consumption at runtime. N The issue circuitry 134 issues the decoded instructions 108D that are ready to be executed to the execution circuitry 116. The instruction processing circuitry 104 also includes a commit circuitry 136 that commits or writes back values ​​produced by the execution of the decoded instructions 108D to a memory, such as the PRF 126, a cache memory, or a system memory.

[0026] Execution circuitry 116 in instruction processing circuitry 104 in processor 102 of FIG. 1 is configured to generate a precise interrupt in response to encountering a hazard (e.g., a structural or control flow hazard) when executing decoded instruction 108D. An instruction 108D that is determined to cause, or is likely to cause, a hazard in processor 102 when executed is referred to herein as a "performance degrading instruction (PDI)." By the time execution circuitry 116 encounters the hazard from executing PDI 108D, a subsequent, younger instruction 108D may already be in the instruction pipeline I0-I1. N In response to the precise interrupt, the instruction processing circuit 104 generates a flush event 138 to flush the instruction 108D that caused the precise interrupt and the instruction pipeline I0-I1. N To overcome the hazard, the PDI 108D and its subsequent younger instruction 108D that have already been fetched within the PDI 108D are flushed and re-executed. Re-fetching the PDI 108D and its subsequent younger instruction 108D undesirably reduces throughput in the instruction processing circuit 104.

[0027] 1 includes a PDI detection circuit 140 and an instruction fetch reuse circuit 142. The PDI detection circuit 140 and the instruction fetch reuse circuit 142 can be included as part of the instruction processing circuit 104 or external to the instruction processing circuit 104. The PDI detection circuit 140 and the instruction fetch reuse circuit 142 are both connected to the instruction pipelines I0-I1. N As discussed in more detail below, the PDI detection circuit 140 detects the instruction pipelines I0-I1 to be processed and executed. N For example, the PDI detection circuit 140 may be configured to detect the PDI 108D after it has been decoded in the instruction decode circuit 120. The PDI detection circuit 140 detects the PDI 108D in the instruction pipelines I0 to I1. N In response to detecting a PDI 108D in the instruction pipeline, the PDI detection circuit 140 is configured to capture the detected instruction into the pipeline fetch refill circuit 144, which may be a subsequent, younger fetched instruction 108D in the instruction pipeline I0-I1 behind the PDI 108D. NThe pipeline fetch refill circuit 144 may be a table circuit including a plurality of fetch refill entries 146(0)-146(R), each configured to store information about a detected PDI 108D and a subsequent, younger fetched instruction 108D. In this manner, later, in response to a flush event 138, the instruction fetch reclaim circuit 142 can determine whether the detected instruction (i.e., the PDI 108D whose execution caused the flush event 138 and / or its younger successor instruction 108D) was previously captured in a fetch refill entry 146(0)-146(R) in the pipeline fetch refill circuit 144. If the detected instruction 108D is present in a fetch refill entry 146(0)-146(R) in the pipeline fetch refill circuit 144, the instruction fetch recycle circuit 142 reclaims the previously captured PDI 108D and / or its younger, subsequent fetched instruction 108D from the pipeline fetch refill circuit 144 into the instruction pipelines I0-I1 for processing. N , and there is no need to re-fetch such decoded instructions 108D.

[0028] In this way, the latency associated with refetching these previously fetched instructions 108D is not incurred in the instruction throughput of the instruction processing circuitry 104. The instruction fetch reuse circuitry 142 can provide a "fall-through" program counter (PC) 148 to the instruction fetch circuitry 106 so that the instruction fetch circuitry 106 knows where to start fetching instructions 108 in response to a flush event 138. The fall-through PC 148 is the PC of the next instruction 108D following the last, previously captured subsequent younger instruction 108D in the pipeline fetch refill circuitry 144 for the PDI 108D whose execution caused the flush event 138. As described in further detail below, the PDI detection circuitry 140 also detects the instruction pipelines I0-I1 and I2. N1. The instruction fetch circuit 106 is also configured to record the fall-through PC 148 in a fetch refill entry 146(0)-146(R) assigned to capture the detected fetched PDI 108D and its younger, subsequent fetched instruction 108D. In this manner, the instruction fetch circuit 106 reclaims instruction pipelines I0-I1 by the instruction fetch reuse circuit 142. N It can then begin fetching new instructions 108D that are not injected into the

[0029] FIG. 2A shows the instruction pipeline I0 to I N 1 to detect and capture a fetched PDI 108D and a fetched younger instruction 108D in the instruction processing circuit 104 of FIG. 1 into the pipeline fetch refill circuit 144 of FIG. 1. This allows the captured fetched PDI 108D and its fetched younger instruction 108D to be reused and reclaimed by the instruction fetch reclaim circuit 142 from the instruction pipeline (I0-I1) without having to be refetched. N ) The process 200 of FIG. 2A is described below in connection with the processor 102 of FIG.

[0030] In this regard, the process 200 routes instructions 108 from the program code as fetched instructions 108F through instruction pipelines I0-I10 for execution. N (Block 202 of FIG. 2A). The process 200 also includes the PDI detection circuit 140 detecting the instruction pipeline I0-I1. N The PDI detection circuit 140 detects whether the fetched instruction 108D in the instruction pipeline I0-I1 is a PDI 108D (block 204 of FIG. 2A). NThere are many ways in which the fetched instruction 108D in the pipeline 140 can detect whether it is a PDI 108D, examples of which are described in detail below. The PDI detection circuit 140 then optionally determines whether the detected instruction 108D was previously captured in the pipeline fetch refill circuit 144, thereby determining whether the PDI 108D and its younger, subsequent fetched instructions 108D have already been captured before.

[0031] In one example, if the PDI 108D is also the type of instruction that needs to be flushed and therefore refetched in response to the flush event 138, the instruction processing circuit 104 is configured to capture the fetched PDI 108D itself in the pipeline fetch refill circuit 144 in response to the detected PDI 108D so that this captured fetched PDI 108 can be later reused by the instruction fetch reuse circuit 142 as a refetched PDI 108, such as in response to the flush event 138, without the need to refetch the PDI 108. Thus, an example of a PDI 108 that is flushed in response to a flush event 138 and refetched for re-execution is a memory load instruction that has encountered a deadlock. In another example, if the PDI 108D is a type of instruction that is not flushed in response to a flush event 138 and therefore needs to be refetched, the instruction processing circuit 104 is not configured to capture the fetched PDI 108D in the pipeline fetch refill circuit 144 in response to the detected PDI 108D. This is because the captured fetched PDI does not need to be re-executed. An example of a PDI 108 that is not flushed in response to a flush event 138 and therefore not refetched for re-execution is a mispredicted conditional branch instruction.

[0032] 2A , in this example, in response to PDI detection circuit 140 detecting fetched instruction 108D as the detected instruction (which may be PDI 108D and / or its younger successor instruction 108D) (block 204 of FIG. 2A ), PDI detection circuit 140 determines whether source identification information 150 (e.g., source address, program counter (PC)) of detected instruction 108D matches source identification information (e.g., source address, PC) in refill tags 152(0) through 152(R) in fetch refill entries 146(0) through 146(R) in pipeline fetch refill circuit 144 (block 206 of FIG. 2A ). This is to determine whether detected instruction 108D has already been previously captured in pipeline fetch refill circuit 144 by PDI detection circuit 140. In response to the source identification 150 of the detected instruction 108D not matching the source identification in the refill tag 152(0)-152(R) in the fetch refill entry 146(0)-146(R) (block 208 of FIG. 2A), the PDI detection circuit 140 allocates an available refill entry 146(0)-146(R) of the plurality of fetch refill entries 146(0)-146(R) in the pipeline fetch refill circuit 144 to capture one or more subsequent, younger instructions 108 following the detected instruction 108D for later use (block 210 of FIG. 2A). As described above, if the detected instruction 108D is an instruction that is refetched in response to the flush event 138, the PDI detection circuit 140 also captures the detected PDI 108D in the available fetch refill entry 146(0)-146(R). The PDI detection circuit 140 then stores the source identification information 150 of the detected PDI instruction 108D (which is the detected PDI 108D and / or its younger successor) in the refill tags 152(0)-152(R) of the available fetch refill entries 146(0)-146(R) (block 212 of FIG. 2A). ... NOne or more subsequent, younger fetched instructions 108D following the detected instruction 108D in the pipeline are captured in assigned fetch refill entries 146(0)-146(R) in the pipeline fetch refill circuitry 144 (block 214 of FIG. 2A). The detected instruction 108D and its subsequent, younger fetched instructions 108D are then processed and executed in the execution circuitry 116 (block 216 of FIG. 2A).

[0033] FIG. 2B illustrates how, in response to a flush event 138, a fetched instruction, which may be a PDI 108D previously captured in a pipeline fetch refill circuit 144 and / or a fetched subsequent younger instruction 108D, is flushed into the instruction pipelines I0-I1. N 1 for reclaiming instruction pipelines I0-I1. As described above, if the PDI 108D whose execution caused the flush event 138 was previously captured, the captured, fetched PDI 108D and / or fetched, subsequent, younger instructions 108D are obtained from the pipeline fetch refill circuit 144 and reclaimed into the instruction pipelines I0-I1. N This allows these instructions 108D to be injected into the instruction pipelines I0 to I1. N Process 220 of FIG. 2B is described below in connection with processor 102 of FIG.

[0034] In this regard, the process 220 may be configured to cause the processor 102 to execute, as a PDI 108D, a hazard-generating instruction 108D among the plurality of instructions 108D, and then to execute the instruction pipelines 100-108D. NIn response to the pipeline flush event 138 (block 224 of FIG. 2B), the instruction fetch refill circuit 144 determines whether the source identification 150 of the fetched instruction matches the source identification in the refill tag 152(0)-152(R) in the fetch refill entry 146(0)-146(R) as the matching fetch refill entry 146(0)-146(R) of the pipeline fetch refill circuit 144 (block 226 of FIG. 2B). In response to the source identification information 150 of the fetched instruction 108D matching the source identification information in the refill tag 152(0)-152(R) of the matching fetch refill entry 146(0)-146(R), the instruction fetch reclamation circuit 142 recycles one or more captured fetch instructions 108D in the matching fetch refill entry 146(0)-146(R) into the instruction pipelines I0-I1 as fetch instructions 108D to be executed. N (block 228 of FIG. 2B). Then, the process 220 inserts the instruction pipeline I0 to I N 2B, block 230.

[0035] There are different options and features that can be provided in the instruction processing circuitry 104 to support reuse of captured and detected instructions in the instruction pipeline in response to a pipeline flush caused by execution of the captured PDI to avoid the need to refetch the PDI and its younger instructions to be processed. In this regard, Figure 3 is a diagram of another exemplary processor-based system 300 including a processor 302 having instruction processing circuitry 304 similar to the instruction processing circuitry 104 of Figure 1. Common circuitry and components between the instruction processing circuitry 104 of Figure 1 and the instruction processing circuitry 304 of Figure 3 are indicated with common element numbers and will not be described again.

[0036] As shown in Figure 3, the instruction processing circuit 304 includes a PDI detection circuit 340 similar to the PDI detection circuit 140 of Figure 1. The instruction processing circuit 304 of Figure 3 includes an instruction fetch reuse circuit 342 similar to the instruction fetch reuse circuit 142 of Figure 1. The PDI detection circuit 340 detects which of the fetched instructions 108D are to be processed and executed in the instruction pipelines I0-I1. N 3. The PDI detection circuit 340 may be configured to detect the PDI 108D fetched in the instruction pipelines I0-I1 such that the PDI detection circuit 340 can receive decoded information about the decoded instruction 108D to detect the decoded PDI 108D. For example, the PDI detection circuit 340 may be configured to detect the PDI 108D after it is decoded in the instruction decode circuit 120. The PDI detection circuit 340 in the example of FIG. 3 may be configured to detect the PDI 108D fetched in the instruction pipelines I0-I1 such that the PDI detection circuit 340 can receive decoded information about the decoded instruction 108D to detect the decoded PDI 108D. N In an in-order stage, the instruction pipelines I0 to I1 are connected between the instruction decode circuit 120 and the rename circuit 122. N The PDI detection circuit 340 in this example is coupled to the instruction pipelines I0 to I N10D, so that if the decoded instruction 108D is detected as a PDI 108D, the PDI detection circuit 340 detects the instruction pipeline I0-I10D that is known to follow the detected PDI 108D in the program code from which the instruction stream 114 was fetched. N The instruction 108B may be configured to capture subsequent decoded instructions 108D in the instruction 108B.

[0037] There are different ways in which the PDI detection circuit 340 can detect whether the fetched instruction 108F or the decoded instruction 108D is a PDI. In one example, if the decoded instruction 108D is a branch instruction with a branch behavior resolved at execution time, such as a conditional branch instruction, an indirect branch instruction, or a conditional indirect branch instruction, the PDI detection circuit 340 can be configured to use the branch predictor confidence 354 updated by the control flow prediction circuit 118. The branch predictor confidence 354 is an indicator of the confidence that the branch behavior of the branch instruction can be accurately predicted. The control flow prediction circuit 118 may be configured to predict the branch behavior of the branch instruction 108D and update the branch predictor confidence 354 based on whether the predicted branch behavior matches the branch behavior resolution determined by the execution circuit 116 when the branch instruction 108D was previously executed in the past. In this way, the PDI detection circuit 340 can use the branch predictor confidence 354 to predict or determine whether the branch instruction 108D is a PDI. A branch instruction 108D with low branch predictor confidence 354 is more likely to be mispredicted and therefore more likely to cause a hazard when executed in the execution circuitry 116 causing a flush event 138.

[0038] The PDI detection circuit 340 may also be configured to determine whether a memory operation instruction 108D, such as a load instruction, is a PDI. The memory operation instruction 108D includes performing a memory operation at a specified memory address, which may be a direct or indirect memory address. The execution circuit 116 may be configured to store a PDI indicator corresponding to the memory operation instruction 108D when the memory operation instruction 108D is executed and a hazard occurs, causing a flush event 138 to occur. The execution circuit 116 may be configured to store the PDI indicator in a PDI indicator circuit 358 that includes multiple PDI indicator entries 360(0) through 360(I). In the PDI indicator entries, PDI indicators may be stored corresponding to the memory operation instructions. When the PDI detection circuit 340 receives a memory operation instruction 108D for determining whether it is a PDI, the PDI detection circuit 340 can refer to the PDI indicator circuit 358 to determine whether a PDI indicator is present in the PDI indicator entries 360(0)-360(I) for that memory operation instruction 108D. The PDI detection circuit 340 can use the PDI indicator to determine whether the corresponding memory operation instruction 108D should be considered a PDI for PDI detection purposes.

[0039] Continuing to refer to FIG. 3, the PDI detection circuit 340 detects the instruction pipelines I0 to I N In response to detecting the received instruction 108D in the pipeline 100 as a PDI, the PDI detection circuit 340 N The fetched PDI 108D in the instruction pipeline I0-I108D and / or any subsequent, younger fetched instructions following the PDI 108D instruction are configured to be captured in the pipeline fetch refill circuit 344. As explained below, this allows the instruction fetch recycle circuit 342 to obtain these fetched instructions 108D and reclaim them from the instruction pipelines I0-I108D in response to a flush event 138 generated by the subsequent execution of the detected PDI 108D. NThe pipeline fetch refill circuit 344 may be a memory table circuit that includes a plurality of fetch refill entries 346(0) through 346(R), each configured to store information about a detected PDI 108D and a subsequent, younger fetched instruction 108D. A more detailed example of the pipeline fetch refill circuit 344 of FIG. 3 is shown in FIG. 4 and described below.

[0040] FIG. 4 shows the instruction pipelines I0 to I1 in the processor 302 of FIG. N 3 configured to store captured fetched PDIs 108D and their fetched younger instructions present in the pipeline fetch refill circuit 344. The pipeline fetch refill circuit 344 includes a plurality of fetch refill entries 346(0) through 346(R), each of which is configured to be assigned to store a PDI 108D detected by the PDI detection circuit 340 for later reuse by the instruction fetch reuse circuit 342. The pipeline fetch refill circuit 344 will be described in connection with discussing an example operation of the PDI detection circuit 340 of FIG.

[0041] In this regard, as explained above, the PDI detection circuit 340 detects the instruction pipelines I0 to I1 NWhen detecting a received decoded instruction 108D being processed in as a PDI, the PDI detection circuit 340 may first determine whether a fetch refill entry 346(0)-346(R) in the pipeline fetch refill circuit 344 is already allocated to store the PDI 108D. If so, there is no need to reallocate another fetch refill entry 346(0)-346(R) for the detected PDI 108D. In this example, to determine whether fetch refill entries 346(0)-346(R) in pipeline fetch refill circuitry 344 are already allocated and store PDI 108D, PDI detection circuitry 340 is configured to determine whether source identification 350 of the detected instruction in FIG. 3 (i.e., PDI 108D and / or its younger, successor instruction 108D) matches source identification 362(0)-362(R) in respective refill tags 352(0)-352(R) in fetch refill entries 346(0)-346(R) in pipeline fetch refill circuitry 344. Source identification 350 of detected instruction 108D may be a program counter (PC) of detected instruction 108D, which uniquely identifies its presence in the program code from which the detected instruction was fetched into instruction stream 114 of instruction processing circuitry 304. If the source identification 350 of the detected instruction 108D is included in the source identification 362(0)-362(R) in the respective refill tags 352(0)-352(R) of the fetch refill entries 346(0)-346(R) in the pipeline fetch refill circuit 344, this means that the PDI 108D and / or its subsequent, younger instruction 108D are already stored in the fetch refill entries 346(0)-346(R) that contained the respective refill tags 352(0)-352(R) with matching source identification 362(0)-362(R). The PDI detection circuit 340 need not further process the detected instruction 108D.

[0042] However, if the source identification information 350 of the detected instruction 108D is not included in the source identification information 362(0)-362(R) in the respective refill tags 352(0)-352(R) of fetch refill entries 346(0)-346(R) in the pipeline fetch refill circuit 344, the PDI detection circuit 340 is configured to process the detected PDI 108D. The PDI detection circuit 340 is configured to allocate an available fetch refill entry 346(0)-346(R) in the pipeline fetch refill circuit 344 for storing the source identification information 350 of the detected instruction 108D for later identification by the instruction fetch reclaim circuit 342, which is described in more detail below. The PDI detection circuit 340 is also configured to store the source identification 350 of the detected instruction 108D in source identification 362(0)-362(R) in an assigned fetch refill entry 346(0)-346(R) in the pipeline fetch refill circuit 344. If the detected PDI 108D is a branch instruction with a branch instruction flow path that can be predicted but is not resolved until execution in the execution circuit 116, the PDI detection circuit 340 stores the source identification 350 of the detected instruction 108D in the source identification 362(0)-362(R) in the instruction pipelines I0-I1. N The instruction fetch refill circuit 342 may also be configured to store the refill path 364 of the branch instruction 108D received from the pipeline fetch refill circuit 344 (e.g., taken or not taken for a conditional branch instruction) in a refill path 366(0)-366(R) within each assigned fetch refill path 346(0)-346(R) within the pipeline fetch refill circuit 344. This allows the instruction fetch recycle circuit 342 to know whether the captured successor instruction 108D in the pipeline fetch refill circuit 344 for the branch instruction 108E that caused the flush event 138 should be reused as being in the correct instruction flow path from the branch instruction 108E.

[0043] 3 is then configured to set the valid indicator 368(0)-368(R) for the corresponding assigned fetch refill entry 346(0)-346(R) in the pipeline fetch refill circuit 344 of FIG. 4 to a valid state, so that the instruction fetch refill circuit 342 knows it is valid to reference the matching fetch refill entry 346(0)-346(R) to reuse the previously fetched, captured instruction 108D in the fetch refill entry 346(0)-346(R) that corresponds to the PDI 108E that caused the flush event 138. The PDI detection circuit 340 then selects the instruction pipeline I0-I1 following the detected PDI 108D for later possible reuse. N 4 in assigned fetch refill entries 346(0)-346(R) in the pipeline fetch refill circuit 344. In this regard, the PDI detection circuit 340 is configured to store received subsequent subsequent younger instructions 108D following the detected PDI 108D as captured instructions 372(1)-372(X) in the assigned fetch refill entries 346(0)-346(R). For example, fetch refill entry 346(0) may be configured to store up to "X" subsequent subsequent younger instructions 108D as captured instructions 372(0)(1)-372(0)(X). The PDI detection circuit 340 also detects the presence of instructions in instruction pipelines I0-I1 that are reused by the instruction fetch refill circuit 342. NThe fetch refill entry 346(0) is configured to capture metadata 374(1)-374(X) for each captured instruction 372(1)-372(X) following the detected PDI 108D as information that can be used to aid in processing the captured instruction 372(1)-372(X) if the instruction is re-injected into the PDI 108D. For example, the fetch refill entry 346(0) may store up to "X" pieces of metadata for the "X" captured instructions 108D as metadata 374(0)(1)-374(0)(X). The metadata 374(1)-374(X) may be used to re-inject the corresponding captured instruction 372(1)-372(X) into a certain instruction pipeline I0-I1 when the corresponding captured instruction 372(1)-372(X) is later reused in response to its corresponding PDI 108E causing a flush event 138. N For example, the direction of a conditional branch within captured instructions 372(1)-372(X) may be stored as metadata 374(1)-374(X).

[0044] The PDI detection circuit 340 is also configured to store a fall-through source address (e.g., PC) 370(0)-370(X) in each assigned fetch refill entry 346(0)-346(R). This enables the instruction fetch reuse circuit 342 to use such information to inform the instruction fetch circuit 106 of FIG. 3 where to begin fetching a new instruction 108 in response to the reuse of a captured instruction 372(1)-372(X) for the PDI 108D whose execution caused the flush event 138. In this regard, the PDI detection circuit 340 may be configured to store the PC following the captured, most recently captured instruction 372(0)-372(X) in each fetch refill entry 346(0)-346(R) for the detected PDI 108D in each fall-through source address 370(0)-370(R). As one example, the PDI detection circuit 340 can be configured to stop capturing subsequent, subsequent, younger instructions 108D after the detected PDI 108D in the captured instructions 372(0)-372(X) in the fetch refill entries 346(0)-346(R) for the detected PDI 108D when the PDI detection circuit 340 encounters the next PDI 108D in the instruction stream 114. As another example, the PDI detection circuit 340 can be configured to stop capturing subsequent, subsequent, younger instructions 108D after the detected PDI 108D in the captured instructions 372(0)-372(X) in the fetch refill entries 346(0)-346(R) for the detected PDI 108D once the pipeline fetch refill circuit 344 is full. Or, as another example, the PDI detection circuitry 340 can be configured to stop capturing subsequent, subsequent, younger instructions 108D when the next PDI 108D is encountered or when the pipeline fetch refill circuitry 344 is full, whichever occurs first.

[0045] Each fetch refill entry 346(0)-346(R) in the pipeline fetch refill circuit 344 of FIG. 4 may also be configured to store a respective useful indicator 376(0)-376(X). As discussed in more detail below, the useful indicators 376(0)-376(X) are configured to store a usefulness indicating how useful the fetch refill entry 346(0)-346(R) is. The usefulness stored in the useful indicator 376(0)-376(X) is an indication of how likely the PDI 108D associated with the respective fetch refill entry 346(0)-346(R) is to be used by the instruction fetch reclaim circuit 342 to reuse the fetched instruction 108D captured in the fetch refill entry 346(0)-346(R). The usefulness may be a count value, and the useful indicators 376(0)-376(X) may be counters, as an example. Useful indicators 376(0)-376(X) allow a separate process to update and monitor the usefulness stored in useful indicators 376(0)-376(X) as a way to control the deallocation of fetch refill entries 346(0)-346(R) to make room for future detected PDIs 108D and their associated successor instructions 108D to be captured for later reuse.

[0046] 3 , as described above, the instruction fetch reclaim circuit 342 is configured to reclaim a previously captured instruction 108D in captured instructions 372(0)-372(X) in fetch refill entries 346(0)-346(R) in the pipeline fetch refill circuit 344 that corresponds to the executed PDI 108E whose execution caused the flush event 138. In this regard, in response to the flush event 138, the instruction fetch reclaim circuit 342 is configured to determine a source identification 378 of the previously captured detected instruction (i.e., the PDI 108D and / or its younger successor instruction 108D). For example, the source identification 378 of the detected instruction 108D may be the PC of the PDI 108D. The instruction fetch reclaim circuit 342 can be configured to determine whether the source identification 378 of the detected instruction 108D matches (i.e., hits) the source identification 362(0)-326(R) in the corresponding refill tag 352(0)-352(R) in the corresponding fetch refill entry 346(0)-346(R) in the pipeline fetch refill circuit 344. If so, the instruction fetch reclaim circuit 342 accesses the captured instructions 372(1)-372(X) in the fetch refill entry 346(0)-346(R) that have source identification 362(0)-326(R) that matches the source identification 378 of the detected instruction 108D, and sends those captured instructions 372(1)-372(X) to the instruction pipelines I0-I1 for processing. N In this way, the captured instructions 372(1)-372(X) do not need to be re-fetched by the instruction fetch circuitry 106. The instruction fetch reuse circuitry 342 can be configured to inject the captured instructions 372(1)-372(X) into the instruction pipelines I0-I1 after the instruction decode circuitry 120, for example, into the rename circuitry 122 or the instruction pipelines I0-I1. NThe instruction fetch refill entries 346(0) through 346(R) can be re-used and injected into a later stage in the instruction pipelines I0 through I1, e.g., into the execution circuitry 116. The instruction fetch re-use circuitry 342 is also configured to provide the fall-through source addresses 370(0) through 370(X) of the matching fetch re-fill entries 346(0) through 346(R) to the instruction fetch circuitry 106. The instruction fetch circuitry 106 re-uses the fall-through source addresses 370(0) through 370(X) of the matching fetch re-fill entries 346(0) through 346(R) to the instruction pipelines I0 through I1. N To avoid refetching the same instruction 108 as the captured instruction 372(1) through 372(X) that was injected into the instruction 108, the instruction 108 can be fetched starting from the fall-through source address 370(0) through 370(X).

[0047] However, if the instruction fetch reclamation circuit 342 determines that the source identification 378 of the detected instruction 108D, whose execution caused the flush event 138, does not match (i.e., misses) the source identification 362(0)-362(R) in the corresponding refill tag 352(0)-352(R) in the corresponding fetch refill entry 346(0)-346(R) in the pipeline fetch reclamation circuit 344, the instruction fetch reclamation circuit 342 may ignore the detected instruction 108D. The instruction fetch circuit 106 refetches the PDI 108D and / or its successor instruction 108D. The instruction fetch reclamation circuit 342 may be configured to provide the fall-through source address 370 to the instruction fetch circuit 106 as the PC of the PDI 108E such that the instruction fetch circuit 106 refetches the PDI 108E and its successor instruction 108D.

[0048] The instruction fetch refill circuit 342 may also be configured to verify that a refill path 366(0)-366(R) in a refill tag 352(0)-352(R) in a corresponding fetch refill entry 346(0)-346(R) in the pipeline fetch refill circuit 344 has a source identification 362(0)-362(R) that matches the source identification 378 of the PDI 108D before reusing the corresponding captured instruction 372(1)-372(X). This allows, for example, if the PDI 108D is a branch instruction that can take different instruction flow paths depending on the resolution of its execution, the instruction fetch refill circuit 342 to ensure that the captured instruction 372(1)-372(X) in the matching fetch refill entry 346(0)-346(R) is from the same instruction flow path that was resolved by the execution of the PDI 108D. In this way, the instruction pipelines I0-I108D can be reclaimed. N The reclamation of captured instructions 372(1)-372(X) by instruction fetch reclamation circuit 342 through injection of captured instructions 372(1)-372(X) in is not for an incorrect instruction flow path. If the captured instructions 372(1)-372(X) in the corresponding matching fetch refill entries 346(0)-346(R) are not for a correct instruction flow path according to their recorded refill paths 366(0)-366(R), instruction fetch reclamation circuit 342 may choose not to reclaim those captured instructions 372(1)-372(X) and instead have them refetched by instruction processing circuit 304. In this case, the instruction fetch reuse circuitry 342 can be configured to provide the source identification information 362(0)-362(R) of the executed PDI 108E that caused the flush event 138 to the instruction processing circuitry 304, which then causes the instruction processing circuitry 304 to refetch the PDI 108E and any subsequent instructions 108D.

[0049] As mentioned above, it may be desirable to provide a mechanism for deallocating fetch refill entries 346(0)-346(R) in the pipeline refill circuitry 344 to make room for capturing for potential reuse more recently executed PDIs 108E and their successor instructions 108D that caused the flush event 138. Some fetch refill entries 346(0)-346(R) in the pipeline fetch refill circuitry 344 may be allocated to PDIs 108D and / or younger successor instructions 108D that are less useful (i.e., less likely to occur in the future) than the more recently executed PDIs 108E that caused the flush event 138.

[0050] As described above, the instruction fetch reclaim circuit 342 determines that the source identification 378 of PDI 108D and / or its younger successor instruction 108D is already included in a valid fetch refill entry 346(0)-346(R) (i.e., the source identification 378 matches the source identification 362(0)-362(R)) in the pipeline fetch refill circuit 344. If the source identification 378 of PDI 108D and / or its younger successor instruction 108D is already included in a valid fetch refill entry 346(0)-346(R), the instruction fetch reclaim circuit 342 can be configured to increase the usefulness in the corresponding useful indicator 376(0)-376(X) in the corresponding fetch refill entry 346(0)-346(R). For example, if the useful indicators 376(0)-376(X) are counters, the instruction fetch reclamation circuit 342 may be configured to increment the useful indicators 376(0)-376(X) to indicate increased usefulness, as an example. However, if the source identification information 378 of the executed PDI 108E is not already contained in a valid fetch refill entry 346(0)-346(R) and a new valid fetch refill entry 346(0)-346(R) needs to be allocated, the instruction fetch reclamation circuit 342 may, as an example, equally decrease the usefulness of all useful indicators 376(0)-376(X) in the corresponding fetch refill entry 346(0)-346(R). If the usefulness in the usefulness indicators 376(0)-376(X) of fetch refill entries 346(0)-346(R) in the pipeline fetch refill circuit 344 falls below a configured threshold usefulness, the instruction fetch reclaim circuit 342 or other circuitry can be configured to deallocate such fetch refill entries 346(0)-346(R) to free such fetch refill entries 346(0)-346(R) to be reallocated for new PDI 108E.

[0051] Alternatively, instead of equally reducing the usefulness of all useful indicators 376(0)-376(X) in the corresponding fetch refill entries 346(0)-346(R) immediately in response to a miss to the pipeline fetch refill circuit 344, the global allocation failure indicator 380 of FIG. 3 can be incremented or increased if the source identification information 378 of the detected instruction 108D (i.e., PDI 108D and / or its younger, successor instruction 108D) is not already included in a valid fetch refill entry 346(0)-346(R). The usefulness of the useful indicators 376(0)-376(X) in each fetch refill entry 346(0)-346(R) can then be reduced once the global allocation failure indicator 380 exceeds a threshold global allocation. This mechanism controls the rate at which the usefulness of the useful indicator 376(0)-376(X) in each fetch refill entry 346(0)-346(R) decays for each miss event in response to the pipeline fetch refill circuit 344. Again, if the usefulness of the useful indicator 376(0)-376(X) of a fetch refill entry 346(0)-346(R) in the pipeline fetch refill circuit 344 falls below a configured threshold usefulness, the instruction fetch reclamation circuit 342 or other circuitry can be configured to deallocate such fetch refill entry 346(0)-346(R) and free such fetch refill entry 346(0)-346(R) for reallocation to a new PDI 108D and / or its younger successor instruction 108D.

[0052] As another alternative, the availability indicators 376(0) through 376(X) of the fetch refill entries 346(0) through 346(R) in the pipeline fetch refill circuit 344 are used to determine the availability of the instruction pipelines I0 through I1. NThe usefulness indicators 376(0) through 376(X) of the fetch refill entries 346(0) through 346(R) in the pipeline fetch refill circuit 344 can be decremented for each number of instructions 108D processed within the pipeline fetch refill circuit 344. As another alternative, the usefulness indicators 376(0) through 376(X) of the fetch refill entries 346(0) through 346(R) in the pipeline fetch refill circuit 344 can be decremented for each number of PDIs 108D detected by the PDI detection circuit 340. As another alternative, the usefulness indicators 376(0) through 376(X) of the fetch refill entries 346(0) through 346(R) in the pipeline fetch refill circuit 344 can be decremented for each number of flush events 138.

[0053] FIG. 5 is a block diagram of an exemplary processor-based system 500 including a processor 502 (e.g., a microprocessor) including an instruction processing circuit 504 including a PDI detection circuit 505 and an instruction fetch reuse circuit 506 for detecting a PDI, capturing a fetched instruction that is the PDI and / or a subsequent, younger instruction following the PDI, and reusing the captured instruction in response to a flush event caused by execution of the corresponding PDI. For example, the processor 502 of FIG. 5 may be the processor 102 of FIG. 1 or the processor 302 of FIG. 3. As another example, the instruction processing circuit 504 may be the instruction processing circuit 104 of FIG. 1 or the instruction processing circuit 304 of FIG. 3. As another example, the PDI detection circuit 505 may be the PDI detection circuit 140 of FIG. 1 or the PDI detection circuit 340 of FIG. 3. As another example, the instruction fetch reuse circuit 506 may be the instruction fetch reuse circuit 142 of FIG. 1 or the instruction fetch reuse circuit 342 of FIG. 3.

[0054] The processor-based system 500 may represent one or more circuits contained in an electronic board card, such as a printed circuit board (PCB), server, personal computer, desktop computer, laptop computer, personal digital assistant (PDA), computing pad, mobile device, or any other device, such as a server or a user's computer. In this example, the processor-based system 500 includes a processor 502. The processor 502 represents one or more general-purpose processing circuits, such as a microprocessor, central processing unit, or the like. More specifically, the processor 502 may be an EDGE instruction set microprocessor or other processor implementing an instruction set that supports explicit consumer naming for communicating product values ​​resulting from the execution of producer instructions. The processor 502 is configured to execute processing logic in instructions to perform the operations and steps discussed herein. In this example, the processor 502 includes an instruction cache 508 for temporary, fast-access memory storage of instructions accessible by the instruction processing circuitry 504. Instructions fetched or prefetched from memory, such as from system memory 510 via a system bus 512, are stored in the instruction cache 508. The instruction processing circuitry 504 is configured to process instructions fetched into an instruction cache 508 and prepare the instructions for execution.

[0055] The processor 502 and the system memory 510 are coupled to a system bus 512, which may interconnect peripheral devices included in the processor-based system 500. As is well known, the processor 500 communicates with these other devices by exchanging address, control, and data information over the system bus 512. For example, the processor 502, as an example of a slave device, may communicate bus transaction requests to a memory controller 514 within the system memory 510. Although not shown in FIG. 5, multiple system buses 512 may be provided, with each system bus constituting a different fabric. In this example, the memory controller 514 is configured to provide memory access requests to a memory array 516 within the system memory 510. The memory array 516 comprises an array of storage bit cells for storing data. The system memory 510 may be, by way of non-limiting example, read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM), and static memory (e.g., flash memory, static random access memory (SRAM), etc.).

[0056] Other devices may be connected to the system bus 512. As shown in FIG. 5, these devices may include, by way of example, a system memory 510, one or more input devices 518, one or more output devices 520, a modem 522, and one or more display controllers 524. The input devices 518 may include any type of input device, including, but not limited to, input keys, switches, audio processors, etc. The output devices 520 may include any type of output device, including, but not limited to, audio, video, other visual indicators, etc. The modem 522 may be any device configured to enable the exchange of data with a network 526. The network 526 may be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH™ network, and the Internet. The modem 522 may be configured to support any type of communication protocol desired. The processor 502 may also be configured to access a display controller 524 through the system bus 512 to control information sent to one or more displays 528. The display 528 may include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc.

[0057] 5 may include a set of instructions 530 executed by the processor 502 for any desired application in accordance with the instructions. The instructions 530 may be stored in the system memory 510, the processor 502, and / or the instruction cache 508 as examples of non-transitory computer-readable media 532. The instructions 530 may also reside, completely or at least partially, within the system memory 510 and / or the processor 502 during their execution. The instructions 530 may further be transmitted or received over a network 526 via the modem 522, whereby the network 526 includes the computer-readable medium 532.

[0058] Although the computer-readable medium 532 is shown in the exemplary embodiment to be a single medium, the term "computer-readable medium" should be interpreted to include a single medium or multiple media (e.g., centralized or distributed databases, and / or associated caches and servers) that store the one or more sets of instructions. The term "computer-readable medium" should also be interpreted to include any medium that can store, encode, or carry a set of instructions for execution by a processing device that causes the processing device to perform any one or more of the method embodiments disclosed herein. Thus, the term "computer-readable medium" should be interpreted to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0059] The embodiments disclosed herein include various steps. The steps of the embodiments disclosed herein may be formed by hardware components or embodied by machine-executable instructions that can be used to cause a general-purpose or special-purpose processor programmed with the instructions to perform the steps. Alternatively, the steps may be performed by a combination of hardware and software.

[0060] The embodiments disclosed herein may include a machine-readable medium (or computer-readable medium) having instructions stored thereon, and may be provided as a computer program product or software that can be used to program a computer system (or other electronic device) to perform a process according to the embodiments disclosed herein. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, machine-readable media include: machine-readable storage media (e.g., ROM, random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.), etc.

[0061] Unless otherwise specifically stated, and as is clear from the preceding discussion, discussions throughout this document using terms such as "processing," "computing," "determining," "displaying," and the like are understood to refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data and memory represented as physical (electronic) quantities in the computer system's registers into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage, transmission, or display devices.

[0062] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the required method steps. The required structure for a variety of these systems will be apparent from the above description. Further, the embodiments described herein are not described with reference to any particular programming language. It will be understood that a variety of programming languages ​​may be used to implement the teachings of the embodiments described herein.

[0063] Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits, and algorithms described in connection with the embodiments disclosed herein may be implemented as electronic hardware, instructions stored in memory or other computer-readable medium and executed by a processor or other processing device, or a combination of both. The components of the distributed antenna system described herein may be used in any circuit, hardware component, integrated circuit (IC), or IC chip, by way of example. The memory disclosed herein may be any type and size of memory and may be configured to store any type of desired information. To clearly illustrate this interchangeability, the various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends on the particular application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the embodiments of the present application.

[0064] The various illustrative logic blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed using a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Further, a controller may be a processor. A processor may be a microprocessor, but alternatively, a processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in combination with a DSP core, or any other such configuration).

[0065] The embodiments disclosed herein may be embodied in hardware and instructions stored on the hardware, which may reside in, for example, RAM, flash memory, ROM, electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disk, removable disk, CD-ROM, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. In the alternative, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.

[0066] It should also be noted that the operational steps described in any of the exemplary embodiments herein are described for the purpose of providing examples and discussion. The described operations may be performed in many different sequences other than the sequence shown. Furthermore, an operation described as a single operational step may actually be performed in several different steps. Furthermore, one or more operational steps described in the exemplary embodiments may be combined. Those skilled in the art will also understand that information and signals may be represented using any of a variety of technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields, or particles, light fields or particles, or any combination thereof.

[0067] Unless otherwise expressly stated, it is in no way intended that any method described herein be construed as requiring that its steps be performed in a particular order. Thus, unless a method claim actually recites the order in which its steps should be followed, or unless the claim or specification otherwise expressly states that the steps are to be limited to a particular order, no particular order is intended to be inferred.

[0068] It will be apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit or scope of the present invention. Since modifications, combinations, subcombinations, and variations of the disclosed embodiments that incorporate the spirit and content of the present invention may occur to those skilled in the art, the present invention should be construed as including all within the scope of the appended claims and their equivalents.

[0069] Several aspects will be described. [Aspect 1] 1. A processor having an instruction processing circuit and an instruction fetch reuse circuit, The instruction processing circuitry: an instruction fetch circuit configured to fetch a plurality of instructions from the program code as a plurality of fetched instructions into the instruction pipeline for execution; an execution circuit coupled to the instruction fetch circuit, the execution circuit comprising: executing a fetched instruction of the plurality of fetched instructions in the instruction pipeline; configured to generate a pipeline flush event to flush the instruction pipeline in response to execution of a fetched instruction of the plurality of instructions that includes a hazard-generating performance-degrading instruction (PDI); The instruction fetch reuse circuitry is coupled to the instruction pipeline, and in response to the pipeline flush event, the instruction fetch reuse circuitry: determining whether source identification information of the fetched instruction matches source identification information in a refill tag in the fetch refill entry as a matching fetch refill entry among a plurality of fetch refill entries of the pipeline fetch refill circuit; configured to, in response to source identification information of the fetched instruction matching source identification information in the refill tag in the fetch refill entry, insert one or more captured instructions in the matching fetch refill entry into the instruction pipeline after the instruction fetch circuitry for processing; Processor. [Aspect 2] The instruction processing circuitry further comprises: a decode circuit coupled to the instruction fetch circuit, the decode circuit configured to decode the plurality of fetched instructions into a plurality of decoded instructions; the execution circuitry executes a decoded instruction of the plurality of decoded instructions in the instruction pipeline; In response to source identification information of the fetched instruction matching source identification information in the refill tag in the fetch refill entry of the pipeline fetch refill circuit: configured to insert the one or more captured instructions in the matching fetch refill entry into the instruction pipeline between the decode circuitry and the execution circuitry for processing. 2. The processor of claim 1. Aspect 3 The instruction processing circuitry, in response to source identification information of the fetched instruction matching source identification information in the refill tag in the fetch refill entry: configured to insert the one or more captured instructions in the matching fetch refill entry into the execution circuitry in the instruction pipeline for execution. 2. The processor of claim 1. Aspect 4 The instruction fetch reclamation circuitry responds to the source identification information of the fetched instruction including the PDI matching the source identification information in the refill tag in the fetch refill entry. determining whether an instruction flow path of the PDI matches a refill path in the refill tag of the matching fetch refill entry; In response to the instruction flow path of the PDI matching the refill path in the refill tag of the matching fetch refill entry: configured to insert the one or more captured instructions in the matching fetch refill entry into the instruction pipeline after the instruction fetch circuitry for processing. 2. The processor of claim 1. Aspect 5 The instruction fetch reclamation circuitry, in response to source identification information of the fetched instruction matching source identification information in the refill tag in the fetch refill entry: configured to communicate a fall-through source address in the matching fetch refill entry to the instruction fetch circuitry; the instruction fetch circuitry is configured to, in response to receiving the fall-through source address, fetch instructions beginning at the fall-through source address; 2. The processor of claim 1. Aspect 6 The instruction fetch reclamation circuitry, in response to source identification information of the fetched instruction matching source identification information in the refill tag in the fetch refill entry: and increasing a utility indicator in the matching fetch refill entry in the pipeline fetch refill circuit that indicates the utility of the matching fetch refill entry. 2. The processor of claim 1. Aspect 7 The instruction fetch reuse circuitry also: determining whether a utility indicator for a fetch refill entry of the plurality of fetch refill entries in the pipeline fetch refill circuit is below a threshold utility; further configured to deallocate the fetch refill entry in the pipeline fetch refill circuit in response to the usefulness in the usefulness indicator in the fetch refill entry falling below the threshold usefulness. 7. The processor of embodiment 6. Aspect 8 further comprising a PDI detection circuit coupled to the instruction pipeline; the PDI detection circuitry is configured to detect whether a fetched instruction in the instruction pipeline is a PDI; In response to detecting the fetched instruction as a PDI, the PDI detection circuitry further: allocating an available fetch refill entry from the plurality of fetch refill entries in the pipeline fetch refill circuit; configured to store source identification information of the detected instruction, including either a PDI instruction or a successor instruction, in the refill tag of the available fetch refill entry. 2. The processor of claim 1. Aspect 9 The PDI detection circuitry, in response to the source identification information of the detected instruction not matching the source identification information in a refill tag in a fetch refill entry: configured to capture one or more subsequent instructions following the detected instruction in the instruction pipeline in an allocated available fetch refill entry in the pipeline fetch refill circuit; 9. The processor of claim 8. Aspect 10 the plurality of instructions includes a branch instruction; the instruction fetch circuitry is configured to fetch the branch instruction into the instruction pipeline for execution; the instruction processing circuitry is configured to determine an instruction flow path for the branch instruction; the PDI detection circuit is configured to detect whether a fetched branch instruction in the instruction pipeline is a PDI; The PDI detection circuit, in response to detecting that the fetched branch instruction is a PDI and in response to a source identification information of the detected PDI not matching a source identification information in a refill tag in the fetch refill entry, further: configured to store the instruction flow path of the detected PDI in a refill path of the available fetch refill entry. 9. The processor of claim 8. Aspect 11 The PDI detection circuit, in response to the source identification information of the detected instruction not matching the source identification information in a refill tag in a fetch refill entry, further: determining whether a subsequent instruction of the one or more subsequent instructions is a PDI; In response to determining that the subsequent instruction is a PDI: configured to not capture the subsequent instruction as the one or more subsequent instructions determined to be a PDI in the instruction pipeline in the allocated available fetch refill entry in the pipeline fetch refill circuit. A processor according to embodiment 9. Aspect 12 1. A method of reclaiming fetched and flushed instructions in an instruction pipeline in a processor, comprising: fetching a plurality of instructions from the program code as a plurality of fetched instructions into the instruction pipeline for execution; executing a fetched instruction of the plurality of fetched instructions in the instruction pipeline; generating a pipeline flush event to flush the instruction pipeline in response to execution of a fetched instruction of the plurality of instructions that generates a hazard as a performance degrading instruction (PDI); In response to the pipeline flush event: determining whether source identification information of the detected instruction matches source identification information in a refill tag in a fetch refill entry as a matching fetch refill entry among a plurality of fetch refill entries of the pipeline fetch refill circuit; In response to the source identification information of the detected instruction matching the source identification information in the refill tag in the fetch refill entry: inserting one or more captured instructions in a matching fetch refill entry into the instruction pipeline as fetched instructions to be executed; method. Aspect 13 responsive to the source identification information of the PDI matching the source identification information in the refill tag in the fetch refill entry, determining whether an instruction flow path of a detected instruction including the PDI matches a refill path in the refill tag of the matching fetch refill entry; In response to the instruction flow path of the PDI matching the refill path in the refill tag of the matching fetch refill entry: inserting the one or more captured instructions in the matching fetch refill entry into the instruction pipeline to be processed without refetching the one or more captured instructions. 13. The method of embodiment 12. Aspect 14 Detecting whether a fetched instruction in the instruction pipeline is a PDI; In response to detecting that the fetched instruction is a PDI: allocating an available fetch refill entry from the plurality of fetch refill entries in the pipeline fetch refill circuit; storing source identification information of one or more subsequent instructions following the detected PDI in the refill tag of the allocated available fetch refill entry. 13. The method of embodiment 12. Aspect 15 In response to detecting that the fetched instruction is a PDI: storing source identification information of the detected instruction in the refill tag of the allocated available fetch refill entry. 15. The method of embodiment 14.

Claims

1. 1. A processor having an instruction processing circuit, a performance degrading instruction (PDI) detection circuit, and an instruction fetch reuse circuit, The instruction processing circuitry: an instruction fetch circuit configured to fetch a plurality of instructions from the program code as a plurality of fetched instructions into the instruction pipeline for execution; an execution circuit coupled to the instruction fetch circuit, the execution circuit comprising: Executing a first fetched instruction of the plurality of fetched instructions in the instruction pipeline; configured to generate a pipeline flush event to flush the instruction pipeline in response to execution of the first fetched instruction that generates a hazard; the PDI detection circuit is coupled to the instruction pipeline, and the PDI detection circuit is configured to detect whether a second fetched instruction of the plurality of fetched instructions in the instruction pipeline is a PDI as an instruction determined to cause a hazard and result in a precise interrupt when executed by the execution circuit; In response to detecting the second fetched instruction as a PDI, the PDI detection circuitry further: allocating an available fetch refill entry from among a plurality of fetch refill entries in the pipeline fetch refill circuit; configured to store source identification information of the second fetched instruction, including a PDI and any of the successor instructions, in a refill tag of the available fetch refill entry; The instruction fetch reuse circuit is coupled to the instruction pipeline, and in response to the pipeline flush event, the instruction fetch reuse circuit: determining whether source identification information of a third fetched instruction of the plurality of fetched instructions matches source identification information in a refill tag in a fetch refill entry as a matching fetch refill entry of the plurality of fetch refill entries of the pipeline fetch refill circuit; configured to, in response to source identification information of the third fetched instruction matching source identification information in the refill tag in the fetch refill entry, insert one or more captured instructions in the matching fetch refill entry into the instruction pipeline after the instruction fetch circuitry for processing; Processor.

2. The instruction processing circuitry further comprises: a decode circuit coupled to the instruction fetch circuit, the decode circuit configured to decode the first fetched instruction into a first decoded instruction; the execution circuitry executes the first decoded instruction in the instruction pipeline; configured to generate the pipeline flush event to flush the instruction pipeline in response to execution of the first decoded instruction creating a hazard; In response to source identification information of the third fetched instruction matching source identification information in the refill tag in the fetch refill entry of the pipeline fetch refill circuitry: configured to insert the one or more captured instructions in the matching fetch refill entry into the instruction pipeline between the decode circuitry and the execution circuitry for processing. The processor of claim 1 .

3. The instruction processing circuitry, in response to source identification information of the third fetched instruction matching source identification information in the refill tag in the fetch refill entry: configured to insert the one or more captured instructions in the matching fetch refill entry into the execution circuitry in the instruction pipeline for execution. The processor of claim 1 .

4. The instruction fetch reclamation circuit, in response to the source identification information of the third fetched instruction matching the source identification information in the refill tag in the fetch refill entry: determining whether the third fetched instruction is a PDI; determining whether an instruction flow path of the third fetched instruction matches a refill path in the refill tag of the matching fetch refill entry; In response to the instruction flow path of the third fetched instruction matching the refill path in the refill tag of the matching fetch refill entry and the third fetched instruction being a PDI: configured to insert the one or more captured instructions in the matching fetch refill entry into the instruction pipeline after the instruction fetch circuitry for processing. The processor of claim 1 .

5. The instruction fetch reclamation circuit, in response to source identification information of the third fetched instruction matching source identification information in the refill tag in the fetch refill entry: configured to communicate a fall-through source address in the matching fetch refill entry to the instruction fetch circuitry; the instruction fetch circuitry is configured to, in response to receiving the fall-through source address, fetch instructions beginning at the fall-through source address; The processor of claim 1 .

6. The instruction fetch reclamation circuit, in response to source identification information of the third fetched instruction matching source identification information in the refill tag in the fetch refill entry: and configuring the pipeline fetch refill circuit to increase a utility indicator in the matching fetch refill entry that indicates a utility of the matching fetch refill entry. The processor of claim 1 .

7. The instruction fetch reclamation circuitry is further configured to, in response to a source identification information of the third fetched instruction not matching a source identification information in the refill tag in the fetch refill entry: configured to decrease a usefulness indicator in each of the plurality of fetch refill entries in the pipeline fetch refill circuit; The processor of claim 6.

8. The instruction fetch reuse circuitry further: determining whether a utility in the utility indicator in a second fetch refill entry of the plurality of fetch refill entries in the pipeline fetch refill circuit is below a threshold utility; further configured to deallocate the second fetch refill entry in the pipeline fetch refill circuit in response to a usefulness in the usefulness indicator in the second fetch refill entry falling below the threshold usefulness. The processor of claim 7.

9. the instruction fetch reclaim circuitry further increases a global allocation in a global allocation miss indicator for the pipeline fetch refill circuitry in response to source identification information of the third fetched instruction not matching source identification information in the refill tag in the fetch refill entry; and reducing a usefulness indicator in each fetch refill entry of the plurality of fetch refill entries in the pipeline fetch refill circuit in response to the global allocation in the global allocation failure indicator exceeding a threshold global allocation.

7. The processor of claim 6, configured to:

10. 10. The processor of claim 9, further comprising: in response to a usefulness in a usefulness indicator in a second fetch refill entry of the plurality of fetch refill entries in the pipeline fetch refill circuit falling below a threshold usefulness, deallocating the second fetch refill entry in the pipeline fetch refill circuit.

11. The PDI detection circuit, in response to the source identification information of the third fetched instruction not matching the source identification information in the refill tag in the fetch refill entry: allocating the available fetch refill entry from the plurality of fetch refill entries in the pipeline fetch refill circuit; storing a source identification of the third fetched instruction in the refill tag of the available fetch refill entry; The processor of claim 1 configured to:

12. The PDI detection circuitry is further configured to, in response to the source identification information of the third fetched instruction not matching the source identification information in the refill tag in the fetch refill entry: configured to capture one or more subsequent instructions following the third fetched instruction in the instruction pipeline in an allocated available fetch refill entry in the pipeline fetch refill circuit; The processor of claim 1 .

13. the plurality of instructions includes a branch instruction; the instruction fetch circuitry is configured to fetch the branch instruction into the instruction pipeline for execution; the instruction processing circuitry is configured to determine an instruction flow path for the branch instruction; the PDI detection circuitry is configured to detect whether a fetched branch instruction in the instruction pipeline is a PDI; The PDI detection circuit, in response to detecting that the fetched branch instruction is a PDI and in response to a source identification information of the fetched branch instruction detected as a PDI not matching a source identification information in a refill tag in a fetch refill entry, further: configured to store the instruction flow path of the detected PDI, which is the fetched branch instruction, into a refill path of the available fetch refill entry; The processor of claim 12.

14. The PDI detection circuit, in response to the source identification information of the third fetched instruction not matching the source identification information in the refill tag in the fetch refill entry, further: determining whether a subsequent instruction of the one or more subsequent instructions is a PDI; In response to determining that the subsequent instruction is a PDI: configured to not capture the subsequent instruction as the one or more subsequent instructions determined to be a PDI in the instruction pipeline in the allocated available fetch refill entry in the pipeline fetch refill circuit. The processor of claim 12.

15. In response to determining that the subsequent instruction is a PDI, the PDI detection circuit:

15. The processor of claim 14, further configured to store source identification information of the subsequent instruction determined to be a PDI as a fall-through source address in an allocated fetch refill entry in the pipeline fetch refill circuitry.

16. The PDI detection circuit, in response to the source identification information of the third fetched instruction not matching the source identification information in the refill tag in the fetch refill entry, further: determining whether the pipeline fetch refill circuit is full; In response to determining that the pipeline fetch refill circuit is full: configured to not capture a subsequent instruction of the one or more subsequent instructions in the instruction pipeline in the allocated available fetch refill entry in the pipeline fetch refill circuitry. The processor of claim 13.

17. The PDI detection circuit: configured to store an identification of the subsequent instruction of the one or more subsequent instructions that has not been captured in the allocated available fetch refill entry in the pipeline fetch refill circuit as a fall-through source address in the allocated available fetch refill entry in the pipeline fetch refill circuit; 17. The processor of claim 16.

18. The PDI detection circuit, in response to the source identification information of the third fetched instruction not matching the source identification information in the refill tag in the fetch refill entry, further: configured to increase a global allocation in a global allocation miss indicator for the pipeline fetch refill circuit; The instruction processing circuitry further comprises: determining whether the global allocation in the global allocation failure indicator exceeds a threshold global allocation; responsive to the global allocation in the global allocation failure indicator exceeding a threshold global allocation, decreasing a usefulness indicator in each fetch refill entry of the plurality of fetch refill entries in the pipeline fetch refill circuit; determining whether a utility in the utility indicator in a second fetch refill entry of the plurality of fetch refill entries in the pipeline fetch refill circuit is below a threshold utility; deallocating the second fetch refill entry in the pipeline fetch refill circuit in response to a utility in the utility indicator of the second fetch refill entry of the plurality of fetch refill entries in the pipeline fetch refill circuit falling below the threshold utility. It is configured as follows: The processor of claim 1 .

19. the plurality of instructions includes a branch instruction having a branch behavior; the instruction fetch circuitry is configured to fetch the branch instruction into the instruction pipeline for execution as a fetched branch instruction; the instruction processing circuitry further comprising a control flow prediction circuitry configured to predict the branch behavior of the branch instruction; the execution circuitry is configured to execute the branch instruction to generate a resolved branch behavior for the branch instruction; The instruction processing circuitry further comprises: determining whether the resolved branch behavior of the executed branch instruction matches the predicted branch behavior of the branch instruction; configured to update a branch predictor confidence value corresponding to the branch instruction based on whether the resolved branch behavior matches the predicted branch behavior of the branch instruction; configured to detect whether the branch instruction in the instruction pipeline is a PDI based on the branch predictor confidence of the branch instruction. The processor of claim 1 .

20. the plurality of instructions includes memory operation instructions; the instruction fetch circuitry is configured to fetch the memory operation instruction to the instruction pipeline for execution as a fetched memory operation instruction; the instruction processing circuitry is configured to execute the memory operation instruction at a memory address of the memory operation instruction; the instruction processing circuitry is further configured to store a PDI indicator for the memory operation instruction as a PDI in response to the execution circuitry generating the pipeline flush event to flush the instruction pipeline in response to executing the memory operation instruction; the PDI detection circuit is configured to detect whether the memory operation instruction in the instruction pipeline is a PDI based on the PDI indicator for the memory operation instruction indicating a PDI. The processor of claim 1 .

21. 1. A method of reclaiming fetched and flushed instructions in an instruction pipeline in a processor, comprising: fetching a plurality of instructions from the program code as a plurality of fetched instructions into an instruction pipeline for execution; executing a first fetched instruction of the plurality of fetched instructions in the instruction pipeline; generating a pipeline flush event to flush the instruction pipeline in response to execution of the first fetched instruction generating a hazard; detecting whether a second fetched instruction in the instruction pipeline is a performance degrading instruction (PDI) as an instruction determined to cause a hazard and result in a precise interrupt when executed by execution circuitry; In response to detecting the second fetched instruction as a PDI, the method further includes: allocating an available fetch refill entry from among a plurality of fetch refill entries in the pipeline fetch refill circuit; storing source identification information of the second fetched instruction, including a PDI and any successor instruction, in a refill tag of the available fetch refill entry; In response to the pipeline flush event: determining whether source identification information of a third fetched instruction of the plurality of fetched instructions matches source identification information in a refill tag in a fetch refill entry as a matching fetch refill entry of the plurality of fetch refill entries of the pipeline fetch refill circuit; In response to the source identification information of the third fetched instruction matching the source identification information in the refill tag in the fetch refill entry: inserting one or more captured instructions in a matching fetch refill entry into the instruction pipeline as fetched instructions to be executed; method.

22. In response to the source identification information of the third fetched instruction matching the source identification information in the refill tag in the fetch refill entry, the method further comprises: determining whether the third fetched instruction is a PDI; determining whether an instruction flow path of the third fetched instruction matches a refill path in the refill tag of the matching fetch refill entry; In response to the instruction flow path of the third fetched instruction matching the refill path in the refill tag of the matching fetch refill entry and the third fetched instruction being a PDI: inserting the one or more captured instructions in the matching fetch refill entry into the instruction pipeline for processing.

22. The method of claim 21.

23. detecting whether the third fetched instruction in the instruction pipeline is a PDI; In response to detecting that the third fetched instruction is a PDI: allocating a second available fetch refill entry of the plurality of fetch refill entries in the pipeline fetch refill circuit; and storing source identification information of one or more subsequent instructions following the detected PDI that is the third fetched instruction in the refill tag of the allocated second available fetch refill entry.

22. The method of claim 21.

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