Semiconductor device

Abstract

An object is to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limitation on the number of times of writing.SOLUTION: The first transistor 160 includes a channel formation region 116, a first gate insulating layer 108, a first gate 110, and first source and drain electrodes 130a and 130b, and the second transistor 162 includes an oxide-semiconductor layer 140, second source and drain electrodes 142a and 142b, a second gate insulating layer 146, and a second gate electrode 148a. A capacitor 164 including a second gate insulating layer and an electrode 148b overlapping with one of the second source electrode and the second drain electrode over the second gate insulating layer, in which the first gate electrode and the one of the second source electrode and the second drain electrode are electrically connected to each other.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The disclosed invention relates to a semiconductor device using a semiconductor element and a manufacturing method thereof. do. [Background technology]

[0002] Memory devices that use semiconductor elements are volatile, meaning that the stored contents are lost when the power supply is cut off. and non-volatile memory, which retains its contents even when the power supply is cut off. .

[0003] A typical example of a volatile memory device is a DRAM (Dynamic Random Access Memory). DRAM is a memory element that can be selected from transistors. By storing charge in the capacitor, information is stored.

[0004] Based on the above principle, in DRAM, when information is read, the charge in the capacitor is lost. Therefore, every time data is read, a write operation is required again. The transistors that make up the transistors have leakage current, and when the transistors are not selected, Therefore, the data retention period is short. A write operation (refresh operation) is required, and power consumption must be reduced sufficiently. Furthermore, if the power supply is cut off, the memory contents are lost, making it difficult to store long-term memories. To store the data, a separate storage device using magnetic or optical materials is required.

[0005] Another example of a volatile memory device is SRAM (Static Random Access Memory). SRAM uses circuits such as flip-flops to store the memory contents. In order to retain data, no refresh operation is required, which is an advantage over DRAM. However, because it uses circuits such as flip-flops, the cost per unit of memory capacity is high. In addition, there is a problem that the memory contents are lost when the power supply is cut off. In this regard, it is no different from DRAM.

[0006] A typical example of a nonvolatile memory device is flash memory. A floating gate is provided between the gate electrode of the transistor and the channel forming region, Since memory is stored by holding an electric charge in the floating gate, the data retention period is extremely long. The advantage is that it lasts for a very long time (semi-permanent) and does not require the refresh operations required for volatile storage devices. The point is as follows (see, for example, Patent Document 1).

[0007] However, the gate insulating layer that constitutes the memory element is damaged by the tunnel current that occurs during writing. This causes a problem in that the memory element will stop functioning after a certain number of writes. To mitigate the effect of this problem, for example, the number of writes to each memory element is made uniform. However, to achieve this, complex peripheral circuits are required. However, even if such a method is adopted, the fundamental problem of lifespan will not be resolved. Therefore, flash memory is not suitable for applications where information needs to be rewritten frequently.

[0008] In order to retain or remove charge on the floating gate, High voltage is required, and a circuit for that is also required. It takes a relatively long time to erase, and it is not easy to speed up writing and erasing. There are also problems. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Publication No. 57-105889 Summary of the Invention [Problem to be solved by the invention]

[0010] In view of the above-mentioned problems, one embodiment of the disclosed invention provides a method for storing stored contents even when power is not supplied. To provide a semiconductor device having a new structure that can retain data and has no limit on the number of times it can be written. This is one of the purposes of the organization. [Means for solving the problem]

[0011] In the disclosed invention, a semiconductor device is formed using a highly purified oxide semiconductor. Since transistors using oxide semiconductors with SiO2 have extremely low leakage current, , it is possible to retain information for a long period of time.

[0012] One embodiment of the disclosed invention is a method for forming a channel formation region and a semiconductor device including a semiconductor layer and a semiconductor layer that is provided to sandwich the channel formation region. a first gate insulating layer provided on the channel forming region; a first gate electrode provided on the insulating layer; and a first source electrically connected to the impurity region. a first transistor including a first electrode and a first drain electrode; an oxide semiconductor layer; and a second source electrode and a second drain electrode electrically connected to the oxide semiconductor layer; a second gate electrode provided to cover the conductor layer, the second source electrode, and the second drain electrode; a second gate insulating layer provided over the second gate insulating layer so as to overlap with the oxide semiconductor layer; a second transistor having a gate electrode of the second transistor and a second source electrode or a second drain electrode of the second transistor; a second gate insulating layer; and a second source electrode or a capacitor element having an electrode provided so as to overlap with one of the first and second drain electrodes; and the first gate electrode is electrically connected to one of the second source electrode and the second drain electrode. It is a semiconductor device that is electrically connected.

[0013] In addition, one embodiment of the disclosed invention is a method for manufacturing a semiconductor device, comprising: forming a channel formation region and a pair of semiconductor layers that are provided to sandwich the channel formation region; a first gate insulating layer provided on the channel forming region; a first gate electrode provided on the gate insulating layer; and a first gate electrode electrically connected to the impurity region. a first transistor having a source electrode and a first drain electrode; and an oxide semiconductor layer a second source electrode and a second drain electrode electrically connected to the oxide semiconductor layer; an insulating layer in contact with the second source electrode and the second drain electrode; an oxide semiconductor layer; a second gate insulating layer provided to cover the source electrode, the second drain electrode, and the insulating layer; a second gate electrode provided on the second gate insulating layer so as to overlap with the oxide semiconductor layer; a second transistor having a second source electrode or a second drain electrode; On the other hand, a second gate insulating layer and a second source electrode or a second drain electrode are formed on the second gate insulating layer. a capacitance element having an electrode provided so as to overlap one of the drain electrodes, The first gate electrode is electrically connected to either the second source electrode or the second drain electrode. It is a semiconductor device.

[0014] In the above, the oxide semiconductor layer is formed on the side surfaces of the second source electrode and the second drain electrode or In the above, the second transistor and the The capacitor element is preferably provided above the first transistor.

[0015] In this specification, the terms "above" and "below" refer to the positional relationship of a component "directly above" or "below." For example, the term "gate electrode on a gate insulating layer" does not necessarily mean "directly below." " excludes those that include other components between the gate insulating layer and the gate electrode. Furthermore, the terms "upper" and "lower" are merely used for the convenience of explanation and are not to be specifically mentioned. Except in certain cases, this also includes cases where the top and bottom are reversed.

[0016] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring." Furthermore, the terms "electrode" and "wiring" are used interchangeably to refer to the plural "electrodes" and "wirings." This also includes cases where the "line" is formed as a single unit.

[0017] Also, the functions of "source" and "drain" may differ depending on whether transistors with different polarities are used or not. However, they may be swapped when the direction of current changes during circuit operation. In this specification, the terms "source" and "drain" can be used interchangeably. It shall be possible.

[0018] In this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a " is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between connected objects.

[0019] For example, "things that have some kind of electrical action" include electrodes, wiring, and transistors. These include switching elements, resistor elements, inductors, capacitors, and other various functions. This includes elements such as [Effects of the Invention]

[0020] In one embodiment of the present invention, a transistor including a material other than an oxide semiconductor and a transistor including an oxide semiconductor are provided. A semiconductor device using the stacked structure of transistors is provided.

[0021] Since a transistor using an oxide semiconductor has an extremely small off-state current, It is possible to retain the memory contents for a much longer period of time. This eliminates the need for refresh operations or makes it possible to reduce the frequency of refresh operations to an extremely low level. Therefore, power consumption can be reduced sufficiently. , it is possible to retain the stored contents for a long period of time.

[0022] Furthermore, high voltage is not required to write information, and there is no problem of element degradation. Unlike non-volatile memory, there is no need to inject or extract electrons from the floating gate. In other words, the semiconductor device according to this embodiment does not suffer from the problem of deterioration of the gate insulating layer. There is no limit to the number of times it can be rewritten, which is a problem with conventional non-volatile memory, and it is highly reliable. Furthermore, the on / off state of the transistor determines the writing of information. Since the data is erased, high-speed operation can be easily realized. It also has the advantage of not being necessary.

[0023] In addition, transistors using materials other than oxide semiconductors can operate at sufficiently high speeds. By using this, it is possible to read out the stored contents at high speed.

[0024] In this way, transistors using materials other than oxide semiconductors and transistors using oxide semiconductors By integrating a transistor, a semiconductor device with unprecedented features can be realized. It is possible. [Brief explanation of the drawings]

[0025] [Figure 1] Cross-sectional and plan views of a semiconductor device [Figure 2] Cross-sectional view of a semiconductor device [Figure 3] Circuit diagram of semiconductor device [Figure 4] Cross-sectional views relating to a manufacturing process of a semiconductor device [Figure 5] Cross-sectional views relating to a manufacturing process of a semiconductor device [Figure 6] Cross-sectional and plan views of a semiconductor device [Figure 7] Cross-sectional views relating to a manufacturing process of a semiconductor device [Figure 8] Circuit diagram of semiconductor device [Figure 9] Cross-sectional and plan views of a semiconductor device [Figure 10] Cross-sectional view of a semiconductor device [Figure 11] Cross-sectional views relating to a manufacturing process of a semiconductor device [Figure 12] Cross-sectional views relating to a manufacturing process of a semiconductor device [Figure 13] Cross-sectional views relating to a manufacturing process of a semiconductor device [Figure 14] FIG. 1 is a perspective view illustrating an electronic device; [Figure 15] Figure showing the results of the memory window width survey DETAILED DESCRIPTION OF THE INVENTION

[0026] The embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description. The present invention is not limited to the above and may be modified in various forms and details without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be achieved by the following embodiments. It should not be construed as being limited to the contents described.

[0027] In addition, the position, size, range, etc. of each component shown in the drawings are not necessarily the same as those in the actual embodiment for ease of understanding. Therefore, the disclosed invention may not necessarily represent the actual position, size, range, etc. The position, size, range, etc. are not necessarily limited to those disclosed in the drawings, etc.

[0028] In this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of components. It should be noted that the numbers are added to avoid confusion and are not intended to limit the number.

[0029] (Embodiment 1) In this embodiment, a structure and a manufacturing method of a semiconductor device according to one embodiment of the disclosed invention will be described. 1 to 5. Note that in the circuit diagrams, To indicate that it is a transistor, the symbol OS may also be added.

[0030] <Planar and cross-sectional configurations of semiconductor device> FIG. 1 shows an example of the configuration of a semiconductor device. FIG. 1(A) shows a cross section of the semiconductor device, and FIG. 1B) shows a plan view of the semiconductor device. Here, FIG. 1A shows the A of FIG. 1B. These correspond to the cross sections at 1-A2 and B1-B2. The semiconductor device has a transistor 160 made of a material other than an oxide semiconductor in the lower part. 162 and a capacitor 164 using an oxide semiconductor. The transistor 160 and the transistor 162 are both n-channel transistors. Although the description will be given assuming that the transistor is a p-channel transistor, a p-channel transistor can also be used. Furthermore, the technical essence of the disclosed invention is that it uses an acid to retain information. The point is that a nitride semiconductor is used for the transistor 162, so the specific configuration of the semiconductor device will be described below. There is no need to be limited to what is shown here.

[0031] The transistor 160 is provided on a substrate 100 that includes a semiconductor material (e.g., silicon). The channel forming region 116 is formed by doping the impurity ions 116. Region 114 and high concentration impurity region 120 (collectively referred to as impurity region) a gate insulating layer 108 provided on the channel forming region 116; A gate electrode 110 is provided on the surface of the semiconductor substrate 100, and a source electrode or drain electrode is electrically connected to the impurity region. It has a drain electrode 130a and a source or drain electrode 130b.

[0032] Here, a sidewall insulating layer 118 is provided on the side surface of the gate electrode 110. In addition, in the region of the substrate 100 that does not overlap with the sidewall insulating layer 118 in a plan view, a high A high concentration impurity region 120 is provided, and a metal compound region 124 is provided in contact with the high concentration impurity region 120. In addition, an element isolation insulating layer 10 is formed on the substrate 100 so as to surround the transistor 160. 6 is provided, and the interlayer insulating layer 126 and the interlayer insulating layer 128 are provided to cover the transistor 160. An insulating layer 128 is provided. A source or drain electrode 130a and a source electrode The source or drain electrode 130b is formed on the interlayer insulating layer 126 and the interlayer insulating layer 128. The source electrode is electrically connected to the metal compound region 124 through the opening. The source or drain electrode 130a and the source or drain electrode 130b are metallized. Electrically connected to the high concentration impurity region 120 and the impurity region 114 through the compound region 124 The electrode 130c is formed on the interlayer insulating layer 126 and the interlayer insulating layer 128. The gate electrode 110 is electrically connected to the transistor 1 through the opening. In some cases, the sidewall insulating layer 118 is not formed due to the integration of 60 or the like.

[0033] The transistor 162 has a source or drain electrode 14 disposed on the insulating layer 138. 2a, and a source or drain electrode 142b, and a source or drain electrode 142a, and an oxide electrically connected to the source electrode or drain electrode 142b. The semiconductor layer 140, the source electrode or drain electrode 142a, and the source electrode or The drain electrode 142b, the insulating layer 144 in contact with the oxide semiconductor layer 140, and the source electrode The drain electrode 142a, the source or drain electrode 142b, and the oxide semiconductor layer 14 0, a gate insulating layer 146 covering the insulating layer 144, and an oxide semiconductor layer on the gate insulating layer 146 and a gate electrode 148a provided so as to overlap with the insulating layer 140. 44 is provided to reduce the capacitance caused by the gate electrode 148a etc. In order to simplify the process, the insulating layer 144 may not be provided.

[0034] As described above, the transistor 162 shown in FIG. 1 is a top-gate type, and The connection between the oxide semiconductor layer 140 and the source electrode or the drain electrode 142a or the like is Since the process is performed in the region including the lower surface of the conductor layer 140, the top gate and bottom contact This can be called the contact type.

[0035] Here, the oxide semiconductor layer 140 is formed from a material from which impurities such as hydrogen have been sufficiently removed or from which sufficient oxidation has been achieved. It is desirable that the raw material be highly purified by supplying it. For example, the hydrogen concentration in the oxide semiconductor layer 140 is 5×10 19 atoms / cm 3 Below, wish Preferably 5 x 10 18 atoms / cm 3 Less than or equal to 5×10 17 atoms / cm 3 The hydrogen concentration in the oxide semiconductor layer 140 is determined by the secondary ion mass. Secondary Ion Mass Spectroscop (SIMS) In this way, the hydrogen concentration was sufficiently reduced and the product was highly purified. The supply of sufficient oxygen reduces the defect levels in the energy gap caused by oxygen deficiency. In the oxide semiconductor layer 140, the carrier concentration is 1×10 12 / cm 3 Less than, preferably 1 x10 11 / cm 3 Less than 1.45 × 10 10 / cm 3 It is less than. For example, when the channel length is 10 μm and the thickness of the oxide semiconductor layer is 30 nm, When the drain voltage is in the range of about 1V to 10V, the off-state current (the voltage between the gate and source) The drain current when the voltage is 0V or less is 1×10 -13 A or less. Or, at room temperature The off-state current density (off-state current divided by the channel width of the transistor) is 1×10 -20 A / μm (10zA (zeptoamperes) / μm) to 1×10 -19 A / μm(100zA / μm), and the off-resistivity is about 1×10 9 Ω·m or more, preferably 1×10 1 0 In this way, the i-type (intrinsic) or substantially i-type oxide By using a semiconductor, the transistor 162 can have excellent off-state current characteristics. Cut.

[0036] The source or drain electrode 142a is electrically connected to the electrode 130c. That is, the source or drain electrode 142a is connected to the gate electrode of the transistor 160. Similarly, the source electrode or drain electrode 130a is electrically connected to the The electrode 142c is in contact with the source or drain electrode 130b, and the electrode 142d is in contact with the source or drain electrode 130b. , respectively.

[0037] The capacitor 164 includes a source or drain electrode 142a, a gate insulating layer 146, an electrode That is, the source electrode or drain electrode 142a is composed of a capacitance element. The electrode 148b functions as one electrode of the capacitor element 164, and the electrode 148c functions as the other electrode of the capacitor element 164. This will function as follows.

[0038] In addition, a protective insulating layer 150 is provided on the transistor 162 and the capacitor element 164. An interlayer insulating layer 152 is provided on the protective insulating layer 150 .

[0039] <Modifications of Upper Transistor and Capacitor> Next, a modification of the transistor and the capacitor in the upper portion shown in FIG. 1A is shown in FIG.

[0040] The transistor and the capacitor shown in FIG. 2A are the upper transistors of the semiconductor device shown in FIG. 10 is a modified example of the capacitor and the capacitance element.

[0041] The difference between the configuration shown in FIG. 2(A) and the configuration shown in FIG. 1(A) is that the insulating layer 144 is The source or drain electrode 142a and the source or drain electrode 142b are formed on the The oxide semiconductor layer 140 is connected to the insulating layer 144 and the source or drain electrode 14 2a and the source or drain electrode 142b. The oxide semiconductor layer 140 is connected to the source electrode through an opening provided in the insulating layer 144. The gate electrode 142a is provided in contact with the source or drain electrode 142a.

[0042] In the transistor and the capacitor shown in FIG. The ends of the source or drain electrode 142a, the source electrode or drain electrode 142b, and the insulating layer 144 are tapered. Here, the taper angle is, for example, 30° or more and 60° or less. The taper angle is preferably set to a value greater than the taper angle of a layer having a tapered shape (for example, a source the electrode or drain electrode 142a) in a direction perpendicular to its cross section (a plane perpendicular to the surface of the substrate) The angle of inclination between the side and bottom of the layer when observed from the direction of the source electrode or drain electrode. The ends of the source electrode 142a and the source or drain electrode 142b are tapered. This improves the coverage of the oxide semiconductor layer 140 and prevents discontinuities.

[0043] In addition, in the structure illustrated in FIG. 2A, the oxide semiconductor layer 140 is not processed. Therefore, the etching performed after the etching can prevent contamination of the oxide semiconductor layer 140. In addition, in the capacitor element 164, the oxide semiconductor layer 140 and the gate insulating layer 146 are stacked. By this, the insulation between the source electrode or drain electrode 142a and the electrode 148b is This allows for sufficient compatibility.

[0044] The transistor and the capacitor shown in FIG. 2B are the same as those shown in FIG. The configuration is slightly different from that of the previous version.

[0045] The difference between the structure shown in FIG. 2B and the structure shown in FIG. 2A is that the oxide semiconductor layer is formed into an island shape. That is, in the structure shown in FIG. 2A, the oxide semiconductor layer 140 The edge layer 144, the source or drain electrode 142a, and the source or drain electrode In contrast to the structure shown in FIG. 2B, the oxide semiconductor By forming the layer into an island shape, the insulating layer 144, the source electrode or the drain electrode 142a, and The source electrode or the drain electrode 142b is partially covered. The end of the conductor layer 140 is preferably tapered. The taper angle is, for example, 3 It is preferable to set the angle between 0° and 60°.

[0046] In addition, in the capacitor 164, the oxide semiconductor layer 140 and the gate insulating layer 146 are stacked. This improves the insulation between the source or drain electrode 142a and the electrode 148b. can be sufficiently secured.

[0047] The transistor and the capacitor shown in FIG. 2C are the same as those shown in FIG. The configuration is slightly different from that of the previous version.

[0048] The difference between the configuration shown in FIG. 2C and the configuration shown in FIG. 2A is the transistor 162 and the capacitor The difference is that the insulating layer 144 is not provided on the capacitor 164. 2A. In this case, since the insulating layer 144 is not provided, the transistor and the capacitor shown in FIG. As a result, the manufacturing process is simplified and the manufacturing cost is reduced.

[0049] In addition, in the structure shown in FIG. 2C, the oxide semiconductor layer 140 is not processed. Therefore, the etching performed after the etching can prevent contamination of the oxide semiconductor layer 140. In addition, in the capacitor element 164, the oxide semiconductor layer 140 and the gate insulating layer 146 are stacked. By this, the insulation between the source electrode or drain electrode 142a and the electrode 148b is This allows for sufficient compatibility.

[0050] The transistor and the capacitor shown in FIG. 2D are the same as those shown in FIG. 2B. The structure is partially different from that of the element.

[0051] The difference between the configuration shown in FIG. 2D and the configuration shown in FIG. 2B is the transistor 162 and the capacitor 163. The point is that the insulating layer 144 is not provided on the capacitor 164. 2B. By providing the insulating layer 144 in the capacitor 164, the As a result, the manufacturing process is simplified and the manufacturing cost is reduced.

[0052] In addition, in the capacitor 164, the oxide semiconductor layer 140 and the gate insulating layer 146 are stacked. This improves the insulation between the source or drain electrode 142a and the electrode 148b. can be sufficiently secured.

[0053] <Circuit Configuration and Operation of Semiconductor Device> Next, an example of the circuit configuration of the semiconductor device and its operation will be described. ) is an example of a circuit configuration corresponding to the semiconductor device shown in FIG.

[0054] In the semiconductor device shown in FIG. 3(A-1), a first wiring (also called a source line) The second wiring (2nd wiring) and the source electrode of the transistor 160 are electrically connected. The drain electrode of the transistor 160 is electrically connected to the line (also called the bit line). In addition, the third wiring (also called the first signal line) and the transistor The other of the source electrode or the drain electrode of the capacitor 162 is electrically connected to the fourth wiring ( The 4th Line (also called the second signal line) and the gate electrode of the transistor 162 are connected to each other. The gate electrode of the transistor 160 and the gate electrode of the transistor 16 One of the source electrode and the drain electrode of the capacitor 164 is electrically connected to one of the electrodes of the capacitor 164. The fifth wiring (also called a word line) and the electrode of the capacitor element 164 are connected to each other. The other is electrically connected.

[0055] The transistor 160 using a material other than an oxide semiconductor can operate at sufficiently high speed. By using this, it is possible to read out the stored contents at high speed. The transistor 162 including an oxide semiconductor has an extremely low off-state current. Therefore, when the transistor 162 is turned off, the transistor 160 The potential of the gate electrode can be maintained for an extremely long period of time. By having the electrode 164, the charge applied to the gate electrode of the transistor 160 can be retained. This makes it easier to read out the stored contents.

[0056] In the semiconductor device described in this embodiment, the potential of the gate electrode of the transistor 160 can be held. By taking advantage of this feature, it is possible to write, store, and read information as follows: .

[0057] First, writing and holding of information will be explained. First, the potential of the fourth wiring is set to The transistor 162 is set to a potential that turns it on, thereby turning it on. As a result, the potential of the third wiring is applied to the gate electrode of the transistor 160 and the capacitor 1 That is, the gate electrode of the transistor 160 is provided with a predetermined Here, the charges that give two different potential levels (hereafter referred to as The charge level is either a low level charge or a high level charge. After that, the potential of the fourth wiring is set to a potential that turns off the transistor 162. By turning off the transistor 162, the voltage applied to the gate electrode of the transistor 160 is The load is held (retention).

[0058] Since the off-state current of the transistor 162 is extremely small, the gate electrode of the transistor 160 The charge is retained for a long time.

[0059] Next, the reading of information will be described. In this state, when an appropriate potential (read potential) is applied to the fifth wire, the gate of the transistor 160 The second wiring has a different potential depending on the amount of charge held in the transistor electrode. If the transistor 160 is an n-channel type, a high level is applied to the gate electrode of the transistor 160. Apparent threshold V for a given charge th_H is the gate of transistor 160 The apparent threshold voltage V when a low-level charge is applied to the gate electrode th_L Lower Here, the apparent threshold voltage is the voltage at which the transistor 160 is in the "on state." Therefore, the potential of the fifth wiring is V place th_H and V th_L By setting the potential V0 to the intermediate potential of The charge applied to the gate electrode can be determined. For example, in writing, If a charge is applied, the potential of the fifth wire is V0 (>V th_H ) then, The transistor 160 is in the "ON state." If a low level charge is applied, The potential of the fifth wire is V0( <V th_L ), transistor 160 remains in the "off state" Therefore, by checking the potential of the second wiring, the stored information can be read. You can put it out.

[0060] When information is not read, the state of the gate electrode of the transistor 160 is not changed. The potential at which transistor 160 is in the "off state," i.e., V th_H Less than Alternatively, the potential may be applied to the fifth wiring. The potential at which transistor 160 remains "on," i.e., V th_L twist A large potential may be applied to the fifth wiring.

[0061] Next, the rewriting of information will be described. That is, the potential of the fourth wiring is held when the transistor 162 is turned on. This turns on the transistor 162. (a potential related to new information) is applied to the gate electrode of the transistor 160 and the capacitor 164. Then, the potential of the fourth wiring is applied to one electrode of the transistor 162. By setting the potential to The gate electrode of 0 is now in a state where a charge related to new information is given.

[0062] In this way, the semiconductor device according to the disclosed invention can directly write information again. It is possible to rewrite information. This is why it is necessary for flash memory etc. This eliminates the need for an erase operation, and can suppress a decrease in operation speed due to the erase operation. That is, high-speed operation of the semiconductor device is realized.

[0063] The source electrode or drain electrode of the transistor 162 is connected to the gate of the transistor 160. By electrically connecting the gate electrode to the flow cell, the flow cell can be used as a nonvolatile memory element. This has the same effect as the floating gate of a floating gate type transistor. In the figure, the source electrode or drain electrode of the transistor 162 and the gate electrode of the transistor 160 The part where the gate electrode is electrically connected is sometimes called the floating gate part FG. When the transistor 162 is off, the floating gate portion FG is buried in an insulator. The floating gate FG holds charge. In the transistor 162 using a conductor, the off-state current is generated by a transistor formed by a silicon semiconductor or the like. Since the current is less than 1 / 100,000 of that of transistor 160, the leakage current of transistor 162 is It is possible to ignore the loss of charge stored in the floating gate portion FG. Therefore, a nonvolatile memory device can be realized by the transistor 162 including an oxide semiconductor. It is possible to do this.

[0064] For example, the off-state current density of the transistor 162 at room temperature is 10 Ω / μm (1 Ω / μm). ampere) is 1 x 10 -21 A) and the capacitance value of the capacitance element 164 is about 1 pF. If so, at least 10 6 It is possible to hold data for more than 10 seconds. It goes without saying that this varies depending on the transistor characteristics and capacitance value.

[0065] In this case, the gate electrode, which has been pointed out in the conventional floating gate type transistor, This avoids the problem of deterioration of the gate insulating film (tunnel insulating film). This solves the problem of gate insulating film degradation when implanting electrons into the floating gate. As a result, in the semiconductor device shown in this embodiment, the fundamental writing In addition, there is no limit to the number of times that the transistor can be turned on. The high voltage required for writing and erasing is also unnecessary.

[0066] The semiconductor device shown in FIG. 3(A-1) is a semiconductor device including elements such as transistors. can be replaced with a circuit like that shown in Figure 3(A-2) as including resistance and capacitance. That is, in FIG. 3(A-2), the transistor 160 and the capacitor 164 are Each is considered to be composed of a resistance and a capacitance. R1 and C1 are the resistance and capacitance values ​​of the capacitive element 164, respectively, and the resistance value R1 is the capacitance value of the capacitive element 164. R2 and C2 correspond to the resistance of the insulating layer that constitutes 64. The resistance and capacitance of the transistor 160 are R1 and R2, respectively. The capacitance C2 corresponds to the resistance value of the gate insulating layer in the gate This corresponds to the capacitance formed between the gate electrode and the source or drain electrode. The resistance value R2 is the resistance value between the gate electrode and the channel forming region of the transistor 160. Some of the connections are shown as dotted lines to clarify this point, as they are for illustration purposes only.

[0067] The resistance between the source and drain electrodes when the transistor 162 is in the off state (actual If R1 and R2 are R1 ≥ ROS and R2 ≥ ROS, When this condition is satisfied, the charge retention period (which can also be called the information retention period) is mainly due to the It is determined by the off-current of the transistor 162.

[0068] On the other hand, if this condition is not satisfied, the off-state current of the transistor 162 is not sufficiently small. However, it becomes difficult to ensure a sufficient retention period. This is because the leakage current is large. It is desirable that the above relationship be satisfied.

[0069] On the other hand, it is desirable that C1 and C2 satisfy the relationship C1≧C2. When the potential of the floating gate portion FG is controlled by the fifth wiring (for example, when reading This is because the potential of the fifth wiring can be kept low when the fifth wiring is broken (when the wiring breaks down).

[0070] By satisfying the above relationship, it is possible to realize a more suitable semiconductor device. In this embodiment, R1 and R2 are formed by the gate insulating layer 108, the gate insulating layer 146, etc. The same applies to C1 and C2. It is desirable to appropriately set the thickness etc. so as to satisfy the above-mentioned relationship.

[0071] FIG. 3(B) shows a semiconductor device having a structure partially different from that of the semiconductor device described above. In the semiconductor device shown in FIG. 1, the gate electrode of the transistor 160 and the transistor 166 One of the source electrode and the drain electrode of the capacitor 164 is electrically connected to one of the electrodes of the capacitor 164. The first wiring and the source electrode of the transistor 160 are electrically connected. The second wiring and the drain electrode of the transistor 160 are electrically connected. The third wiring and the other of the source electrode and the drain electrode of the transistor 166 are connected to each other. , and the fourth wiring and the first gate electrode of the transistor 166 are electrically connected. The fifth wiring and the other electrode of the capacitor 164 are electrically connected to each other. The sixth wiring and the second gate electrode of the transistor 166 are electrically connected. The sixth wiring may be given the same potential as the fourth wiring, or may be given a potential different from the fourth wiring. Alternatively, a potential different from that of the fourth wiring may be applied to the second wiring and controlled independently of the fourth wiring.

[0072] That is, the semiconductor device shown in FIG. 3B is a transistor of the semiconductor device shown in FIG. The transistor 162 is replaced with a transistor 166 having a second gate electrode. As a result, in the semiconductor device shown in FIG. 3B, In addition to the effect obtained, the electrical characteristics (e.g., threshold voltage) of the transistor 166 can be adjusted. For example, applying a negative potential to the sixth wiring The transistor 166 can be easily set to normally off.

[0073] The above explanation is for n-type transistors (n-channel transistors) in which electrons are the majority carriers. This is about using a large number of hole-capacitors instead of n-type transistors. It goes without saying that a p-type transistor can be used as a carrier.

[0074] <Method for manufacturing semiconductor device> Next, an example of a method for manufacturing the semiconductor device shown in FIGS. 1 and 3(A-1) will be described. First, a method for manufacturing the lower transistor 160 will be described below with reference to FIG. Then, a method for manufacturing the upper transistor 162 and the capacitor 164 will be described with reference to FIG. This will be explained in light of the above.

[0075] <Method for manufacturing the lower transistor> First, a substrate 100 containing a semiconductor material is prepared (see FIG. 4(A)). The plate 100 may be a single crystal semiconductor substrate such as silicon or silicon carbide, or a polycrystalline semiconductor substrate. Compound semiconductor substrates such as silicon germanium, SOI substrates, etc. can be used. Here, the substrate 100 containing a semiconductor material is a single crystal silicon substrate. An example will be shown below. Generally, an "SOI substrate" is a substrate in which silicon semiconductor is formed on an insulating surface. It refers to a substrate having a structure in which a conductor layer is provided, but in this specification, it refers to a substrate having a silicon layer on an insulating surface. The term "substrate" is used as a concept that also includes a substrate having a semiconductor layer made of a material other than The semiconductor layer of the "SOI substrate" is not limited to a silicon semiconductor layer. The plate has a structure in which a semiconductor layer is provided on an insulating substrate such as a glass substrate via an insulating layer. shall be included.

[0076] A protective layer 102 is formed on the substrate 100 to serve as a mask for forming an element isolation insulating layer. (See FIG. 4(A)). The protective layer 102 may be made of, for example, silicon oxide or silicon nitride. An insulating layer made of silicon oxynitride or the like can be used. In order to control the threshold voltage of the transistor, impurities that give n-type conductivity are used. The substrate 100 may be doped with an impurity element that imparts p-type conductivity or a metal element that imparts p-type conductivity. In the case of silicon, impurities that give n-type conductivity include phosphorus and arsenic. In addition, impurities that impart p-type conductivity include, for example, boron and aluminum. Sodium, gallium, etc. can be used.

[0077] Next, etching is performed using the protective layer 102 as a mask, and the The part of the substrate 100 in the area where the semiconductor substrate 100 is not exposed is removed. The conductive region 104 is formed (see FIG. 4(B)). It is preferable to use an etching gas or an etchant, but wet etching may also be used. The etching liquid can be appropriately selected depending on the material to be etched.

[0078] Next, an insulating layer is formed so as to cover the semiconductor region 104, and the region overlapping the semiconductor region 104 is The insulating layer is selectively removed to form an element isolation insulating layer 106 (see FIG. 4(B)). The insulating layer is formed using silicon oxide, silicon nitride, silicon oxynitride, or the like. The insulating layer can be removed by polishing such as CMP or etching. After the semiconductor region 104 is formed or after the element isolation insulating film is formed, After the layer 106 is formed, the protective layer 102 is removed.

[0079] Next, an insulating layer is formed on the semiconductor region 104, and a layer containing a conductive material is formed on the insulating layer. do.

[0080] The insulating layer will later become the gate insulating layer and is obtained using a CVD method, sputtering method, etc. Silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide It is preferable to use a single layer or multilayer structure of a film containing aluminum, tantalum oxide, etc. By oxidizing or nitriding the surface of the semiconductor region 104 through plasma treatment or thermal oxidation treatment, The insulating layer may be formed by the high density plasma treatment, for example, using He, Ar, Kr, or X. It is performed using a mixture of rare gases such as e, oxygen, nitrogen oxide, ammonia, nitrogen, hydrogen, etc. The thickness of the insulating layer is not particularly limited, but may be, for example, 1 nm or more and 100 nm or less. m or less.

[0081] The layer containing the conductive material is made of a metal material such as aluminum, copper, titanium, tantalum, or tungsten. Also, a conductive material such as polycrystalline silicon can be used to form the conductive layer. The method for forming the layer is not particularly limited, and may be a vapor deposition method, a CVD method, a sputtering method, or the like. Various film forming methods such as talc coating and spin coating can be used. In this embodiment, an example in which a layer containing a conductive material is formed using a metal material is shown. Let's say.

[0082] Thereafter, the insulating layer and the layer containing the conductive material are selectively etched to form the gate insulating layer 108. Then, the gate electrode 110 is formed (see FIG. 4(C)).

[0083] Next, an insulating layer 112 is formed to cover the gate electrode 110 (see FIG. 4(C)). The conductor region 104 is doped with phosphorus (P) or arsenic (As) to form an impurity region with a shallow junction depth. 114 is formed (see FIG. 4(C)). In the case of forming a p-type transistor, boron (B) or arsenic is added. An impurity element such as aluminum (Al) may be added. As a result, a channel forming region 116 is formed below the gate insulating layer 108 in the semiconductor region 104. (See FIG. 4(C)). Here, the concentration of the added impurity can be set appropriately. However, when semiconductor elements are highly miniaturized, it is desirable to increase the concentration. In this case, the step of forming the impurity region 114 after forming the insulating layer 112 is adopted. However, the insulating layer 112 may be formed after the impurity regions 114 are formed.

[0084] Next, a sidewall insulating layer 118 is formed (see FIG. 4(D)). The layer 118 is formed by forming an insulating layer to cover the insulating layer 112 and then applying a highly anisotropic By applying a simple etching process, it can be formed in a self-aligned manner. Then, the insulating layer 112 is partially etched to expose the upper surface of the gate electrode 110 and the impurity region 1 It is advisable to expose the top surface of 14.

[0085] Next, a layer is formed so as to cover the gate electrode 110, the impurity region 114, the sidewall insulating layer 118, etc. Then, an insulating layer is formed on the impurity region 114. Then, phosphorus (P) or arsenic ( As) or the like is added to form a high concentration impurity region 120 (see FIG. 4(E)). The insulating layer is removed, and the gate electrode 110, the sidewall insulating layer 118, and the high concentration impurity A metal layer 122 is formed so as to cover the region 120 and the like (see FIG. 4(E)). 2 is formed using various film formation methods such as vacuum deposition, sputtering, and spin coating. The metal layer 122 can react with the semiconductor material that makes up the semiconductor region 104. It is desirable to form the metal layer using a metal material that forms a low-resistance metal compound. Examples of materials include titanium, tantalum, tungsten, nickel, cobalt, and platinum. be.

[0086] Next, a heat treatment is performed to react the metal layer 122 with the semiconductor material. A metal compound region 124 is formed in contact with the high concentration impurity region 120 (see FIG. 4(F)). When polycrystalline silicon or the like is used as the gate electrode 110, the gate electrode 110 A metal compound region is also formed in the portion in contact with the metal layer 122.

[0087] The heat treatment may be, for example, a heat treatment by irradiation with a flash lamp. Of course, other heat treatment methods may be used, but the chemical reaction involved in the formation of metal compounds In order to improve the controllability of the heat treatment, it is desirable to use a method that can realize heat treatment in a very short time. The metal compound region is preferably formed by a reaction between a metal material and a semiconductor material. The metal compound region is formed in a region where the conductivity is sufficiently increased. This can sufficiently reduce the electrical resistance and improve the device characteristics. After forming region 124, metal layer 122 is removed.

[0088] Next, an interlayer insulating layer 126 and an interlayer insulating layer 127 are formed to cover the respective components formed by the above-described steps. The interlayer insulating layer 126 and the interlayer insulating layer 128 are formed by oxidation. Silicon, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, titanium oxide The insulating layer can be formed using a material containing an inorganic insulating material such as palladium. It is also possible to form the layer using an organic insulating material such as acrylic resin. The structure is a two-layer structure of an interlayer insulating layer 126 and an interlayer insulating layer 128. After the interlayer insulating layer 128 is formed, the surface may be subjected to a process such as CMP or etching. It is desirable to flatten the surface by using a method such as

[0089] Thereafter, an opening is formed in the interlayer insulating layer so as to reach the metal compound region 124. The source or drain electrode 130a and the source or drain electrode 130b are The source or drain electrode 130a and the source or drain electrode 130b are formed (see FIG. 4(H)). The drain electrode 130b is formed by, for example, using a PVD method or a CVD method in the region including the opening. After forming the conductive layer, a part of the conductive layer is removed by a method such as etching or CMP. can be formed by removing

[0090] More specifically, for example, a thin titanium film is formed in the area including the opening by the PVD method, and then CV After forming a thin titanium nitride film by the D method, a tungsten film is formed to fill the opening. Here, the titanium film formed by the PVD method is The oxide film (such as a natural oxide film) on the surface is reduced, and the lower electrode (here, the metal compound region 124 ) and the titanium nitride film formed thereafter has the function of reducing the contact resistance with the It has a barrier function that suppresses the diffusion of conductive materials. After the barrier film is formed, a copper film may be formed by plating.

[0091] In addition, a part of the conductive layer is removed to form the source electrode or drain electrode 130a and the source electrode Alternatively, when forming the drain electrode 130b, the surface thereof is processed to be flat. For example, after forming a thin titanium film or titanium nitride film in the region including the opening, When a tungsten film is formed to fill the opening, the inclusions are removed by the subsequent CMP. Removes unnecessary tungsten, titanium, titanium nitride, etc. and improves the flatness of the surface. In this way, the source electrode or drain electrode 130a, the source electrode Alternatively, by planarizing the surface including the drain electrode 130b, it is possible to improve the quality of the surface in a later process. It becomes possible to form favorable electrodes, wiring, insulating layers, semiconductor layers, and the like.

[0092] Here, the source electrode or drain electrode 130 in contact with the metal compound region 124 Although only the gate electrode 130a and the source electrode or the drain electrode 130b are shown, An electrode 130c in contact with the source electrode 110 may also be formed. The electrode or drain electrode 130a and the source or drain electrode 130b can be used as There are no particular limitations on the material that can be used, and various conductive materials can be used. For example, Molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, Conductive materials such as scandium can be used. Also, taking into consideration the heat treatment that will be performed later, The source or drain electrode 130a and the source or drain electrode 130b are It is desirable to form the insulating layer using a material that has sufficient heat resistance to withstand the heat treatment that will be performed later. I wish.

[0093] As a result of the above, a transistor 160 using the substrate 100 containing a semiconductor material is formed (see FIG. 4(H)). After the above process, electrodes, wiring, insulating layers, etc. may be formed. The wiring structure is a multi-layer wiring structure consisting of a laminated structure of interlayer insulating layers and conductive layers. By doing so, it is possible to provide a highly integrated semiconductor device.

[0094] <Method of manufacturing the upper transistor> Next, referring to FIG. 5, a process for manufacturing the transistor 162 on the interlayer insulating layer 128 will be described. 5 shows various electrodes on the interlayer insulating layer 128 and transistors 162, etc. Since this shows the manufacturing process, the transistor 162 located below the transistor 16 Details such as 0 are omitted.

[0095] First, an interlayer insulating layer 128, a source electrode or drain electrode 130a, and a source electrode or drain electrode 130b are formed. An insulating layer 138 is formed on the drain electrode 130b and the electrode 130c. The insulating layer 138 is formed by PVD. The film can be formed by using a method such as a CVD method. Inorganic insulating materials such as silicon nitride, hafnium oxide, aluminum oxide, and tantalum oxide The insulating layer 138 can be formed using a material containing The insulating layer 138 functions as a base.

[0096] Next, the source or drain electrode 130a, the source or drain electrode 130b, and the insulating layer 138 are Openings are formed that reach the drain electrode 130b and the electrode 130c (see FIG. 5(A)). The opening can be formed by a method such as etching using a mask. The etching can be performed by exposure using a photomask. Either wet etching or dry etching may be used. Therefore, it is preferable to use dry etching. , this step can be omitted.

[0097] Next, the source or drain electrode 142a, the source or drain electrode 142b , an electrode 142c and an electrode 142d are formed (see FIG. 5(B)). A source electrode 142a, a source or drain electrode 142b, an electrode 142c, and an electrode 142d In this case, a conductive layer is formed to cover the insulating layer 138, and then the conductive layer is selectively etched. It can be formed by

[0098] The conductive layer is formed by PVD methods such as sputtering, or CVD methods such as plasma CVD. The conductive layer can be formed by a method. , copper, tantalum, titanium, molybdenum, tungsten, or the elements mentioned above Alloys containing the elements manganese, magnesium, zirconium, etc. can be used. Alternatively, a material selected from one or more of fluorine, beryllium, and thorium may be used. In addition to aluminum, titanium, tantalum, tungsten, molybdenum, chromium, and neodymium Alternatively, a material containing a single element selected from the group consisting of zinc, zinc oxide, and scandium, or a combination of multiple elements may be used. The conductive layer may have a single layer structure or a laminated structure of two or more layers. Single layer structure of aluminum film containing titanium, and two layer structure of titanium film laminated on aluminum film. and a three-layer structure in which a titanium film, an aluminum film and another titanium film are laminated.

[0099] The conductive layer may be formed using a conductive metal oxide. Indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), Indium tin oxide alloy (In2O3-SnO2, sometimes abbreviated as ITO), oxide Indium-zinc oxide alloy (In2O3-ZnO), or these metal oxide materials It is possible to use a material containing silicon or silicon oxide.

[0100] The channel length (L) of the transistor is the distance from the bottom end of the source or drain electrode 142a to the The distance between the source electrode or the drain electrode 142b and the lower end of the channel When the length (L) is less than 25 nm, the wavelength of the extreme ultraviolet (Ex It is recommended to use a fluorine-containing fluorine-containing film (fluorine-containing film) to form an etching mask. Extreme ultraviolet light exposure has high resolution and a large depth of focus. It is possible to form a turn, and the channel length (L) of the transistor can be increased to 10 nm or more. It is possible to make the channel length smaller than 0.000 nm. This is preferable because the circuit has a high operating speed and consumes less power.

[0101] Also, the source electrode or drain electrode 142a and the source electrode or drain electrode 1 The source electrode 42b is preferably formed so that its end is tapered. Alternatively, the ends of the drain electrode 142a and the source or drain electrode 142b are By forming the insulating film in a micro-shape, the coverage of the oxide semiconductor layer to be formed later can be improved, and the step-like structure can be prevented. Here, the taper angle is, for example, 30° to 60°. The taper angle is preferably equal to or less than 100°. The source electrode or drain electrode 142a) is perpendicular to the cross section (plane perpendicular to the surface of the substrate). This indicates the inclination angle between the side and bottom surfaces of the layer when observed from a perpendicular direction.

[0102] Next, the source or drain electrode 142a, the source or drain electrode 142b After forming an oxide semiconductor layer to cover the Therefore, the oxide semiconductor layer is processed to form an island-shaped oxide semiconductor layer 140 (FIG. 5(C) )reference).

[0103] The oxide semiconductor layer is preferably formed by a sputtering method. are quaternary metal oxides such as In-Sn-Ga-Zn-O and ternary metal oxides such as In-Ga-Zn-O series, In-Sn-Zn-O series, In-Al-Zn-O series, Sn-G a-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, and binary metal oxide In-Zn-O, Sn-Zn-O, Al-Zn-O, Zn-Mg-O, Sn-Mg-O, In-Mg-O, In-O, Sn-O, Zn-O, etc. It can be formed by using a metal oxide. For example, oxide semiconductors can be produced by using a target containing 2% to 10% by weight of SiO2. A conductor layer may be formed.

[0104] Among these, by using In-Ga-Zn-O based metal oxides, the resistance in the absence of an electric field is sufficiently low. To form a semiconductor device having sufficiently high field-effect mobility (sufficiently small off-state current) In this respect, In-Ga-Zn-O based metal oxides are suitable for semiconductor devices. It is suitable as a material.

[0105] A typical example of an In-Ga-Zn-O metal oxide is InGaO3(ZnO). m (m >0). Also, M is used instead of Ga, and InMO3(ZnO) is used. m There are metal oxides that are written as (m>0), where M is gallium (Ga), Aluminum (Al), iron (Fe), nickel (Ni), manganese (Mn), cobalt (C o) represents one or more metal elements selected from the following. For example, M is: Ga, Ga and Al, Ga and Fe, Ga and Ni, Ga and Mn, Ga and Co, etc. can be applied. Note that the above composition is derived from the crystal structure. It should be noted that this is merely an example.

[0106] In this embodiment, the oxide semiconductor layer is grown using an In—Ga—Zn—O-based metal oxide target. The film is formed by a sputtering method using a fluorine-containing compound.

[0107] The oxide semiconductor layer is formed by holding a substrate in a treatment chamber kept in a reduced pressure state, and adjusting the substrate temperature to Preferably, the temperature is 100°C or higher and 600°C or lower, more preferably 200°C or higher and 400°C or lower. Here, by forming the oxide semiconductor layer while heating the substrate, the oxide semiconductor The concentration of impurities contained in the oxide semiconductor layer can be reduced by sputtering. Damage can be reduced.

[0108] The atmosphere in which the oxide semiconductor layer is formed is one in which impurities such as hydrogen, water, hydroxyl groups, and hydrides are sufficiently reduced. Inert gas (typically argon) atmosphere, oxygen atmosphere, or inert gas (typically It is preferable to use a mixed atmosphere of hydrogen, water, and argon. Impurities such as hydroxyl groups and hydrides are at a concentration of 1 ppm or less (preferably 10 ppb or less). It is preferable to use a high purity gas atmosphere in which the concentration of impurities is reduced to as low as 100%.

[0109] Here, in order to remove the residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump may be used. In addition, a turbo molecular pump with a cold trap can be used as an exhaust means. The film formation chamber evacuated using a cryopump may contain, for example, hydrogen atoms, Compounds containing hydrogen atoms such as water (H2O) (and more preferably compounds containing carbon atoms) Since the gas is exhausted, the concentration of impurities contained in the oxide semiconductor layer formed in the deposition chamber can be reduced. Cut.

[0110] The thickness of the oxide semiconductor layer is 2 nm or more and 200 nm or less, preferably 5 nm or more and 30 nm or less. The appropriate thickness varies depending on the oxide semiconductor material used. The thickness may be appropriately selected depending on the material used.

[0111] In addition, by using a pulsed direct current (DC) power supply when forming the oxide semiconductor layer, (powder or flake-like substances formed during film formation) can be reduced, and the film thickness distribution is uniform. It can be said that:

[0112] The sputtering conditions for the oxide semiconductor layer are, for example, The distance between the chamber and the test piece was 170 mm, the pressure was 0.4 Pa, the direct current (DC) power was 0.5 kW, and the atmosphere was The conditions that can be applied are an oxygen atmosphere (oxygen flow rate 100%).

[0113] Before forming the oxide semiconductor layer by a sputtering method, argon gas was introduced. The reverse sputtering is performed to generate plasma, and the metal adhering to the surface of the insulating layer 138 is removed. Here, the reverse sputtering is a method of removing the In this method, ions are bombarded onto the sputtering target, but conversely, ions are directed onto the surface to be treated. This refers to a method of modifying a surface by bombarding it with ions. The method is to apply a high frequency voltage to the surface to be treated in an argon atmosphere. In addition, nitrogen, helium, Oxygen or the like may also be used.

[0114] The oxide semiconductor layer can be etched by either dry etching or wet etching. Of course, both can be used in combination. To enable etching, the etching conditions (etching gas, etching solution, etc.) are adjusted to suit the material. The etching time, temperature, etc. may be set appropriately.

[0115] The etching gas used in dry etching is, for example, a gas containing chlorine (chlorine-based gas, For example, chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), carbon tetrachloride fluorine (CCl4, etc.) and gases containing fluorine (fluorine-based gases, for example, tetrafluorine Carbon fluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), trifluoromethane (CHF3), hydrogen bromide (HBr), oxygen (O2), and helium (H e) or a gas to which a rare gas such as argon (Ar) is added may also be used.

[0116] As a dry etching method, parallel plate type RIE (Reactive Ion Etch) ing) method and ICP (Inductively Coupled Plasma) A plasma-coupled plasma etching method can be used. As shown in the figure, the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side) The amount of power, the temperature of the electrode on the substrate, etc. are set appropriately.

[0117] The etching solution used for wet etching is a mixture of phosphoric acid, acetic acid, and nitric acid. Ammonia peroxide water (31% by weight hydrogen peroxide: 28% by weight ammonia water: water = 5:2:2) In addition, etching solutions such as ITO07N (manufactured by Kanto Chemical Co., Ltd.) can be used. It's fine.

[0118] Next, the oxide semiconductor layer is preferably subjected to first heat treatment. By this heat treatment, impurities such as hydrogen in the oxide semiconductor layer can be removed. If the etching is performed after the etching, even if wet etching is used, The first heat treatment temperature is 30 The temperature is set to 0°C or higher and 750°C or lower, preferably 400°C or higher and 700°C or lower. For example, resistance heating The substrate is placed in an electric furnace using a furnace or the like, and the oxide semiconductor layer 140 is heated to 450 ... Heat treatment is performed at 0° C. for 1 hour. During this time, the oxide semiconductor layer 140 is not exposed to the air. In addition, the first heat treatment temperature is set to 1000°C, and hydrogen (including water) is not re-mixed. The temperature is preferably determined taking into consideration the heat resistance of the electrodes and wiring of the transistor 160 in the lower layer. It's nice.

[0119] The heat treatment device is not limited to an electric furnace, and may be any device that uses heat conduction from a medium such as heated gas, or It may also be a device that heats the object to be treated by thermal radiation. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be equipped with halogen lamps, metal halide lamps, etc. Lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure water A device that heats the object to be treated by radiating light (electromagnetic waves) emitted from a lamp such as a silver lamp. The GRTA device is a device that performs heat treatment using high-temperature gas. An inert gas that does not react with the material to be treated by heat treatment, such as a rare gas such as argon or nitrogen. A gas is used.

[0120] For example, in the first heat treatment, the substrate is immersed in an inert gas heated to a high temperature of 650°C to 700°C. After heating for several minutes, the substrate is taken out of the inert gas (GRTA) treatment. GRTA treatment allows high-temperature heat treatment in a short time. Since this is a heat treatment, when using a substrate with low heat resistance such as a glass substrate, distortion of the substrate may occur. This makes it possible to apply the method even under temperature conditions exceeding the melting point.

[0121] The first heat treatment is performed in a gas atmosphere containing nitrogen or a rare gas (helium, neon, argon, etc.) as the main component. It is desirable to carry out the process in an atmosphere that does not contain hydrogen, water, etc. The purity of nitrogen or rare gases such as helium, neon, and argon introduced into the heat treatment device is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (i.e. The impurity concentration is 1 ppm or less, preferably 0.1 ppm or less.

[0122] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may be crystallized. In addition, the semiconductor layer may contain crystalline components. Depending on the material of the oxide semiconductor layer, it may become an amorphous oxide semiconductor layer that does not contain crystalline components. be.

[0123] In addition, by providing a crystalline layer on the amorphous surface, the electrical characteristics of the oxide semiconductor layer can be changed. For example, it is possible to form a crystal layer in which crystal grains having electrical anisotropy are oriented. In this way, the electrical characteristics of the oxide semiconductor layer can be changed.

[0124] The first heat treatment on the oxide semiconductor layer 140 is performed to process the oxide semiconductor layer 140 into an island-shaped oxide semiconductor layer 140. In this case, the first heat treatment is performed on the oxide semiconductor layer. The substrate is then removed and subjected to a photolithography process.

[0125] The heat treatment may have a dehydrogenation (dehydration) effect on the oxide semiconductor layer 140. This type of treatment can be called dehydrogenation treatment (dehydration treatment) or the like. After forming the conductor layer, an insulating layer (such as a gate insulating layer) is laminated on the oxide semiconductor layer 140. This can be done at any timing, for example, after forming the gate electrode. This process may be performed multiple times instead of just once.

[0126] In addition, by controlling the atmosphere in which the oxide semiconductor layer is formed, it is possible to prevent hydrogen from being sufficiently introduced. In a case where a reduced oxide semiconductor layer can be obtained, the first heat treatment may be omitted. It is also possible.

[0127] After the above process, plasma treatment using gas such as N2O, N2, or Ar may be performed. By the plasma treatment, the oxide semiconductor layer may be adhered to the exposed surface thereof. It is also possible to remove oxygen-containing gases such as a mixture of oxygen and argon. In this case, plasma treatment using a gas containing oxygen may be performed to supply oxygen to the oxide semiconductor layer. This allows the reduction of defect levels in the energy gap caused by oxygen deficiency. .

[0128] Next, the source or drain electrode 142a, the source or drain electrode 142b An insulating layer 144 is formed above the oxide semiconductor layer 140 and the like, and a gate electrode is formed in the region where the gate electrode is to be formed. An opening is formed in a part of the region where the electrode of the capacitor element is to be formed. After forming a gate insulating layer 146 so as to cover the region including the opening, a gate electrode 148a The opening in the insulating layer 144 is formed using a mask. The gate electrode 148a and the electrode The electrode 148b is formed by forming a conductive layer to cover the gate insulating layer 146 and then selectively insulating the conductive layer. It can be formed by selectively etching.

[0129] The insulating layer 144 and the gate insulating layer 146 are formed by using a CVD method, a sputtering method, or the like. The insulating layer 144 and the gate insulating layer 146 may be made of silicon oxide, nitride, or the like. silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, tantalum oxide, etc. The insulating layer 144 and the gate insulating layer 146 are preferably formed to include a single layer. The thickness of the film may be, but is not particularly limited to, For example, the insulating layer 144 may be 10 nm or more and 500 nm or less. For example, the insulating layer 144 is provided to reduce capacitance caused by overlapping. By forming the gate electrode 148a, the source electrode or the drain electrode 142a, etc. The capacitance due to this is reduced.

[0130] The insulating layer 144 and the gate insulating layer 146 are formed by a method that is less likely to be contaminated with impurities such as hydrogen and water. It is preferable that the insulating layer 144 and the gate insulating layer 146 contain hydrogen. and hydrogen penetration into the oxide semiconductor layer and extraction of oxygen from the oxide semiconductor layer by hydrogen. This is because there is a risk of the following occurring.

[0131] For example, when the insulating layer 144 and the gate insulating layer 146 are formed by sputtering, The sputtering gas contains impurities such as hydrogen, water, hydroxyl groups, or hydrides at a concentration of 1ppm. High-purity gas with a concentration of about 10 ppb is used. It is desirable to remove any remaining moisture in the processing chamber.

[0132] As shown in this embodiment, the oxide semiconductor that has been made intrinsic by removing impurities is Conductors (highly purified oxide semiconductors) are extremely sensitive to interface states and interface charges. Therefore, when such an oxide semiconductor is used for the oxide semiconductor layer, the boundary with the gate insulating layer Therefore, the surface of the gate insulating layer 146 in contact with the highly purified oxide semiconductor layer is important. This will require high quality.

[0133] For example, the high-density plasma CVD method using microwaves (frequency 2.45 GHz) produces dense, insulating This is advantageous in that it allows the formation of a high-quality gate insulating layer 146 with high breakdown voltage. The close contact between the oxide semiconductor layer and the high-quality gate insulating layer reduces the interface state and improves the interface characteristics. This is because it can improve the quality of the product.

[0134] Of course, if a high-quality insulating layer can be formed as a gate insulating layer, highly purified acid is also suitable. Even when a nitride semiconductor layer is used, other methods such as sputtering and plasma CVD are used. In addition, the film quality and interface characteristics can be improved by heat treatment after formation. In any case, it is necessary to use an insulating layer having good film quality and an oxide semiconductor layer. The gate insulating layer 146 may be formed to reduce the interface state density with the semiconductor layer.

[0135] In this embodiment, the insulating layer 144 and the gate insulating layer 146 are made of a material containing silicon oxide. The insulating layer is formed by a sputtering method.

[0136] After forming the insulating layer 144 or the gate insulating layer 146, an inert gas atmosphere is A second heat treatment is carried out in an atmosphere or an oxygen gas atmosphere (preferably at a temperature of 200°C to 400°C). For example, it is desirable to carry out the heating at a temperature of 250°C or higher and 350°C or lower. The second heat treatment is performed at 0°C for 1 hour. After the second heat treatment, the electrical characteristics of the transistor In addition, the second heat treatment can reduce the variation in the insulating layer containing oxygen. Oxygen is supplied to the oxide semiconductor layer from the source, and defect levels in the energy gap caused by oxygen deficiency are eliminated. The atmosphere for the heat treatment is not limited to the above, and may be air or the like. In this case, however, hydrogen may be mixed into the oxide semiconductor layer. It is desirable to use an atmosphere free of oxygen and water. There is no need to specify this, so it can be omitted.

[0137] The conductive layer to be the gate electrode 148a and the electrode 148b can be formed by a method such as sputtering. It can be formed by using a PVD method, which uses a CVD method such as a plasma CVD method. , the same as the source electrode or drain electrode 142a, etc., and the description thereof should be taken into consideration. can.

[0138] Etching for forming an opening in the insulating layer 144 and etching for forming the gate electrode 148a and the like are performed. For this etching, either dry etching or wet etching may be used. Of course, both can be used in combination. The etching conditions (etching gas, etching solution, etching time, temperature, etc.) are adjusted to suit the material. The degree of reflection, etc. can be set appropriately.

[0139] Next, a protective insulating layer 150 and an interlayer insulating layer 152 are formed (see FIG. 5(E)).

[0140] The protective insulating layer 150 and the interlayer insulating layer 152 are formed by using a PVD method, a CVD method, or the like. In addition, silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, and oxide The insulating layer can be formed using a material containing an inorganic insulating material such as aluminum oxide or tantalum oxide. do.

[0141] The protective insulating layer 150 is located relatively close to the oxide semiconductor layer 140. Therefore, it is formed using a method such as sputtering that is less likely to introduce impurities such as hydrogen and water. It is more desirable to

[0142] Furthermore, it is desirable that the interlayer insulating layer 152 be formed so that its surface is flat. By forming the interlayer insulating layer 152 so that the surface is flat, electrodes and This is because wiring and the like can be formed suitably.

[0143] The protective insulating layer 150 and the interlayer insulating layer 152 are not essential components and may be omitted as needed. It can be abbreviated.

[0144] Through the above steps, the transistor 162 and the capacitor 164 each including an oxide semiconductor are completed. (See FIG. 5(E)).

[0145] The transistor 162 including an oxide semiconductor manufactured by the above method has an off-state current For example, in a fully intrinsic (i-type) oxide semiconductor, In a body, the carrier density is, for example, 1 × 10 12 / cm 3 Less than 1.45× 10 10 / cm 3 The off-state current of the transistor is, for example, When the gate voltage Vg is in the range of -5V to -20V, even if it is +1V or +10V, , 1×10 -13 Therefore, the data retention period of the semiconductor device is sufficiently secured. Furthermore, when a fully intrinsic oxide semiconductor is used, Leakage current 1×10 -20 A (10zA (zeptoamperes)) to 1×10 -19 A (100zA). In other words, the leakage current is reduced to virtually zero. By using such an oxide semiconductor, it is possible to extend the data retention period. Therefore, a semiconductor device with sufficient reliability can be provided.

[0146] In addition, by forming the capacitor element 164 together, the gate electrode of the transistor 160 This makes it easier to hold the applied charge and to read out the stored contents. In the method shown in the embodiment, it is not necessary to add a process for forming the capacitor element 164. This is preferable from the viewpoint of cost reduction.

[0147] Note that in this embodiment, a transistor using a material other than an oxide semiconductor and a transistor using an oxide semiconductor are The semiconductor device relating to the stacked structure (two layers) with the transistor using the body has been explained. The structure that can be used in the present invention is not limited to the laminated structure. Alternatively, a laminated structure of three or more layers may be used.

[0148] In addition, the arrangement and connection of electrodes (wiring), insulating layers, semiconductor layers, etc., wiring width, channel width, Various parameters such as channel length and other conditions are required for semiconductor integrated circuits. For example, when a semiconductor device is formed in a single layer structure, The configuration of electrodes and wiring in the case of a laminated structure is significantly different from that in the case of a laminated structure.

[0149] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0150] (Embodiment 2) In this embodiment, a semiconductor device having a different configuration from the semiconductor device shown in the previous embodiment is used. The device and manufacturing method thereof will be described with reference to FIGS. The structure and manufacturing process of the semiconductor device are common to those of the first embodiment in many respects. Therefore, in the following, we will omit the explanation of the overlapping parts and will explain the differences in detail. do.

[0151] <Planar and cross-sectional configurations of semiconductor device> FIG. 6 shows an example of the configuration of a semiconductor device. FIG. 6(A) shows a cross section of the semiconductor device, and FIG. 6(B) shows a plan view of the semiconductor device. Here, FIG. 6(A) shows the A of FIG. 6(B). These correspond to the cross sections taken along lines A3-A4 and B3-B4. The semiconductor device to be fabricated has a structure in which a semiconductor other than an oxide semiconductor is provided at the bottom, as in FIGS. 1A and 1B. The transistor 160 includes a transistor 160 using an oxide semiconductor material, and the transistor 160 includes a transistor 160 using an oxide semiconductor material. 2 and a capacitor 164. The semiconductor device shown in this embodiment has an insulating layer Since the semiconductor device does not have the 144, the manufacturing process is simpler than that of the semiconductor device shown in FIG. This simplifies the manufacturing process and reduces the manufacturing cost. To reduce the amount of charge, an insulating layer 144 may be provided.

[0152] The transistor 162 illustrated in FIG. 6A includes an oxide semiconductor layer 1 40, and a source electrode or a drain electrode electrically connected to the oxide semiconductor layer 140. 142a, and a source or drain electrode 142b, and a source or drain electrode The electrode 142a, the source electrode or the drain electrode 142b, and the oxide semiconductor layer 140 are The gate insulating layer 146 is formed on the gate insulating layer 146 so as to overlap with the oxide semiconductor layer 140. The transistor shown in FIG. 162 is a top gate type, and is connected to the oxide semiconductor layer 140 and the source electrode or drain electrode. The connection to the doped electrodes 142a and the like is made in a region including the upper surface of the oxide semiconductor layer 140. Therefore, it can be called a top-gate, top-contact type.

[0153] <Method for manufacturing semiconductor device> Next, an example of a method for manufacturing the semiconductor device will be described. A method for manufacturing the lower transistor 162 will be described with reference to FIG. The method for producing 0 is the same as that shown in FIG. 4, and therefore will not be described.

[0154] First, an interlayer insulating layer 128, a source electrode or drain electrode 130a, and a source electrode or drain electrode 130b are formed. An insulating layer 138 is formed on the drain electrode 130b and the electrode 130c. Source or drain electrode 130a, source or drain electrode 130b, electrode An opening reaching 130c is formed (see FIG. 7(A)). The method can be seen in FIG. 5(A), so the explanation will be omitted. It can be formed by a method such as etching using a mask.

[0155] Next, an oxide semiconductor layer is formed over the insulating layer 138, and then subjected to etching or the like using a mask. The oxide semiconductor layer is processed by a method to form an island-shaped oxide semiconductor layer 140 ( (See FIG. 7B). The material and the formation method of the island-shaped oxide semiconductor layer 140 are the same as those shown in FIG. Since reference can be made to the above, the description will be omitted.

[0156] Next, the insulating layer 138, the openings provided in the insulating layer 138, and the island-shaped oxide semiconductor layer 1 A conductive layer is formed to cover 40, and the conductive layer is removed by a method such as etching using a mask. The electrode layer is processed to form a source electrode or a drain electrode 142a in contact with the oxide semiconductor layer 140. , a source electrode or a drain electrode 142b, an electrode 142c, and an electrode 142d are formed. Then, the source electrode or drain electrode 142a, the source electrode or drain electrode 14 2b, a gate insulating layer 146 is formed to cover the electrode 142c and the electrode 142d ( (See FIG. 7(C)). The materials and forming methods of the electrodes 142b, 142c, and 142d are the same as those shown in FIG. 5(B). The material and shape of the gate insulating layer 146 can be determined by referring to the relevant document. The method of forming the same can be seen in FIG. 5(D), and therefore the explanation will be omitted.

[0157] Next, a conductive layer is formed on the gate insulating layer 146, and then the conductive layer is removed by a method such as etching using a mask. The conductive layer is processed by a method to form a gate electrode 148a and an electrode 148b (FIG. 7). The materials and forming methods of the gate electrode 148a and the electrode 148b are shown in FIG. Therefore, the explanation will be omitted.

[0158] Next, a protective insulating layer is formed to cover the gate insulating layer 146, the gate electrode 148a, and the electrode 148b. An edge layer 150 and an interlayer insulating layer 152 are formed (see FIG. 7(E)). The material and method of forming the interlayer insulating layer 152 can be seen from FIG. 5(E). The clarification is omitted.

[0159] In this manner, the semiconductor device shown in FIG. 6 can be manufactured.

[0160] (Embodiment 3) In this embodiment mode, a semiconductor device formed using a plurality of the semiconductor devices shown in Embodiment 1 will be described. An example of the circuit configuration and operation will be described with reference to FIGS. 8 and 9. FIG.

[0161] <Circuit Configuration and Operation of Semiconductor Device> 8(A) and 8(B) are diagrams illustrating the semiconductor device shown in FIG. 3(A-1) (hereinafter referred to as memory cell 19) 8A is a circuit diagram of a semiconductor device formed using a plurality of 8(B) is a circuit diagram of a NAND-type semiconductor device in which memory cells 190 are connected in series. ) is a circuit diagram of a NOR type semiconductor device in which memory cells 190 are connected in parallel.

[0162] The semiconductor device shown in FIG. 8A includes a source line SL, a bit line BL, a first signal line S1, a second signal line S2, a The memory cell 190 includes a signal line S2, a word line WL, and a plurality of memory cells 190. The gate electrode of transistor 160 and the source or drain electrode of transistor 162 are connected to each other. One of the electrodes of the capacitor 164 is electrically connected to one of the electrodes of the capacitor 164. The signal line S1 and the other of the source electrode and the drain electrode of the transistor 162 are electrically connected to each other. The second signal line S2 and the gate electrode of the transistor 162 are electrically connected to each other. The word line WL and the other electrode of the capacitor 164 are electrically connected to each other. There are.

[0163] The source electrode of the transistor 160 in the memory cell 190 is connected to the adjacent memory cell The drain electrode of the transistor 160 in the memory cell 190 is electrically connected to the drain electrode of the transistor 160 in the memory cell 190. The drain electrode of the transistor 160 is connected to the transistor of the adjacent memory cell 190. 160. However, the plurality of memory cells connected in series are electrically connected to the source electrode of the memory cell 160. The drain of the transistor 160 of the memory cell 190 provided at one end of the The electrode is electrically connected to a bit line. That is, the source electrode of the transistor 160 of the memory cell 190 provided at the other end is , and are electrically connected to the source line. In FIG. 8A, the source line SL and the bit line B However, the present invention is not limited to this, and the source line SL and the A configuration having a plurality of bit lines BL may also be used.

[0164] The semiconductor device shown in FIG. 8A performs writing and reading operations for each row. The write operation is performed as follows: Transistor 16 is connected to the second signal line S2 of the row to be written. 2 is turned on, and the transistor 162 of the row to be written is turned on. As a result, the voltage of the first signal line S1 is applied to the gate electrodes of the transistors 160 in the specified row. A predetermined charge is applied to the gate electrode. Data can be written to the memory cells.

[0165] The read operation is performed as follows: First, the word lines WL other than the row from which the read is to be performed are connected. Therefore, the transistor 160 is turned on regardless of the charge on the gate electrode of the transistor 160. A potential is applied so that the transistors 160 in the rows other than the row to be read out are turned on. Then, a constant potential is applied to the source line SL, and the bit line BL is connected to a read circuit (not shown). Here, a plurality of transistors 160 between the source line SL and the bit line BL are connected to the read Since all rows except for the one that is being read are on, the conductance between the source line SL and the bit line BL is The state of the transistor 160 in the row being read is determined. The readout circuit detects the charge on the gate electrode of the transistor 160 in the row that is being read out. The potential of the bit line BL to be read is different. The data can be read out.

[0166] Next, the semiconductor device shown in FIG. 8B includes a source line SL, a bit line BL, a first signal line S1, The memory cell array includes a plurality of second signal lines S2 and word lines WL, and a plurality of memory cells 190. The gate electrode of each transistor 160 and the source electrode or drain of each transistor 162 One of the drain electrodes and one of the electrodes of the capacitor 164 are electrically connected. The source line SL and the source electrode of the transistor 160 are electrically connected, and the bit line B L is electrically connected to the drain electrode of the transistor 160. The line S1 and the other of the source electrode and the drain electrode of the transistor 162 are electrically connected. The second signal line S2 and the gate electrode of the transistor 162 are electrically connected. The word line WL and the other electrode of the capacitor 164 are electrically connected to each other.

[0167] The semiconductor device shown in FIG. 8B performs writing and reading operations for each row. The read operation is performed in the same manner as in the semiconductor device shown in FIG. This is done as follows: First, the word line WL of the row to be read is connected to the transistor 160. The on or off state of transistor 160 is selected depending on the charge carried by the gate electrode. Then, a constant potential is applied to the source line SL, and the bit line BL is read. The transistors 160 in the unselected rows are in the off state. Here, the conductance between the source line SL and the bit line BL is This is determined by the state of the row transistor 160. The potential of the gate electrode of the transistor 160 determines the potential of the bit line BL read by the read circuit. In this way, data can be read from the memory cells in a specified row. .

[0168] The semiconductor device shown in FIGS. 8A and 8B is a transistor using a material other than an oxide semiconductor. Since the register 160 is capable of sufficiently high-speed operation, it is possible to read out the memory contents at high speed. Furthermore, the off-state current of the transistor 162 including an oxide semiconductor is extremely small. Therefore, by turning off the transistor 162, The potential of the gate electrode of transistor 160 can be maintained for a very long time. In addition, by including the capacitor 164, the gate electrode of the transistor 160 This makes it easier to hold a given charge and to read out the stored contents.

[0169] In the semiconductor device configured with a plurality of memory cells as described above, the storage capacity is In order to reduce the unit cost, it is necessary to reduce the area occupied by each memory cell. In order to solve this problem, for example, in the NAND type semiconductor device shown in FIG. By configuring the serially connected transistors 160 as shown in the cross-sectional view of FIG. As a result, the area occupied by each memory cell can be reduced. These correspond to the cross sections C1-C2 and D1-D2 in (B).

[0170] In the semiconductor device shown in FIG. 9A, a transistor 160 provided in a substrate 100 is The impurity region 120 (also simply referred to as the impurity region) and the metal compound region 124 are adjacent to each other. In other words, the transistor 160 is sandwiched between the The heavily doped region 120 and the metal compound region 124 form the source of one of the transistors 160. region and serves as the drain region of the other transistor 160 .

[0171] Further, an interlayer insulating layer 126 and an interlayer insulating layer 128 are formed so as to cover the transistor 160. At the end of the series-connected transistors 160, the interlayer insulating layer 12 6 and the metal compound region 124 through an opening formed in the interlayer insulating layer 128. An electrode 192 is formed to connect the two layers.

[0172] Here, the transistor 160 is substantially the same as the transistor 160 shown in FIG. 1 of the first embodiment. For details, please refer to the above. In this embodiment, in order to achieve high integration of the transistor 160, the sidewall insulating layer 1 shown in FIG. The configuration does not include 18.

[0173] The configuration shown in FIG. 9A can be used not only in the NAND type semiconductor device shown in FIG. It can also be used in the NOR type semiconductor device shown in FIG. In this case, the memory cells of adjacent columns are arranged symmetrically, and the memory cells of adjacent columns are arranged The transistor 160 of the transistor is connected to the high concentration impurity region 120 and the metal compound region 124. In this case, at least two transistors 160 are connected. , are connected via the high concentration impurity region 120 and the metal compound region 124 .

[0174] By connecting a plurality of transistors 160 in the above configuration, the transistor 16 0 and memory cells 190 can be highly integrated. The unit price per capacity can be reduced.

[0175] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination.

[0176] (Fourth embodiment) Next, FIG. 10 shows a modified example of the configuration of the semiconductor device.

[0177] The semiconductor device shown in FIG. 10A is a modified example of the semiconductor device shown in FIG.

[0178] The difference between the configuration shown in FIG. 10(A) and the configuration shown in FIG. 1(A) is that the electrode 130c is 1(A) is electrically connected to the metal compound region provided in the metal compound region 10. In the configuration shown in FIG. 1, the source electrode or drain electrode 142a and the gate electrode 110 are electrically connected. , whereas in the configuration shown in FIG. 10(A), the source electrode or the drain electrode is connected to The electrode 142a and the metal compound region are electrically connected.

[0179] The structure shown in FIG. 10A is similar to the semiconductor device shown in the previous embodiment. In this way, semiconductor devices with different circuit configurations can be realized.

[0180] The semiconductor device shown in FIG. 10B is a modified example of the semiconductor device shown in FIG.

[0181] The difference between the configuration shown in FIG. 10B and the configuration shown in FIG. 6A is that the electrode 130c is 6(A) is electrically connected to the metal compound region provided in the metal compound region 10. In the configuration shown in FIG. 1, the source electrode or drain electrode 142a and the gate electrode 110 are electrically connected. , whereas in the configuration shown in FIG. 10(B), the source electrode or the drain electrode is connected to The electrode 142a and the metal compound region are electrically connected.

[0182] The structure shown in FIG. 10B is the same as the semiconductor device shown in the previous embodiment. In this way, semiconductor devices with different circuit configurations can be realized.

[0183] The structures, methods, and the like described in this embodiment may be combined as appropriate with the structures, methods, and the like described in other embodiments. They can be used in combination.

[0184] (Embodiment 5) Next, the transistor 162 in the previous embodiment (Embodiment 1, etc.) FIG. 1 shows another example of a method for manufacturing a transistor including an oxide semiconductor. In this embodiment, a highly purified oxide semiconductor (particularly, an amorphous In the following, we will explain in detail the case where a top gate type transistor is used. Although a transistor is used as an example, the transistor structure does not have to be limited to the top gate type. stomach.

[0185] First, an insulating layer 202 is formed on a lower substrate 200. Then, an oxide film is formed on the insulating layer 202. A semiconductor layer 206 is formed (see FIG. 11(A)).

[0186] For example, the lower layer substrate 200 may be the same as that of the semiconductor device of the previous embodiment (FIG. 1 or FIG. 6, etc.). The structure below the interlayer insulating layer 128 can be used as the structure for the above-mentioned embodiment. The surface of the lower substrate 200 is as flat as possible. For example, it is desirable to reduce the height difference on the surface by using a chemical mechanical polishing method (CMP method). , 5 nm or less, preferably 1 nm or less. Alternatively, the root mean square of the surface roughness (RMS) may be set to 2 nm or less, preferably 0.4 nm or less.

[0187] The insulating layer 202 functions as a base, and is different from the insulating layer 138 in the previous embodiment. It can be formed in the same manner as the insulating layer 144. For details, refer to the previous embodiment. Note that the insulating layer 202 is formed so as not to contain hydrogen or water as much as possible. It is desirable that:

[0188] The oxide semiconductor layer 206 is made of a quaternary metal oxide such as In—Sn—Ga—Zn—O, or a ternary metal oxide such as In—Sn—Ga—Zn—O. The metal oxides In-Ga-Zn-O, In-Sn-Zn-O, and In-Al- Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn-O and binary metal oxides such as In-Zn-O, Sn-Zn-O, and Al-Zn-O. , Zn-Mg-O system, Sn-Mg-O system, In-Mg-O system, In-O system, Sn-O system The insulating film 10 can be formed using an oxide semiconductor such as a Zn—O-based semiconductor.

[0189] Among these, In-Ga-Zn-O oxide semiconductor materials have sufficiently high resistance in the absence of an electric field. It is possible to sufficiently reduce the electron current and the field effect mobility is high, so it is It is suitable as a semiconductor material for use in devices.

[0190] A typical example of an In-Ga-Zn-O oxide semiconductor material is InGaO3(ZnO). m (m>0). Also, M is used instead of Ga, and InMO3(Zn O) m There are oxide semiconductor materials that are written as (m>0), where M is gallium. (Ga), aluminum (Al), iron (Fe), nickel (Ni), manganese (Mn), It refers to one or more metal elements selected from the group consisting of cobalt (Co), etc. For example, M includes Ga, Ga and Al, Ga and Fe, Ga and Ni, and Ga and Mn. The above composition is derived from the crystal structure. Please note that this is merely an example.

[0191] The oxide semiconductor layer 206 is formed by sputtering using a target such as In: A material represented by the formula Ga:Zn=1:x:y (x is 0 or more, y is 0.5 or more and 5 or less) For example, In:Ga:Zn=1:1:1 [atomic ratio] (x=1, y= 1), (i.e., In2O3:Ga2O3:ZnO=1:1:2 [molar ratio]) Alternatively, a target having a composition ratio of In:Ga:Zn=1:1:0.5 may be used. [atom ratio] (x=1, y=0.5) and In:Ga:Z A target with a composition ratio of n=1:1:2 (x=1, y=2) and In : A target having a composition ratio of Ga:Zn=1:0:1 [atom ratio] (x=0, y=1) A marker can also be used.

[0192] The relative density of the metal oxide in the metal oxide target is 80% or more, preferably 95% or more; More preferably, it is 99.9% or more. A metal oxide target with a high relative density is used. This makes it possible to form the oxide semiconductor layer 206 with a dense structure.

[0193] In this embodiment, the amorphous oxide semiconductor layer 206 is made of an In—Ga—Zn—O-based metal. The film is formed by sputtering using a metal oxide target.

[0194] The oxide semiconductor layer 206 is formed in a rare gas (typically, argon) atmosphere or an oxygen atmosphere. It is preferable to use a mixed atmosphere of oxygen or a rare gas (typically argon) and oxygen. Specifically, impurities such as hydrogen, water, hydroxyl groups, and hydrides are present at a concentration of 1 ppm or less. It is preferable to use a high-purity gas atmosphere in which the concentration has been reduced to 10 ppb or less. is.

[0195] When the oxide semiconductor layer 206 is formed, for example, the substrate is placed in a processing chamber maintained in a reduced pressure state. The substrate temperature is maintained at 100°C or higher and lower than 550°C, preferably 200°C or higher and 400°C or lower. Then, the substrate is heated to remove the moisture in the processing chamber and hydrogen and water are removed. The oxide semiconductor layer 206 is formed using the target. The oxide semiconductor layer 206 is formed while the substrate is heated. It is possible to reduce impurities contained in the material. It also reduces damage caused by sputtering. To remove moisture from the processing chamber, an adsorption type vacuum pump can be used. For example, cryopumps, ion pumps, titanium sublimation pumps, etc. A turbo molecular pump with a cold trap can also be used. Hydrogen and water can be removed from the processing chamber by evacuating it using a cryopump. Therefore, the impurity concentration in the oxide semiconductor layer 206 can be reduced.

[0196] The oxide semiconductor layer 206 is formed under the conditions, for example, when the distance between the substrate and the target is 1 70 mm, pressure 0.4 Pa, direct current (DC) power 0.5 kW, atmosphere oxygen (oxygen 10 0%) atmosphere, or argon (100% argon) atmosphere, or a mixture of oxygen and argon It is possible to apply conditions such as a mixed atmosphere. This reduces dust (powder-like substances formed during film formation) and makes the film thickness distribution uniform. The thickness of the oxide semiconductor layer 206 is 2 nm to 200 nm, preferably 5 However, the thickness is determined depending on the oxide semiconductor material and the application of the semiconductor device. The appropriate thickness varies depending on the material and application. That's fine.

[0197] Note that before the oxide semiconductor layer 206 is formed by a sputtering method, argon gas is Inverse sputtering is performed by introducing a gas to generate plasma, and deposits on the surface of the insulating layer 202 are removed. Here, the reverse sputtering is performed by removing the In this case, instead of bombarding the sputtering target with ions, the ions are bombarded on the surface to be treated. This refers to a method of modifying the surface by bombarding the surface with ions. The method is to apply a high frequency voltage to the surface to be treated in an argon atmosphere, and then apply a proton to the surface near the substrate. In addition, nitrogen, helium, or oxygen can be used instead of argon. The atmosphere may be changed as follows.

[0198] Next, the oxide semiconductor layer 206 is processed by a method such as etching using a mask. An island-shaped oxide semiconductor layer 206a is formed.

[0199] The oxide semiconductor layer 206 can be etched by either dry etching or wet etching. Of course, both of them can be used in combination. The etching conditions (etching temperature) are adjusted to suit the material so that the layer can be etched into the desired shape. The etching gas, etching solution, etching time, temperature, etc. are set appropriately. The etching may be performed in the same manner as the etching of the oxide semiconductor layer in the above embodiment. For details of etching conditions and the like, please refer to the previous embodiment.

[0200] After that, the oxide semiconductor layer 206a is preferably subjected to heat treatment (first heat treatment). The first heat treatment removes excess hydrogen (water or hydroxyl groups) from the oxide semiconductor layer 206a. The structure of the oxide semiconductor layer is adjusted, and the energy The defect level in the gap can be reduced. The temperature of the first heat treatment is, for example, 300 The temperature is set to 550°C or higher, or 400°C or higher and 500°C or lower. When wet etching is used after etching, This has the advantage of reducing the time required.

[0201] The heat treatment is carried out by, for example, placing the lower substrate 200 in an electric furnace using a resistance heating element or the like, and heating the lower substrate 200 in a nitrogen atmosphere. The heat treatment can be performed under the conditions of air, 450° C., and 1 hour. Do not expose to the air and prevent contamination with water or hydrogen.

[0202] The heat treatment device is not limited to an electric furnace, and may be heat conduction from a medium such as a heated gas, or A device that heats the object to be treated by thermal radiation may be used. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be equipped with halogen lamps, metal halide lamps, etc. Lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure water A device that heats the object to be treated by radiating light (electromagnetic waves) emitted from a lamp such as a silver lamp. The GRTA device is a device that performs heat treatment using high-temperature gas. An inert gas that does not react with the material to be treated by heat treatment, such as a rare gas such as argon or nitrogen. A gas is used.

[0203] For example, in the first heat treatment, the substrate is placed in a heated inert gas atmosphere and heated for several minutes. After that, a GRTA process may be performed in which the substrate is removed from the inert gas atmosphere. Treatment A allows high-temperature heat treatment in a short time. This makes it possible to apply the process even under temperature conditions that exceed the heat resistance temperature of the substrate. The reactive gas may be switched to a gas containing oxygen. By doing this, it is possible to reduce the defect level in the energy gap caused by oxygen vacancies. This is because

[0204] The inert gas atmosphere is nitrogen or a rare gas (helium, neon, argon, etc.). It is desirable to use an atmosphere containing ) as the main component and not containing water, hydrogen, etc. For example, nitrogen and rare gases such as helium, neon, and argon introduced into a heat treatment device Purity should be 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher ( That is, the impurity concentration is set to 1 ppm or less, preferably 0.1 ppm or less.

[0205] In any case, the first heat treatment reduces impurities and makes the silicon nitride into an i-type or substantially i-type. By forming the oxide semiconductor layer 206a, a transistor with excellent characteristics can be realized. It is possible.

[0206] The first heat treatment is performed on the oxide semiconductor layer 206 before it is processed into the island-shaped oxide semiconductor layer 206a. In this case, the lower substrate 20 is removed from the heating device after the first heat treatment. 0 is extracted and the photolithography process is carried out.

[0207] The first heat treatment has the effect of removing hydrogen and water, so the first heat treatment is called dehydration treatment. The dehydration treatment or the dehydrogenation treatment may be called hydrogenation treatment or the like. After forming the oxide semiconductor layer 206a or after stacking a source electrode or a drain electrode over the oxide semiconductor layer 206a, It is also possible to carry out such dehydration treatment and dehydrogenation at the timing of The treatment may be carried out not only once but also multiple times.

[0208] Next, a conductive layer is formed in contact with the oxide semiconductor layer 206a. The source or drain electrode 208a, the source or drain electrode The source electrode 208b is formed (see FIG. 11(B)). The process is similar to that for the electrode or drain electrode 142a. The embodiments can be referred to.

[0209] Next, a gate insulating layer 212 is formed in contact with a part of the oxide semiconductor layer 206a (FIG. 11). For details, please refer to the description of the insulating layer 138 in the previous embodiment. It is possible.

[0210] After the gate insulating layer 212 is formed, a second thermal treatment is performed in an inert gas atmosphere or an oxygen atmosphere. The temperature of the heat treatment is 200°C or higher and 450°C or lower, preferably 25 The temperature is between 0°C and 350°C. For example, heat treatment can be performed at 250°C for 1 hour in a nitrogen atmosphere. By performing the second heat treatment, the variation in the electrical characteristics of the transistors can be reduced. When the gate insulating layer 212 contains oxygen, the oxide semiconductor layer 206 Oxygen is supplied to the oxide semiconductor layer 206a, and oxygen vacancies in the oxide semiconductor layer 206a are compensated for, resulting in an i-type (intrinsic) semiconductor. Alternatively, an oxide semiconductor layer that is as close to i-type as possible can be formed.

[0211] In this embodiment, the second heat treatment is performed after the gate insulating layer 212 is formed. The timing of the second heat treatment is not particularly limited to this.

[0212] Next, a gate electrode was formed on the gate insulating layer 212 in a region overlapping with the oxide semiconductor layer 206a. The gate electrode 214 is formed on the gate insulating layer 212 (see FIG. 11(D)). After forming a conductive layer on the substrate, the conductive layer is selectively patterned to form the insulating film. For details, please refer to the description of the gate electrode 148a in the previous embodiment. You can pour drinks.

[0213] Next, an interlayer insulating layer 216 and an interlayer insulating film 218 are formed on the gate insulating layer 212 and the gate electrode 214. An edge layer 218 is formed (see FIG. 11(E)). The interlayer insulating layer 216 and the interlayer insulating layer 218 The film can be formed by using a PVD method, a CVD method, etc. Silicon nitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, etc. The insulating layer 100 can be formed using a material containing an organic insulating material. The insulating layer 216 and the interlayer insulating layer 218 are stacked in a layered structure. There are no limitations on the number of layers, and the structure may be a single layer or a laminated structure of three or more layers.

[0214] It is desirable that the interlayer insulating layer 218 be formed so that its surface is flat. By forming the interlayer insulating layer 218 so that the surface is flat, it is possible to form an electrode on the interlayer insulating layer 218. This is because electrodes, wiring, etc. can be formed in a suitable manner.

[0215] Through the above steps, the transistor 250 including the highly purified oxide semiconductor layer 206a is completed. (See FIG. 11(E)).

[0216] The transistor 250 shown in FIG. 11(E) is disposed on the lower substrate 200 via the insulating layer 202. The oxide semiconductor layer 206a is electrically connected to the source a source or drain electrode 208a, a source or drain electrode 208b, and an oxide semiconductor The conductor layer 206a, the source electrode or the drain electrode 208a, the source electrode or the drain electrode a gate insulating layer 212 covering the electrode 208b; and a gate electrode 214 on the gate insulating layer 212. An interlayer insulating layer 216 on the gate insulating layer 212 and the gate electrode 214; and an interlayer insulating layer 218.

[0217] In the transistor 250 described in this embodiment, the oxide semiconductor layer 206a is highly purified. Therefore, the hydrogen concentration is 5×10 19 atoms / cm 3 Below, preferably 5 x10 18 atoms / cm 3 Less than or equal to 5×10 17 atoms / cm 3 Below The carrier density of the oxide semiconductor layer 206a is lower than that of a general silicon wafer. carrier density (1×10 14 / cm 3 A sufficiently small value (e.g., , 1×10 12 / cm 3 less than 1.45 x 10 10 / cm 3 (less than) This results in a sufficiently small off-state current. When the thickness of the oxide semiconductor layer is 30 nm, the drain voltage is 1 V to 10 V. When the gate-source voltage is in the range of about 0V, the off-state current (the drain current when the gate-source voltage is 0V or less) current) is 1×10 -13 A or less. Or, the off-current density at room temperature (off-current divided by the transistor channel width) is 1 x 10 -20 A / μm (10zA / μm) From 1×10 -19 A / μm (100zA / μm).

[0218] In addition to the off-state current and off-state current density, the characteristics of the above-mentioned transistors include the off-state resistance (transistor Resistivity (resistance when the transistor is off) and off resistivity (resistivity when the transistor is off) Here, the off-resistance R can be expressed using the off-current and drain voltage as The off-resistivity ρ is a value calculated from Ohm's law. This value can be calculated from ρ=RA / L using the area A and the channel length L. In the above case, the off-resistivity is 1×10 9Ω·m or more (or 1×10 10 Ω·m or more) The cross-sectional area A is expressed as A=dW, where d is the thickness of the oxide semiconductor layer and W is the channel width. will be done.

[0219] By using the oxide semiconductor layer 206a that has been highly purified and made intrinsic, Therefore, the off-state current of the transistor can be sufficiently reduced.

[0220] In this embodiment, a transistor Although the case where the stan 250 is used has been described, it is not necessary to interpret the disclosed invention as being limited to this case. For example, by sufficiently improving the electrical properties of oxide semiconductors, It is also possible to use an oxide semiconductor for all transistors including the transistor. In such a case, it is not necessary to have a laminated structure as shown in the previous embodiment. To achieve good circuit operation, the field-effect mobility μ of the oxide semiconductor must be μ > 100 cm 2 In this case, it is desirable to use a glass substrate or other substrate for the semiconductor. It is possible to form a body device.

[0221] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0222] (Sixth embodiment) Next, the transistor 162 in the previous embodiment (Embodiment 1, etc.) FIG. 1 shows another example of a method for manufacturing a transistor including an oxide semiconductor, which can be used for the In this embodiment, the oxide semiconductor layer has a crystalline region. A first oxide semiconductor layer and a second oxide semiconductor layer grown as crystals from a crystalline region of the first oxide semiconductor layer. In the following, the case where a top gate type semiconductor layer is used will be described in detail. However, the transistor structure does not necessarily have to be limited to a top-gate type. There's no need.

[0223] First, an insulating layer 302 is formed on a lower substrate 300. Then, a first insulating layer 302 is formed on the insulating layer 302. An oxide semiconductor layer is formed, and a first heat treatment is performed to form a first oxide semiconductor layer on at least the surface of the first oxide semiconductor layer. The region containing the oxide semiconductor layer is crystallized to form the first oxide semiconductor layer 304 (see FIG. 12A). ).

[0224] For example, the lower layer substrate 300 may be the same as that of the semiconductor device of the previous embodiment (FIG. 1 or FIG. 6, etc.). The structure below the interlayer insulating layer 128 can be used as the structure for the above-mentioned embodiment. The surface of the lower substrate 300 is as flat as possible. For example, it is desirable to reduce the height difference on the surface by using a chemical mechanical polishing method (CMP method). , 5 nm or less, preferably 1 nm or less. Alternatively, the root mean square of the surface roughness (RMS) may be set to 2 nm or less, preferably 0.4 nm or less.

[0225] The insulating layer 302 functions as a base, and is different from the insulating layer 138 in the previous embodiment. It can be formed in the same manner as the insulating layer 144. For details, refer to the previous embodiment. Note that the insulating layer 302 is formed so as not to contain hydrogen or water as much as possible. It is desirable that:

[0226] The first oxide semiconductor layer is formed in the same manner as the oxide semiconductor layer 206 in the above embodiment. The details of the first oxide semiconductor layer and the method for forming the same can be found in the previous embodiment. However, in this embodiment, the first oxide is formed by the first heat treatment. In order to intentionally crystallize the semiconductor layer, the first layer is formed using an oxide semiconductor that is easily crystallized. It is desirable to form an oxide semiconductor layer. Examples of such an oxide semiconductor include: ZnO, etc. In addition, oxide semiconductors such as In-Ga-Zn-O are also available. For example, a high concentration of Zn is easily crystallized, and the metal elements of Zn (In, Ga, Zn) A ratio of 60% or more is desirable for this purpose. The thickness of the semiconductor layer is preferably 3 nm or more and 15 nm or less. However, depending on the oxide semiconductor material and the application of the semiconductor device, the thickness may vary. The appropriate thickness varies depending on the material and application. good.

[0227] The temperature of the first heat treatment is 550°C or higher and 850°C or lower, preferably 600°C or higher and 750°C or lower. The heat treatment time should preferably be between 1 minute and 24 hours. The temperature and time of the heat treatment vary depending on the type of oxide semiconductor. The atmosphere for the heat treatment is preferably an atmosphere that does not contain hydrogen or water. The atmosphere is nitrogen, oxygen, or rare gas (helium, neon, argon, etc.) from which oxygen has been sufficiently removed. It is possible.

[0228] Heat treatment equipment includes electric furnaces, as well as equipment that uses heat conduction from a medium such as heated gas or heat radiation. For example, a GRTA (Gas Ra pid Thermal Anneal) device, LRTA (Lamp Rapid Th RTA (Rapid Thermal Anneal) equipment l) The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure mercury lamps It is a device that heats the object to be treated by radiating light (electromagnetic waves) emitted from a lamp such as a The GRTA device is a device that performs heat treatment using high-temperature gas. Inert gases that do not react with the material to be treated by heat treatment, such as rare gases such as fluorine or nitrogen. is used.

[0229] By the first heat treatment, at least a region including the surface of the first oxide semiconductor layer is crystalline. The crystalline region extends from the surface of the first oxide semiconductor layer to the inside of the first oxide semiconductor layer. The crystalline region is formed by the progress of crystal growth toward the It may contain plate-like crystals with an average thickness of 2 nm to 10 nm. The oxide semiconductor layer has an ab-plane that is substantially parallel to the surface thereof, and a c-axis that is substantially perpendicular to the surface thereof. In this case, "almost parallel" means within ±10° from the parallel direction. "Approximately perpendicular" refers to a state within ±10° from the perpendicular direction.

[0230] Furthermore, the first heat treatment forms a crystalline region and also removes hydrogen from the first oxide semiconductor layer. It is desirable to remove hydrogen and other substances (including water and hydroxyl groups). Nitrogen and acid with a purity of 6N (99.9999%) or more (i.e., impurity concentration of 1 ppm or less) The first heat treatment is preferably performed in a nitrogen or rare gas (helium, neon, argon, etc.) atmosphere. More preferably, the purity is 7N (99.99999%) or more (i.e., the concentration of impurities is 0.1 In addition, it is preferable to use an ultra-dry atmosphere with H2O of 20 ppm or less. Alternatively, the first heat treatment may be carried out in ultra-dry air with an H2O concentration of 1 ppm or less.

[0231] Furthermore, the first heat treatment is performed to form a crystalline region and to supply oxygen to the first oxide semiconductor layer. For example, by changing the atmosphere for heat treatment to an oxygen atmosphere, Oxygen can be supplied to the oxide semiconductor layer 1.

[0232] In this embodiment, the first heat treatment is performed at 700° C. for 1 hour in a nitrogen atmosphere. After removing hydrogen and the like from the oxide semiconductor layer, the atmosphere was changed to an oxygen atmosphere. The first heat treatment is performed to supply oxygen to the inside of the first oxide semiconductor layer. Since this is the formation of the region, the removal of hydrogen and other substances and the treatment for the purpose of supplying oxygen must be carried out separately. For example, after heat treatment to remove hydrogen and other substances or treatment to supply oxygen, It is possible to carry out a heat treatment for crystallization.

[0233] By such a first heat treatment, a crystalline region is formed and hydrogen (including water and hydroxyl groups) is removed. The oxygen-supplied first oxide semiconductor layer is obtained.

[0234] Next, a first oxide semiconductor layer 304 having a crystalline region at least in a region including a surface thereof is formed with a A second oxide semiconductor layer 305 is formed (see FIG. 12B).

[0235] The second oxide semiconductor layer 305 is formed in the same manner as the oxide semiconductor layer 206 in the above embodiment. The details of the second oxide semiconductor layer 305 and the method for forming the second oxide semiconductor layer 305 are described below. The above embodiment may be referred to. However, the second oxide semiconductor layer 305 is formed by It is desirable to form the first oxide semiconductor layer 304 thicker than the first oxide semiconductor layer 304. The first oxide semiconductor layer 304 and the second oxide semiconductor layer 305 are formed so that the sum of their thicknesses is 3 nm to 50 nm. It is preferable to form the oxide semiconductor layer 305 of the oxide semiconductor material 2. The appropriate thickness varies depending on the material and application of the semiconductor device. The method may be selected depending on the purpose.

[0236] The second oxide semiconductor layer 305 is made of a material having the same main component as the first oxide semiconductor layer 304. Therefore, it is desirable to use materials with close lattice constants after crystallization (mismatch of 1% or less). When such a material is used, the second oxide semiconductor layer 305 is crystallized. This is because crystal growth using the crystalline region of the first oxide semiconductor layer 304 as a seed is likely to proceed. Furthermore, when the main components are the same, the interface properties and electrical characteristics are also improved.

[0237] If the desired film quality can be obtained by crystallization, a second film may be formed using a material with a different main component. Alternatively, the oxide semiconductor layer 305 may be formed as follows.

[0238] Next, the second oxide semiconductor layer 305 is subjected to a second heat treatment, and the first oxide semiconductor layer 304 The crystalline region is used as a seed for crystal growth to form a second oxide semiconductor layer 306 (FIG. 12). (C))).

[0239] The temperature of the second heat treatment is 550°C or higher and 850°C or lower, preferably 600°C or higher and 750°C or lower. The heating time for the second heat treatment is 1 minute or more and 100 hours or less, preferably 5 hours or more. The heat treatment time is set to 20 hours or less, typically 10 hours. It is desirable that the atmosphere used for the process does not contain hydrogen, water, etc.

[0240] The details of the atmosphere and the effects of the heat treatment are the same as those of the first heat treatment. The heat treatment apparatus that can perform this is the same as that for the first heat treatment. The inside of the furnace is sometimes in a nitrogen atmosphere, and when cooling, the inside of the furnace is in an oxygen atmosphere. Hydrogen and the like can be removed in the atmosphere, and oxygen can be supplied in the oxygen atmosphere.

[0241] By performing the second heat treatment as described above, the oxide semiconductor layer 304 formed in the first oxide semiconductor layer 304 Crystal growth is promoted from the crystalline region to the entire second oxide semiconductor layer 305, and the second oxide semiconductor A conductor layer 306 can be formed. In addition, hydrogen (including water and hydroxyl groups) and the like are removed. In this case, the second oxide semiconductor layer 306 to which oxygen is supplied can be formed. The heat treatment can improve the orientation of the crystalline region of the first oxide semiconductor layer 304. be.

[0242] For example, an In—Ga—Zn—O-based oxide semiconductor material is used for the second oxide semiconductor layer 306. In this case, the second oxide semiconductor layer 306 is InGaO3 (ZnO) m (m: integer) and crystals represented by In2Ga2ZnO7 (In:Ga:Zn:O=2:2:1:7). Such crystals may include crystals whose c-axes are aligned in the second direction by the second heat treatment. The oxide semiconductor layer 306a is oriented in a direction substantially perpendicular to the surface of the oxide semiconductor layer 306a.

[0243] Here, the above-mentioned crystal contains any one of In, Ga, and Zn, and has an a-axis and It can be understood as a stacked structure of layers parallel to the a-axis and b-axis. In general, the crystals described above are composed of layers containing In and layers not containing In (Ga or The layer has a structure in which layers containing Zn or Zn are stacked in the c-axis direction.

[0244] In the case of In-Ga-Zn-O based oxide semiconductor crystals, the in-plane direction of the layer containing In, That is, the conductivity in the direction parallel to the a-axis and b-axis is good. In a-Zn-O oxide semiconductor crystals, electrical conduction is mainly controlled by In. , and the 5s orbital of one In atom overlaps with the 5s orbital of the adjacent In atom. , as career paths are formed.

[0245] In addition, the first oxide semiconductor layer 304 may have an amorphous region at the interface with the insulating layer 302. In the case of the structure, the second heat treatment is performed to form a thin film on the surface of the first oxide semiconductor layer 304. Crystal growth proceeds from the crystalline region under the first oxide semiconductor layer downward, and the non-crystalline region The crystalline region may be crystallized depending on the material of the insulating layer 302 and the conditions of the heat treatment. Depending on the conditions, the amorphous region may remain.

[0246] The first oxide semiconductor layer 304 and the second oxide semiconductor layer 305 are made of oxide semiconductors having the same main component. When a dielectric material is used, as shown in FIG. 12C, a first oxide semiconductor layer 304 and a second oxide semiconductor layer 305 are formed. The oxide semiconductor layer 306 may have the same crystal structure as the oxide semiconductor layer 306 in FIG. In C), the dotted line indicates the distance between the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306. The boundary between the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306 becomes indistinguishable. In some cases they can be considered the same layer.

[0247] Next, the first oxide semiconductor layer 304 and the The second oxide semiconductor layer 306 is processed to form the first oxide semiconductor layer 304a and the second oxide semiconductor layer 306b. An oxide semiconductor layer 306a is formed (see FIG. 12D). After the treatment, the oxide semiconductor is processed into an island-shaped oxide semiconductor layer. In this case, a second heat treatment may be performed after the first heat treatment. However, there is an advantage in that the time required for etching can be shortened.

[0248] The first oxide semiconductor layer 304 and the second oxide semiconductor layer 306 are etched using a dry etching method. Either etching or wet etching may be used. Of course, a combination of both may also be used. The material can be used in combination so that the oxide semiconductor layer can be etched into a desired shape. Etching conditions (etching gas, etching solution, etching time, temperature, etc.) The etching time of the first oxide semiconductor layer 304 and the second oxide semiconductor layer 306 is set appropriately. The etching can be performed in a manner similar to the etching of the oxide semiconductor layer in the above embodiment. For details, please refer to the previous embodiment.

[0249] Note that a region of the oxide semiconductor layer that serves as a channel formation region has a flat surface. For example, it is desirable that the height difference of the surface of the second oxide semiconductor layer 306 is such that the surface overlaps with the gate electrode. In the region where the layers overlap (channel formation region), the thickness is 1 nm or less (preferably 0.2 nm or less). It is preferable to have one.

[0250] Next, a conductive layer is formed in contact with the second oxide semiconductor layer 306a. The conductive layer is selectively etched to form the source or drain electrode 308a, the source or drain electrode 308b, The source or drain electrode 308b is formed (see FIG. 12(D)). The electrode 308a and the source or drain electrode 308b are the same as those in the previous embodiment. The source or drain electrode 142a has a shape similar to that of the source or drain electrode 142b. For details, please refer to the above embodiment.

[0251] In the step shown in FIG. 12D, the first oxide semiconductor layer 304a and the second oxide semiconductor layer On the side of the conductor layer 306a, a source or drain electrode 308a, a source or drain electrode Alternatively, the crystalline layer in contact with the drain electrode 308b may become amorphous. The entire region of the first oxide semiconductor layer 304a and the second oxide semiconductor layer 306a is crystalline. It doesn't necessarily have to be a structure.

[0252] Next, a gate insulating layer 312 is formed in contact with part of the second oxide semiconductor layer 306a. The gate insulating layer 312 can be formed by using a CVD method, a sputtering method, or the like. Then, the first oxide semiconductor layer 304a and the second oxide semiconductor layer 304b on the gate insulating layer 312 are A gate electrode 314 is formed in a region overlapping with the layer 306a. An interlayer insulating layer 316 and an interlayer insulating layer 318 are formed on the gate electrode 314 (FIG. 12(E)). The gate insulating layer 312, the gate electrode 314, the interlayer insulating layer 316 and the layer The interlayer insulating layer 318 is the same as the insulating layer 138, the gate electrode 148a, and the interlayer insulating layer 318 in the previous embodiment. The insulating layer 216 and the insulating interlayer 218 can be formed in the same manner. Please refer to the embodiment of the present invention.

[0253] After the gate insulating layer 312 is formed, a third heat treatment is performed in an inert gas atmosphere or an oxygen atmosphere. The temperature of the third heat treatment is preferably 200°C or higher and 450°C or lower. The temperature is 250°C or higher and 350°C or lower. For example, By performing the third heat treatment, the electrical characteristics of the transistor are improved. In addition, when the gate insulating layer 312 is an insulating layer containing oxygen, In this case, oxygen is supplied to the second oxide semiconductor layer 306a, and the oxygen in the second oxide semiconductor layer 306a is Compensating for the electron deficiency to form an i-type (intrinsic semiconductor) or an oxide semiconductor layer that is as close to i-type as possible You can also do this.

[0254] In this embodiment, the third heat treatment is performed after the gate insulating layer 312 is formed. The timing of the third heat treatment is not limited to this. In addition, the timing of the third heat treatment may be set to other treatments such as the second heat treatment. Therefore, when oxygen is supplied to the second oxide semiconductor layer, the third heat treatment can be omitted. good.

[0255] As a result of the above, the first oxide semiconductor layer 304a and the A transistor 350 including a second oxide semiconductor layer 306a grown from a crystalline region is completed (see Figure 12(E)).

[0256] The transistor 350 shown in FIG. 12(E) is provided on the lower substrate 300 via the insulating layer 302. The first oxide semiconductor layer 304a is formed on the first oxide semiconductor layer 304a. The second oxide semiconductor layer 306a is electrically connected to the second oxide semiconductor layer 306a. A source or drain electrode 308a, a source or drain electrode 308b, and a the second oxide semiconductor layer 306a, the source or drain electrode 308a, the source or drain electrode 308b, The gate insulating layer 312 covers the drain electrode 308b, and the gate electrode 308b is formed on the gate insulating layer 312. a gate insulating layer 312 and an interlayer insulating layer 316 on the gate electrode 314; and an interlayer insulating layer 318 on the edge layer 316.

[0257] In the transistor 350 described in this embodiment, the first oxide semiconductor layer 304a and Since the second oxide semiconductor layer 306a and the second oxide semiconductor layer 306b are highly purified, the hydrogen concentration in the second oxide semiconductor layer 306a is 5×10 19 / cm 3 Below 5×10 18 / cm 3 Less than or equal to 5×10 17 / cm 3 The carrier density of the oxide semiconductor layer 206a is as follows: Carrier density in the silicon wafer (1×10 14 / cm 3 is sufficiently small compared to value (e.g., 1×10 12 / cm 3 less than 1.45 x 10 10 / cm 3 This makes the off-state current sufficiently small. For example, When the thickness of the oxide semiconductor layer is 30 nm, the drain voltage is 1 When the voltage is in the range of approximately V to 10V, the off-state current (when the gate-source voltage is 0V or less) The drain current when -13 A or less. Or, the off-state current density at room temperature (Off-state current divided by the channel width of the transistor) is 1×10 -20 A / μm(10z A / μm) to 1×10 -19 A / μm (100zA / μm).

[0258] In addition to the off-state current and off-state current density, the characteristics of the above-mentioned transistors include the off-state resistance (transistor Resistivity (resistance when the transistor is off) and off resistivity (resistivity when the transistor is off) Here, the off-resistance R can be expressed using the off-current and drain voltage as The off-resistivity ρ is a value calculated from Ohm's law. This value can be calculated from ρ=RA / L using the area A and the channel length L. In the above case, the off-resistivity is 1×10 9 Ω·m or more (or 1×10 10 Ω·m or more) The cross-sectional area A is expressed as A=dW, where d is the thickness of the oxide semiconductor layer and W is the channel width. will be done.

[0259] The first oxide semiconductor layer 304a and the second oxide semiconductor layer 304b are thus highly purified and made intrinsic. By using the compound semiconductor layer 306a, the off-state current of the transistor can be sufficiently reduced. Cut.

[0260] Furthermore, in this embodiment, the oxide semiconductor layer is a first oxide semiconductor having a crystalline region. The first oxide semiconductor layer 304a and the second oxide semiconductor layer 304b are grown as crystals from the crystalline region of the first oxide semiconductor layer 304a. The use of the oxide semiconductor layer 306a improves the field effect mobility and provides good electrical characteristics. It is possible to realize a transistor having the above structure.

[0261] In this embodiment, a transistor Although the case where the stator 350 is used has been described, it is not necessary to interpret the disclosed invention as being limited to this case. For example, the transistor 350 described in this embodiment has a first oxide film having a crystalline region. The first oxide semiconductor layer 304a and the second oxide semiconductor layer 304b are grown from the crystalline region of the first oxide semiconductor layer 304a. The second oxide semiconductor layer 306a has a good field-effect mobility, and therefore, integration It is possible to use oxide semiconductors for all transistors, including those that constitute circuits. In such a case, the laminated structure shown in the previous embodiment can be used. However, to achieve good circuit operation, the field-effect mobility of the oxide semiconductor must be high. μ is μ>100cm 2 / V·s. In this case, the glass substrate A semiconductor device can be formed using a substrate such as a silicon substrate.

[0262] As described above, the configurations, methods, etc. shown in this embodiment may be applied to the configurations, methods, etc. shown in other embodiments. They can be used in any suitable combination.

[0263] (Embodiment 7) In this embodiment mode, a manufacturing method of a semiconductor device different from the manufacturing method of the semiconductor device shown in Embodiment Mode 1 will be described. In this embodiment, the gate voltage of the lower transistor is formed by a so-called damascene method. The electrode is formed, and the source electrode and drain electrode of the upper transistor are formed using the electrode material. It is characterized by forming a rain electrode and the like.

[0264] First, the state shown in FIG. 4(G) is obtained by the method shown in the first embodiment. Then, the interlayer insulating layer 126 and the interlayer insulating layer 128 are polished by a CMP method or the like, and the gate The upper surface of the gate electrode 110 is then exposed by selective etching. The electrode 110 is etched to form a cavity 127 (see FIG. 13(B)).

[0265] Next, a conductive film made of metal or metal nitride is formed by a film forming method so as to completely fill the voids 127. The conductive layer may be a single layer or a multilayer. Then, the conductive layer is etched to form an electrode layer. (Source or drain electrode 142a and source or drain electrode 142b ) is obtained (see FIG. 13(C)). At this stage, a diagram equivalent to FIG. 5(B) shown in the first embodiment is obtained. The composition is as follows.

[0266] Thereafter, in the same manner as in the first embodiment, the island-shaped oxide semiconductor layer 140, the gate insulating layer 146, A gate electrode 148a and an electrode 148b are formed (see FIG. 13(D)). What should be done is that the electrode layer (source electrode or drain electrode 142a) is It is the gate electrode of the upper transistor and also the source or drain electrode of the upper transistor. In this embodiment, the lower transistor that was necessary in the first embodiment is eliminated. This allows the step of forming a contact hole to the gate electrode 110 of the capacitor to be omitted. In the embodiment, the island-shaped oxide semiconductor layer 140 is in contact with the interlayer insulating layer 128. Before forming the oxide semiconductor layer 140, the surface of the interlayer insulating layer 128 is sufficiently dehydrogenated. It is hoped that this will happen.

[0267] (Embodiment 8) In this embodiment, when the semiconductor device described in the above embodiment is applied to an electronic device, This will be described with reference to FIG. 14. In this embodiment, telephones, mobile phone devices), portable information terminals (including portable game consoles and audio playback devices) digital cameras, digital video cameras, electronic paper, television equipment (television The semiconductor device described above is applied to electronic devices such as a television receiver. This section explains the case where

[0268] FIG. 14A shows a notebook personal computer, which includes a housing 401, a housing 402, The display unit 403 and the keyboard 404 are included. The semiconductor device described in the above embodiment is provided inside the memory cell. and readout is fast, long-term storage is possible, and power consumption is sufficiently reduced. A portable personal computer is realized.

[0269] FIG. 14B shows a personal digital assistant (PDA), and a main body 411 includes a display unit 413 and an external An external interface 415 and operation buttons 414 are provided. The main body 411 is provided with a stylus 412 for operating the terminal. Therefore, writing and reading of information can be performed at high speed and for a long time. This realizes a portable information terminal that can store data for a long period of time and consumes a sufficient amount of power.

[0270] FIG. 14C shows an electronic book 420 equipped with electronic paper, which is made up of a housing 421 and a housing 422. The display unit 42 is mounted on the housing 421 and the housing 423. 5 and a display unit 427 are provided. The housing 421 and the housing 423 are connected by a shaft portion 437. The housing 421 is connected to the shaft 437, and can be opened and closed around the shaft 437. The device includes a power supply 431, operation keys 433, a speaker 435, etc. At least one of the bodies 423 is provided with the semiconductor device shown in the previous embodiment. Therefore, it is possible to write and read information at high speed, retain data for a long period of time, and consume little power. This allows for the realization of an electronic book with sufficiently reduced image quality.

[0271] FIG. 14D shows a mobile phone that is composed of two housings, a housing 440 and a housing 441. Furthermore, the housing 440 and the housing 441 slide and unfold as shown in FIG. 14(D). The two can be folded into an overlapping state, making them compact and suitable for portability. The housing 441 also includes a display panel 442, a speaker 443, a microphone 444, a pointing device, and a The camera is equipped with a viewing device 446, a camera lens 447, an external connection terminal 448, etc. The housing 440 also includes a solar cell 449 for charging the mobile phone, an external memory slot, and The antenna is built into the housing 441. At least one of the housing 40 and the housing 441 is provided with the semiconductor device shown in the previous embodiment. Therefore, information can be written and read at high speed, and long-term storage is possible. A mobile phone with sufficiently reduced power consumption is realized.

[0272] FIG. 14(E) shows a digital camera, which includes a main body 461, a display unit 467, an eyepiece 463, and an operation unit. It is composed of an operation switch 464, a display unit 465, a battery 466, etc. The semiconductor device described in the previous embodiment is provided in the memory 461. It has high speed writing and reading, long-term memory retention, and low power consumption. This will result in a digital camera with this technology.

[0273] FIG. 14F shows a television device 470, which includes a housing 471, a display unit 473, a stand, and the like. The television device 470 is operated by a switch provided in the housing 471. This can be done by a switch or a remote control 480. The semiconductor device described in the above embodiment is mounted on the device 480. It has high speed writing and reading, long-term memory retention, and low power consumption. A television device having such a configuration is realized.

[0274] As described above, the electronic device described in this embodiment mode is equipped with the semiconductor device according to the above embodiment. This allows for the realization of electronic devices with reduced power consumption. [Example]

[0275] The number of times that a semiconductor device according to one embodiment of the disclosed invention can be rewritten was investigated. The survey results will now be explained with reference to FIG.

[0276] The semiconductor device used in the investigation has a circuit configuration shown in FIG. An oxide semiconductor is used for the transistor corresponding to the transistor 162. The capacitance element corresponding to the capacitor 164 had a capacitance of 0.33 pF.

[0277] The investigation involves setting the initial memory window width and holding and writing data a predetermined number of times. This is done by comparing the memory window width after each iteration. Data is written by applying 0 V or Apply either 0V or 5V to the wire corresponding to the fourth wire. When the potential of the wiring corresponding to the fourth wiring is 0V, the transistor Since the transistor corresponding to the transistor 162 is in the off state, the floating gate portion FG If the potential of the wiring corresponding to the fourth wiring is 5V, the transistor Since the transistor corresponding to the third wiring is turned on, the transistor corresponding to the third wiring is turned on. The potential of the line is applied to the floating gate portion FG.

[0278] The memory window width is one of the indicators that show the characteristics of a memory device. Between the states, the potential Vcg of the wiring corresponding to the fifth wiring and the potential Vcg of the wiring corresponding to the transistor 160 The shift of the curve (Vcg-Id curve) showing the relationship between the drain current Id of the transistor The different memory states are when 0V is applied to the floating gate FG. (hereinafter referred to as the Low state) and when 5V is applied to the floating gate FG. This refers to a given state (hereinafter referred to as the High state). In other words, the memory window width is This can be confirmed by sweeping the potential Vcg in the low and high states.

[0279] Figure 15 shows the memory window width in the initial state and the 9 After writing The horizontal axis in Figure 15 represents Vcg (V). The vertical axis shows Id(A). 9 Before and after writing, It can be seen that the memory window width has not changed. 9 Before and after writing The fact that the memory window width remains unchanged means that the semiconductor device will This indicates that there is no deterioration.

[0280] As described above, the semiconductor device according to one embodiment of the disclosed invention can store and write data many times. The characteristics do not change even after repeated use. In other words, one embodiment of the disclosed invention provides extremely reliable It can be said that a highly efficient semiconductor device can be realized. [Explanation of symbols]

[0281] 100 boards 102 Protective layer 104 Semiconductor Area 106 Element isolation insulating layer 108 Gate insulating layer 110 gate electrode 112 Insulating layer 114 Impurity region 116 Channel formation region 118 Sidewall insulating layer 120 High concentration impurity region 122 Metal layer 124 Metal compound area 126 Interlayer insulation layer 128 Interlayer Insulation Layer 130 electrodes 130a Source electrode or drain electrode 130b Source electrode or drain electrode 130c electrode 138 Insulating Layer 140 Oxide semiconductor layer 140a Oxide semiconductor layer 140b Oxide semiconductor layer 142a Source electrode or drain electrode 142b Source electrode or drain electrode 142c electrode 142d electrode 144 Insulating Layer 146 Gate insulating layer 148a Gate electrode 148b Electrode 150 Protective insulation layer 152 Interlayer insulation layer 160 transistors 162 transistors 164 Capacitor 166 transistors 190 memory cells 200 Lower layer board 202 Insulating layer 206 Oxide semiconductor layer 206a Oxide semiconductor layer 208a Source electrode or drain electrode 208b Source electrode or drain electrode 212 Gate insulating layer 214 gate electrode 216 Interlayer insulating layer 218 Interlayer Insulation Layer 250 transistors 300 Lower layer board 302 Insulation layer 304 Oxide semiconductor layer 304a Oxide semiconductor layer 305 Oxide semiconductor layer 306 Oxide semiconductor layer 306a Oxide semiconductor layer 308a Source electrode or drain electrode 308b Source electrode or drain electrode 312 Gate insulating layer 314 Gate electrode 316 Interlayer insulation layer 318 Interlayer Insulation Layer 350 transistors 401 Case 402 Case 403 Display section 404 Keyboard 411 Main Unit 412 Stylus 413 Display section 414 Operation Button 415 external interface 420 e-books 421 Case 423 Case 425 Display section 427 Display section 431 Power supply 433 Operation Key 435 Speaker 437 Shaft 440 chassis 441 Case 442 Display Panel 443 Speaker 444 Microphone 446 Pointing Device 447 Camera Lenses 448 External connection terminal 449 Solar Cells 450 external memory slot 461 Main Unit 463 Eyepiece 464 Operation Switch 465 Display section 466 Battery 467 Display section 470 Television Equipment 471 Case 473 Display section 475 Stand 480 Remote Controlled Machine

Claims

1. a first transistor, a second transistor, and a capacitor; one of a source electrode and a drain electrode of the second transistor is electrically connected to a gate electrode of the first transistor; one electrode of the capacitance element is electrically connected to a gate electrode of the first transistor; a constant potential is applied to one of the source electrode and the drain electrode of the first transistor; A semiconductor device in which a signal is input to the other electrode of the capacitive element, a first conductive film that functions as a gate electrode of the first transistor; a first insulating film having a region disposed above the first conductive film; a semiconductor film having a region disposed above the first insulating film and having a channel formation region of the second transistor; a second conductive film having a region disposed above the first insulating film, electrically connected to the semiconductor film, and functioning as one of a source electrode and a drain electrode of the second transistor; a third conductive film having a region disposed above the first insulating film, electrically connected to the semiconductor film, and functioning as the other of the source electrode and the drain electrode of the second transistor; a fourth conductive film having a region disposed above the first insulating film and functioning as one of a source electrode and a drain electrode of the first transistor; a fifth conductive film having a region disposed above the semiconductor film and functioning as a gate electrode of the second transistor; a sixth conductive film that functions as the other electrode of the capacitor element; the semiconductor film includes an oxide semiconductor, the second conductive film functions as one electrode of the capacitor element, the sixth conductive film has a region overlapping with the semiconductor film; Semiconductor device.

2. a first transistor, a second transistor, and a capacitor; one of a source electrode and a drain electrode of the second transistor is electrically connected to a gate electrode of the first transistor; one electrode of the capacitance element is electrically connected to a gate electrode of the first transistor; a constant potential is applied to one of the source electrode and the drain electrode of the first transistor; A semiconductor device in which a signal is input to the other electrode of the capacitive element, a first conductive film that functions as a gate electrode of the first transistor; a first insulating film having a region disposed above the first conductive film; a semiconductor film having a region disposed above the first insulating film and having a channel formation region of the second transistor; a second conductive film having a region disposed above the first insulating film, electrically connected to the semiconductor film, and functioning as one of a source electrode and a drain electrode of the second transistor; a third conductive film having a region disposed above the first insulating film, electrically connected to the semiconductor film, and functioning as the other of the source electrode and the drain electrode of the second transistor; a fourth conductive film having a region disposed above the first insulating film and functioning as one of a source electrode and a drain electrode of the first transistor; a fifth conductive film having a region disposed above the semiconductor film and functioning as a gate electrode of the second transistor; a sixth conductive film that functions as the other electrode of the capacitor element; the semiconductor film includes an oxide semiconductor, the second conductive film functions as one electrode of the capacitor element, a region of the second conductive film that overlaps with the semiconductor film includes a region that overlaps with the sixth conductive film; Semiconductor device.

3. a first transistor, a second transistor, and a capacitor; one of a source electrode and a drain electrode of the second transistor is electrically connected to a gate electrode of the first transistor; one electrode of the capacitance element is electrically connected to a gate electrode of the first transistor; a constant potential is applied to one of the source electrode and the drain electrode of the first transistor; A semiconductor device in which a signal is input to the other electrode of the capacitive element, a first conductive film that functions as a gate electrode of the first transistor; a first insulating film having a region disposed above the first conductive film; a semiconductor film having a region disposed above the first insulating film and having a channel formation region of the second transistor; a second conductive film having a region disposed above the first insulating film, electrically connected to the semiconductor film, and functioning as one of a source electrode and a drain electrode of the second transistor; a third conductive film having a region disposed above the first insulating film, electrically connected to the semiconductor film, and functioning as the other of the source electrode and the drain electrode of the second transistor; a fourth conductive film having a region disposed above the first insulating film and functioning as one of a source electrode and a drain electrode of the first transistor; a fifth conductive film having a region disposed above the semiconductor film and functioning as a gate electrode of the second transistor; a sixth conductive film that functions as the other electrode of the capacitor; a second insulating film having a region in contact with an upper surface of the fifth conductive film and a region in contact with an upper surface of the sixth conductive film; the semiconductor film includes an oxide semiconductor, the second conductive film functions as one electrode of the capacitor element, the sixth conductive film has a region overlapping with the semiconductor film; Semiconductor device.

4. a first transistor, a second transistor, and a capacitor; one of a source electrode and a drain electrode of the second transistor is electrically connected to a gate electrode of the first transistor; one electrode of the capacitance element is electrically connected to a gate electrode of the first transistor; a constant potential is applied to one of the source electrode and the drain electrode of the first transistor; A semiconductor device in which a signal is input to the other electrode of the capacitive element, a first conductive film that functions as a gate electrode of the first transistor; a first insulating film having a region disposed above the first conductive film; a semiconductor film having a region disposed above the first insulating film and having a channel formation region of the second transistor; a second conductive film having a region disposed above the first insulating film, electrically connected to the semiconductor film, and functioning as one of a source electrode and a drain electrode of the second transistor; a third conductive film having a region disposed above the first insulating film, electrically connected to the semiconductor film, and functioning as the other of the source electrode and the drain electrode of the second transistor; a fourth conductive film having a region disposed above the first insulating film and functioning as one of a source electrode and a drain electrode of the first transistor; a fifth conductive film having a region disposed above the semiconductor film and functioning as a gate electrode of the second transistor; a sixth conductive film that functions as the other electrode of the capacitor; a second insulating film having a region in contact with an upper surface of the fifth conductive film and a region in contact with an upper surface of the sixth conductive film; the semiconductor film includes an oxide semiconductor, the second conductive film functions as one electrode of the capacitor element, a region of the second conductive film that overlaps with the semiconductor film includes a region that overlaps with the sixth conductive film; Semiconductor device.

5. In any one of claims 1 to 4, the second conductive film has a region overlapping with the first conductive film; Semiconductor device.

6. In any one of claims 1 to 5, each of the second conductive film and the third conductive film contains at least one of aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten; Semiconductor device.

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