Semiconductor device and method of manufacturing the same

Abstract

To suppress the temperature rise at the 101a part of an active region and to reduce the loss.SOLUTION: The semiconductor element includes a drift layer 1 of a first conductivity type provided in an active region 101 and a termination region 102 surrounding the active region 101, a base region 3 of a second conductivity type provided on an upper surface side of the drift layer 1 in the active region 101, a main region 4 of the first conductivity type provided on an upper surface side of the base region 3, and an insulated gate structure (7, 8) provided in contact with the main region 4 and the base region 3, and an effective career concentration of the base region 3 is relatively high at a 101a of a central portion of the active region 101 and relatively low at a 101b of a peripheral portion of the active region 101. The depth of the peak concentration of the base region 3 is deeper than the lower surface of the main region 4.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] Patent Document 1 discloses a configuration in which the impurity concentration of the p-type base region is made higher in the center of the cell region than in the periphery of the cell region in order to reduce the current carrying capacity in the center of the cell region. Patent Document 2 discloses a configuration in which the impurity concentration of the channel formation region in the region close to the bonding pad is made higher to increase the threshold voltage.

[0003] Non-Patent Document 1 discloses non-melt laser annealing using a KrF excimer laser or a green laser. Non-Patent Document 2 discloses the temperature dependence of the activation rate when nitrogen and phosphorus ions are implanted into a silicon carbide substrate and then RTA is performed. Non-Patent Document 3 discloses the temperature dependence of the activation rate when boron ions are implanted into a silicon substrate and then furnace annealing is performed. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 5561922 specification [Patent Document 2] Japanese Patent Application Publication No. 5-63202 [Non-patent literature]

[0005] [Non-Patent Document 1] Siti Rahmah Aid et al., “Formation of shallow p+ / n junction in silicon using non-melt laser annealing” 11th International Workshop on Junction Technology (IWJT), 2011, p.132-135 [Non-patent document 2] S. Blanque et al., “Room Temperature Implantation and Activation Kinetics of Nitrogen and Phosphorus in 4H-SiC Crystals” Materials Science Forum, Vols. 457-460, 2004, p.893-896 [Non-patent document 3] Seung-Han Yoo et al., “Activation and Deactivation in Heavily Boron-Doped Silicon” Journal of the Korean Physical Society, Vol. 43, No.2, August 2003, p.290-295 Summary of the Invention [Problem to be solved by the invention]

[0006] Because the gate threshold voltage Vth of the active elements is uniform across the surface of the active region of a semiconductor chip, the current during operation is also uniform across the surface, and heat is generated at the same time. As a result, the heat in the center of the active region has nowhere to escape, so the temperature in the center becomes higher than in the peripheral areas, increasing loss.

[0007] An object of the present disclosure is to provide a semiconductor device that can suppress a temperature rise in the center of an active region and reduce loss, and a method for manufacturing the same. [Means for solving the problem]

[0008] In order to achieve the above object, one aspect of the present disclosure is a semiconductor device comprising: an active region; a first conductivity type drift layer provided in an termination region surrounding the active region; a second conductivity type base region provided on an upper surface side of the drift layer in the active region; a first conductivity type main region provided on an upper surface side of the base region; and an insulated gate electrode structure provided in contact with the main region and the base region, wherein the effective carrier concentration of the base region is relatively high in a central portion of the active region and relatively low in a peripheral portion of the active region; and the depth of the peak concentration in the base region is deeper than the bottom surface of the main region.

[0009] Another aspect of the present disclosure is a method for manufacturing a semiconductor device, including the steps of: preparing a drift layer of a first conductivity type partitioned into an active region and an termination region surrounding the active region; forming a base region of a second conductivity type on an upper surface side of the drift layer in the active region; and forming a main region of the first conductivity type on an upper surface side of the base region, wherein the step of forming the base region includes ion-implanting impurities of the second conductivity type from the upper surface side of the drift layer and performing laser annealing so that the temperature in the peripheral part of the active region is lower than that in the central part. [Effects of the Invention]

[0010] According to the present disclosure, it is possible to provide a semiconductor device and a method for manufacturing the same that can suppress a temperature rise in the center of the active region and reduce loss. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a plan view illustrating an example of a semiconductor device according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a cross-sectional view taken along the line AA′ in FIG. [Figure 3] FIG. 3 is an enlarged cross-sectional view of an area C in FIG. 2. [Figure 4] 1 is a graph showing an impurity concentration profile of a semiconductor device according to an embodiment of the present disclosure. [Figure 5] 10 is a graph showing an impurity concentration profile of a semiconductor device according to a comparative example. [Figure 6] 1A to 1C are cross-sectional views illustrating steps in a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. [Figure 7] 7A to 7C are cross-sectional views illustrating steps subsequent to FIG. 6 in the method for manufacturing a semiconductor device according to an embodiment of the present disclosure. [Figure 8] 8A to 8C are cross-sectional views illustrating steps subsequent to FIG. 7 in the method for manufacturing a semiconductor device according to an embodiment of the present disclosure. [Figure 9] 9A to 9C are cross-sectional views illustrating steps subsequent to FIG. 8 in the method for manufacturing a semiconductor device according to an embodiment of the present disclosure. [Figure 10] 10A to 10C are cross-sectional views illustrating steps subsequent to FIG. 9 in the method for manufacturing a semiconductor device according to an embodiment of the present disclosure. [Figure 11] FIG. 2 is a plan view of a semiconductor wafer in a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. [Figure 12] 1 is a graph showing the temperature dependence of the activation rate of impurity ions. [Figure 13] 11A to 11C are cross-sectional views illustrating steps subsequent to FIG. 10 in the method for manufacturing a semiconductor device according to an embodiment of the present disclosure. [Figure 14] 14A to 14C are cross-sectional views illustrating steps subsequent to FIG. 13 in the method for manufacturing a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the description of the drawings, identical or similar parts are designated by identical or similar reference numerals, and redundant explanations will be omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Furthermore, parts with different dimensional relationships and ratios may be included between the drawings. Furthermore, the embodiments of the present disclosure described below are examples of devices and methods for embodying the technical idea of ​​the present disclosure, and the technical idea of ​​the present disclosure does not specify the materials, shapes, structures, arrangements, etc. of component parts to those described below.

[0013] In this specification, the emitter region of an insulated gate bipolar transistor (IGBT) is "one main region (first main region)" that can be selected as the source region of a metal-oxide semiconductor field-effect transistor (MOSFET). In addition, in a thyristor such as a MOS-controlled static induction thyristor (SI thyristor), "one main region" can be selected as the cathode region. The collector region of an IGBT is "the other main region (second main region)" of a semiconductor device that can be selected as the drain region in a MOSFET or the anode region in an SI thyristor. In this specification, the term "main region" simply refers to either the first main region or the second main region, as appropriate based on the common technical knowledge of a person skilled in the art.

[0014] Furthermore, the definitions of directions such as up and down in the following description are merely for the convenience of explanation and do not limit the technical idea of ​​the present disclosure. For example, if an object is rotated 90 degrees and observed, up and down are converted to left and right and read as such, and if it is rotated 180 degrees and observed, up and down are inverted and read as such. Furthermore, "top surface" may be read as "front surface" and "bottom surface" may be read as "rear surface."

[0015] In the following description, the first conductivity type is n-type and the second conductivity type is p-type. However, the conductivity types may be reversed, with the first conductivity type being p-type and the second conductivity type being n-type. The + or - affixed to n or p indicates a semiconductor region with a relatively higher or lower impurity concentration, respectively, compared to a semiconductor region without the + or - affixed. However, semiconductor regions with the same n and n affixed do not necessarily have the exact same impurity concentration.

[0016] Furthermore, in the following explanation, "same," "identical," or "uniform" does not necessarily mean "same," "identical," or "uniform" in the strict sense, and includes cases where the item is strictly the same, identical, or uniform, as well as cases where the item is approximately the same, approximately the same, or approximately uniform. Although the terms "approximately the same," "approximately the same," or "approximately uniform" depend on the subject, they fall within a range of ±10% of the strictly same, identical, or uniform.

[0017] (Embodiment) <Structure of semiconductor device> FIG. 1 is a plan view of a semiconductor device (semiconductor chip) according to an embodiment of the present disclosure, viewed from the top surface (front surface). As shown in FIG. 1, the semiconductor device according to an embodiment of the present disclosure has a substantially rectangular planar pattern. The semiconductor device according to an embodiment of the present disclosure is configured with a semiconductor substrate made of, for example, silicon (Si). The semiconductor device according to an embodiment of the present disclosure may be configured with a semiconductor substrate made of a semiconductor (wide bandgap semiconductor) with a wider bandgap than Si, such as silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), diamond (C), or aluminum nitride (AlN). When the semiconductor substrate is a wide bandgap semiconductor, the temperature conditions of the heat treatment may be changed.

[0018] A semiconductor device according to an embodiment of the present disclosure includes an active region 101 having a substantially rectangular planar pattern, and a termination region (breakdown resistance structure portion) 102 having an annular (frame-shaped) planar pattern provided so as to surround the periphery of the active region 101. As shown in Fig. 1, the active region 101 includes a central portion 101a on the central side (inside) including the center (center of gravity) of the planar pattern of the active region 101, and a peripheral portion 101b on the outer periphery (outside) of the planar pattern of the active region 101. In Fig. 1, an imaginary circle B of any size is indicated by a dashed line; for example, the central portion 101a is inside the circle B, and the peripheral portion 101b is outside the circle B.

[0019] The active region 101 includes an active element such as an IGBT or a MOSFET. A temperature detection diode (temperature detection unit) 100 is provided in a peripheral portion 101b of the active region 101. The temperature detection diode 100 is configured as a pn junction diode made of polysilicon or the like. An anode pad (not shown) and a cathode pad (not shown) provided in the peripheral portion 101b of the active region 101 are electrically connected to the temperature detection diode 100 via wiring (not shown). The position of the temperature detection diode 100 is not particularly limited. The temperature detection diode 100 may be provided in, for example, a central portion 101a of the active region 101.

[0020] FIG. 2 shows a cross-sectional view taken along line AA′, which crosses a portion of the active region 101 and the breakdown voltage structure 102 in FIG. 1 . As shown in FIG. 2 , the active region 101 includes a transistor section 103 including a transistor element and a diode section 104 including a diode element, all on the same semiconductor chip. The semiconductor device according to the embodiment of the present disclosure is a reverse-conducting IGBT (RC-IGBT) in which the diode element of the diode section 104 is connected in anti-parallel as a freewheeling diode (FWD) to the IGBT, which is the transistor element, of the transistor section 103. The positions of the transistor section 103 and the diode section 104 in the active region 101 are not particularly limited. For example, multiple configurations similar to the transistor section 103 and the diode section 104 may be arranged alternately in the left-right direction of FIG. 1 . The transistor section 103 is included in each of the central section 101a and the peripheral section 101b of the active region 101.

[0021] The semiconductor device according to the embodiment of the present disclosure includes a first conductivity type (n - The drift layer 1 is of the type.

[0022] 3 is an enlarged cross-sectional view of a region C surrounding a part of the transistor section 103 in the active region 101 of FIG. 2. As shown in FIG. 3, an n-type carrier accumulation layer (CS layer) 2 having a higher impurity concentration than the drift layer 1 is provided on the upper surface side of the drift layer 1 of the transistor section 103. The lower surface of the carrier accumulation layer 2 is in contact with the upper surface of the drift layer 1. By providing the carrier accumulation layer 2, the carrier injection enhancement effect (IE effect) can be improved, and the on-voltage can be reduced.

[0023] A base region 3 of the second conductivity type (p-type) is provided on the upper surface side of the carrier accumulation layer 2. The lower surface of the base region 3 contacts the upper surface of the carrier accumulation layer 2. The carrier accumulation layer 2 does not necessarily have to be provided. If the carrier accumulation layer 2 is not provided, the lower surface of the base region 3 contacts the upper surface of the drift layer 1.

[0024] The effective carrier concentration of the base region 3 is highest in the central portion 101a of the active region 101 and decreases from the central portion 101a toward the periphery. The effective carrier concentration of the base region 3 is relatively high in the central portion 101a of the active region 101 and relatively low in the peripheral portion 101b of the active region 101. Therefore, the gate threshold voltage Vth of the IGBT in the transistor portion 103 is relatively high in the central portion 101a of the active region 101 and relatively low in the peripheral portion 101b of the active region 101. In the embodiments of the present disclosure, the "effective carrier concentration" refers to the concentration of carriers that are activated, placed in interstitial sites, and act as acceptors or donors among all implanted ions.

[0025] Furthermore, the activation rate of p-type impurity ions implanted into the base region 3 is highest in the central portion 101a of the active region 101 and decreases from the central portion 101a toward the periphery. The activation rate of p-type impurity ions implanted into the base region 3 is relatively high in the central portion 101a of the active region 101 and relatively low in the peripheral portion 101b of the active region 101. In the embodiments of the present disclosure, the "activation rate" refers to the proportion of all implanted ions that are activated and placed at interstitial sites, becoming carriers that act as acceptors or donors. The activation rate can be calculated as the ratio of the sheet carrier concentration to the dose.

[0026] Furthermore, the dose of p-type impurities ion-implanted into the base region 3 is uniform (the same) throughout the entire surface including the central portion 101a and peripheral portion 101b of the active region 101. Therefore, the concentration of the p-type impurities, which is the sum of the p-type impurities ion-implanted into the base region 3 and activated and the p-type impurities ion-implanted into the base region 3 and not activated, is uniform (the same) throughout the entire surface including the central portion 101a and peripheral portion 101b of the active region 101.

[0027] The depth of the base region 3 is uniform (the same) throughout the entire surface including the central portion 101a and peripheral portion 101b of the active region 101. The depth of the base region 3 may be deepest in the central portion 101a of the active region 101 and may become shallower from the central portion 101a toward the outer periphery. The depth of the base region 3 may be relatively deep in the central portion 101a of the active region 101 and relatively shallow in the peripheral portion 101b of the active region 101.

[0028] As shown in FIG. 3, the upper surface of the base region 3 is provided with a first conductivity type (n + The first main region (emitter region) 4 is provided in the base region 3. The lower surface of the emitter region 4 is in contact with the upper surface of the base region 3. The impurity concentration of the emitter region 4 is higher than the impurity concentrations of the drift layer 1 and the carrier accumulation layer 2.

[0029] Here, the position (depth) of the peak concentration, which is the highest impurity concentration of the p-type impurity in the base region 3, is set to a predetermined depth from the upper surface of the emitter region 4, and is deeper than the position of the lower surface of the emitter region 4. In the embodiment of the present disclosure, the "position of the lower surface of the emitter region 4" is defined as the position where the impurity concentration decreases from the peak concentration of the n-type impurity in the emitter region 4 in the depth direction and becomes the same as the concentration of the p-type impurity. In other words, the pn junction interface with the base region 3 is the lower surface of the emitter region 4.

[0030] FIG. 4 shows impurity concentration profiles of the emitter region 4, the base region 3, and the carrier accumulation layer 2 in the depth direction from the top surface of the emitter region 4, as indicated by arrow D in FIG. 3 , for a semiconductor device according to an embodiment of the present disclosure. This impurity concentration profile was measured by secondary ion mass spectrometry (SIMS). As shown in FIG. 4 , in the semiconductor device according to an embodiment of the present disclosure, the position (depth) d1 of the peak concentration in the base region 3 is deeper than the position d2 of the bottom surface of the emitter region 4. This configuration eliminates the influence of n-type impurities in the emitter region 4 when forming the in-plane distribution of the threshold voltage by laser annealing. In the manufacturing process of the semiconductor device according to an embodiment of the present disclosure, as described below, when ion implanting p-type impurities to form the base region 3, the entire surface of the active region 101 is not subsequently driven at a high temperature of approximately 1100°C. Instead, the acceleration energy of the ion implantation is increased to approximately 300 keV or higher to deepen the position d1 of the peak concentration and expand the base region 3 in the depth direction.

[0031] FIG. 5 shows the impurity concentration profiles of the emitter region 4, base region 3, and carrier accumulation layer 2 in the depth direction from the top surface of the emitter region 4, as indicated by arrow D in FIG. 3, for a semiconductor device according to the comparative example. As shown in FIG. 5, in the semiconductor device according to the comparative example, the position (depth) d3 of the peak concentration in the base region 3 is near the top surface of the emitter region 4 and is shallower than the position d4 of the bottom surface of the emitter region 4. In the manufacturing process of the semiconductor device according to the comparative example, after ion implantation of p-type impurities to form the base region 3, the active region 101 is subsequently heated to a high temperature of approximately 1100°C, causing the p-type impurities to diffuse in the depth direction. For this reason, the acceleration energy of the ion implantation is reduced to approximately 100 keV, and the position d3 of the peak concentration is located near the top surface of the emitter region 4.

[0032] As shown in FIG. 3, on the upper surface side of the base region 3, in contact with the base region 3 and the emitter region 4, there is a second conductivity type (p +3. Although the contact regions 5 are in contact with the emitter regions 4 in the left-right direction of FIG. 3, the contact regions 5 and the emitter regions 4 may be provided alternately and periodically in the front and back directions of FIG.

[0033] A plurality of trenches 6 are provided at intervals from one another in the depth direction from the top surface of the emitter region 4. The trenches 6 penetrate the emitter region 4, the base region 3, and the carrier accumulation layer 2 to reach the drift layer 1. The side surfaces (sidewall surfaces) of the trenches 6 are in contact with the side surfaces of the emitter region 4, the base region 3, and the carrier accumulation layer 2. The plurality of trenches 6 may have a linear (striped) planar pattern extending parallel to one another in the front and back directions of FIG. 3 .

[0034] 3, a mesa portion is provided between adjacent trenches 6 in the direction in which the trenches 6 are aligned. The mesa portion is a region sandwiched between adjacent trenches 6 and above the deepest position of the trenches 6. In the mesa portion, an upper portion of the drift layer 1, a carrier accumulation layer 2, a base region 3, an emitter region 4, and a contact region 5 are provided.

[0035] A gate insulating film 7 is provided so as to cover the bottom and side surfaces of the trench 6. The gate insulating film 7 may be, for example, a single layer film of any one of a silicon dioxide film (SiO2 film), a silicon oxynitride (SiON) film, a strontium oxide (SrO) film, a silicon nitride (Si3N4) film, an aluminum oxide (Al2O3) film, a magnesium oxide (MgO) film, an yttrium oxide (Y2O3) film, a hafnium oxide (HfO2) film, a zirconium oxide (ZrO2) film, a tantalum oxide (Ta2O5) film, and a bismuth oxide (Bi2O3) film, or a composite film obtained by laminating two or more of these films.

[0036] A gate electrode 8 is buried inside the trench 6 via a gate insulating film 7. The gate electrode 8 can be made of a polysilicon film (doped polysilicon film) doped with a high concentration of impurities such as phosphorus (P) or boron (B). The gate insulating film 7 and the gate electrode 8 form an insulated gate electrode structure (7, 8).

[0037] An interlayer insulating film 21 is provided on the upper surface of the insulated gate electrode structure (7, 8). The interlayer insulating film 21 is made of a single layer film such as a non-doped silicon oxide film (SiO2 film) that does not contain phosphorus (P) or boron (B), known as "NSG," a silicon oxide film doped with phosphorus (PSG film), a silicon oxide film doped with boron (BSG film), a silicon oxide film doped with boron and phosphorus (BPSG film), a silicon nitride film (Si3N4 film), or a high-temperature oxide film (HTO film), or a laminate film of these.

[0038] The interlayer insulating film 21 is provided with a contact hole that exposes a part of the emitter region 4 and the upper surface of the contact region 5. A contact plug 31 made of tungsten (W) or the like is buried in the contact hole via a titanium silicide (TiSi2) film (not shown) and a barrier metal film (not shown) made of titanium nitride (TiN) or the like.

[0039] A surface electrode 32 is provided on the interlayer insulating film 21. The surface electrode 32 is electrically connected to the emitter region 4 and the contact region 5 via the contact plug 31. The surface electrode 32 functions as an emitter electrode in the transistor section 103. The surface electrode 32 can be made of metal such as aluminum (Al), an Al alloy, or copper (Cu). Examples of Al alloys include Al-silicon (Si), Al-Si-copper (Cu), and Al-Cu.

[0040] An n-type field stop (FS) layer 9 having a higher impurity concentration than the drift layer 1 is provided on the lower surface side of the drift layer 1. The upper surface of the FS layer 9 is in contact with the lower surface of the drift layer 1. The FS layer 9 prevents a depletion layer spreading from the lower surface side of the base region 3 from reaching a second main region (collector region) 10, which will be described later. + The collector region 10 has a lower surface in contact with the lower surface of the FS layer 9. The collector region 10 has a higher impurity concentration than the base region 3.

[0041] A back electrode 50 is provided on the lower surface side of the collector region 10. The back electrode 50 can be formed, for example, of a single layer film made of gold (Au) or a metal film laminated in this order of titanium (Ti), nickel (Ni), and gold (Au). The back electrode 50 functions as a collector electrode in the transistor section 103.

[0042] 2, in the diode section 104, an n-type carrier accumulation layer 2 having a higher impurity concentration than the drift layer 1 is provided on the upper surface side of the drift layer 1. An anode region 11 of a second conductivity type (p-type) is provided on the upper surface side of the carrier accumulation layer 2. The lower surface of the anode region 11 is in contact with the upper surface of the carrier accumulation layer 2. The anode region 11 may be provided at the same depth as the base region 3 of the transistor section 103 and with the same impurity concentration.

[0043] In the diode section 104, a plurality of trenches 6 are provided in the depth direction from the top surface of the anode region 11. The trenches 6 in the diode section 104 are provided to the same depth as the trenches 6 in the transistor section 103. The trenches 6 penetrate the anode region 11 and the carrier accumulation layer 2 to reach the drift layer 1. The side surfaces of the anode region 11 and the carrier accumulation layer 2 contact the side surfaces of the trenches 6.

[0044] An upper portion of the drift layer 1, the carrier accumulation layer 2, and the anode region 11 are provided in the mesa portion between the trenches 6 of the diode portion 104. A surface electrode 32 is provided on the upper surface side of the anode region 11 with an interlayer insulating film 21 interposed therebetween. The surface electrode 32 is provided continuously from the transistor portion 103. The surface electrode 32 is electrically connected to the anode region 11 via a contact plug 31 embedded in a contact hole provided in the interlayer insulating film 21. The surface electrode 32 functions as an anode electrode in the diode portion 104. A protective resist film 42 is provided on the upper surface side of the surface electrode 32. The protective resist film 42 is provided across the transistor portion 103 and the diode portion 104.

[0045] In the diode section 104, the lower surface side of the FS layer 9 is provided with an n-type semiconductor layer having a higher impurity concentration than the FS layer 9. + The cathode region 12 has a shaped cathode region 12. The upper surface of the cathode region 12 is in contact with the lower surface of the FS layer 9. The cathode region 12 is provided at the same depth as the collector region 10. The side surface of the cathode region 12 is in contact with the side surface of the collector region 10. The back electrode 50 functions as a cathode electrode in the diode section 104.

[0046] In a region of the active region 101 outside the transistor section 103 and adjacent to the breakdown voltage structure section 102, an n-type carrier accumulation layer 2 and a p-type well region 13 are provided on the upper surface of the drift layer 1. A p-type well region 14, which is deeper than the well region 13 and is provided outside the carrier accumulation layer 2 and well region 13, is provided in contact with the carrier accumulation layer 2 and well region 13. A temperature detection diode 100 is provided on the upper surface of the well region 14 via an insulating film (not shown). A surface electrode 32 is provided on the upper surface of the temperature detection diode 100 via an interlayer insulating film 21. The surface electrode 32 is electrically connected to the temperature detection diode 100 via a contact plug 31 embedded in a contact hole provided in the interlayer insulating film 21. The surface electrode 32 functions as wiring and is electrically connected to an anode pad or a cathode pad (not shown).

[0047] As shown in FIG. 2, in the breakdown voltage structure 102, a plurality of guard ring layers 15 are provided spaced apart from one another on the upper surface of the drift layer 1. A p-type channel stopper 16 is provided on the upper surface of the drift layer 1 at the outer periphery of the breakdown voltage structure 102. A surface electrode 32 is provided on the upper surfaces of the guard ring layers 15 and the channel stopper 16, with an insulating film 20 and an interlayer insulating film 21 interposed therebetween. The surface electrode 32 is electrically connected to the guard ring layer 15 via a contact plug 31 embedded in a contact hole provided in the interlayer insulating film 21. A protective film 41 made of polyimide or the like is provided on the upper surface of the surface electrode 32. A protective resist film 42 is provided on the upper surface of the protective film 41.

[0048] During operation of the semiconductor device according to the embodiment of the present disclosure, in the IGBT of the transistor unit 103, when the front surface electrode 32 is at ground potential, a positive voltage is applied to the back surface electrode 50, and a positive voltage equal to or greater than the gate threshold voltage Vth is applied to the gate electrode 8, an inversion layer (channel) is formed on the side surface of the trench 6 in the base region 3, turning the device into an ON state. In the ON state, a current flows from the back surface electrode 50 to the front surface electrode 32 via the collector region 10, the FS layer 9, the drift layer 1, the carrier accumulation layer 2, the inversion layer in the base region 3, and the emitter region 4.

[0049] On the other hand, when the voltage applied to the gate electrode 8 is less than the gate threshold voltage Vth, no inversion layer is formed in the base region 3, resulting in an off state and no current flowing from the back electrode 50 to the front electrode 32. When the IGBT of the transistor section 103 is turned off, the diode section 104 passes a return current that conducts in the reverse direction. Heat is generated due to switching loss and conduction loss during the on / off operation of the IGBT.

[0050] In conventional semiconductor devices, active elements such as IGBTs are managed to minimize manufacturing variations within a wafer, within a lot, between batches, etc. Therefore, the gate threshold voltage Vth is also strictly controlled, and various parameters such as the thickness of the gate insulating film are also strictly managed to improve uniformity in manufacturing. On the other hand, as miniaturization of IGBTs and the like progresses, the cell density increases, and the current density also increases. Therefore, the chip temperature is likely to rise, and the maximum junction temperature Tj increases due to heat generation. max If the voltage exceeds this limit, the chip will not function properly, its lifespan may be shortened, or it may even be destroyed.

[0051] To ensure normal operation and prevent breakdown, it is necessary to protect the chip from temperature rise. To protect the chip, a temperature detection diode is placed near the center of the chip to detect the maximum junction temperature Tj max When the temperature exceeds this limit, the thermal protection function activates and stops operation to prevent damage to the chip. Because the chip is protected in this way, it can be restarted when the temperature drops, and operation is guaranteed. Since the temperature detection diode is placed near the center of the chip, the active area is narrowed and the chip size is increased.

[0052] In contrast, in the semiconductor device according to the embodiment of the present disclosure, the effective carrier concentration of the base region 3 has a gradient and is non-uniform within the surface of the active region 101, being relatively high in the central portion 101a of the active region 101 and relatively low in the peripheral portion 101b of the active region 101. As a result, the gate threshold voltage Vth of the IGBT in the transistor portion 103 has a gradient and is non-uniform within the surface of the active region 101, being relatively high in the central portion 101a of the active region 101 and relatively low in the peripheral portion 101b of the active region 101.

[0053] This causes the IGBTs to turn on at non-uniform times across the surface of the active region 101, with the IGBTs in the peripheral portion 101b of the active region 101 turning on first and the IGBTs in the central portion 101a of the active region 101 turning on later. As a result, the time during which current flows in the IGBTs in the central portion 101a of the active region 101 is relatively shorter than that in the IGBTs in the peripheral portion 101b, making it possible to suppress temperature rise in the central portion 101a of the active region 101 and reduce losses.

[0054] Furthermore, by suppressing the temperature rise of the IGBT in the central portion 101a of the active region 101, it is possible to make the temperature rise uniform across the entire surface of the active region 101. This eliminates the need to place the temperature detection diode 100 in the central portion 101a of the active region 101, and it can be placed in the peripheral portion 101b or on the outer periphery other than the central portion 101a. This allows the area of ​​the active region 101 to be expanded, and the chip size to be reduced.

[0055] Furthermore, the maximum junction temperature Tj, which was previously determined at the center of the chip, max This makes it possible to widen the margin of error and the safe operating area (SOA) against temperature rise, thereby reducing the failure rate and improving reliability.

[0056] <Method of manufacturing a semiconductor device> Next, an example of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure will be described. Note that the method for manufacturing a semiconductor device described below is just one example, and it goes without saying that various other manufacturing methods, including modifications thereof, can be implemented within the scope of the spirit of the claims.

[0057] First, a first conductivity type (n - A semiconductor substrate (semiconductor wafer) of the same type as that of FIG. 2 is prepared and used as drift layer 1 (see FIG. 6). Note that the following explanation focuses on the cross section corresponding to the semiconductor chip of FIG. 2, and multiple chip regions that will become multiple semiconductor chips similar to the semiconductor chip of FIG. 2 are formed on the semiconductor wafer.

[0058] The drift layer 1 is partitioned into an active region 101 and a breakdown voltage structure portion 102. Next, an insulating film 20 (see FIG. 6) is formed on the upper surface of the drift layer 1, and the insulating film 20 is patterned by photolithography and dry etching. Using the patterned insulating film 20 as an ion implantation mask, p-type impurities such as boron (B) are ion-implanted to form a p-type well region 14 and a p-type guard ring layer 15 (see FIG. 6). Thereafter, a heat treatment is performed to form the p-type well region 14 and the p-type guard ring layer 15, as shown in FIG. 6. Of the insulating film 20 used as the ion implantation mask, the insulating film 20 located in the active region 101 is removed, leaving a portion of the insulating film 20 located in the breakdown voltage structure portion 102.

[0059] Next, photolithography and dry etching are used to selectively remove a portion of the upper part of the drift layer 1 in the active region 101. As a result, a plurality of trenches 6 are formed in the upper part of the drift layer 1 in the active region 101, as shown in FIG.

[0060] Next, a gate insulating film 7 (see FIG. 8) is formed on the bottom and side surfaces of the trench 6 by thermal oxidation, chemical vapor deposition (CVD), or the like. Next, a polysilicon film (doped polysilicon film) doped with a high concentration of impurities such as phosphorus (P) or boron (B) is deposited by CVD or the like so as to fill the inside of the trench 6 via the gate insulating film 7. Thereafter, the polysilicon film and the gate insulating film 7 are selectively removed by photolithography and dry etching. As a result, as shown in FIG. 8, a gate electrode 8 made of the gate insulating film 7 and a polysilicon film is formed inside the trench 6, thereby forming an insulated gate electrode structure (7, 8). Furthermore, a temperature detection diode 100 made of a polysilicon film is formed on the upper surface side of the well region 14, with an insulating film (not shown) interposed between the active region 101 and the temperature detection diode 100.

[0061] Next, a photoresist film is applied to the upper surface of the drift layer 1, and the photoresist film is patterned by photolithography. Using the patterned photoresist film as an ion implantation mask, p-type impurities such as boron (B) are ion-implanted from the upper surface of the drift layer 1 to form the p-type base region 3 of the transistor section 103 and the p-type anode region 11 of the diode section 104. The ion implantation may be performed in a single stage, or in multiple stages with different acceleration energies. The acceleration energy of the ion implantation is uniform (same) throughout the entire surface of the active region 101. The acceleration energy of the ion implantation is adjusted so that the position (depth) of the peak concentration of the p-type impurity in the base region 3 is deeper than the bottom surface of the emitter region 4. The acceleration energy of the ion implantation is, for example, about 300 keV or more and 650 keV or less. The dose of the ion implantation is uniform (same) throughout the entire surface of the active region 101, for example, 1×10 13 ions / cm 2 That's it, 1 x 10 15 ions / cm 2 The photoresist film is then removed.

[0062] Next, a photoresist film is applied to the upper surface of the drift layer 1 and patterned by photolithography. Using the patterned photoresist film as an ion implantation mask, n-type impurities such as phosphorus (P) or arsenic (As) are ion-implanted from the upper surface side of the drift layer 1 to form an n-type carrier accumulation layer 2. The photoresist film is then removed. The state up to this point is shown in Figure 9.

[0063] Next, a photoresist film is applied to the upper surface of the drift layer 1, and the photoresist film is patterned by photolithography. The patterned photoresist film is used as an ion implantation mask to implant p + To form p-type contact region 5, p-type impurities such as boron (B) are ion-implanted from the upper surface side of drift layer 1. Thereafter, the photoresist film is removed.

[0064] Next, a photoresist film is applied to the upper surface of the drift layer 1, and the photoresist film is patterned by photolithography. The patterned photoresist film is used as an ion implantation mask to implant n-type ions into the transistor section 103. + To form n-type emitter regions 4, n-type impurities such as phosphorus (P) or arsenic (As) are ion-implanted from the upper surface side of the drift layer 1. Thereafter, the photoresist film is removed.

[0065] The order of the ion implantation for forming the base region 3 and the anode region 11, the ion implantation for forming the carrier accumulation layer 2, the ion implantation for forming the contact region 5, and the ion implantation for forming the emitter region 4 is not particularly limited, and may be changed in any order.

[0066] Next, a heat treatment (activation annealing) is performed to activate the p-type impurities and n-type impurities that are dopants implanted into the drift layer 1 by the ion implantation for forming the base region 3 and the anode region 11, the ion implantation for forming the carrier accumulation layer 2, the ion implantation for forming the contact region 5, and the ion implantation for forming the emitter region 4. As a result, as shown in FIG. 10, in the transistor section 103, the n-type carrier accumulation layer 2, the p-type base region 3, the n-type + type emitter region 4 and p + In the diode section 104, an n-type carrier accumulation layer 2 and a p-type anode region 11 are formed on the upper surface side of the drift layer 1. In addition, a p-type well region 13 is formed on the outer periphery of the active region 101, and a p-type channel stopper 16 is formed in the breakdown voltage structure section 102.

[0067] The heat treatment (activation annealing) includes a heat treatment (first heat treatment) performed to heat the central portion 101a of the active region 101 at a higher temperature than the peripheral portion 101b. For example, the central portion 101a of the active region 101 is heated to, for example, about 1000°C or higher and 1100°C or lower, while the peripheral portion 101b of the active region 101 is annealed at a lower temperature, for example, about 900°C or higher and 1000°C or lower, than the heating temperature of the central portion 101a of the active region 101. Since the activation rate depends on the annealing temperature, the activation rate of the p-type impurity ions implanted into the base region 3 is relatively high in the central portion 101a of the active region 101 and relatively low in the peripheral portion 101b of the active region 101. Therefore, the effective carrier concentration of the base region 3 is also relatively high in the central portion 101a of the active region 101 and relatively low in the peripheral portion 101b of the active region 101.

[0068] As a heat treatment for creating a temperature gradient within the surface of the active region 101, for example, laser annealing is performed using a step-and-repeat laser annealing apparatus. For example, by locally irradiating a laser onto the central portion 101a of the active region 101 from the upper surface side of the drift layer 1, the central portion 101a becomes the highest temperature, and the temperature decreases from the central portion 101a toward the outer periphery.

[0069] As a laser used in laser annealing, for example, an excimer laser (wavelength 248 nm) such as krypton fluoride (KrF) or a green laser (wavelength 532 nm) can be used. In the case of KrF, for example, the laser power is 250 mJ / cm 2 More than 500mJ / cm 2 The pulse duration (full width at half maximum) is about 30 ns or more and 40 ns or less. In the case of a green laser, the laser power is 655 mJ / cm 2 More than 800mJ / cm 2 The pulse duration (full width at half maximum) is about 100 ns or more and 120 ns or less.

[0070] The laser spot diameter is smaller than the area of ​​the active region 101, for example, approximately 1 / 4 to 1 / 2 of the area of ​​the active region 101. The laser spot shape may be circular or rectangular. The heating temperature for laser annealing is, for example, approximately 1000°C to 1100°C. For example, when the semiconductor substrate is silicon, non-melt annealing can be performed at a temperature below the melting temperature of silicon (1420°C) to maintain the flatness of the upper surface of the semiconductor substrate. Alternatively, melt annealing may be performed at a temperature above the melting temperature of silicon, followed by a surface flattening process.

[0071] For example, coarse alignment for positioning a semiconductor wafer involves adjusting the X-axis position, Y-axis position, and rotation θ. If precision is required, fine alignment is then performed, measuring the misalignment at each location on the wafer surface using sampling measurements, performing statistical processing, and correcting for wafer rotation, magnification, etc. The stage position or light source is then moved in a step-and-repeat manner, and the laser irradiation is turned on and off (or sometimes weaker) for each chip area to anneal the entire chip area. For each chip area, the laser is turned on at the center of the chip area. If the chip area is small, the laser can be fixed (stopped) at one location and irradiated locally. For larger chip areas, the spot diameter can be adjusted to a larger value, the laser can be irradiated at multiple different locations in the center of the chip area, or the center of the chip area can be scanned in a cross pattern. By irradiating the center of the chip area with the laser, the heating temperature decreases from the center to the edge of the chip.

[0072] 11 is a schematic plan view of a semiconductor wafer 200. A plurality of chip regions 211, 212, 213, 221, 222, ... are formed on the semiconductor wafer 200. For example, in the laser annealing process, a laser is fixed and locally irradiated to central portions 211a, 212a, 213a, 221a, 222a, ... of the chip regions 211, 212, 213, 221, 222, ... in a step-and-repeat manner for each of the chip regions 211, 212, 213, 221, 222, ....

[0073] Laser annealing may be performed by scanning instead of step-and-repeat. For example, as shown in Fig. 11, when chip regions 211, 212, and 213 of a semiconductor wafer 200 are successively scanned in this order, the power may be relatively weakened in peripheral regions other than central regions 211a, 212a, and 213a of the chip regions 211, 212, and 213, and the power may be relatively strengthened in central regions 211a, 212a, and 213a of the chip regions 211, 212, and 213. Furthermore, the activation rate may be adjusted by relatively increasing the scanning speed in the peripheral regions of the chip regions 211, 212, and 213, and relatively decreasing the scanning speed in central regions 211a, 212a, and 213a of the chip regions 211, 212, and 213.

[0074] Fig. 12 shows the temperature dependence of the ion activation rate. As shown in Fig. 12, the higher the heat treatment temperature, the higher the ion activation rate tends to be. As an example, Fig. 12 shows the temperature dependence of the ion activation rate when nitrogen (N) and phosphorus (P) are ion-implanted into silicon carbide (SiC), but a similar tendency also occurs when p-type impurities such as boron (B) are ion-implanted into silicon (Si).

[0075] In addition, either before or after the local laser annealing, a global annealing (second heat treatment) is performed to uniformly heat the entire surface of the active region 101. Global annealing is performed by heating using a batch-type heat treatment device or rapid thermal processing (RTA) using a single-wafer heat treatment device to uniformly heat the entire surface of the semiconductor wafer and the entire surface of each chip region. The heating temperature for global annealing is lower than the heating temperature for laser annealing, and is, for example, about 900°C or higher and 1000°C or lower. Note that if the laser annealing is sufficient to activate the active region 101, including the peripheral portion 101b, global annealing may not be performed.

[0076] Next, an interlayer insulating film 21 (see FIG. 13) is formed on the upper surfaces of the active region 101 and the breakdown voltage structure 102 by a CVD method or the like. Next, a contact hole is opened in the interlayer insulating film 21 by photolithography and dry etching. Next, a contact plug 31 (see FIG. 13) is embedded in the contact hole via a barrier metal film (not shown) by a sputtering method or a vapor deposition method and dry etching or the like.

[0077] Next, a surface electrode 32 (see FIG. 13) is deposited on the upper surfaces of the contact plug 31 and the interlayer insulating film 21 by sputtering, vapor deposition, or the like. Then, a portion of the surface electrode 32 is selectively removed by photolithography and dry etching, as shown in FIG. 13. Next, a protective film 41 (see FIG. 14) is formed so as to cover the surface electrode 32 of the breakdown voltage structure portion 102. Next, a protective resist film 42 is formed so as to cover the surface electrode 32 of the active region 101 and the protective film 41 of the breakdown voltage structure portion 102, as shown in FIG. 14.

[0078] Next, the drift layer 1 is ground from the bottom side by back grinding (BG) or the like, and the thickness of the drift layer 1 is adjusted to the product thickness. Next, an n-type FS layer 9 is formed on the bottom side of the drift layer 1 shown in FIG. 2 by a photolithography process and ion implantation. Furthermore, a p-type FS layer 9 is formed on the bottom side of the FS layer 9 of the transistor section 103 shown in FIG. 2 by a photolithography process and ion implantation. + The diode section 104 has a collector region 10 of n type formed thereon, and the FS layer 9 of the diode section 104 has a lower surface side of the n type formed thereon. + The cathode region 12 of the mold is formed.

[0079] Next, a back electrode 50 made of gold (Au) or the like is formed by sputtering, vapor deposition, or the like on the lower surfaces of the collector region 10 and the cathode region 12 shown in Fig. 2. Thereafter, the semiconductor device according to the embodiment of the present disclosure is completed by cutting (dicing) the plurality of chip regions formed on the semiconductor substrate into individual pieces.

[0080] According to the manufacturing method of the semiconductor device according to the embodiment of the present disclosure, after ion implantation of p-type impurities to form the base region 3, activation annealing is performed so that the temperature is higher in the central portion 101a of the active region 101 than in the peripheral portion 101b, thereby making the activation rate of ions relatively high in the central portion 101a of the active region 101 and relatively low in the peripheral portion 101b of the active region 101. Therefore, it is possible to suppress the temperature rise in the central portion 101a of the active region 101 that accompanies the operation of the IGBT, thereby reducing loss.

[0081] Furthermore, according to the semiconductor device manufacturing method according to the embodiment of the present disclosure, ion implantation to form the base region 3 is performed with a uniform dose throughout the entire surface of the active region 101, and then laser annealing is performed to make the ion activation rate non-uniform within the surface of the active region 101, thereby making the effective carrier concentration non-uniform. Therefore, compared to the case where the impurity concentration is made non-uniform by performing ion implantation multiple times with different doses, the photolithography process and the ion implantation process can be reduced, thereby reducing costs and lead time. Furthermore, since it is only necessary to adjust the laser annealing conditions, the in-plane distribution of the effective carrier concentration of the base region 3 in the active region 101 can be easily changed.

[0082] (Other embodiments) Although the embodiments of the present disclosure have been described above, the descriptions and drawings that form part of this disclosure should not be understood to limit the present disclosure. Various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art from this disclosure.

[0083] For example, although an RC-IGBT is exemplified as an active element in the active region 101 of the semiconductor device according to the embodiment of the present disclosure, the present disclosure can also be applied to IGBTs other than the RC-IGBT. For example, the present disclosure can also be applied to a reverse-blocking insulated gate bipolar transistor (RB-IGBT) or an IGBT alone. In addition, the present disclosure can also be applied to the p-type IGBT of the transistor section 103 shown in FIGS. 2 and 3 as an active element in the active region 101 of the semiconductor device according to the embodiment of the present disclosure. + n-type collector region 10 +The present invention is also applicable to a MOSFET having a drain region of a trench gate type. Although a trench gate type active element has been exemplified as an active element in the active region 101 of the semiconductor device according to the embodiment of the present disclosure, the present invention is also applicable to a planar gate type active element.

[0084] Furthermore, the configurations disclosed in the embodiments of the present disclosure can be appropriately combined within the scope of not causing any contradiction. As such, the present disclosure naturally includes various embodiments not described herein. Therefore, the technical scope of the present disclosure is defined only by the invention-specifying matters according to the scope of the claims that are appropriate from the above description. [Explanation of symbols]

[0085] 1...Drift layer 2...Carrier accumulation layer 3...Base area 4...Emitter area 5...Contact area 6...Trench 7...Gate insulating film 8...Gate electrode 9...Field stop layer 10...Collector region 11...Anode region 12...Cathode region 13, 14...Well area 15...Guard ring layer 16...Channel stopper 20...Insulating film 21...Interlayer insulating film 31...Contact plug 32…Surface electrode 41...Protective film 42...Protective resist film 50...Back electrode 100...Temperature detection diode 101...Active region 101a...Central part 101b...periphery 102...Termination region (voltage-resistant structure) 103...Transistor section 104...Diode section 200...Semiconductor wafers 211, 212, 213, 221, 222...Chip area 211a, 212a, 213a, 221a, 222a...Central part

Claims

1. an active region and a drift layer of a first conductivity type provided in a termination region surrounding the active region; a second conductivity type base region provided on an upper surface side of the drift layer in the active region; a first conductivity type main region provided on an upper surface side of the base region; an insulated gate electrode structure provided in contact with the main region and the base region; Equipped with an effective carrier concentration of the base region is relatively high in a central portion of the active region and relatively low in a peripheral portion of the active region; The depth of the peak concentration of the base region is deeper than the bottom surface of the main region. Semiconductor device.

2. The concentration of impurities, including activated and non-activated impurities, in the base region is uniform across the entire surface of the active region. The semiconductor device according to claim 1 .

3. The depth of the base region is uniform across the entire surface of the active region.

3. The semiconductor device according to claim 1.

4. The activation rate of the impurity ions in the base region is relatively high in the center of the active region and relatively low in the peripheral region of the active region.

3. The semiconductor device according to claim 1.

5. providing a drift layer of a first conductivity type partitioned into an active region and a termination region surrounding the active region; forming a base region of a second conductivity type on an upper surface side of the drift layer in the active region; forming a first conductivity type main region on an upper surface side of the base region; Including, The step of forming the base region includes: ion-implanting a second conductivity type impurity from the upper surface side of the drift layer; Laser annealing is performed so that the temperature at the periphery of the active region is lower than that at the center. Including A method for manufacturing a semiconductor device.

6. The second conductivity type impurity is ion-implanted so that the depth of the peak concentration of the second conductivity type impurity is deeper than the lower surface of the main region. The method for manufacturing a semiconductor device according to claim 5 .

7. The laser annealing is performed by locally irradiating a laser beam to a central portion of each of a plurality of chip regions formed on a semiconductor wafer.

7. The method for manufacturing a semiconductor device according to claim 5 or 6.

8. The step of forming the base region further includes uniformly heat-treating the entire surface of the active region at a temperature lower than that of the laser annealing.

7. The method for manufacturing a semiconductor device according to claim 5 or 6.

9. The method further includes the step of forming a guard ring layer of a second conductivity type on the upper surface side of the drift layer in the termination region before the step of forming the base region.

7. The method for manufacturing a semiconductor device according to claim 5 or 6.

10. The method further includes the step of forming a contact plug in contact with the main region after the step of forming the base region.

7. The method for manufacturing a semiconductor device according to claim 5 or 6.

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