Semiconductor device

Abstract

To improve the trade-off relationship between the breakdown voltage and on-resistance of a semiconductor device.SOLUTION: The semiconductor device includes a drift layer of a first conductivity type, a channel layer of a second conductivity type, a source layer of the first conductivity type, a gate electrode, a source electrode, and a drain electrode, an impurity concentration of the drift layer is different in the drift layer, and when an integrated value of an electric field applied to the drift layer is defined as a breakdown voltage value and an integrated value of an electric field when the impurity concentration of the drift layer is constant in the drift layer is defined as a reference value, (breakdown voltage value-reference value) / reference value is 0 or more and 0.32 or less.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to semiconductor technology. [Background technology]

[0002] In semiconductor devices, the breakdown voltage and on-resistance are in a trade-off relationship, with the thickness and concentration of the drift layer as parameters. Therefore, there is a demand for technology that can simultaneously improve these two characteristics (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-232355 Summary of the Invention [Problem to be solved by the invention]

[0004] However, the technology of Patent Document 1 does not sufficiently improve the trade-off between breakdown voltage and on-resistance, and there is room for improvement.

[0005] The technology disclosed in the present specification has been made in consideration of the problems described above, and is a technology for improving the trade-off between the breakdown voltage and the on-resistance of a semiconductor device. [Means for solving the problem]

[0006] A semiconductor device that is a first aspect of the technology disclosed in the present specification includes a drift layer of a first conductivity type, a channel layer of a second conductivity type above the drift layer, a source layer of the first conductivity type above the channel layer, a gate electrode facing the channel layer sandwiched between the drift layer and the source layer via a gate insulating film, a source electrode connected to the source layer, and a drain electrode on a lower surface of the drift layer, wherein the impurity concentration of the drift layer varies within the drift layer, and where the integral value of the electric field applied to the drift layer is taken as a breakdown voltage and the integral value of the electric field when the impurity concentration of the drift layer is constant within the drift layer is taken as a reference value, (the breakdown voltage value−the reference value) / the reference value is greater than or equal to 0 and less than 0.32. [Effects of the Invention]

[0007] According to at least the first aspect of the technology disclosed in the present specification, by setting the increment in the breakdown voltage value / reference value to be 0 or more and 0.32 or less, the trade-off between the breakdown voltage and on-resistance of the semiconductor device can be improved compared to when the impurity concentration of the drift layer is constant.

[0008] Furthermore, objects, features, aspects, and advantages associated with the technology disclosed herein will become more apparent from the detailed description and accompanying drawings set forth below. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a plan view showing an example of a configuration of a semiconductor device according to an embodiment; [Figure 2] 2 is a plan view showing an example of the configuration of a region that is a part of the active region in FIG. 1. FIG. [Figure 3] FIG. 3 is a cross-sectional view showing an example of the AA' cross section in FIG. [Figure 4] FIG. 4 is a diagram showing an example of an impurity concentration profile at the cross section BB′ in FIG. [Figure 5] 4 is a diagram showing an example of an electric field distribution in the off state in the cross section BB' of FIG. 3. FIG. [Figure 6]FIG. 10 is a diagram showing an example of an electric field distribution generated by an n-drift layer during off-state. [Figure 7] FIG. 4 is a diagram showing a modified example of the impurity concentration profile at the cross section BB' in FIG. [Figure 8] FIG. 8 is a diagram showing an example of an electric field distribution during off-state caused by the n-drift layer shown in FIG. 7. [Figure 9] This figure shows the boundary where an improvement in breakdown voltage and a reduction in on-resistance are both achieved for a 600V-class device when the drift layer thickness is set to 5.5 μm. [Figure 10] FIG. 10 is a diagram showing the boundary at which an improvement in breakdown voltage and a reduction in on-resistance are both achieved for a 1200 V class device when the drift layer thickness is set to 10 μm. [Figure 11] FIG. 10 is a diagram showing the boundary where an improvement in breakdown voltage and a reduction in on-resistance are both achieved for a 1700 V class device when the drift layer thickness is set to 15 μm. [Figure 12] 1A to 1C are diagrams illustrating an example of a manufacturing method of a semiconductor device according to an embodiment. [Figure 13] 1A to 1C are diagrams illustrating an example of a manufacturing method of a semiconductor device according to an embodiment. [Figure 14] 1A to 1C are diagrams illustrating an example of a manufacturing method of a semiconductor device according to an embodiment. [Figure 15] 1A to 1C are diagrams illustrating an example of a manufacturing method of a semiconductor device according to an embodiment. [Figure 16] FIG. 3 is a cross-sectional view showing a modified example of the cross section AA' in FIG. 2 according to the embodiment. [Figure 17] 17 is a diagram showing an example of an impurity concentration profile of the CC' cross section in FIG. 16. FIG. [Figure 18] FIG. 3 is a cross-sectional view showing a modified example of the cross section AA' in FIG. 2 according to the embodiment. [Figure 19] FIG. 19 is a diagram showing an example of an impurity concentration profile at the DD' cross section in FIG. 18. [Figure 20] FIG. 3 is a cross-sectional view showing a modified example of the cross section AA' in FIG. 2 according to the embodiment. [Figure 21] FIG. 21 is a diagram showing an example of an impurity concentration profile at the EE' cross section in FIG. 20. [Figure 22] FIG. 3 is a cross-sectional view showing a modified example of the cross section AA' in FIG. 2 according to the embodiment. [Figure 23] 23 is a diagram showing an example of an impurity concentration profile at the FF' cross section in FIG. 22. FIG. [Figure 24] FIG. 10 is a plan view showing an example of the configuration of an insulated gate semiconductor device according to a comparative example. [Figure 25] 25 is a plan view showing an example of the configuration of a region that is a part of the active region in FIG. 24. FIG. [Figure 26] FIG. 26 is a cross-sectional view showing an example of the GG' cross section in FIG. [Figure 27] FIG. 27 is a diagram showing an example of an impurity concentration profile at the HH′ cross section in FIG. 26. [Figure 28] 27 is a diagram showing an example of an electric field distribution in the HH' cross section in FIG. 26 when the electric field is off. FIG. [Figure 29] FIG. 27 is a diagram showing an example of voltage distribution in the HH′ cross section in FIG. 26 when the voltage is off. [Figure 30] FIG. 10 is a diagram showing an example of resistance values ​​in an n-drift layer. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments will be described with reference to the accompanying drawings. In the following embodiments, detailed features are shown for the purpose of explaining the technology, but these are merely examples and are not necessarily essential features for enabling the embodiments to be implemented.

[0011] The drawings are schematic, and for the sake of convenience, components may be omitted or simplified as appropriate. The relative sizes and positions of components shown in different drawings are not necessarily accurately depicted and may be changed as appropriate. Hatching may also be used in drawings such as plan views that are not cross-sectional views to facilitate understanding of the embodiments.

[0012] In the following description, the same components are denoted by the same reference numerals, and their names and functions are also the same. Therefore, detailed descriptions of them may be omitted to avoid duplication.

[0013] Furthermore, in the description given in this specification, when a certain component is described as "comprising," "including," or "having," unless otherwise specified, this is not an exclusive expression that excludes the presence of other components.

[0014] Furthermore, although ordinal numbers such as "first" or "second" may be used in the descriptions in this specification, these terms are used for convenience to facilitate understanding of the contents of the embodiments, and the contents of the embodiments are not limited to the order that may result from these ordinal numbers.

[0015] Furthermore, in the description provided in this specification, terms that indicate specific positions or directions, such as "top," "bottom," "left," "right," "side," "bottom," "front," or "back," may be used, but these terms are used for convenience to facilitate understanding of the contents of the embodiments and have no relation to the positions or directions when the embodiments are actually implemented.

[0016] Furthermore, in the description of the present specification, when "the upper surface of ..." or "the lower surface of ..." is used, it is intended to include not only the upper surface or lower surface of the target component itself, but also a state in which another component is formed on the upper surface or lower surface of the target component. For example, when it is described as "B provided on the upper surface of A," it does not preclude another component "C" from being interposed between A and B.

[0017] First Embodiment The semiconductor device according to this embodiment will be described below.

[0018] <Configuration of semiconductor device> Power semiconductor devices, generally known as power devices, are used as switching elements that control the power supply to motor loads, etc. Power devices are required to have various performance characteristics, one of which is low loss.

[0019] Reducing loss in power devices has the effect of making the equipment smaller and lighter, which in turn reduces energy consumption and contributes to environmental friendliness. Furthermore, it is desirable to achieve these characteristics at the lowest possible cost.

[0020] As power semiconductor elements that meet these requirements, insulated gate semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are widely used, and in recent years, MOSFETs or IGBTs that use wide bandgap semiconductors such as silicon carbide (SiC) have been proposed.

[0021] MOSFETs using silicon carbide are devices that can achieve both low on-resistance and high main breakdown voltage, and because they are monopolar devices, their use is expanding to high-speed switching applications.

[0022] Fig. 1 is a plan view showing an example of the configuration of a semiconductor device according to this embodiment. As shown in Fig. 1, an active region 101, a gate wiring 102 (voltage-resistance holding region) formed to surround the active region 101, and a gate pad region 103 (control electrode) formed to contact the active region 101 are formed in an element region 100.

[0023] Fig. 2 is a plan view showing an example of the configuration of region 104, which is a part of the active region in Fig. 1. Source electrode contact region 16 is shown in Fig. 2. Fig. 3 is a cross-sectional view showing an example of the A-A' cross section in Fig. 2.

[0024] 2 and 3, an n+ buffer layer 2 is formed on the upper surface of an n+ semiconductor substrate 1 made of silicon carbide (SiC). An n- drift layer 3b is formed on the upper surface of n+ buffer layer 2, and an n- drift layer 3a is further formed on the upper surface of n- drift layer 3b.

[0025] Furthermore, an n-type junction field effect transistor (nJFET) doped layer 8 is formed on the n-drift layer 3a, and a p-channel doped layer 4 is formed on the nJFET doped layer 8. A p-well layer 7 is formed below the p-channel doped layer 4.

[0026] Furthermore, an n+ source layer 5 is formed on the p-channel doped layer 4, and a p+ contact layer 6 is formed on the p-channel doped layer 4 and surrounded by the n+ source layer 5.

[0027] Furthermore, a gate electrode 10 made of polysilicon or the like faces p-channel doped layer 4 sandwiched between n+ source layer 5 and nJFET doped layer 8 (the upper layer of n- drift layer 3a) via a gate insulating film 9. An interlayer insulating film 11 is formed to cover gate electrode 10. A source electrode 13 is connected to n+ source layer 5 and p+ contact layer 6 via a silicide layer 12.

[0028] Furthermore, a silicide layer 14 is formed on the lower surface of the n+ semiconductor substrate 1, and a drain electrode 15 is formed on the lower surface of the silicide layer 14.

[0029] Figure 3 shows the basic cell structure of the active region. A source electrode 13 is formed on the upper surface of the substrate, and a drain electrode 18 is formed on the lower surface of the substrate. The main current flows vertically across the substrate. A MOSFET consisting of an n+ source layer 5, a p-channel doped layer 4, drift layers (n-drift layer 3a and n-drift layer 3b), a gate insulating film 9, and a gate electrode 10 controls the current.

[0030] Furthermore, n+ buffer layer 2 is a region formed with a high concentration of n-type impurities to prevent holes from reaching n+ semiconductor substrate 1 during FWD operation of the device. In principle, as the depletion layer extends, it becomes partially depleted and shares voltage, but n+ buffer layer 2 has a high concentration and is set to share less voltage than the drift layers (n- drift layer 3a and n- drift layer 3b). Therefore, n+ buffer layer 2 will be omitted in the following discussion.

[0031] Fig. 4 is a diagram showing an example of an impurity concentration profile at the B-B' cross section in Fig. 3. In Fig. 4, the vertical axis represents impurity concentration, and the horizontal axis represents depth. Fig. 5 is a diagram showing an example of an electric field distribution at the B-B' cross section in Fig. 3 when the device is off. Fig. 6 is a diagram showing an example of an electric field distribution generated by n-drift layer 3a and n-drift layer 3b when the device is off. In Figs. 5 and 6, the vertical axis represents electric field strength, and the horizontal axis represents depth.

[0032] In this embodiment, as shown in FIG. 4, the drift layer is made up of n-drift layer 3a and n-drift layer 3b having two types of concentration gradients, and the electric field strength is as shown in FIG.

[0033] 6, we consider the area corresponding to the integral of the electric field strength that occurs in the range where n-drift layer 3a and n-drift layer 3b are formed. The integral of the electric field strength that occurs corresponds to the applied voltage, and the voltage value (integral value of the electric field strength, withstand voltage area) that corresponds to the critical electric field strength that causes avalanche breakdown is generally called the withstand voltage (withstand voltage value).

[0034] In the region where the n-drift layer 3a and the n-drift layer 3b are formed, the area of ​​the triangle enclosed by the line connecting the critical electric field strength at the boundary position between the n-drift layer 3a and the p-channel doped layer 4 and the electric field strength (which becomes 0) at the boundary position between the n-drift layer 3b and the n+ buffer layer 2, is defined as S. A Let this S Ais the area corresponding to the integrated value of the electric field strength when the impurity concentration is constant (no change in concentration) throughout the drift layer, and is also called the reference area (reference value). In Figure 6, the electric field strength applied to n-drift layer 3a and n-drift layer 3b is higher throughout the entire area than in the case of the reference value, and the breakdown voltage increases above the reference value.

[0035] Furthermore, from the above pressure-resistant area (pressure-resistant value), S A The area after subtracting S X In addition, the increase in the breakdown voltage value (increase in breakdown voltage) in the electric field distribution that is the limit at which the trade-off relationship between breakdown voltage and on-resistance improves is defined as S B In this case, S X is S B ≦ 0.32S A S that satisfies (condition 1) B The details of conditional expression 1 will be described later.

[0036] In this embodiment, as shown in the example of FIG. 4, the impurity concentration of n-drift layer 3a is set lower than the impurity concentration of n-drift layer 3b.

[0037] In this embodiment, as shown in the example of FIG. 4, the concentration gradient of n-drift layer 3a is set lower than the concentration gradient of n-drift layer 3b.

[0038] Here, a comparative example will be described.

[0039] 24 is a plan view showing an example of the configuration of an insulated gate semiconductor device (MOSFET) according to a comparative example. As shown in the example in Fig. 24, an active region 101, a gate wiring 102 formed to surround the active region 101, and a gate pad region 103 formed outside the active region 101 are formed in an element region 100.

[0040] Fig. 25 is a plan view showing an example of the configuration of region 104, which is a part of the active region in Fig. 24. Source electrode contact region 16 is shown in Fig. 25. Also, Fig. 26 is a cross-sectional view showing an example of the G-G' cross section in Fig. 25.

[0041] 25 and 26, an n+ buffer layer 2 is formed on the upper surface of an n+ semiconductor substrate 1. Then, an n- drift layer 3 is formed on the upper surface of the n+ buffer layer 2.

[0042] Furthermore, an nJFET doped layer 8 is formed on the n-drift layer 3, and a p-channel doped layer 4 is formed on the nJFET doped layer 8. A p-well layer 7 is formed below the p-channel doped layer 4.

[0043] Furthermore, an n+ source layer 5 is formed on the p-channel doped layer 4, and a p+ contact layer 6 is formed on the p-channel doped layer 4 and surrounded by the n+ source layer 5.

[0044] Furthermore, a gate electrode 10 made of polysilicon or the like faces p-channel doped layer 4 sandwiched between n+ source layer 5 and nJFET doped layer 8 via a gate insulating film 9. An interlayer insulating film 11 is formed to cover gate electrode 10. A source electrode 13 contacts n+ source layer 5 and p+ contact layer 6 via a silicide layer 12.

[0045] Furthermore, a silicide layer 14 is formed on the lower surface of the n+ semiconductor substrate 1, and a drain electrode 15 is formed on the lower surface of the silicide layer 14.

[0046] FIG. 27 is a diagram showing an example of an impurity concentration profile in the H-H' cross section in FIG. 26. In FIG. 27, the vertical axis represents impurity concentration, and the horizontal axis represents depth. FIG. 28 is a diagram showing an example of an electric field distribution in the H-H' cross section in FIG. 26 when the device is off. In FIG. 28, the vertical axis represents electric field strength, and the horizontal axis represents depth. FIG. 29 is a diagram showing an example of a voltage distribution in the H-H' cross section in FIG. 26 when the device is off. In FIG. 29, the vertical axis represents voltage strength, and the horizontal axis represents depth. FIG. 30 is a diagram showing an example of resistance values ​​in the n-drift layer 3. In FIG. 30, the vertical axis represents resistance value, and the horizontal axis represents depth.

[0047] First, the effects of this embodiment will be described.

[0048] As a premise, the depletion layer also penetrates into p-channel doped layer 4 and shares the voltage, but because the impurity concentration of p-channel doped layer 4 is at least one order of magnitude higher than the impurity concentration of n-drift layer 3a and n-drift layer 3b, the voltage sharing on the p-channel doped layer 4 side will be approximated as 0 in the following discussion, for the same reason as in the technique usually referred to as a one-sided abrupt junction.

[0049] In principle, n+ semiconductor substrate 1 and n+ buffer layer 2 also share the voltage, but since this is minute compared to the share of n- drift layer 3a and n- drift layer 3b, their voltage share is also approximated to 0, and the discussion will focus only on n- drift layer 3a and n- drift layer 3b.

[0050] Switching elements including MOSFETs require two functions: current interruption when turned off, and current carrying capacity when turned on.

[0051] When the MOSFET (see Figure 26) is turned off and current is cut off, the MOSFET channel, which is composed of the n+ source layer 5, p-channel doped layer 4, and n- drift layer 3, turns off, and the n- drift layer 3 becomes depleted, maintaining the breakdown voltage, thereby realizing its function.

[0052] The electric field is determined based on the impurity concentration, and the main parameters of this breakdown voltage are the thickness and impurity concentration of n-drift layer 3. Since the breakdown voltage is determined by the integral of the electric field, the lower the impurity concentration of n-drift layer 3 and the thicker the n-drift layer 3, the higher the breakdown voltage.

[0053] In contrast, when it is on, the channel is on and current flows through it. Because MOSFETs are monopolar devices and do not undergo conductivity modulation, the on-resistance when current is applied is determined by the sum of components such as the channel resistance, the drift resistance of the n-drift layer 3, and the contact resistance. At this time, the drift resistance is determined by the impurity concentration and thickness of the n-drift layer 3; the lower the impurity concentration of the n-drift layer 3 and the thinner the n-drift layer 3, the lower the resistance.

[0054] For this reason, the breakdown voltage and the on-resistance exhibit a trade-off relationship with the thickness and impurity concentration of the n-drift layer 3 as parameters, and it is therefore difficult to improve these two characteristics simultaneously.

[0055] However, in this embodiment, as compared to the comparative example shown in Figure 27, the n-drift layer is formed of two types of layers, n-drift layer 3a and n-drift layer 3b, as shown in the example of Figure 4, and the impurity concentration and concentration gradient (rate of change in concentration) of n-drift layer 3a are set lower than the impurity concentration and concentration gradient (rate of change in concentration) of n-drift layer 3b.

[0056] In such a case, when the depletion layer reaches the n+ buffer layer 2, the electric field distribution in the n- drift layer 3a and the n- drift layer 3b is a triangular area (S A ) but a pressure-bearing area (S A +S X 5 and 6, the maximum electric field strength is the same as in the comparative example, but the electric field applied to n-drift layer 3a and n-drift layer 3b is always higher than the triangular electric field in the comparative example. As a result, the arc of the breakdown voltage area is convex upward.

[0057] In this embodiment, the breakdown voltage value corresponding to the level of breakdown voltage is S A S is larger than A +S X Therefore, even if the drift layer thickness is the same, the breakdown voltage increases. In other words, by forming a concentration gradient in the drift layer, the breakdown voltage area can be increased by increasing the electric field while maintaining the critical electric field strength. Therefore, the breakdown voltage can be increased.

[0058] This electric field distribution having an arched arc varies depending on the impurity concentration, concentration gradient, and thickness of n-drift layer 3a and the impurity concentration, concentration gradient, and thickness of n-drift layer 3b, and therefore, a higher breakdown voltage can be obtained by setting these parameters.

[0059] Fig. 7 is a diagram showing a modified example of the impurity concentration profile of the B-B' cross section in Fig. 3. In Fig. 7, the vertical axis represents impurity concentration, and the horizontal axis represents depth. The impurity concentration profile shown by the dotted line in Fig. 7 corresponds to a case where, compared to the case in Fig. 4 (solid line), the impurity concentration and concentration gradient in n-drift layer 3a are set low, the thickness of n-drift layer 3a is set thick, the impurity concentration and concentration gradient in n-drift layer 3b are set high, and the thickness of n-drift layer 3b is set thin.

[0060] Fig. 8 is a diagram showing an example of an electric field distribution during off-state caused by n-drift layer 3a and n-drift layer 3b shown in Fig. 7. In Fig. 8, the vertical axis represents electric field strength, and the horizontal axis represents depth.

[0061] As shown in the example of FIG. 8, the electric field strength (dotted line) corresponding to the impurity concentration profile shown in FIG. 7 has a larger breakdown voltage value than the case (solid line) shown in FIG. 6. In other words, the area S A The breakdown voltage and area S of the comparative example based on A +S X The breakdown voltage in the case shown in FIG. 8 is higher than the breakdown voltage in the case shown in FIG.

[0062] In the case shown in FIG. 8, the breakdown voltage is increased, but the increase in on-resistance is also large. Therefore, compared to the comparative example in which the same breakdown voltage is achieved by increasing the thickness of n-drift layer 3, the on-resistance may increase, or the on-resistance may increase conversely when the substrate thickness is adjusted.

[0063] The inventors have found that the region in which the breakdown voltage can be increased and the on-resistance can be improved is substantially limited, and is restricted to the electric field distribution in the range in which a bow-shaped arc is formed (the range in which a drift layer is formed) as shown in Figure 8.

[0064] FIG. 9 is a diagram showing the boundary where both an improvement in breakdown voltage and a reduction in on-resistance are achieved for a 600V class device when the drift layer thickness is 5.5 μm. FIG. 10 is a diagram showing the boundary where both an improvement in breakdown voltage and a reduction in on-resistance are achieved for a 1200V class device when the drift layer thickness is 10 μm. FIG. 11 is a diagram showing the boundary where both an improvement in breakdown voltage and a reduction in on-resistance are achieved for a 1700V class device when the drift layer thickness is 15 μm. In FIGS. 9, 10, and 11, the vertical axis represents the index (on-resistance variation rate / breakdown voltage variation rate), and the horizontal axis represents S B / S A Shows.

[0065] In Figures 9, 10 and 11, S A indicates the area (reference value) of the triangle shown in Figure 28, and S B is the increase (S A +S B -S A ) indicates S B is the increase in the breakdown voltage value (increase in breakdown voltage) in the electric field distribution that is the limit at which the trade-off relationship between breakdown voltage and on-resistance is improved in this embodiment compared to the case shown in FIG. 28 (comparison example).

[0066] The breakdown voltage fluctuation rate is the breakdown voltage / S A The on-resistance variation rate is defined as the on-resistance of the structure / the on-resistance of the comparative example structure.

[0067] In other words, the condition for the index (on-resistance fluctuation rate / breakdown voltage fluctuation rate) to be 1.0 is when the fluctuations in the breakdown voltage and on-resistance are effectively balanced, and S B / S A =0(S B This indicates that the trade-off relationship between breakdown voltage and on-resistance is the same as that in the comparative example (=0). If the index (on-resistance fluctuation rate / breakdown voltage fluctuation rate) is greater than 1, it indicates that the trade-off has worsened, and if the index (on-resistance fluctuation rate / breakdown voltage fluctuation rate) is 1 or less, it indicates that the trade-off has improved.

[0068] In Figures 9, 10 and 11, the above index is S B / S A = 0, it shows a concave characteristic as a whole, which is 1. The inventors have found that the range in which the above exponent is 1 or less is limited, and that it is approximately S B / S A It was confirmed that the range is limited to ≦ 0.32 (conditional expression 1). B / S A When is greater than or equal to 0 and less than or equal to 0.32, it is less than or equal to 1, and S B / S A When is 0.11 or more and 0.21 or less, it is 0.93 or less, and S B / S A When is 0.16, it becomes 0.922.

[0069] If conditional expression 1 is not satisfied, the trade-off cannot be improved from the comparative example. However, if conditional expression 1 is satisfied, the trade-off between on-resistance and breakdown voltage can be improved compared to the comparative example by appropriate design.

[0070] In this embodiment, the step-shaped region is formed to satisfy this condition.

[0071] As a condition for forming such a structure, it is effective that the impurity concentration of n-drift layer 3a is lower than the impurity concentration of n-drift layer 3b and lower than the impurity concentration of n-drift layer 3 in the comparative example. Specifically, the impurity concentration of n-drift layer 3a and n-drift layer 3b is 5×10 16 / cm 3 The impurity concentration of the n-drift layer 3a on the source side is 1×10 15 / cm 3 Above and 2 x 10 16 / cm 3 The impurity concentration of the n-drift layer 3b on the drain side is 5×10 15 / cm 3 Above and 5 x 10 16 / cm 3 The following configuration can efficiently satisfy the above conditions.

[0072] Also, considering manufacturing variations, S B / S A But always S B / S A =0 and S B / S A Therefore, it is effective to manufacture the product so that the value is between 0.11 and S = 0.32. B / S A Narrow the range to ≦0.21, or B / S A If the concentration is designed around =0.16, the possibility of improving the trade-off can be increased. B / S A Even if there is variation, as long as some of the variations satisfy conditional expression 1, an improvement in the trade-off can be achieved.

[0073] <About the manufacturing method of semiconductor devices> Next, a method for manufacturing a semiconductor device according to this embodiment will be described with reference to Figures 12, 13, 14, and 15. Figures 12, 13, 14, and 15 are diagrams showing an example of the method for manufacturing a semiconductor device according to this embodiment.

[0074] 12 shows a state where nothing is formed on n+ semiconductor substrate 1. In this state, n+ buffer layer 2 is formed at an appropriate concentration on the upper surface side of n+ semiconductor substrate 1 by means of epitaxial growth or the like (see FIG. 13).

[0075] Next, n-drift layer 3b is formed by epitaxial growth or other means while changing the concentration of the gas that is the source of the N-type impurity so as to obtain an appropriate concentration and concentration gradient (see FIG. 14).

[0076] Furthermore, n-drift layer 3a is formed by epitaxial growth or other methods while changing the gas flow rate and other conditions to achieve an appropriate concentration (see FIG. 15).

[0077] By forming structures on the upper and lower surfaces of the structure shown in Fig. 15, the structure shown in Fig. 3 can be manufactured. Note that the steps from Fig. 15 onwards can be formed using a general semiconductor device formation process, so details will be omitted.

[0078] As described above, in this embodiment, by forming the drift layer so as to satisfy the electric field distribution conditions discovered by the inventors, it is possible to increase the breakdown voltage even with the same drift layer thickness and improve the trade-off relationship between the breakdown voltage and on-resistance. In other words, by increasing the breakdown voltage area without changing the critical electric field strength, the breakdown voltage can be increased and the trade-off relationship between the breakdown voltage and on-resistance can be improved.

[0079] <Second embodiment> A semiconductor device according to the present embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0080] <Configuration of semiconductor device> Fig. 16 is a cross-sectional view showing a modified example of the A-A' cross section in Fig. 2 according to this embodiment. Fig. 17 is a diagram showing an example of an impurity concentration profile in the C-C' cross section in Fig. 16. In Fig. 17, the vertical axis represents the impurity concentration, and the horizontal axis represents the depth.

[0081] The manufacturing method of the structure shown in FIG. 16 is similar to that shown in the first embodiment except for the n-drift layer 3c, and therefore details will be omitted.

[0082] In this embodiment, n-drift layer 3c is formed in the area where n-drift layer 3a and n-drift layer 3b in FIG. 3 were formed.

[0083] The n-drift layer 3c has a certain gradient of impurity concentration, as shown in Fig. 17. The n-drift layer 3c has a low impurity concentration on the source side, and the impurity concentration increases gradually (linearly) toward the drain side.

[0084] The electric field distribution formed by the concentration gradient in the n-drift layer 3c is shown in S B Specifically, the concentration gradient of the n-drift layer 3c is controlled to be within the range of S A The inclination angle of the oblique side is appropriately adjusted to satisfy the above conditional expression 1.

[0085] According to the present embodiment, since it is configured as described above, it is possible to increase the breakdown voltage even with the same drift layer thickness, and improve the trade-off relationship between the breakdown voltage and the on-resistance. That is, by increasing the breakdown voltage area without changing the critical electric field strength, it is possible to increase the breakdown voltage and improve the trade-off relationship between the breakdown voltage and the on-resistance.

[0086] The impurity concentration of the n-drift layer 3c is 5×10 16 / cm 3 The impurity concentration of the n-drift layer 3c on the source side is 1×10 15 / cm3 Above and 2 x 10 16 / cm 3 The impurity concentration of the n-drift layer 3c on the drain side is 5×10 15 / cm 3 Above and 5 x 10 16 / cm 3 It is desirable to configure it as follows:

[0087] <Third embodiment> A semiconductor device according to the present embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0088] <Configuration of semiconductor device> Fig. 18 is a cross-sectional view showing a modified example of the A-A' cross section in Fig. 2 according to this embodiment. Fig. 19 is a diagram showing an example of an impurity concentration profile in the D-D' cross section in Fig. 18. In Fig. 19, the vertical axis represents the impurity concentration, and the horizontal axis represents the depth.

[0089] The method for manufacturing the structure shown in FIG. 18 is similar to that shown in the first embodiment except for the n-drift layer 3d and n-drift layer 3e, and therefore details will be omitted.

[0090] In this embodiment, n-drift layers 3d and 3e are formed in the portions where n-drift layers 3a and 3b in FIG. 3 were formed.

[0091] 19, n-drift layer 3d and n-drift layer 3e each have a constant impurity concentration, and the impurity concentration of lower n-drift layer 3e is higher than the impurity concentration of upper n-drift layer 3d. In other words, the impurity concentration of the n-drift layer increases in a stepwise manner from the source side to the drain side.

[0092] The electric field distribution formed in the n-drift layer 3d and the n-drift layer 3e is shown in S B Specifically, the concentration gradient of the n-drift layer 3d and the n-drift layer 3e is controlled to be within the range of S A The inclination angle of the oblique side is appropriately adjusted to satisfy the above conditional expression 1.

[0093] According to this embodiment, the impurity concentration of the n-drift layer is constant in the portion on the surface where the MOS structure is formed.

[0094] According to the present embodiment, since it is configured as described above, it is possible to increase the breakdown voltage even with the same drift layer thickness, and improve the trade-off relationship between the breakdown voltage and the on-resistance. That is, by increasing the breakdown voltage area without changing the critical electric field strength, it is possible to increase the breakdown voltage and improve the trade-off relationship between the breakdown voltage and the on-resistance.

[0095] Furthermore, as shown in FIG. 19, in this embodiment, the impurity concentration is constant in the portion where the surface MOS structure (p channel doped layer 4, n+ source layer 5, etc.) is formed, so that it is possible to reduce fluctuations in threshold voltage or on-resistance due to the influence of concentration variations during manufacturing.

[0096] The impurity concentration of the n-drift layer 3d and the n-drift layer 3e is 5×10 16 / cm 3 The impurity concentration of the n-drift layer 3d on the source side is 1×10 15 / cm 3 Above and 2 x 10 16 / cm 3 The impurity concentration of the n-drift layer 3e on the drain side is 5×10 15 / cm 3 Above and 5 x 10 16 / cm 3 It is desirable to configure it as follows:

[0097] <Fourth embodiment> A semiconductor device according to the present embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0098] <Configuration of semiconductor device> Fig. 20 is a cross-sectional view showing a modified example of the A-A' cross section in Fig. 2 according to the present embodiment. Fig. 21 is a diagram showing an example of an impurity concentration profile in the E-E' cross section in Fig. 20. In Fig. 21, the vertical axis represents the impurity concentration, and the horizontal axis represents the depth.

[0099] The method for manufacturing the structure shown in FIG. 20 is similar to that shown in the first embodiment except for n-drift layer 3f, n-drift layer 3g, and n-drift layer 3h, and therefore details will be omitted.

[0100] In this embodiment, n-drift layers 3f, 3g, and 3h are formed in the portions where n-drift layers 3a and 3b in FIG. 3 were formed.

[0101] 21, n-drift layer 3f and n-drift layer 3h each have a constant impurity concentration, with the impurity concentration of lower n-drift layer 3h being higher than the impurity concentration of upper n-drift layer 3f. N-drift layer 3g is formed between n-drift layer 3f and n-drift layer 3h, and has an impurity concentration that changes continuously from the impurity concentration of n-drift layer 3f to the impurity concentration of n-drift layer 3h.

[0102] The electric field distribution formed in the n-drift layer 3f, the n-drift layer 3g, and the n-drift layer 3h is shown in S B Specifically, the concentration gradients of n-drift layer 3f, n-drift layer 3g, and n-drift layer 3h are controlled to reduce the area of ​​S in the diagram showing the electric field distribution. AThe inclination angle of the hypotenuse is appropriately adjusted to satisfy the above conditional expression 1.

[0103] According to this embodiment, the impurity concentration of the n-drift layer is constant in the portion on the surface where the MOS structure is formed.

[0104] According to the present embodiment, since it is configured as described above, it is possible to increase the breakdown voltage even with the same drift layer thickness, and improve the trade-off relationship between the breakdown voltage and the on-resistance. That is, by increasing the breakdown voltage area without changing the critical electric field strength, it is possible to increase the breakdown voltage and improve the trade-off relationship between the breakdown voltage and the on-resistance.

[0105] Furthermore, as shown in FIG. 21, in this embodiment, the impurity concentration is constant in the portion of the surface where the MOS structure is formed, and therefore, it is possible to reduce fluctuations in threshold voltage or on-resistance due to the influence of concentration variations during manufacturing.

[0106] The impurity concentration of n-drift layer 3f, n-drift layer 3g, and n-drift layer 3h is 5×10 16 / cm 3 The impurity concentration of the n-drift layer 3f on the source side is 1×10 15 / cm 3 Above and 2 x 10 16 / cm 3 The impurity concentration of the n-drift layer 3h on the drain side is 5×10 15 / cm 3 Above and 5 x 10 16 / cm 3 It is desirable to configure it as follows:

[0107] <Fifth embodiment> A semiconductor device according to the present embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0108] <Configuration of semiconductor device> Fig. 22 is a cross-sectional view showing a modified example of the A-A' cross section in Fig. 2 according to the present embodiment. Fig. 23 is a diagram showing an example of an impurity concentration profile in the F-F' cross section in Fig. 22. In Fig. 23, the vertical axis represents the impurity concentration, and the horizontal axis represents the depth.

[0109] The method for manufacturing the structure shown in FIG. 22 is similar to that shown in the first embodiment except for the n-drift layer 3i, n-drift layer 3j, and n-drift layer 3k, and therefore details will be omitted.

[0110] In this embodiment, n-drift layers 3i, 3j, and 3k are formed in the portions where n-drift layers 3a and 3b in FIG. 3 were formed.

[0111] 23, n-drift layer 3i, n-drift layer 3j, and n-drift layer 3k each have a constant impurity concentration, and the impurity concentration of lower n-drift layer 3k is higher than the impurity concentration of upper n-drift layer 3i. N-drift layer 3j is formed between n-drift layer 3i and n-drift layer 3k, and has an impurity concentration that is between the impurity concentration of n-drift layer 3i and the impurity concentration of n-drift layer 3k.

[0112] The electric field distribution formed in the n-drift layer 3i, the n-drift layer 3j, and the n-drift layer 3k is S B Specifically, the concentration gradients of n-drift layer 3i, n-drift layer 3j, and n-drift layer 3k are controlled to reduce the area of ​​S A The inclination angle of the hypotenuse is appropriately adjusted to satisfy the above conditional expression 1.

[0113] According to this embodiment, the impurity concentration of the n-drift layer is constant in the portion on the surface where the MOS structure is formed.

[0114] According to the present embodiment, since it is configured as described above, it is possible to increase the breakdown voltage even with the same drift layer thickness, and improve the trade-off relationship between the breakdown voltage and the on-resistance. That is, by increasing the breakdown voltage area without changing the critical electric field strength, it is possible to increase the breakdown voltage and improve the trade-off relationship between the breakdown voltage and the on-resistance.

[0115] Furthermore, as shown in FIG. 23, in this embodiment, the impurity concentration is constant in the portion where the MOS structure is formed on the surface, and therefore, it is possible to reduce fluctuations in threshold voltage or on-resistance due to the influence of concentration variations during manufacturing.

[0116] The impurity concentration of n-drift layer 3i, n-drift layer 3j, and n-drift layer 3k is 5×10 16 / cm 3 The impurity concentration of the n-drift layer 3i on the source side is 1×10 15 / cm 3 Above and 2 x 10 16 / cm 3 The impurity concentration of the n-drift layer 3k on the drain side is 5×10 15 / cm 3 Above and 5 x 10 16 / cm 3 or less, and it is desirable that the impurity concentration of the drain-side n-drift layer 3j be between the impurity concentrations of the n-drift layer 3i and the n-drift layer 3k.

[0117] <Effects Produced by the Multiple Embodiments Described Above> Next, examples of effects obtained by the above-described embodiments will be described. Note that in the following description, the effects will be described based on the specific configurations exemplified in the above-described embodiments, but these may be replaced with other specific configurations exemplified in the present specification as long as the same effects are obtained. In other words, for convenience, only one of the associated specific configurations may be described as a representative below, but the representatively described specific configuration may be replaced with another associated specific configuration.

[0118] Furthermore, the replacement may be made across multiple embodiments, i.e., configurations illustrated in different embodiments may be combined to produce the same effect.

[0119] According to the embodiment described above, the semiconductor device includes a drift layer of a first conductivity type, a channel layer of a second conductivity type above the drift layer, a source layer of the first conductivity type above the channel layer, a gate electrode 10 facing the channel layer sandwiched between the drift layer and the source layer via a gate insulating film 9, a source electrode 13 connected to the source layer, and a drain electrode 15 on the lower surface side of the drift layer. Here, the drift layer corresponds to, for example, n-drift layer 3a, n-drift layer 3b, n-drift layer 3c, n-drift layer 3d, n-drift layer 3e, n-drift layer 3f, n-drift layer 3g, n-drift layer 3h, n-drift layer 3i, n-drift layer 3j, n-drift layer 3k, etc. The channel layer corresponds to, for example, p-channel doped layer 4, etc. The source layer corresponds to, for example, n+ source layer 5, etc. The impurity concentration of the drift layer varies within the drift layer. Furthermore, if the integral value of the electric field applied to the drift layer is the breakdown voltage value, and the integral value of the electric field when the impurity concentration of the drift layer is constant within the drift layer is the reference value, then (breakdown voltage value - reference value) / reference value is greater than or equal to 0 and less than or equal to 0.32.

[0120] With this configuration, the increment in the breakdown voltage value / reference value is greater than or equal to 0 and less than or equal to 0.32, thereby improving the trade-off between the breakdown voltage and on-resistance of the semiconductor device compared to when the impurity concentration of the drift layer is constant.

[0121] Furthermore, even if other configurations shown as examples in this specification are appropriately added to the above configuration, that is, even if other configurations in this specification that were not mentioned as the above configuration are appropriately added, the same effect can be achieved.

[0122] Furthermore, according to the embodiment described above, (breakdown voltage value-reference value) / reference value is 0.11 or more and 0.21 or less. With this configuration, even if manufacturing variations occur, it becomes easier to realize a drift layer concentration design that improves the trade-off.

[0123] Furthermore, according to the embodiment described above, (breakdown voltage value-reference value) / reference value is 0.16. With this configuration, even if manufacturing variations occur, it becomes easier to realize a drift layer concentration design that improves the trade-off.

[0124] Furthermore, according to the embodiment described above, the electric field strength applied to the drift layer corresponding to the breakdown voltage value is higher across the entire drift layer than the electric field strength applied to the drift layer corresponding to the reference value. With this configuration, the breakdown voltage value is increased, and therefore the breakdown voltage of the semiconductor device can be increased.

[0125] Furthermore, according to the embodiment described above, the drift layer has a first region (n-drift layer 3a) and a second region (n-drift layer 3b) that is closer to drain electrode 15 than the first region. The first rate of change, which is the rate of change of the electric field applied to n-drift layer 3a, is lower than the second rate of change, which is the rate of change of the electric field applied to n-drift layer 3b. With this configuration, the arch of the breakdown voltage area is convex upward, and the breakdown voltage value increases. This makes it possible to increase the breakdown voltage of the semiconductor device.

[0126] Furthermore, according to the embodiment described above, the rate of change of the electric field applied to the n-drift layer 3 corresponding to the reference value is defined as the reference rate of change. The first rate of change is lower than the reference rate of change, and the second rate of change is higher than the reference rate of change. With this configuration, the arch of the voltage-resistant area is convex upward, increasing the voltage-resistant value. This increases the voltage-resistant value of the semiconductor device.

[0127] According to the embodiment described above, the drift layer is made of silicon carbide. The impurity concentration of the drift layer is 5×10 16 / cm 3 According to this configuration, the increment in the breakdown voltage value / reference value is equal to or greater than 0 and equal to or less than 0.32, and therefore the trade-off between the breakdown voltage and the on-resistance of the semiconductor device can be improved compared to when the impurity concentration of the drift layer is constant.

[0128] Furthermore, according to the embodiment described above, the drift layer has a first region (n-drift layer 3a, n-drift layer 3d, n-drift layer 3f, n-drift layer 3g, n-drift layer 3i, n-drift layer 3j) and a second region (n-drift layer 3b, n-drift layer 3e, n-drift layer 3h, n-drift layer 3k) that is closer to drain electrode 15 than the first region. The impurity concentration of the drift layer in the first region is equal to or lower than the impurity concentration of the drift layer in the second region. With this configuration, the increment in the breakdown voltage / reference value is equal to or greater than 0 and equal to or less than 0.32, which improves the trade-off between the breakdown voltage and on-resistance of the semiconductor device compared to when the impurity concentration of the drift layer is constant.

[0129] Furthermore, according to the embodiment described above, the impurity concentration of the drift layer in the first region (n-drift layer 3a, n-drift layer 3d, n-drift layer 3f, n-drift layer 3i) is 1×10 15 / cm 3 Above and 2 x 10 16 / cm 3or less, and the impurity concentration of the drift layers in the second region (n-drift layer 3b, n-drift layer 3e, n-drift layer 3h, n-drift layer 3k) is 5×10 15 / cm 3 Above and 5 x 10 16 / cm 3 According to this configuration, the increment in the breakdown voltage value / reference value is equal to or greater than 0 and equal to or less than 0.32, and therefore the trade-off between the breakdown voltage and the on-resistance of the semiconductor device can be improved compared to when the impurity concentration of the drift layer is constant.

[0130] Furthermore, according to the embodiment described above, the impurity concentration of n-drift layer 3c increases linearly from source electrode 13 to drain electrode 15. With such a configuration, it is possible to easily form a drift layer having an impurity concentration that satisfies the conditions.

[0131] Furthermore, according to the embodiment described above, the impurity concentration of the drift layer increases stepwise from the first region (n-drift layer 3d, n-drift layer 3f, n-drift layer 3i, n-drift layer 3j) to the second region (n-drift layer 3e, n-drift layer 3h, n-drift layer 3k). With this configuration, it is possible to easily form a drift layer having an impurity concentration that satisfies the conditions.

[0132] Furthermore, according to the embodiment described above, the impurity concentration of the drift layer in one of the first region (n-drift layer 3a, n-drift layer 3d, n-drift layer 3f, n-drift layer 3g, n-drift layer 3i, n-drift layer 3j) and the second region (n-drift layer 3b, n-drift layer 3e, n-drift layer 3h, n-drift layer 3k) does not change, but the impurity concentration of the drift layer in the other region changes. With this configuration, it is possible to easily form drift layers having impurity concentrations that satisfy certain conditions.

[0133] Furthermore, according to the embodiment described above, there is no change in the impurity concentration of the drift layers (n-drift layer 3d, n-drift layer 3f, n-drift layer 3i) closer to source electrode 13. This configuration can reduce fluctuations in threshold voltage or on-resistance due to the influence of concentration variations during manufacturing.

[0134] Furthermore, according to the embodiment described above, p-channel doped layer 4 and n+ source layer 5 are provided in the drift layer (n-drift layer 3d, n-drift layer 3f, n-drift layer 3i) closer to source electrode 13, where the impurity concentration does not change. This configuration can reduce fluctuations in threshold voltage or on-resistance due to concentration variations during manufacturing.

[0135] <Modifications of the above-described embodiments> In the multiple embodiments described above, a concentration gradient of the impurity concentration, or the number or width of the step-type steps, etc. are shown, but these are merely examples, and as long as a structure satisfies the electric field distribution in the multiple embodiments described above, it is possible to improve the trade-off between breakdown voltage and on-resistance even if the concentration gradient, the number or width of the step-type steps, etc. are not as exemplified.

[0136] Furthermore, in the above-described embodiments, planar type semiconductor devices have been shown, but trench type semiconductor devices may also be used.

[0137] In the multiple embodiments described above, the material, composition, dimensions, shape, relative positional relationship, or implementation conditions of each component may also be described, but these are merely examples in all aspects and are not limiting.

[0138] Therefore, countless modifications and equivalents not shown as examples are contemplated within the scope of the technology disclosed in the present specification, including, for example, modifying, adding, or omitting at least one component, and further, extracting at least one component in at least one embodiment and combining it with a component in another embodiment.

[0139] Furthermore, in at least one of the embodiments described above, when a material name or the like is stated without being specifically specified, unless a contradiction arises, it is assumed that the material in question includes other additives, such as alloys.

[0140] Furthermore, unless a contradiction arises, when it is stated in the above-described embodiments that "one" component is provided, "one or more" of that component may also be provided.

[0141] Furthermore, each component in the embodiments described above is a conceptual unit, and the scope of the technology disclosed in this specification includes cases where one component is made up of multiple structures, cases where one component corresponds to part of a structure, and even cases where multiple components are provided in one structure.

[0142] Furthermore, each of the components in the embodiments described above includes structures having other structures or shapes as long as they perform the same function.

[0143] Furthermore, the descriptions in this specification are incorporated by reference for all purposes related to the present technology, and none of them are admitted to be prior art.

[0144] Various aspects of the present disclosure are summarized below as appendices.

[0145] (Appendix 1) a drift layer of a first conductivity type; a second conductivity type channel layer above the drift layer; a first conductivity type source layer above the channel layer; a gate electrode facing the channel layer sandwiched between the drift layer and the source layer via a gate insulating film; a source electrode connected to the source layer; a drain electrode on a lower surface of the drift layer, the impurity concentration of the drift layer varies within the drift layer, When an integral value of the electric field applied to the drift layer is defined as a breakdown voltage value, and an integral value of the electric field when the impurity concentration of the drift layer is constant within the drift layer is defined as a reference value, (the breakdown voltage value - the reference value) / the reference value is equal to or greater than 0 and equal to or less than 0.32. Semiconductor device.

[0146] (Appendix 2) 10. The semiconductor device according to claim 1, (the withstand voltage value - the reference value) / the reference value is 0.11 or more and 0.21 or less, Semiconductor device.

[0147] (Appendix 3) 3. The semiconductor device according to claim 1, (the withstand voltage value - the reference value) / the reference value is 0.16, Semiconductor device.

[0148] (Appendix 4) The semiconductor device according to any one of Supplementary Notes 1 to 3, an electric field strength applied to the drift layer corresponding to the breakdown voltage value is higher than an electric field strength applied to the drift layer corresponding to the reference value over the entire region of the drift layer; Semiconductor device.

[0149] (Appendix 5) A semiconductor device according to any one of Supplementary Notes 1 to 4, the drift layer has a first region and a second region that is closer to the drain electrode than the first region, a first rate of change that is a rate of change of the electric field applied to the drift layer in the first region is lower than a second rate of change that is a rate of change of the electric field applied to the drift layer in the second region; Semiconductor device.

[0150] (Appendix 6) 6. The semiconductor device according to claim 5, a change rate of the electric field applied to the drift layer corresponding to the reference value is defined as a reference change rate; the first rate of change is lower than the reference rate of change, and the second rate of change is higher than the reference rate of change; Semiconductor device.

[0151] (Appendix 7) 7. The semiconductor device according to claim 1, the drift layer is formed of silicon carbide, The impurity concentration of the drift layer is 5×10 16 / cm 3 Below is the Semiconductor device.

[0152] (Appendix 8) 8. The semiconductor device according to claim 1, the drift layer has a first region and a second region that is closer to the drain electrode than the first region, an impurity concentration of the drift layer in the first region is equal to or lower than an impurity concentration of the drift layer in the second region; Semiconductor device.

[0153] (Appendix 9) 9. The semiconductor device according to claim 8, The impurity concentration of the drift layer in the first region is 1×10 15 / cm 3 Above and 2 x 10 16 / cm 3 the impurity concentration of the drift layer in the second region is 5×10 or less 15 / cm 3 Above and 5 x 1016 / cm 3 Below is the Semiconductor device.

[0154] (Appendix 10) 10. The semiconductor device according to claim 8 or 9, an impurity concentration of the drift layer linearly increasing from the source electrode to the drain electrode; Semiconductor device.

[0155] (Appendix 11) 10. The semiconductor device according to claim 8 or 9, the impurity concentration of the drift layer increases stepwise from the first region toward the second region; Semiconductor device.

[0156] (Appendix 12) 10. The semiconductor device according to claim 8 or 9, the impurity concentration of the drift layer in one of the first region and the second region does not change, and the impurity concentration of the drift layer in the other region changes; Semiconductor device.

[0157] (Appendix 13) 10. The semiconductor device according to claim 8 or 9, the impurity concentration of the drift layer on the side closer to the source electrode does not change; Semiconductor device.

[0158] (Appendix 14) 14. The semiconductor device according to claim 13, the channel layer and the source layer are provided in the drift layer on a side closer to the source electrode where the impurity concentration does not change; Semiconductor device. [Explanation of symbols]

[0159] 1 n+ semiconductor substrate, 2 n+ buffer layer, 3 n- drift layer, 3a n- drift layer, 3b n- drift layer, 3c n- drift layer, 3d n- drift layer, 3e n- drift layer, 3f n- drift layer, 3g n- drift layer, 3h n- drift layer, 3i n- drift layer, 3j n- drift layer, 3k n- drift layer, 4 p channel doped layer, 5 n+ source layer, 6 p+ contact layer, 7 p well layer, 8 nJFET doped layer, 9 gate insulating film, 10 gate electrode, 11 interlayer insulating film, 12 silicide layer, 13 source electrode, 14 silicide layer, 15 drain electrode, 16 source electrode contact region, 18 drain electrode, 100 element region, 101 active region, 102 gate wiring, 103 gate pad region, 104 region.

Claims

1. a drift layer of a first conductivity type; a second conductivity type channel layer above the drift layer; a source layer of a first conductivity type above the channel layer; a gate electrode facing the channel layer sandwiched between the drift layer and the source layer via a gate insulating film; a source electrode connected to the source layer; a drain electrode on a lower surface of the drift layer, the impurity concentration of the drift layer varies within the drift layer, When an integral value of the electric field applied to the drift layer is defined as a breakdown voltage value, and an integral value of the electric field when the impurity concentration of the drift layer is constant within the drift layer is defined as a reference value, (the breakdown voltage value−the reference value) / the reference value is equal to or greater than 0 and equal to or less than 0.

32. Semiconductor device.

2. 2. The semiconductor device according to claim 1, (the withstand voltage value−the reference value) / the reference value is 0.11 or more and 0.21 or less, Semiconductor device.

3. 3. The semiconductor device according to claim 1, (the withstand voltage value−the reference value) / the reference value is 0.16, Semiconductor device.

4. 3. The semiconductor device according to claim 1, an electric field strength applied to the drift layer corresponding to the breakdown voltage value is higher than an electric field strength applied to the drift layer corresponding to the reference value over the entire region of the drift layer; Semiconductor device.

5. 3. The semiconductor device according to claim 1, the drift layer has a first region and a second region that is closer to the drain electrode than the first region, a first rate of change that is a rate of change of an electric field applied to the drift layer in the first region is lower than a second rate of change that is a rate of change of an electric field applied to the drift layer in the second region; Semiconductor device.

6. 6. The semiconductor device according to claim 5, a change rate of the electric field applied to the drift layer corresponding to the reference value is set as a reference change rate; the first rate of change is lower than the reference rate of change, and the second rate of change is higher than the reference rate of change; Semiconductor device.

7. 3. The semiconductor device according to claim 1, the drift layer is formed of silicon carbide, The impurity concentration of the drift layer is 5×10 １６ / cm ３ Below is the Semiconductor device.

8. 3. The semiconductor device according to claim 1, the drift layer has a first region and a second region that is closer to the drain electrode than the first region, an impurity concentration of the drift layer in the first region is equal to or lower than an impurity concentration of the drift layer in the second region; Semiconductor device.

9. 9. The semiconductor device according to claim 8, The impurity concentration of the drift layer in the first region is 1×10 １５ / cm ３ or more, and 2 x 10 １６ / cm ３ the impurity concentration of the drift layer in the second region is 5×10 １５ / cm ３ Above and 5 x 10 １６ / cm ３ Below is the Semiconductor device.

10. 9. The semiconductor device according to claim 8, an impurity concentration of the drift layer linearly increasing from the source electrode to the drain electrode; Semiconductor device.

11. 9. The semiconductor device according to claim 8, the impurity concentration of the drift layer increases stepwise from the first region toward the second region; Semiconductor device.

12. 9. The semiconductor device according to claim 8, the impurity concentration of the drift layer in one of the first region and the second region does not change, and the impurity concentration of the drift layer in the other region changes; Semiconductor device.

13. 9. The semiconductor device according to claim 8, the impurity concentration of the drift layer on the side closer to the source electrode does not change; Semiconductor device.

14. 14. The semiconductor device according to claim 13, the channel layer and the source layer are provided in the drift layer on a side closer to the source electrode where the impurity concentration does not change; Semiconductor device.

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