A / d converter

Abstract

To provide an A / D converter including a comparator capable of outputting a comparison result at a high speed with a simple configuration.SOLUTION: The A / D converter 10 is a successive approximation A / D converter including a comparator 100. The comparator 100 includes a first transistor TR1, a second transistor TR2, and a third transistor TR3 as P-type MOS transistors. The comparator 100 includes a fourth transistor N2, a fifth transistor, and an eighth transistor having sources connected to the ground potential VSS, drains connected to the second node TR4, and gates connected to the reference potential, the third node, and the first signal, respectively. Further, the comparator 100 includes a sixth transistor N3, a seventh transistor N2, and a ninth transistor TR6 whose sources are connected to the ground potential VSS, whose drains are connected to the third node TR7, and whose gates are connected to the second node TR9, the comparison potential, and the first signal, respectively.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to an A / D converter. [Background technology]

[0002] Conventionally, there have been proposed techniques relating to comparators used in successive approximation A / D converters and the like, which are configured with an operational amplifier circuit and a latch circuit. Patent Document 1 discloses a comparator applied to an A / D converter. The comparator disclosed in Patent Document 1 amplifies the potential difference between a reference potential, which is input to a current mirror operational amplifier provided in the first stage, and a comparison potential, and holds the amplified output as a comparison result in a latch circuit in the second stage. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 5-346441 Summary of the Invention [Problem to be solved by the invention]

[0004] In the comparator disclosed in Patent Document 1, the signal amplified by the operational amplifier circuit is stored in a latch circuit, so the time required for amplifying the signal by the operational amplifier circuit and the time required for latching the amplified signal are required for comparing potentials. Furthermore, the operational amplifier circuit and the latch circuit must be provided separately, which increases the circuit size.

[0005] The present disclosure has been made in view of the problems inherent in the conventional techniques, and an object of the present disclosure is to provide an A / D converter including a comparator that has a simple configuration and is capable of outputting a comparison result at high speed. [Means for solving the problem]

[0006] An A / D converter according to an embodiment of the present disclosure includes: a capacitive DAC that samples an analog input potential and generates a comparison potential based on control from a conversion data generator; a reference potential generator that generates a reference potential that is half the potential between a power supply potential and a ground potential; a comparator that compares the comparison potential and the reference potential to generate a comparison result; and a conversion data generator that generates conversion data from the comparison result, controls the capacitive DAC based on the conversion data, and calculates and outputs a digital conversion value. The comparator includes a first transistor that is a P-type MOS transistor having a source connected to the power supply potential, a gate connected to a clock signal, and a drain connected to a first node, and that is turned on during a comparison period; and a P-type MOS transistor having a source connected to the first node, a gate connected to a third node, and a drain connected to a second node. a third transistor consisting of a P-type MOS transistor having a source connected to a ground potential and a drain connected to the second node, the third transistor being a P-type MOS transistor having a source connected to a ground potential and a drain connected to the second node, the fourth transistor having a gate connected to a reference potential, a fifth transistor having a gate connected to the third node, and an eighth transistor having a gate connected to a first signal that is turned on during a period in which the first transistor is off; and a sixth transistor having a gate connected to the second node, a seventh transistor having a gate connected to a comparison potential, and a ninth transistor having a gate connected to the first signal, the sixth transistor having a gate connected to the second node, a seventh transistor having a gate connected to a comparison potential, and a ninth transistor having a gate connected to the first signal. [Effects of the Invention]

[0007] According to the present disclosure, it is possible to provide an A / D converter including a comparator that can output a comparison result at high speed with a simple configuration. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing the configuration of an A / D converter according to the first embodiment. [Figure 2]FIG. 2 is a diagram showing an operational amplifier circuit and a latch circuit applied to an A / D converter as a comparative example. [Figure 3] FIG. 3 is a diagram for explaining the operation of a latch circuit shown as a comparative example. [Figure 4] FIG. 4 is a diagram showing the configuration of a comparator applied to the A / D converter according to the first embodiment. [Figure 5] FIG. 5 is a diagram showing the configuration of an A / D converter according to the second embodiment. [Figure 6] FIG. 6 is a diagram showing the configuration of a comparator applied to the A / D converter according to the second embodiment. [Figure 7A] FIG. 7A is a diagram showing an example of the configuration of a discharge signal generating circuit applied to the A / D converter according to the second embodiment. [Figure 7B] FIG. 7B is a diagram for explaining the operation of the discharge signal generating circuit applied to the A / D converter according to the second embodiment. [Figure 8] FIG. 8 is a diagram for explaining the operation of the comparator applied to the A / D converter according to the second embodiment. [Figure 9A] FIG. 9A is a diagram for explaining the operation of a comparator applied to the A / D converter according to the second embodiment. [Figure 9B] FIG. 9B is a diagram for explaining the operation of the comparator as a comparative example. [Figure 9C] FIG. 9C is a diagram for explaining the operation of the comparator as a comparative example. [Figure 9D] FIG. 9D is a diagram for explaining the operation of the comparator applied to the A / D converter according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, an A / D converter 10 according to several embodiments of the present disclosure will be described in detail with reference to the drawings. The same or equivalent parts in the drawings of the A / D converter 10 according to each embodiment will be designated by the same reference numerals, and their description will be omitted.

[0010] 1 is a diagram showing the configuration of an A / D converter 10 according to the first embodiment. The A / D converter 10 is a successive approximation type A / D converter including a comparator 100, a conversion data generator 200, a capacitive DAC 300 (D / A converter), and a reference potential generator 400.

[0011] The capacitive DAC 300 samples the analog input potential and generates a comparison potential under control of the conversion data generator 200. The reference potential generator 400 generates a reference potential that is half the potential between the power supply potential VCC and the ground potential VSS. The comparator 100 compares the comparison potential with the reference potential to generate a comparison result. The conversion data generator 200 generates conversion data from the comparison result, controls the capacitive DAC 300 based on the conversion data, and calculates and outputs a digital conversion value.

[0012] (Comparative example of a comparator) 2 is a diagram showing an operational amplifier circuit and a latch circuit applied to an A / D converter as a comparative example. In the comparative example shown in FIG. 2, the comparator is made up of two circuits: an operational amplifier circuit and a latch circuit.

[0013] 2, a current mirror operational amplifier is provided in the first stage, and the operational amplifier circuit amplifies the potential difference between the reference potential and the comparison potential, which is the input. A latch circuit is provided in the second stage, and holds the output amplified by the operational amplifier circuit as the comparison result.

[0014] In the conventional comparator shown in Figure 2, the signal amplified by the operational amplifier circuit is held in a latch circuit, so the time required to compare potentials is the time it takes for the operational amplifier circuit to amplify the signal and the time it takes to latch the amplified signal, which poses a problem in terms of speed in a comparator configured with a conventional operational amplifier circuit and latch circuit.

[0015] Furthermore, in conventional comparators, the operational amplifier circuit requires a constant current circuit, as shown in Figure 2. Therefore, in order to obtain a stable constant current, a large-scale circuit is required, which poses the problem of a large layout area.

[0016] 3 is a diagram for explaining the operation of a latch circuit shown as a comparative example. The latch circuit shown in FIG. 3 is a circuit configured with a first transistor TR1 to a seventh transistor TR7. The circuit configured with the second transistor TR2 to the seventh transistor TR7 is a circuit similar to a general SRAM memory cell. The first transistor TR1 is a circuit that turns on / off the circuit configured with the second transistor TR2 to the seventh transistor TR7.

[0017] The first transistor TR1 is a P-type MOS (P-type Metal-Oxide Semiconductor) transistor having a source connected to a power supply potential VCC, a gate connected to a clock signal / CLK, and a drain connected to a first node N1. The first transistor TR1 is turned on during the comparison period of the comparator 100.

[0018] The second transistor TR2 is configured as a P-type MOS transistor having a source connected to the first node N1, a gate connected to the third node N3, and a drain connected to the second node N2.

[0019] The third transistor TR3 is configured as a P-type MOS transistor having a source connected to the first node N1, a gate connected to the second node N2, and a drain connected to a third node N3.

[0020] The fourth transistor TR4 is configured as an N-type MOS transistor having a source connected to the ground potential VSS, a gate connected to the reference potential, and a drain connected to the second node N2.

[0021] The fifth transistor TR5 is an N-type MOS transistor having a source connected to the ground potential VSS, a gate connected to the third node N3, and a drain connected to the second node N2. The fourth transistor TR4 and the fifth transistor TR5 correspond to a plurality of N-type MOS transistors having sources connected to the ground potential VSS and drains connected to the second node N2.

[0022] The sixth transistor TR6 is configured as an N-type MOS transistor having a source connected to the ground potential VSS, a gate connected to the second node N2, and a drain connected to the third node N3.

[0023] The seventh transistor TR7 is an N-type MOS transistor having a source connected to the ground potential VSS, a gate connected to a comparison potential, and a drain connected to the third node N3. The sixth transistor TR6 and the seventh transistor TR7 correspond to a plurality of N-type MOS transistors having sources connected to the ground potential VSS and drains connected to the third node N3.

[0024] Next, we will explain the operation of the latch circuit shown in Fig. 3. First, when a Hi (High) potential is applied to / CLK and the first transistor TR1 is off, it is assumed that the first node N1, the second node N2, and the third node N3 are at 0 V (=ground potential VSS).

[0025] In this case, the first transistor TR1 is the only transistor connected to the power supply potential VCC, so the potentials of the first node N1 to the third node N3 remain at 0V regardless of the behavior of the second transistor TR2 to the seventh transistor TR7.

[0026] Next, when the potential of / CLK changes from Hi to Lo (Low), that is, when the first transistor TR1 turns on, one of the second node N2 and the third node N3 will become Hi and the other will become Lo.

[0027] On the other hand, when the circuit formed by the second transistor TR2 and the fifth transistor TR5 in this circuit is treated as a NOT circuit (inverter circuit), the third node N3 ≠ the second node N2. Similarly, when the circuit formed by the third transistor TR3 and the sixth transistor TR6 is treated as a NOT circuit (inverter circuit), the second node N2 ≠ the third node N3.

[0028] That is, this circuit is stable when the potential of the second node N2 is not equal to the potential of the third node N3. Whether the second node N2 or the third node N3 becomes Hi or Lo is determined the moment the potential of / CLK changes from Hi to Lo. That is, whether the second node N2 or the third node N3 becomes Hi or Lo is determined by whether the fourth transistor TR4 or the seventh transistor TR7 passes more current the moment the first transistor TR1 turns on.

[0029] The magnitude of the currents in the fourth transistor TR4 and the seventh transistor TR7 is determined by the gate potential (=reference potential) of the fourth transistor TR4 and the gate potential (=comparison potential) of the seventh transistor TR7.

[0030] Assume that the fourth transistor TR4 and the seventh transistor TR7 have the same characteristics. In this case, when the comparison potential is higher than the reference potential, when / CLK switches from Hi to Lo (when the first transistor TR1 turns on), more current flows through the seventh transistor TR7 than through the fourth transistor TR4. As a result, the potential of the third node N3 drops below the potential of the second node N2, and the circuit operates in a more stable direction. As a result, the third node N3 stabilizes at the potential of the ground potential VSS, and the second node N2 stabilizes at the potential of the power supply potential VCC. In this case, the comparison result (= the potential of the second node N2) is Hi, which indicates that the comparison potential is higher than the reference potential.

[0031] On the other hand, conversely, when the comparison potential is lower than the reference potential and / CLK switches from Hi to Lo (the first transistor TR1 turns on), more current flows through the fourth transistor TR4 than through the seventh transistor TR7. As a result, the potential of the second node N2 drops below the potential of the third node N3, and the circuit operates in a more stable direction. As a result, the second node N2 stabilizes at the potential of the ground potential VSS, and the third node N3 stabilizes at the potential of the power supply potential VCC. In this case, the comparison result (= the potential of the second node N2) is Lo, which indicates that the comparison potential is lower than the reference potential.

[0032] If the above operation could be achieved, the operational amplifier circuit shown in Figure 2 would be unnecessary, and a high-speed, small-scale comparator could be realized. However, in reality, the circuit shown in Figure 3 cannot be used as a comparator.

[0033] Specifically, for example, when the reference potential is half the power supply potential VCC and the comparison potential is lower than half the power supply potential VCC and lower than the Vth (threshold voltage) of the N-type MOS transistor, the second node N2 is at the ground potential VSS, the third node N3 is at the power supply potential VCC, and the comparison result is Lo.

[0034] In this case, the first transistor TR1 must be turned off temporarily to perform the next comparison. When the first transistor TR1 is turned off, the second transistor TR2 to the seventh transistor TR7 are disconnected from the power supply potential VCC. Here, the gate of the fourth transistor TR4 is at the reference potential (1 / 2 the power supply potential VCC), and the fourth transistor TR4 is on. Therefore, the potential of the second node N2 is the ground potential VSS.

[0035] Since the potential of the second node N2 is the ground potential VSS, the third transistor TR3 is on, the sixth transistor TR6 is off, and the comparison potential is assumed to be lower than the Vth of the NMOS, so the seventh transistor TR7 is off.

[0036] At this time, there are no transistors that clearly drive the first node N1 and the third node N3, so the first node N1 and the third node N3 are in a floating state and have an unstable potential with an unclear charge.

[0037] Furthermore, even if the comparison potential changes and exceeds the reference potential, for example, if / CLK becomes Lo and the comparison operation is started before the charge is completely discharged (before the first node N1 and the third node N3 become the ground potential VSS level), a malfunction may occur. That is, even if the comparison potential becomes a potential higher than the reference potential, the comparison result may become Lo and a malfunction may occur.

[0038] The comparator 100 according to this embodiment prevents the above malfunction and realizes a comparator that can output a comparison result at high speed with a simple configuration.

[0039] (First embodiment) FIG. 4 is a diagram showing the configuration of a comparator 100 used in the A / D converter 10 according to the first embodiment. As shown in FIG. 4, the comparator 100 includes an eighth transistor TR8, which is an N-type MOS transistor having a drain connected to the second node N2, a gate connected to a reference potential, and a source connected to the ground potential VSS. The comparator 100 also includes a ninth transistor TR9, which is an N-type MOS transistor having a drain connected to the third node N3, a gate connected to the reference potential, and a source connected to the ground potential VSS. In the first embodiment, the first signal corresponds to a signal to which the reference potential is supplied. That is, the first signal is a signal that is turned on even when the first transistor TR1 is off.

[0040] The malfunction in the comparative example described above is caused by the charge and potential of the third node N3 being unstable at the start of the comparison operation (the time when / CLK changes from Hi to Lo). Therefore, the comparator 100 according to this embodiment includes a ninth transistor TR9 for extracting the charge of the third node N3 while / CLK is Hi.

[0041] Furthermore, since the second node N2 and the third node N3 need to have a symmetrical relationship, an eighth transistor TR8 having the same characteristics as the ninth transistor TR9 is provided at the second node N2.

[0042] By the eighth transistor TR8 and the ninth transistor TR9, the first node N1, the second node N2, the third node N3, and the ground potential VSS are set at the start of the comparison operation, making it possible to prevent malfunctions during the comparison operation.

[0043] Furthermore, in the comparator 100 according to this embodiment, the potential applied to the gates of the eighth transistor TR8 and the ninth transistor TR9 is the "reference potential" of the A / D converter 10, so that only two transistors are newly added. Therefore, by eliminating the operational amplifier circuit in the comparator 100 of the A / D converter 10, a high-speed, small-scale circuit can be realized.

[0044] (Second embodiment) As described above, one specific embodiment has been described, but the above-described embodiment is merely an example and is not intended to limit the scope of the present invention. For example, the above-described embodiment illustrates a configuration including an eighth transistor TR8 and a ninth transistor TR9 that operate at a reference potential. Here, a configuration different from that of the first embodiment will be described for an A / D converter 10 according to a second embodiment in which the eighth transistor TR8 and the ninth transistor TR9 in the comparator 100 operate in response to a discharge signal (discharge).

[0045] Fig. 5 is a diagram showing the configuration of an A / D converter 10 according to the second embodiment. The example shown in Fig. 5 differs from the A / D converter 10 according to the first embodiment in that it includes a discharge signal generation circuit 110.

[0046] 6 is a diagram showing the configuration of a comparator 100 used in the A / D converter 10 according to the second embodiment. As shown in Fig. 6, the comparator 100 includes an eighth transistor TR8 which is an N-type MOS transistor having a drain connected to the second node N2, a gate connected to the discharge signal generation circuit 110, and a source connected to the ground potential VSS. The comparator 100 also includes a ninth transistor TR9 which is an N-type MOS transistor having a drain connected to the third node N3, a gate connected to the discharge signal generation circuit 110, and a source connected to the ground potential VSS.

[0047] That is, the comparator 100 according to the second embodiment differs from the comparator 100 according to the first embodiment in that a discharge signal generated by the discharge signal generating circuit 110 is input to the gates of the eighth transistor TR8 and the ninth transistor TR9.

[0048] Fig. 7A is a diagram showing an example of the configuration of a discharge signal generation circuit 110 applied to the A / D converter 10 according to the second embodiment. Fig. 7B is a diagram for explaining the operation of the discharge signal generation circuit 110 applied to the A / D converter 10 according to the second embodiment.

[0049] The discharge signal is a pulse signal obtained by multiplying the / CLK signal by a signal obtained by delaying the CLK signal and inverting High and Low. In the discharge signal generation circuit 110, for example, a discharge signal that turns on during a delay period from time T2 to time T3 in FIG. 7B is generated. That is, the discharge signal generation circuit 110 generates the discharge signal as the output of an AND circuit that receives as input a clock signal ( / CLK) and a signal obtained by inverting and delaying the clock signal. Note that in the second embodiment, the first signal corresponds to the discharge signal. That is, the first signal is a signal that turns on when the first transistor TR1 is off (while / CLK is Hi).

[0050] 8 is a diagram illustrating the operation of the comparator 100 applied to the A / D converter 10 according to the second embodiment. The problem in the comparative example described above arises from the fact that the charges and potentials of the second node N2 and the third node N3 are indefinite at the start of the comparison operation (times T4 and T7 when / CLK changes from Hi to Lo). Therefore, the discharge signal generation circuit 110 generates a discharge signal that turns on when / CLK changes from Lo to Hi, that is, at times T5 and T8 when the comparison period ends (the end of the comparison period). Furthermore, since the discharge signal turns on when / CLK changes from Lo to Hi, it is on during the period when the first transistor TR1 is off. Furthermore, the discharge signal turns off (at time T6) before the start of the comparison period (time T7).

[0051] When the discharge signal is turned on, the eighth transistor TR8 and the ninth transistor TR9 are turned on, the charges at the second node N2 and the third node N3 are discharged, and the potentials at the second node N2 and the third node N3 become the ground potential VSS level.

[0052] As a result, the second node N2 and the third node N3 are reset to the ground potential VSS after the comparison period ends, so that the next comparison operation is performed normally and no malfunction occurs in the comparison operation.

[0053] The comparator 100 according to the second embodiment only includes an eighth transistor TR8, a ninth transistor TR9, and a simple logic of a discharge signal generation circuit 110 for generating a discharge signal. Therefore, by not using an operational amplifier circuit in the comparator 100 of the A / D converter 10, a high-speed and small-scale circuit can be realized.

[0054] Here, the operation of the comparator 100 according to the second embodiment will be described when / CLK, rather than a discharge signal, is input to the gates of the eighth transistor TR8 and the ninth transistor TR9. When / CLK is input to the gates of the eighth transistor TR8 and the ninth transistor TR9, the charges at the second node N2 and the third node N3 are also drawn before the comparison operation starts. However, in this case, the following problem occurs.

[0055] 9A is a diagram for explaining the operation of the comparator 100 applied to the A / D converter 10 according to the second embodiment. Fig. 9A illustrates the operation when a discharge signal is input to the gates of the eighth transistor TR8 and the ninth transistor TR9 in the configuration according to the second embodiment. At time T10, / CLK changes from Hi to Lo, and at time T11, the first transistor TR1 turns on. Thus, the eighth transistor TR8 and the ninth transistor TR9 must be in the off state (OFF state) at the start of the comparison operation when / CLK changes from Hi to Lo (time T10).

[0056] 9B and 9C are diagrams illustrating the operation of the comparator 100 as a comparative example. The examples shown in FIGS. 9B and 9C illustrate the operation when / CLK is input to the gates of the eighth transistor TR8 and the ninth transistor TR9. Ideally, when the comparison operation starts and / CLK changes from Hi to Lo, the first transistor TR1, the eighth transistor TR8, and the ninth transistor TR9 operate simultaneously (multiple state transitions occur). For example, FIG. 9B shows waveforms illustrating this ideal operation, but considering the "physical properties" of transistors, it is difficult for multiple state transitions to occur at exactly the same time.

[0057] 9C, if slight variations in transistor characteristics cause a delay in the timing at which the ninth transistor TR9 turns off, there will be a period (period P1) in which both the first transistor TR1 and the ninth transistor TR9 are on. In this case, regardless of the potentials of the reference potential and the comparison potential, when the ninth transistor TR9 turns on, the third node N3 goes from Lo to Lo and the second node N2 goes from Lo to Hi. As a result, the comparator will not function properly.

[0058] Therefore, for example, as shown in Fig. 9D, it is necessary that the eighth transistor TR8 and the ninth transistor TR9 are off and the states of the eighth transistor TR8 and the ninth transistor TR9 are determined before the first transistor TR1 is turned on. In the comparator 100 according to the second embodiment, the state shown in Fig. 9D is realized by inputting a discharge signal to the gates of the eighth transistor TR8 and the ninth transistor TR9.

[0059] (Other embodiments) Although the embodiments have been described in detail with reference to the drawings, the present embodiments are not limited to the contents described in the above embodiments. Furthermore, the components described above include those that can be easily imagined by a person skilled in the art and those that are substantially the same. Furthermore, the configurations described above can be combined as appropriate. Furthermore, various omissions, substitutions, or modifications of the configurations can be made without departing from the spirit of the embodiments.

[0060] The features of the A / D converter 10 and the comparator 100 are described below.

[0061] An A / D converter 10 according to a first aspect includes a capacitive DAC 300 that samples an analog input potential and generates a comparison potential under control of a conversion data generator 200. The A / D converter 10 also includes a reference potential generator 400 that generates a reference potential that is half the potential between a power supply potential VCC and a ground potential VSS. The A / D converter 10 also includes a comparator 100 that compares the comparison potential with the reference potential to generate a comparison result. The A / D converter 10 also includes a conversion data generator 200 that generates conversion data from the comparison result, controls the capacitive DAC 300 based on the conversion data, and calculates and outputs a digital conversion value. The comparator 100 includes a first transistor TR1 that is a P-type MOS transistor having a source connected to the power supply potential VCC, a gate connected to a clock signal, and a drain connected to a first node N1 and is turned on during a comparison period. The comparator 100 also includes a second transistor TR2 configured as a P-type MOS transistor having a source connected to the first node N1, a gate connected to a third node N3, and a drain connected to the second node N2. The comparator 100 also includes a third transistor TR3 configured as a P-type MOS transistor having a source connected to the first node N1, a gate connected to the second node N2, and a drain connected to the third node N3. The comparator 100 also includes a plurality of N-type MOS transistors having a source connected to a ground potential VSS and a drain connected to the second node N2. The N-type MOS transistors are a fourth transistor TR4 having a gate connected to a reference potential, a fifth transistor TR5 having a gate connected to the third node N3, and an eighth transistor TR8 having a gate connected to a first signal. The first signal is turned on while the first transistor TR1 is off. The comparator 100 also includes a plurality of N-type MOS transistors having a source connected to the ground potential VSS and a drain connected to the third node N3. The plurality of N-type MOS transistors are a sixth transistor TR6 having a gate connected to the second node N2, a seventh transistor TR7 having a gate connected to the comparison potential, and a ninth transistor TR9 having a gate connected to the first signal.

[0062] With this configuration, the comparator 100 of the A / D converter 10 can extract the charges from the first node N1, the second node N2, and the third node N3 using the eighth transistor TR8 and the ninth transistor TR9, thereby enabling the A / D converter 10 to include a comparator that can prevent malfunctions in comparison operations and output comparison results at high speed with a simple configuration.

[0063] The first signal of the A / D converter 10 according to the second embodiment may be a signal to which a reference potential is supplied.

[0064] With this configuration, in the comparator 100 of the A / D converter 10, the operational amplifier circuit used in the conventional comparator is eliminated, thereby making it possible to realize a high-speed, small-scale circuit.

[0065] The A / D converter 10 according to the third aspect may further include a discharge signal generation circuit 110 that generates a discharge signal that is turned on while the first transistor TR1 is off. Also, the first signal may be the discharge signal.

[0066] With this configuration, the comparator 100 of the A / D converter 10 can discharge the charges at the first node N1, the second node N2, and the third node N3 by the eighth transistor TR8 and the ninth transistor TR9, which input a discharge signal to their gates. Furthermore, by using the discharge signal, the charges at the first node N1, the second node N2, and the third node N3 can be discharged more reliably.

[0067] The discharge signal of the A / D converter 10 according to the fourth embodiment may be turned on at the end of the comparison period and turned off before the comparison period starts.

[0068] With this configuration, the comparator 100 of the A / D converter 10 has already completed drawing out the charges from the first node N1, the second node N2, and the third node N3 by the time the first transistor TR1 turns on and the comparison operation starts, making it possible to prevent malfunction.

[0069] The discharge signal generation circuit 110 of the A / D converter 10 according to the fifth aspect may generate a discharge signal as the output of an AND circuit to which a clock signal and a signal obtained by inverting and delaying the clock signal are input.

[0070] With this configuration, the comparator 100 of the A / D converter 10 realizes the discharge signal generation circuit 110 with a simple configuration that only receives the clock signal ( / CLK) as input, making it possible to realize a high-speed, small-scale circuit.

[0071] A comparator 100 according to a sixth aspect is a comparator circuit provided in a successive approximation A / D converter including a capacitive DAC 300, a reference potential generator 400, a comparator 100, and a conversion data generator 200. The comparator 100 includes a first transistor TR1, which is a P-type MOS transistor having a source connected to a power supply potential VCC, a gate connected to a clock signal, and a drain connected to a first node N1, and which is turned on during a comparison period. The comparator 100 also includes a second transistor TR2, which is a P-type MOS transistor having a source connected to the first node N1, a gate connected to a third node N3, and a drain connected to a second node N2. The comparator 100 also includes a third transistor TR3, which is a P-type MOS transistor having a source connected to the first node N1, a gate connected to the second node N2, and a drain connected to the third node N3. The comparator 100 also includes a plurality of N-type MOS transistors having sources connected to a ground potential VSS and drains connected to the second node N2. The plurality of N-type MOS transistors are a fourth transistor TR4 whose gate is connected to a reference potential, a fifth transistor TR5 whose gate is connected to a third node N3, and an eighth transistor TR8 whose gate is connected to a first signal. The first signal is turned on while the first transistor TR1 is off. The comparator 100 also includes a plurality of N-type MOS transistors whose sources are connected to a ground potential VSS and whose drains are connected to the third node N3. The plurality of N-type MOS transistors are a sixth transistor TR6 whose gate is connected to the second node N2, a seventh transistor TR7 whose gate is connected to a comparison potential, and a ninth transistor TR9 whose gate is connected to the first signal.

[0072] With this configuration, the comparator 100 can extract the charges from the first node N1, the second node N2, and the third node N3 using the eighth transistor TR8 and the ninth transistor TR9, thereby preventing malfunctions in the comparison operation and enabling the comparator 100 to output the comparison result at high speed with a simple configuration. [Explanation of symbols]

[0073] 10 A / D converter 100 Comparator 101 Comparator (comparison example) 110 Discharge signal generation circuit 200 Conversion Data Generator 300 capacity DAC 400 Reference potential generator TR1 First transistor TR2 Second transistor TR3 Third transistor TR4 Fourth transistor TR5 Fifth transistor TR6 6th transistor TR7 Seventh transistor TR8 8th transistor TR9 9th transistor N1 First node N2 Second node N3 Third node

Claims

1. a capacitive DAC that samples an analog input potential and generates a comparison potential based on control from a conversion data generator; a reference potential generator that generates a reference potential that is half the potential between a power supply potential and a ground potential; a comparator that compares the magnitude of the comparison potential with a reference potential to generate a comparison result; a conversion data generator that generates conversion data from the comparison result, controls the capacitive DAC based on the conversion data, and calculates and outputs a digital conversion value; The comparator a first transistor, which is a P-type MOS transistor having a source connected to the power supply potential, a gate connected to a clock signal, and a drain connected to a first node, and which is turned on during a comparison period; a second transistor configured as a P-type MOS transistor having a source connected to the first node, a gate connected to a third node, and a drain connected to a second node; a third transistor configured as a P-type MOS transistor having a source connected to the first node, a gate connected to the second node, and a drain connected to the third node; a plurality of N-type MOS transistors each having a source connected to the ground potential and a drain connected to the second node, the N-type MOS transistor including a fourth transistor having a gate connected to the reference potential, a fifth transistor having a gate connected to the third node, and an eighth transistor having a gate connected to a first signal that is turned on during a period in which the first transistor is off; an N-type MOS transistor having a source connected to the ground potential and a drain connected to the third node, the N-type MOS transistor having a gate connected to the second node, a sixth transistor having a gate connected to the second node, a seventh transistor having a gate connected to the comparison potential, and a ninth transistor having a gate connected to the first signal.

2. 2. The A / D converter according to claim 1, wherein the first signal is a signal to which the reference potential is supplied.

3. a discharge signal generating circuit that generates a discharge signal that is turned on during a period in which the first transistor is off; 2. The A / D converter according to claim 1, wherein the first signal is the discharge signal.

4. 4. The A / D converter according to claim 3, wherein the discharge signal is turned on at the end of the comparison period and turned off before the comparison period starts.

5. 5. The A / D converter according to claim 3, wherein the discharge signal generating circuit generates the discharge signal as the output of an AND circuit to which the clock signal and a signal obtained by inverting and delaying the clock signal are input.

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