Display device

Abstract

To provide a display device capable of providing an excellent image.SOLUTION: A display device is provided. A display device includes a semiconductor substrate, a plurality of light emitting elements disposed on the semiconductor substrate, and a plurality of nano patterns disposed on the plurality of light emitting elements and overlapping the plurality of light emitting elements, wherein the plurality of light emitting elements include a first light emitting element disposed at a center and a second light emitting element disposed at one side of the first light emitting element, the plurality of nano patterns include a first nano pattern overlapping the first light emitting element and a second nano pattern overlapping the second light emitting element, and the first nano pattern includes a first structure and a second structure. The second nano pattern may include a third structure and a fourth structure, the first structure and the second structure may have the same width, and the third structure and the fourth structure may have different widths.SELECTED DRAWING: Figure 17

Description

[Technical Field]

[0001] The present invention relates to a display device. [Background technology]

[0002] With the development of an information society, the demands for display devices for displaying images are becoming increasingly diverse. The display devices may be display devices such as liquid crystal displays (LCDs), field emission displays (FEDs), light emitting displays (LEMs), etc. The light emitting display devices may include organic light emitting display devices including organic light emitting diode devices as light emitting elements, or inorganic light emitting display devices including inorganic light emitting diode devices as light emitting elements.

[0003] Among display devices, a head-mounted display (HMD) is an image display device worn on the user's head in the form of glasses or a helmet, and focuses an image at a close distance in front of the user's eyes. A head-mounted display device can realize virtual reality (VR) or augmented reality (AR).

[0004] A head-mounted display device uses multiple lenses to magnify an image displayed by a small display device. Therefore, a display device used in a head-mounted display device needs to provide a high-resolution image, for example, an image with a resolution of 3000 PPI (Pixels Per Inch) or more. For this reason, a high-resolution, small-sized organic light-emitting display device, called an OLEDoS (Organic Light Emitting Diode on Silicon), is used as a display device used in a head-mounted display device. An OLEDoS is a device that displays an image by arranging organic light-emitting diodes (OLEDs) on a semiconductor wafer substrate including a CMOS (Complementary Metal Oxide Semiconductor). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] U.S. Patent Application Publication No. 2023-0393305 Summary of the Invention [Problem to be solved by the invention]

[0006] An object of the present invention is to provide a display device capable of providing a good image.

[0007] The objectives of the present invention are not limited to those mentioned above, and other technical objectives not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0008] A display device according to one embodiment for solving the above problem includes a semiconductor substrate, a plurality of light-emitting elements arranged on the semiconductor substrate, and a plurality of patterns arranged on the plurality of light-emitting elements and overlapping with the plurality of light-emitting elements, the plurality of light-emitting elements including a first light-emitting element arranged in the center and a second light-emitting element arranged on one side of the first light-emitting element, the plurality of patterns including a first pattern overlapping with the first light-emitting element and a second pattern overlapping with the second light-emitting element, the first pattern including a first structure and a second structure, the second pattern including a third structure and a fourth structure, the widths of the first structure and the second structure being the same, and the widths of the third structure and the fourth structure being different.

[0009] The third structure may be disposed closer to the center than the fourth structure, and the width of the third structure may be smaller than the width of the fourth structure.

[0010] The second pattern may further include a fifth structure and a sixth structure, wherein the third structure, the fourth structure, the fifth structure, and the sixth structure are arranged adjacent to the center in that order, and the widths of the third structure, the fourth structure, the fifth structure, and the sixth structure may be smaller in that order.

[0011] The third structure may have a width of 114 nm, the fourth structure may have a width of 124 nm, the fifth structure may have a width of 134 nm, and the sixth structure may have a width of 170 nm.

[0012] The traveling direction of the light passing through the second pattern may be tilted by 25 to 35 degrees from the thickness direction of the semiconductor substrate.

[0013] The plurality of light-emitting elements includes a third light-emitting element disposed between the first light-emitting element and the second light-emitting element, the plurality of patterns includes a third pattern overlapping the third light-emitting element, the third pattern includes a seventh structure and an eighth structure, and the widths of the seventh structure and the eighth structure may be different.

[0014] The seventh structure may be disposed closer to the center than the eighth structure, and the width of the seventh structure may be smaller than the width of the eighth structure.

[0015] The width of the third structure may be smaller than the width of the seventh structure, and the width of the fourth structure may be smaller than the width of the eighth structure.

[0016] The distance between the third structure and the fourth structure may be greater than the distance between the seventh structure and the eighth structure.

[0017] The plurality of light-emitting elements may include a fourth light-emitting element arranged on the other side of the first light-emitting element, the plurality of patterns may include a fourth pattern overlapping the fourth light-emitting element, the fourth pattern may include a ninth structure and a tenth structure, the width of the ninth structure may be the same as the width of the third structure, and the width of the tenth structure may be the same as the width of the fourth structure.

[0018] The second pattern and the fourth pattern may be symmetrical with respect to the first pattern.

[0019] The plurality of light emitting elements and the plurality of patterns may be arranged in a straight line.

[0020] The first to fourth structures may include silicon or metal.

[0021] The first to fourth structures may be in the shape of nanopins, nanorods, or nanopolygons.

[0022] According to another embodiment for solving the above problem, a display device includes a semiconductor substrate, a plurality of light-emitting elements arranged on the semiconductor substrate, and a plurality of patterns overlapping the plurality of light-emitting elements, and includes a pattern layer arranged on the plurality of light-emitting elements, the plurality of light-emitting elements including a first light-emitting element arranged in the center and a second light-emitting element arranged on one side of the first light-emitting element, the pattern layer does not include the pattern in an area overlapping with the first light-emitting element, and includes a first pattern overlapping with the second light-emitting element, the first pattern includes a first structure and a second structure, and the widths of the first structure and the second structure may be different.

[0023] The first structure may be disposed closer to the center than the second structure, and the width of the first structure may be smaller than the width of the second structure.

[0024] The first pattern may further include a third structure and a fourth structure, and the first structure, the second structure, the third structure, and the fourth structure may be arranged adjacent to the center in that order, and the widths of the first structure, the second structure, the third structure, and the fourth structure may be smaller in that order.

[0025] The plurality of light-emitting elements includes a third light-emitting element disposed between the first light-emitting element and the second light-emitting element, the plurality of patterns includes a second pattern overlapping the third light-emitting element, the second pattern includes a fifth structure and a sixth structure, and the widths of the fifth structure and the sixth structure may be different.

[0026] The plurality of light-emitting elements may include a fourth light-emitting element arranged on the other side of the first light-emitting element, the plurality of patterns may include a third pattern overlapping the fourth light-emitting element, the third pattern may include a seventh structure and an eighth structure, the width of the seventh structure may be the same as the width of the first structure, and the width of the eighth structure may be the same as the width of the second structure.

[0027] The plurality of light emitting elements and the plurality of patterns may be arranged in a straight line. [Effects of the Invention]

[0028] According to the display device of the present invention, it is possible to provide a display device capable of providing a good image.

[0029] According to an embodiment of the display device, a field of view (FOV) can be increased by adjusting a path of light according to a chief ray angle (CRA).

[0030] According to the display device according to an embodiment of the present invention, the process can be simplified.

[0031] The effects of the embodiments are not limited to the above examples, and a wider variety of effects are included in this specification. [Brief explanation of the drawings]

[0032] [Figure 1] 1 is an exploded perspective view showing a display device according to an embodiment; [Figure 2] 1 is a block diagram illustrating a display device according to an embodiment. [Figure 3] FIG. 4 is an equivalent circuit diagram of a first sub-pixel according to an embodiment. [Figure 4] FIG. 1 is a plan view illustrating an example of a display panel according to an embodiment. [Figure 5] 5 is a plan view showing an embodiment of the display area of ​​FIG. 4. [Figure 6] 5 is a plan view showing an embodiment of the display area of ​​FIG. 4. [Figure 7] 6 is a cross-sectional view showing an example of a display panel taken along the line X1-X1' in FIG. 5. [Figure 8] 6 is a cross-sectional view showing another example of a display panel taken along the line X1-X1′ in FIG. 5. FIG. [Figure 9] 7 is a cross-sectional view showing still another example of the display panel taken along the line X1-X1' in FIG. 5. FIG. [Figure 10]1 is a schematic cross-sectional view illustrating a display element layer, a color filter layer, a lens, a nanopattern layer, and an optical module of a display device according to an embodiment. [Figure 11] 1 is a schematic cross-sectional view illustrating a display panel and an optical module according to an embodiment. [Figure 12] FIG. 10 is a diagram showing an example of an image displayed by a display device according to a comparative embodiment. [Figure 13] FIG. 10 is a diagram illustrating an example of an image displayed by a display device according to an embodiment. [Figure 14] 11 is a cross-sectional view showing a nanopattern overlapping with the first pixel shown in FIG. 10. FIG. [Figure 15] 11 is a cross-sectional view showing a nanopattern overlapping with the third pixel shown in FIG. 10. FIG. [Figure 16] FIG. 2 is a perspective view showing a second nanopattern of a nanopattern layer according to an embodiment. [Figure 17] FIG. 10 is a perspective view showing a sixth nanopattern of the nanopattern layer according to one embodiment. [Figure 18] 1 is a plan view showing first to third nanopatterns of a nanopattern layer according to an embodiment. [Figure 19] FIG. 10 is a plan view showing fourth to sixth nanopatterns of a nanopattern layer according to one embodiment. [Figure 20] 10 is a cross-sectional view illustrating a nanopattern overlapping a first pixel of a display device according to another embodiment. [Figure 21] FIG. 10 is a perspective view showing a nanopattern layer according to another embodiment. [Figure 22] FIG. 10 is a perspective view showing a nanopattern layer according to another embodiment. [Figure 23] 1 is an exploded perspective view showing a head-mounted display device according to an embodiment. [Figure 24] 1 is a perspective view illustrating an augmented reality content providing device according to an embodiment. [Figure 25] 25 is an exploded perspective view of the augmented reality content providing device of FIG. 24 as viewed from the rear side. [Figure 26]25 is an exploded perspective view of the augmented reality content providing device of FIG. 24 in the front direction. DETAILED DESCRIPTION OF THE INVENTION

[0033] The advantages and features of the present invention, as well as methods for achieving them, will become clearer with reference to the following detailed embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and can be realized in various different forms. The present embodiments are provided solely for the purpose of complete disclosure of the present invention and to fully convey the scope of the invention to those skilled in the art to which the present invention pertains. The present invention is defined solely by the scope of the claims.

[0034] When elements or layers are referred to as "on" another element or layer, this includes either being directly on top of or having intervening layers or elements. Similarly, when references are made to "below," "left," and "right," this includes either being directly adjacent to or having intervening layers or materials. Like reference numbers refer to like elements throughout the specification.

[0035] Although terms such as "first" and "second" are used to describe various components, it is understood that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it is understood that a "first" component referred to below may be a "second" component within the technical concept of the present invention.

[0036] The features of the various embodiments of the present invention may be partially or wholly combined or combined with one another, and may be technically interlocked and driven in various ways, and each embodiment may be implemented independently of the others or in conjunction with one another.

[0037] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0038] 1 is an exploded perspective view showing a display device according to an embodiment, and FIG. 2 is a block diagram showing a display device according to an embodiment.

[0039] 1 and 2, a display device 10 according to an embodiment may be a device for displaying moving images or still images. The display device 10 according to an embodiment may be applied to portable electronic devices such as mobile phones, smartphones, tablet personal computers (PCs), mobile communication terminals, electronic organizers, electronic books, portable multimedia players (PMPs), navigation systems, and ultra-mobile PCs (UMPCs). For example, the display device 10 according to an embodiment may be applied to a television, a notebook computer, a monitor, a billboard, or a display unit of an Internet of Things (IoT). Alternatively, the display device 10 according to an embodiment may be applied to a smart watch, a watch phone, or a head-mounted display (HMD) for implementing virtual reality and augmented reality.

[0040] The display device 10 according to an embodiment may include a display panel 100 , a heat dissipation layer 200 , a circuit board 300 , a timing control circuit 400 , a power supply circuit 500 , and an optical module 800 .

[0041] The display panel 100 has a planar shape similar to a rectangle. For example, the display panel 100 may have a planar shape similar to a rectangle having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. In the display panel 100, the corner where the short side in the first direction DR1 intersects with the long side in the second direction DR2 may be rounded or right-angled to have a predetermined curvature. The planar shape of the display panel 100 is not limited to a rectangle and may be other polygonal, circular, or elliptical shapes. The planar shape of the display device 10 may conform to the planar shape of the display panel 100, but the embodiments of the present specification are not limited thereto.

[0042] In the illustrated drawings, the first direction DR1 and the second direction DR2 are horizontal directions that intersect with each other. For example, the first direction DR1 and the second direction DR2 may be perpendicular to each other. The third direction DR3 may be a vertical direction that intersects with the first direction DR1 and the second direction DR2, for example, perpendicular to them. Unless otherwise defined, the direction indicated by the arrows of the first to third directions DR1, DR2, and DR3 will be referred to as one side, and the opposite direction will be referred to as the other side. Furthermore, in this specification, "upper," "upper side," "upper portion," "top," and "upper surface" refer to the direction indicated by the arrow in the third direction DR3 based on the drawings, and "lower," "lower side," "lower portion," "bottom," and "lower surface" refer to the opposite direction to the direction indicated by the arrow in the third direction DR3 based on the drawings.

[0043] The display panel 100 may include a display area DAA for displaying an image and a non-display area NDA for not displaying an image, as shown in FIG.

[0044] The display area DAA may include a plurality of pixels PX, a plurality of scan lines SL, a plurality of light emitting control lines EL, and a plurality of data lines DL.

[0045] The pixels PX are arranged in a matrix in a first direction DR1 and a second direction DR2. The scan lines SL and the light-emitting control lines EL extend in the first direction DR1 and are arranged in the second direction DR2. The data lines DL extend in the second direction DR2 and are arranged in the first direction DR1.

[0046] The plurality of scan lines SL may include a plurality of write scan lines GWL, a plurality of control scan lines GCL, and a plurality of bias scan lines GBL. The plurality of light-emitting control lines EL may include a plurality of first light-emitting control lines EL1 and a plurality of second light-emitting control lines EL2.

[0047] The pixels PX may include sub-pixels SP1, SP2, and SP3. As shown in FIG. 3, the sub-pixels SP1, SP2, and SP3 may include pixel transistors formed by a semiconductor process and disposed on a semiconductor substrate SSUB (see FIG. 7). For example, the pixel transistors of the data driver 700 may be configured using a complementary metal oxide semiconductor (CMOS).

[0048] Each of the sub-pixels SP1, SP2, and SP3 may be connected to one of the write scan lines GWL, one of the control scan lines GCL, one of the bias scan lines GBL, one of the first light-emitting control lines EL1, one of the second light-emitting control lines EL2, and one of the data lines DL. Each of the sub-pixels SP1, SP2, and SP3 may receive a data voltage on the data line DL in response to a write scan signal on the write scan line GWL, and cause its light-emitting element to emit light in response to the data voltage.

[0049] The non-display area NDA may include a scan driver 610, a light emitting driver 620, and a data driver 700.

[0050] The scan driver 610 may include a plurality of scan transistors, and the light-emitting driver 620 may include a plurality of light-emitting transistors. The plurality of scan transistors and the plurality of light-emitting transistors are formed by a semiconductor process and disposed on a semiconductor substrate SSUB (see FIG. 7). For example, the plurality of scan transistors and the plurality of light-emitting transistors may be configured with CMOS. FIG. 2 illustrates an example in which the scan driver 610 is disposed on the left side of the display area DAA and the light-emitting driver 620 is disposed on the right side of the display area DAA, but this is not limiting. For example, the scan driver 610 and the light-emitting driver 620 may be disposed on both the left and right sides of the display area DAA.

[0051] The scan driver 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 may generate a write scan signal in response to the scan timing control signal SCS of the timing control circuit 400 and output it sequentially to the write scan line GWL. The control scan signal output unit 612 may generate a control scan signal in response to the scan timing control signal SCS and output it sequentially to the control scan line GCL. The bias scan signal output unit 613 may generate a bias scan signal in response to the scan timing control signal SCS and output it sequentially to the bias scan line GBL.

[0052] The light emitting driver 620 may include a first light emitting control driver 621 and a second light emitting control driver 622. The first light emitting control driver 621 and the second light emitting control driver 622 may each receive a light emitting timing control signal ECS from the timing control circuit 400. The first light emitting control driver 621 may generate first light emitting control signals in response to the light emitting timing control signal ECS and sequentially output the first light emitting control signals to the first light emitting control line EL1. The second light emitting control driver 622 may generate second light emitting control signals in response to the light emitting timing control signal ECS and sequentially output the second light emitting control signals to the second light emitting control line EL2.

[0053] The data driver 700 includes a plurality of data transistors, which are formed by a semiconductor process and disposed on a semiconductor substrate SSUB (see FIG. 7). For example, the data transistors may be configured with CMOS.

[0054] The data driver 700 may receive digital video data DATA and a data timing control signal DCS from the timing control circuit 400. The data driver 700 converts the digital video data DATA into an analog data voltage in response to the data timing control signal DCS and outputs the analog data voltage to the data line DL. In this case, the sub-pixels SP1, SP2, and SP3 may be selected by a write scan signal from the scan driver 610, and data voltages may be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0055] The heat dissipation layer 200 overlaps the display panel 100 in a third direction DR3, which is a thickness direction of the display panel 100. The heat dissipation layer 200 is disposed on one surface, for example, the rear surface, of the display panel 100. The heat dissipation layer 200 may serve to dissipate heat generated in the display panel 100. The heat dissipation layer 200 may include a metal layer having high thermal conductivity, such as graphite, silver (Ag), copper (Cu), or aluminum (Al).

[0056] The circuit board 300 may be electrically connected to a plurality of first pads PD1 (see FIG. 4) of a first pad unit PDA1 (see FIG. 4) of the display panel 100 using a conductive adhesive member such as an anisotropic conductive film. The circuit board 300 may be a flexible printed circuit board or a flexible film made of a soft material. Although FIG. 1 illustrates the circuit board 300 unfolded, the circuit board 300 may be bendable. In this case, one end of the circuit board 300 is disposed on the rear surface of the display panel 100 and / or the rear surface of the heat dissipation layer 200. The one end of the circuit board 300 may be the end opposite to the other end of the circuit board 300 connected to the plurality of first pads PD1 (see FIG. 4) of the first pad unit PDA1 (see FIG. 4) of the display panel 100 using a conductive adhesive member.

[0057] The timing control circuit 400 receives digital video data and timing signals from the outside. The timing control circuit 400 generates a scan timing control signal SCS, a light emission timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100 in response to the timing signals. The timing control circuit 400 outputs the scan timing control signal SCS to the scan driver 610 and outputs the light emission timing control signal ECS to the light emission driver 620. The timing control circuit 400 outputs the digital video data and the data timing control signal DCS to the data driver 700.

[0058] The power supply circuit 500 generates a plurality of panel driving voltages in response to an external power supply voltage. For example, the power supply circuit 500 generates a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT and supplies them to the display panel 100. The first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT will be described later with reference to FIG. 3.

[0059] The timing control circuit 400 and the power supply circuit 500 are each formed as an integrated circuit (IC) and attached to one side of the circuit board 300. In this case, the scan timing control signal SCS, the light emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the timing control circuit 400 are supplied to the display panel 100 via the circuit board 300. In addition, the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT of the power supply circuit 500 can be supplied to the display panel 100 via the circuit board 300.

[0060] Alternatively, the timing control circuit 400 and the power supply circuit 500 may be disposed in the non-display area NDA of the display panel 100, similar to the scan driver 610, the light emitting driver 620, and the data driver 700. In this case, the timing control circuit 400 may include a plurality of timing transistors, and each of the power supply circuits 500 may include a plurality of power transistors. The plurality of timing transistors and the plurality of power transistors may be formed by a semiconductor process and disposed on a semiconductor substrate SSUB (see FIG. 7). For example, the plurality of timing transistors and the plurality of power transistors may be configured with CMOS. The timing control circuit 400 and the power supply circuit 500 may be disposed between the data driver 700 and the first pad unit PDA1 (see FIG. 4).

[0061] The optical module 800 is disposed on the display panel 100. The optical module 800 can adjust the path and polarization state of light emitted from the display panel 100. The optical module 800 can realize folded optics that folds the light path. The optical module 800 will be described later with reference to FIG. 11.

[0062] FIG. 3 is an equivalent circuit diagram of a first sub-pixel according to an embodiment.

[0063] Referring to FIG. 3 in addition to FIGS. 1 and 2, the first subpixel SP1 may be connected to the write scan line GWL, the control scan line GCL, the bias scan line GBL, the first light-emitting control line EL1, the second light-emitting control line EL2, and the data line DL. The first subpixel SP1 may also be connected to a first driving voltage line VSL to which a first driving voltage VSS corresponding to a low potential voltage is applied, a second driving voltage line VDL to which a second driving voltage VDD corresponding to a high potential voltage is applied, and a third driving voltage line VIL to which a third driving voltage VINT corresponding to an initialization voltage is applied. That is, the first driving voltage line VSL may be a low potential voltage line, the second driving voltage line VDL may be a high potential voltage line, and the third driving voltage line VIL may be an initialization voltage line. In this case, the first driving voltage VSS may be lower than the third driving voltage VINT. The second driving voltage VDD may be higher than the third driving voltage VINT.

[0064] The first sub-pixel SP1 may include a plurality of transistors T1 to T6, a light emitting element (LE), a first capacitor CP1, and a second capacitor CP2.

[0065] The light emitting element LE receives a driving current (source-drain current: I ds ) and emits light in response to the driving current. The light-emitting element LE emits light in proportion to the driving current. The light-emitting element LE is disposed between the fourth transistor T4 and the first driving voltage line VSL. A first electrode of the light-emitting element LE may be connected to the drain electrode of the fourth transistor T4, and a second electrode of the light-emitting element LE may be connected to the first driving voltage line VSL. The first electrode of the light-emitting element LE may be an anode electrode, and the second electrode of the light-emitting element LE may be a cathode electrode. The light-emitting element LE may be an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first and second electrodes, but the embodiments herein are not limited thereto. For example, the light-emitting element LE may be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first and second electrodes, for example, the light-emitting element LE may be a micro light-emitting diode.

[0066] The first transistor T1 may be a drive transistor that controls a drive current flowing between a source electrode and a drain electrode in response to a voltage applied to a gate electrode of the first transistor T1. The first transistor T1 may include a gate electrode connected to a first node N1, a source electrode connected to a drain electrode of the sixth transistor T6, and a drain electrode connected to a second node N2.

[0067] The second transistor T2 is disposed between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 may be turned on by a write scan signal on the write scan line GWL to connect one electrode of the first capacitor CP1 to the data line DL, thereby allowing the data voltage of the data line DL to be applied to one electrode of the first capacitor CP1. The second transistor T2 may include a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to one electrode of the first capacitor CP1.

[0068] The third transistor T3 is disposed between the first node N1 and the second node N2. The third transistor T3 may be turned on by a write control signal on the control scan line GCL to connect the first node N1 to the second node N2. This allows the gate electrode and source electrode of the first transistor T1 to be connected, allowing the first transistor T1 to operate like a diode. The third transistor T3 may include a gate electrode connected to the control scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0069] The fourth transistor T4 may be disposed between the second node N2 and the third node N3. The fourth transistor T4 may be turned on by a first light-emitting control signal from the first light-emitting control line EL1 to connect the second node N2 to the third node N3, thereby allowing the driving current of the first transistor T1 to be supplied to the light-emitting element LE. The fourth transistor T4 may include a gate electrode connected to the first light-emitting control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0070] The fifth transistor T5 is disposed between the third node N3 and the third driving voltage line VIL. The fifth transistor T5 may be turned on by a bias scan signal from the bias scan line GBL to connect the third node N3 to the third driving voltage line VIL, thereby applying the third driving voltage VINT from the third driving voltage line VIL to the first electrode of the light emitting element LE. The fifth transistor T5 may include a gate electrode connected to the bias scan line GBL, a source electrode connected to the third node N3, and a drain electrode connected to the third driving voltage line VIL.

[0071] The sixth transistor T6 is disposed between the source electrode of the first transistor T1 and the second driving voltage line VDL. The sixth transistor T6 may be turned on by a second light-emitting control signal from the second light-emitting control line EL2 to connect the source electrode of the first transistor T1 to the second driving voltage line VDL. This allows the second driving voltage VDD from the second driving voltage line VDL to be applied to the source electrode of the first transistor T1. The sixth transistor T6 may include a gate electrode connected to the second light-emitting control line EL2, a source electrode connected to the second driving voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0072] The first capacitor CP1 is disposed between the first node N1 and the drain electrode of the second transistor T2, and may include one electrode connected to the drain electrode of the second transistor T2 and another electrode connected to the first node N1.

[0073] The second capacitor CP2 is disposed between the gate electrode of the first transistor T1 and the second drive voltage line VDL, and may include one electrode connected to the gate electrode of the first transistor T1 and another electrode connected to the second drive voltage line VDL.

[0074] The first node N1 may be a junction of the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor CP1, and one electrode of the second capacitor CP2. The second node N2 may be a junction of the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 may be a junction of the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE.

[0075] Each of the first to sixth transistors T1 to T6 may be a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). For example, each of the first to sixth transistors T1 to T6 may be a P-type MOSFET, but the embodiment of the present specification is not limited thereto. Each of the first to sixth transistors T1 to T6 may be an N-type MOSFET. Alternatively, some of the first to sixth transistors T1 to T6 may be P-type MOSFETs, and the remaining transistors may be N-type MOSFETs.

[0076] 3 illustrates the first sub-pixel SP1 including six transistors T1 to T6 and two capacitors C1 and C2, but the equivalent circuit diagram of the first sub-pixel SP1 is not limited to that shown in FIG 3. For example, the numbers of transistors and capacitors in the first sub-pixel SP1 may be variously modified.

[0077] Furthermore, the equivalent circuit diagram of the second subpixel SP2 and the equivalent circuit diagram of the third subpixel SP3 may be substantially the same as the equivalent circuit diagram of the first subpixel SP1 described with reference to Fig. 3. Therefore, in this specification, descriptions of the equivalent circuit diagram of the second subpixel SP2 and the equivalent circuit diagram of the third subpixel SP3 will be omitted.

[0078] FIG. 4 is a plan view showing an example of a display panel according to an embodiment.

[0079] 4, the display area DAA of the display panel 100 according to an embodiment may include a plurality of pixels PX arranged in a matrix. The non-display area NDA of the display panel 100 according to an embodiment may include a scan driver 610, a light emitting driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a first pad unit PDA1, and a second pad unit PDA2.

[0080] The scan driver 610 is disposed on a first side of the display area DAA, and the emission driver 620 is disposed on a second side of the display area DAA. For example, the scan driver 610 is disposed on the other side of the display area DAA in the first direction DR1, and the emission driver 620 is disposed on one side of the display area DAA in the first direction DR1. That is, the scan driver 610 is disposed on the left side of the display area DAA, and the emission driver 620 is disposed on the right side of the display area DAA. However, the embodiments herein are not limited thereto, and the scan driver 610 and the emission driver 620 may be disposed on both the first and second sides of the display area DAA.

[0081] The first pad unit PDA1 may include a plurality of first pads PD1 connected to pads or bumps of the circuit board 300 via conductive adhesive members. The first pad unit PDA1 is disposed on a third side of the display area DAA. For example, the first pad unit PDA1 is disposed on the other side of the display area DAA in the second direction DR2. That is, the first pad unit PDA1 may be disposed below the display area DAA.

[0082] The first pad unit PDA1 is disposed outside the data driver 700 in the second direction DR2. That is, the first pad unit PDA1 may be disposed closer to the edge of the display panel 100 than the data driver 700.

[0083] The second pad unit PDA2 may include a plurality of second pads PD2 corresponding to test pads for testing whether the display panel 100 operates normally. The second pads PD2 may be connected to a jig or probe pins during the test process, or to a test circuit board. The test circuit board may be a printed circuit board made of a rigid material or a flexible printed circuit board made of a flexible material.

[0084] The first distribution circuit 710 distributes a data voltage applied via the first pad unit PDA1 to a plurality of data lines DL. For example, the first distribution circuit 710 distributes a data voltage applied via one first pad PD1 of the first pad unit PDA1 to P (P is a positive integer greater than or equal to 2) data lines DL, thereby reducing the number of first pads PD1. The first distribution circuit 710 is disposed on a third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 is disposed on the other side of the display area DAA in the second direction DR2. That is, the first distribution circuit 710 may be disposed below the display area DAA.

[0085] The second distribution circuit 720 distributes signals applied via the second pad unit PDA2 to the scan driver 610, the light emitting driver 620, and the data lines DL. The second pad unit PDA2 and the second distribution circuit 720 may be configured to test the operation of each pixel PX in the display area DAA. The second distribution circuit 720 is disposed on a fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 is disposed on one side of the display area DAA in the second direction DR2. That is, the second distribution circuit 720 may be disposed on the upper side of the display area DAA.

[0086] 5 and 6 are plan views showing embodiments of the display area of ​​FIG.

[0087] Referring to Figures 5 and 6, each of the multiple pixels PX may include a first light-emitting region EA1 which is the light-emitting region of the first sub-pixel SP1, a second light-emitting region EA2 which is the light-emitting region of the second sub-pixel SP2, and a third light-emitting region EA3 which is the light-emitting region of the third sub-pixel SP3.

[0088] In some embodiments, the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may have a substantially rectangular shape as shown in Fig. 5. Also, as shown in Fig. 6, the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may have a hexagonal planar shape consisting of six straight lines, but the embodiments of the present specification are not limited thereto. The first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may have a polygonal, circular, elliptical, or irregular planar shape in addition to a hexagonal shape.

[0089] 5, the maximum length in the first direction DR1 of the third light-emitting region EA3 may be smaller than the maximum length in the first direction DR1 of the first light-emitting region EA1 and the maximum length in the first direction DR1 of the second light-emitting region EA2. The maximum length in the first direction DR1 of the first light-emitting region EA1 and the maximum length in the first direction DR1 of the second light-emitting region EA2 may be substantially the same.

[0090] 5, the maximum length in the second direction DR2 of the third light-emitting region EA3 may be longer than the maximum length in the second direction DR2 of the first light-emitting region EA1 and the maximum length in the second direction DR2 of the second light-emitting region EA2. The maximum length in the second direction DR2 of the first light-emitting region EA1 may be longer than the maximum length in the second direction DR2 of the second light-emitting region EA2.

[0091] In one embodiment, as shown in FIG. 5, in each of the multiple pixels PX, the first light-emitting region EA1 and the second light-emitting region EA2 are adjacent to each other in the second direction DR2. The first light-emitting region EA1 and the third light-emitting region EA3 are adjacent to each other in the first direction DR1. The second light-emitting region EA2 and the third light-emitting region EA3 are adjacent to each other in the first direction DR1. The areas of the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 may be different. Also, as shown in FIG. 5, the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 form a single unit with a rectangular or square shape. A plurality of units are arranged consecutively in a matrix.

[0092] In another embodiment, as shown in FIG. 6 , in each of the pixels PX, the first light-emitting region EA1 and the second light-emitting region EA2 are adjacent to each other in the first direction DR1, the second light-emitting region EA2 and the third light-emitting region EA3 are adjacent to each other in the first diagonal direction DD1, and the first light-emitting region EA1 and the third light-emitting region EA3 are adjacent to each other in the second diagonal direction DD2. Also, as shown in FIG. 6 , the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 form a triangular unit. Each triangular unit includes the first and second light-emitting regions EA1 and EA2 adjacent to each other in the first direction DR1, and the second light-emitting region EA2 is adjacent to the third light-emitting region EA3 in the first diagonal direction DD1, and the first light-emitting region EA1 is adjacent to the third light-emitting region EA3 in the second diagonal direction DD2. The light-emitting regions of another triangular unit adjacent to the first triangular unit in the first direction DR1 are arranged invertedly in the second direction DR2. That is, another triangular unit includes first and second light-emitting regions EA1 and EA2 adjacent to each other in the first direction DR1, the second light-emitting region EA2 is adjacent to the third light-emitting region EA3 in the opposite direction of the second diagonal direction DD2, and the first light-emitting region EA1 is adjacent to the third light-emitting region EA3 in the opposite direction of the first diagonal direction DD1. A plurality of units are continuously arranged in a matrix.

[0093] In the illustrated figure, the first diagonal direction DD1 is horizontal to the first direction DR1 and the second direction DR2 and intersects with each other. For example, the first diagonal direction DD1 may be inclined at 45 degrees with respect to each of the first direction DR1 and the second direction DR2, but is not limited thereto. The second diagonal direction DD2 is horizontal to the first direction DR1 and the second direction DR2 and intersects with each other. For example, the second diagonal direction DD2 may be in the opposite direction to the first direction DR1 and inclined at 45 degrees with respect to each of the second direction DR2, but is not limited thereto. The second diagonal direction DD2 may be perpendicular to the first diagonal direction DD1.

[0094] The first light-emitting region EA1 emits light of a first color, the second light-emitting region EA2 emits light of a second color, and the third light-emitting region EA3 emits light of a third color. Here, the first light may be light in the red wavelength band, the second light may be light in the green wavelength band, and the third light may be light in the blue wavelength band. For example, the blue wavelength band refers to light whose main peak wavelength is within a wavelength band of approximately 370 nm to 460 nm, the green wavelength band refers to light whose main peak wavelength is within a wavelength band of approximately 480 nm to 560 nm, and the red wavelength band refers to light whose main peak wavelength is within a wavelength band of approximately 600 nm to 750 nm.

[0095] 5 and 6 illustrate that each of the pixels PX includes three light-emitting areas EA1, EA2, and EA3, but the embodiments of this specification are not limited to this. That is, each of the pixels PX may include four or more light-emitting areas.

[0096] Furthermore, the shapes and arrangement of the light-emitting regions of the plurality of pixels PX are not limited to those shown in Figures 5 and 6. For example, the light-emitting regions of the plurality of pixels PX may be arranged in a stripe structure in which the light-emitting regions are arranged in a first direction DR1, a PenTile (registered trademark) structure in which the light-emitting regions have a diamond arrangement, or a hexagonal structure in which light-emitting regions having hexagonal planar shapes are arranged as shown in Figure 6.

[0097] FIG. 7 is a cross-sectional view showing an example of a display panel taken along the line X1-X1′ in FIG.

[0098] Referring to FIG. 7, the display panel 100 may include a semiconductor backplane SBP, a light-emitting element backplane EBP, a display element layer EML, an encapsulation layer TFE, an optical layer OPL, a cover layer CVL, and a polarizer POL.

[0099] The semiconductor backplane SBP may include a semiconductor substrate SSUB including a plurality of pixel transistors PTR, a plurality of semiconductor insulating films covering the plurality of pixel transistors PTR, and a plurality of contact terminals CTE electrically connected to the plurality of pixel transistors PTR, respectively. The plurality of pixel transistors PTR may be the first to sixth transistors T1 to T6 (see FIG. 4) described with reference to FIG.

[0100] The semiconductor substrate SSUB may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB may be a substrate doped with a first type impurity. A plurality of well regions WA are disposed on an upper surface of the semiconductor substrate SSUB. The plurality of well regions WA may be regions doped with a second type impurity. The second type impurity may be different from the aforementioned first type impurity. For example, if the first type impurity is a p-type impurity, the second type impurity may be an n-type impurity. Alternatively, if the first type impurity is an n-type impurity, the second type impurity may be a p-type impurity.

[0101] Each of the multiple well regions WA may include a source region SA corresponding to the source electrode of the pixel transistor PTR, a drain region DA corresponding to the drain electrode, and a channel region CH disposed between the source region SA and the drain region DA.

[0102] A lower insulating film BINS is disposed between the gate electrode GE and the well region WA. Side insulating films SINS are disposed on the sides of the gate electrode GE. The side insulating films SINS are disposed on the lower insulating film BINS.

[0103] The source region SA and the drain region DA may each be a region doped with a first-type impurity. A gate electrode GE of the pixel transistor PTR overlaps the well region WA in a third direction DR3. A channel region CH overlaps the gate electrode GE in the third direction DR3. The source region SA is disposed on one side of the gate electrode GE, and the drain region DA is disposed on the other side of the gate electrode GE.

[0104] Each of the plurality of well regions WA may further include a first lightly doped impurity region LDD1 disposed between the channel region CH and the source region SA, and a second lightly doped impurity region LDD2 disposed between the channel region CH and the drain region DA. The first lightly doped impurity region LDD1 may be a region having a lower impurity concentration than the source region SA due to the lower insulating film BINS. The second lightly doped impurity region LDD2 may be a region having a lower impurity concentration than the drain region DA due to the lower insulating film BINS. The first lightly doped impurity region LDD1 and the second lightly doped impurity region LDD2 may increase the distance between the source region SA and the drain region DA. Therefore, the length of each channel region CH of the pixel transistor PTR is increased, thereby preventing punch-through and hot carrier phenomena due to a short channel.

[0105] The first semiconductor insulating film SINS1 is disposed on the semiconductor substrate SSUB. The first semiconductor insulating film SINS1 is formed of a silicon carbon nitride (SiCN) or silicon oxide (SiOx)-based inorganic film, but the embodiment of this specification is not limited thereto.

[0106] The second semiconductor insulating film SINS2 is disposed on the first semiconductor insulating film SINS1. The second semiconductor insulating film SINS2 is formed of a silicon oxide (SiOx)-based inorganic film, but the embodiments of this specification are not limited to this.

[0107] The plurality of contact terminals CTE are disposed on the second semiconductor insulating film SINS2. Each of the plurality of contact terminals CTE can be connected to one of the gate electrode GE, source region SA, and drain region DA of the pixel transistor PTR via a hole penetrating the first semiconductor insulating film SINS1 and the second semiconductor insulating film SINS2. The plurality of contact terminals CTE are made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of these.

[0108] A third semiconductor insulating film SINS3 is disposed on each side surface of the plurality of contact terminals CTE. An upper surface of each of the plurality of contact terminals CTE may be exposed and not covered by the third semiconductor insulating film SINS3. The third semiconductor insulating film SINS3 is formed of a silicon oxide (SiOx)-based inorganic film, but the embodiment of this specification is not limited thereto.

[0109] The semiconductor substrate SSUB can be replaced with a glass substrate or a polymer resin substrate such as polyimide. In this case, thin film transistors can be arranged on the glass substrate or polymer resin substrate. The glass substrate is a rigid substrate that does not bend, while the polymer resin substrate can be a flexible substrate that can be bent or curved.

[0110] The light-emitting element backplane EBP may include a plurality of conductive layers ML1 to ML8, a plurality of vias VA1 to VA9, and a plurality of insulating films INS1 to INS9.

[0111] The first through eighth conductive layers ML1 through ML8 connect the contact terminals CTE exposed on the semiconductor backplane SBP to realize the pixel circuit of the first sub-pixel SP1 shown in Figure 4. For example, only the first through sixth transistors T1 through T6 are arranged on the semiconductor backplane SBP, and the connection wiring of the first through sixth transistors T1 through T6, the first capacitor C1, and the second capacitor C2 are arranged on the first through eighth conductive layers ML1 through ML8. In addition, the connection portion between the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE is also arranged on the first through eighth conductive layers ML1 through ML8.

[0112] The first insulating film INS1 is disposed on the semiconductor backplane SBP. Each of the first vias VA1 can be connected to a contact terminal CTE exposed on the semiconductor backplane SBP through the first insulating film INS1. Each of the first conductive layers ML1 can be disposed on the first insulating film INS1 and connected to the first vias VA1.

[0113] The second insulating film INS2 is disposed on the first insulating film INS1 and the first conductive layer ML1. Each of the second vias VA2 may be connected to the first conductive layer ML1 exposed through the second insulating film INS2. Each of the second conductive layers ML2 may be disposed on the second insulating film INS2 and connected to the second vias VA2.

[0114] The third insulating film INS3 is disposed on the second insulating film INS2 and the second conductive layer ML2. Each of the third vias VA3 may be connected to the second conductive layer ML2 exposed through the third insulating film INS3. Each of the third conductive layers ML3 may be disposed on the third insulating film INS3 and connected to the third vias VA3.

[0115] The fourth insulating film INS4 is disposed on the third insulating film INS3 and the third conductive layer ML3. Each of the fourth vias VA4 may be connected to the third conductive layer ML3 exposed through the fourth insulating film INS4. Each of the fourth conductive layers ML4 may be disposed on the fourth insulating film INS4 and connected to the fourth vias VA4.

[0116] The fifth insulating film INS5 is disposed on the fourth insulating film INS4 and the fourth conductive layer ML4. Each of the fifth vias VA5 may be connected to the fourth conductive layer ML4 exposed through the fifth insulating film INS5. Each of the fifth conductive layers ML5 may be disposed on the fifth insulating film INS5 and connected to the fifth vias VA5.

[0117] The sixth insulating film INS6 is disposed on the fifth insulating film INS5 and the fifth conductive layer ML5. Each of the sixth vias VA6 may be connected to the fifth conductive layer ML5 exposed through the sixth insulating film INS6. Each of the sixth conductive layers ML6 may be disposed on the sixth insulating film INS6 and connected to the sixth vias VA6.

[0118] The seventh insulating film INS7 is disposed on the sixth insulating film INS6 and the sixth conductive layer ML6. Each of the seventh vias VA7 may be connected to the sixth conductive layer ML6 exposed through the seventh insulating film INS7. Each of the seventh conductive layers ML7 may be disposed on the seventh insulating film INS7 and connected to the seventh vias VA7.

[0119] The eighth insulating film INS8 is disposed on the seventh insulating film INS7 and the seventh conductive layer ML7. Each of the eighth vias VA8 may be connected to the seventh conductive layer ML7 exposed through the eighth insulating film INS8. Each of the eighth conductive layers ML8 may be disposed on the eighth insulating film INS8 and connected to the eighth vias VA8.

[0120] The first through eighth conductive layers ML1-ML8 and the first through eighth vias VA1-VA8 are made of substantially the same material. The first through eighth conductive layers ML1-ML8 and the first through eighth vias VA1-VA8 are made of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of these. The first through eighth insulating films INS1-ILD8 are formed of silicon oxide (SiOx)-based inorganic films, but the embodiment of the present specification is not limited thereto.

[0121] The thicknesses of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be greater than the thicknesses of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6, respectively. The thicknesses of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be greater than the thickness of the first conductive layer ML1. The thicknesses of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be substantially the same. For example, the thickness of the first conductive layer ML1 is approximately 1360 Å, the thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6 are each approximately 1440 Å, and the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6 are each approximately 1150 Å, however, the thicknesses of the first to sixth conductive layers ML1, ML2, ML3, ML4, ML5, ML6 and the first to sixth vias VA1, VA2, VA3, VA4, VA5, VA6 are not limited to these.

[0122] The thickness of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be greater than the thickness of the first conductive layer ML1, the thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6, respectively. The thickness of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be greater than the thickness of the seventh via VA7 and the thickness of the eighth via VA8, respectively. The thickness of the seventh via VA7 and the eighth via VA8 may be greater than the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6, respectively. The thickness of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be substantially the same. For example, the thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 are each approximately 9000 Å, and the thickness of the seventh via VA7 and the eighth via VA8 are each approximately 6000 Å, but the thicknesses of the seventh conductive layer ML7, the eighth conductive layer ML8, the seventh via VA7, and the eighth via VA8 are not limited to these.

[0123] The ninth insulating film INS9 is disposed on the eighth insulating film INS8 and the eighth conductive layer ML8. The ninth insulating film INS9 is formed of a silicon oxide (SiOx)-based inorganic film, but the embodiments of this specification are not limited to this.

[0124] Each of the ninth vias VA9 may be connected to the eighth conductive layer ML8 exposed through the ninth insulating film INS9. The ninth vias VA9 may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of these elements. The thickness of the ninth vias VA9 is approximately 16,500 Å. However, the thickness of the ninth vias VA9 is not limited to this.

[0125] The display element layer EML is disposed on the light-emitting element backplane EBP and may include a reflective electrode layer RL, tenth and eleventh insulating films INS10 and INS11, a tenth via VA10, a light-emitting element LE each including a first electrode AND, a light-emitting stack IL, and a second electrode CAT, a pixel defining layer PDL, and a plurality of trenches TRC.

[0126] A reflective electrode layer RL is disposed on the ninth insulating film INS9. The reflective electrode layer RL may include at least one reflective electrode RL1, RL2, RL3, and RL4. For example, as shown in FIG. 7, the reflective electrode layer RL may include first to fourth reflective electrodes RL1, RL2, RL3, and RL4, but is not limited thereto.

[0127] Each of the first reflective electrodes RL1 may be disposed on a ninth insulating film INS9 and connected to a ninth via VA9. The first reflective electrodes RL1 may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of these. For example, the first reflective electrodes RL1 may include titanium nitride (TiN).

[0128] Each of the second reflective electrodes RL2 is disposed on the first reflective electrode RL1. The second reflective electrodes RL2 are made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of these. For example, the second reflective electrodes RL2 may include aluminum (Al).

[0129] Each of the third reflective electrodes RL3 is disposed on the second reflective electrode RL2. The third reflective electrodes RL3 are made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of these. For example, the third reflective electrodes RL3 may include titanium nitride (TiN).

[0130] Each of the fourth reflective electrodes RL4 is disposed on the third reflective electrode RL3. The fourth reflective electrodes RL4 are made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of these. For example, the fourth reflective electrodes RL4 may include titanium (Ti).

[0131] Since the second reflective electrode RL2 is an electrode that substantially reflects light from the light-emitting element LE, the thickness of the second reflective electrode RL2 is greater than the thicknesses of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4. For example, the thicknesses of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4 are each approximately 100 Å, and the thickness of the second reflective electrode RL2 is approximately 850 Å. However, the thicknesses of the first to fourth reflective electrodes RL1, RL2, RL3, and RL4 are not limited to this.

[0132] The tenth insulating film INS10 is disposed on the ninth insulating film INS9. The tenth insulating film INS10 is disposed between the reflective electrode layers RL adjacent to each other in the horizontal direction. The tenth insulating film INS10 is formed of a silicon oxide (SiOx)-based inorganic film, but the embodiments of the present specification are not limited thereto. In some embodiments, although not shown in the drawings, the tenth insulating film INS10 may be disposed not only between the reflective electrode layers RL but also on the reflective electrode layer RL.

[0133] The eleventh insulating film INS11 is disposed on the tenth insulating film INS10 and the reflective electrode layer RL. The eleventh insulating film INS11 is formed of a silicon oxide (SiOx)-based inorganic film, but the embodiment of the present specification is not limited to this. The tenth insulating film INS10 and the eleventh insulating film INS11 may be optical auxiliary layers through which light emitted from the light-emitting element LE and reflected by the reflective electrode layer RL passes.

[0134] In some embodiments, in order to match the resonance distance of light emitted from the light-emitting element LE in at least one of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3, the total thickness of the insulating film disposed between the first electrode AND and the reflective electrode layer RL in each of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 may be different from each other.

[0135] In one embodiment, as shown in the drawing, when the tenth insulating film INS10 is not disposed between the first electrode AND and the reflective electrode layer RL but the eleventh insulating film INS11 is disposed between the first electrode AND and the reflective electrode layer RL, the thicknesses of the eleventh insulating films INS11 disposed in the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 may be different from each other. For example, the thickness of the eleventh insulating film INS11 disposed in the first subpixel SP1 may be smaller than the thickness of the eleventh insulating film INS11 disposed in the second subpixel SP2, and the thickness of the eleventh insulating film INS11 disposed in the second subpixel SP2 may be smaller than the thickness of the eleventh insulating film INS11 disposed in the third subpixel SP3.

[0136] In another embodiment, in the first subpixel SP1, neither the tenth insulating film INS10 nor the eleventh insulating film INS11 is arranged between the first electrode AND and the reflective electrode layer RL, in the second subpixel SP2, either the tenth insulating film INS10 or the eleventh insulating film INS11 is arranged between the first electrode AND and the reflective electrode layer RL, and in the third subpixel SP3, both the tenth insulating film INS10 and the eleventh insulating film INS11 are arranged between the first electrode AND and the reflective electrode layer RL.

[0137] In still another embodiment, a twelfth insulating film may be further disposed between the first electrode AND and the reflective electrode layer RL. In this case, the first subpixel SP1 may have one of the tenth insulating film INS10, the eleventh insulating film INS11, and the twelfth insulating film disposed between the first electrode AND and the reflective electrode layer RL, the second subpixel SP2 may have two of the tenth insulating film INS10, the eleventh insulating film INS11, and the twelfth insulating film disposed between the first electrode AND and the reflective electrode layer RL, and the third subpixel SP3 may have all of the tenth insulating film INS10, the eleventh insulating film INS11, and the twelfth insulating film disposed between the first electrode AND and the reflective electrode layer RL.

[0138] In summary, the distance between the first electrode AND and the reflective electrode layer RL may be different in each of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3. That is, the presence or absence or thickness of the tenth insulating film INS10 and the eleventh insulating film INS11 can be set in each of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 to adjust the distance from the reflective electrode layer RL to the second electrode CAT depending on the main wavelength of the light emitted from each of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3.

[0139] Although the drawings illustrate the total thickness of the insulating films disposed between the first electrode AND and the reflective electrode layer RL in the order of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3, the total thickness is not limited thereto. That is, the distance between the first electrode AND and the reflective electrode layer RL in the third subpixel SP3 is greater than the distance between the first electrode AND and the reflective electrode layer RL in the second subpixel SP2 and the distance between the first electrode AND and the reflective electrode layer RL in the first subpixel SP1, and the distance between the first electrode AND and the reflective electrode layer RL in the second subpixel SP2 is greater than the distance between the first electrode AND and the reflective electrode layer RL in the first subpixel SP1, the embodiment of the present specification is not limited thereto. The relationship in the total thickness of the insulating films disposed between the first electrode AND and the reflective electrode layer RL in each of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 may vary in various ways depending on the resonance distance.

[0140] Each of the tenth vias VA10 may be connected to the ninth conductive layer ML9 exposed through the tenth insulating film INS10 and / or the eleventh insulating film INS11. The tenth vias VA10 may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of these. The thickness of the tenth via VA10 in the second subpixel SP2 may be smaller than the thickness of the tenth via VA10 in the third subpixel SP3, and the thickness of the tenth via VA10 in the first subpixel SP1 may be smaller than the thickness of the tenth via VA10 in the second subpixel SP2, but is not limited thereto.

[0141] The first electrode AND of each light-emitting element LE may be disposed on the eleventh insulating film INS11 and connected to the tenth via VA10. The first electrode AND of each light-emitting element LE may be connected to the drain region DA or the source region SA of the pixel transistor PTR via the tenth via VA10, the first to fourth reflective electrodes RL1 to RL4, the first to ninth vias VA1 to VA9, the first to eighth conductive layers ML1 to ML8, and the contact terminal CTE. The first electrode AND of each light-emitting element LE may be made of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy containing any one of these. For example, the first electrode AND of each light-emitting element LE may be made of titanium nitride (TiN).

[0142] The pixel defining layer PDL is disposed on a portion of the first electrode AND of each of the light-emitting elements LE. The pixel defining layer PDL may cover the edges of the first electrode AND of each of the light-emitting elements LE. The pixel defining layer PDL serves to divide the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3.

[0143] The first light-emitting region EA1 can be defined as a region in the first sub-pixel SP1 where the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked to emit light. The second light-emitting region EA2 can be defined as a region in the second sub-pixel SP2 where the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked to emit light. The third light-emitting region EA3 can be defined as a region in the third sub-pixel SP3 where the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked to emit light.

[0144] The pixel defining layer PDL may include first, second, and third pixel defining layers PDL1, PDL2, and PDL3. The first pixel defining layer PDL1 is disposed on an edge of each first electrode AND of the light-emitting element LE, the second pixel defining layer PDL2 is disposed on the first pixel defining layer PDL1, and the third pixel defining layer PDL3 is disposed on the second pixel defining layer PDL2. The first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 are formed of silicon oxide (SiOx)-based inorganic layers, although embodiments of the present specification are not limited thereto. The thickness of the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may each be approximately 500 Å.

[0145] When the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 are formed as a single pixel defining layer, the height of the single pixel defining layer increases, and the first sealing inorganic layer TFE1 may be divided due to step coverage. Step coverage refers to the ratio of the extent to which the thin film is applied to a sloped portion to the extent to which the thin film is applied to a flat portion. The lower the step coverage, the higher the possibility that the thin film will be divided at a sloped portion.

[0146] Therefore, to prevent the first sealing inorganic film TFE1 from being divided by the step coverage, the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 may each have a cross-sectional structure with a staircase-shaped step in each of the opening regions of the pixel defining film PDL including the first to third light-emitting regions EA1 to EA3. For example, the width of the first pixel defining film PDL1 may be greater than the widths of the second pixel defining film PDL2 and the third pixel defining film PDL3, and the width of the second pixel defining film PDL2 may be greater than the width of the third pixel defining film PDL3. That is, in the opening region of the pixel defining film PDL, the first pixel defining film PDL1 protrudes horizontally more than the second pixel defining film PDL2, and the second pixel defining film PDL2 protrudes horizontally more than the third pixel defining film PDL3. The width of the first pixel defining film PDL1, the width of the second pixel defining film PDL2, and the width of the third pixel defining film PDL3 each refer to the length in the horizontal direction perpendicular to the third direction DR3. Here, the thickness of the first pixel defining film PDL1 in the third direction DR3 can be adjusted depending on the thickness of the eleventh insulating film INS11. For example, since the thickness of the eleventh insulating film INS11 corresponding to the first light-emitting region EA1 is smaller than the thickness of the eleventh insulating film INS11 corresponding to the second light-emitting region EA2, the thickness of the first pixel defining film PDL1 corresponding to the first light-emitting region EA1 is larger than the thickness of the first pixel defining film PDL1 corresponding to the second light-emitting region EA2. Also, since the thickness of the eleventh insulating film INS11 disposed in the second light-emitting region EA2 is smaller than the thickness of the eleventh insulating film INS11 disposed in the third light-emitting region EA3, the thickness of the first pixel defining film PDL1 disposed in the second light-emitting region EA2 is larger than the thickness of the first pixel defining film PDL1 disposed in the third light-emitting region EA3. As a result, in the example of FIG. 7, the height of the upper surface of the first pixel defining film PDL1 is approximately the same throughout the first to third light-emitting regions EA1 to EA3.

[0147] Each of the trenches TRC may penetrate the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3. Each of the trenches TRC may penetrate the eleventh insulating film INS11. In each of the trenches TRC, the eleventh insulating film INS11 may have a partially recessed shape. In the example of FIG. 7, each trench TRC communicates with the first to third pixel defining films PDL1 to PDL3 and the eleventh insulating film INS11 in the third direction DR3. As described below, although not limited thereto, in the example of FIG. 7, a first stack layer IL1 is located on the bottom surface of each trench TRC (the upper surface of the tenth insulating film INS10 in the trench TRC).

[0148] At least one trench TRC is disposed between adjacent sub-pixels SP1, SP2, and SP3. Although Fig. 7 illustrates an example in which two trenches TRC are disposed between adjacent sub-pixels SP1, SP2, and SP3, the embodiment of this specification is not limited thereto.

[0149] The light emitting stack IL may include multiple intermediate layers. While FIG. 7 illustrates the light emitting stack IL having a three-tandem structure including a first stack layer IL1, a second stack layer IL2, and a third stack layer IL3, the embodiments herein are not limited thereto. For example, the light emitting stack IL may have a two-tandem structure including two intermediate layers.

[0150] In the three-tandem structure, the light-emitting stack IL may have a tandem structure including multiple stack layers IL1, IL2, and IL3 that emit different light from each other. For example, the light-emitting stack IL may include a first stack layer IL1 that emits light of a first color, a second stack layer IL2 that emits light of a third color, and a third stack layer IL3 that emits light of a second color. The first stack layer IL1, the second stack layer IL2, and the third stack layer IL3 are stacked in sequence.

[0151] The first stack layer IL1 may have a structure in which a first hole transport layer, a first organic light-emitting layer that emits light of a first color, and a first electron transport layer are sequentially stacked. The second stack layer IL2 may have a structure in which a second hole transport layer, a second organic light-emitting layer that emits light of a third color, and a second electron transport layer are sequentially stacked. The third stack layer IL3 may have a structure in which a third hole transport layer, a third organic light-emitting layer that emits light of a second color, and a third electron transport layer are sequentially stacked.

[0152] A first charge generation layer is disposed between the first stack layer IL1 and the second stack layer IL2 to supply charges to the second stack layer IL2 and electrons to the first stack layer IL1. The first charge generation layer may include an N-type charge generation layer that supplies electrons to the first stack layer IL1 and a P-type charge generation layer that supplies holes to the second stack layer IL2. The N-type charge generation layer may include a metal dopant.

[0153] A second charge generation layer is disposed between the second stack layer IL2 and the third stack layer IL3 to supply charges to the third stack layer IL3 and to supply electrons to the second stack layer IL2. The second charge generation layer may include an N-type charge generation layer that supplies electrons to the second stack layer IL2 and a P-type charge generation layer that supplies holes to the third stack layer IL3.

[0154] The first stack layer IL1 is disposed on the first electrode AND and the pixel defining layer PDL, and is disposed on the bottom surface of each trench TRC. The first stack layer IL1 may be divided between adjacent subpixels SP1, SP2, and SP3 by the trench TRC. The second stack layer IL2 is disposed on the first stack layer IL1. The second stack layer IL2 may be divided between adjacent subpixels SP1, SP2, and SP3 by the trench TRC. A cavity ESS or empty space is disposed between the first stack layer IL1 and the second stack layer IL2. The third stack layer IL3 is disposed on the second stack layer IL2. The third stack layer IL3 is not divided by the trench TRC and is disposed to cover the second stack layer IL2 in each trench TRC. That is, in a three-tandem structure, each of the plurality of trenches TRC may be a structure for separating the first and second stack layers IL1 and IL2, the first charge generation layer, and the second charge generation layer of the display element layer EML between adjacent subpixels SP1, SP2, and SP3. Also, in a two-tandem structure, each of the plurality of trenches TRC may be a structure for separating the charge generation layer and the lower intermediate layer disposed between the lower intermediate layer and the upper intermediate layer.

[0155] To stably separate the first and second stack layers IL1 and IL2 of the display element layer EML between adjacent subpixels SP1, SP2, and SP3, the height of each of the trenches TRC may be greater than the height of the pixel defining layer PDL. The height of each of the trenches TRC refers to the length of each of the trenches TRC in the third direction DR3. The height of the pixel defining layer PDL refers to the length of the pixel defining layer PDL in the third direction DR3. Other structures may be present instead of the trenches TRC to separate the first to third stack layers IL1, IL2, and IL3 of the display element layer EML between adjacent subpixels SP1, SP2, and SP3. For example, instead of the trenches TRC, a reverse-tapered partition wall may be disposed on the pixel defining layer PDL. 7, each trench TRC is formed in the pixel defining film PDL and the eleventh insulating film INS11, but it may be formed only in the pixel defining film PDL without being formed in the eleventh insulating film INS11.

[0156] The number of stack layers IL1, IL2, and IL3 that emit different light rays is not limited to that shown in FIG. 7. For example, the light-emitting stack IL may include two intermediate layers. In this case, one of the two intermediate layers may be substantially identical to the first stack layer IL1, and the other may include a second hole transport layer, a second organic light-emitting layer, a third organic light-emitting layer, and a second electron transport layer. In this case, a charge generation layer may be disposed between the two intermediate layers to supply electrons to one of the intermediate layers and charge to the other intermediate layer.

[0157] 7 illustrates an example in which the first, second, and third stack layers IL1, IL2, and IL3 are all disposed in the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3, but the embodiments of the present specification are not limited thereto. For example, the first stack layer IL1 may be disposed in the first light-emitting region EA1, but not in the second light-emitting region EA2 or the third light-emitting region EA3. The second stack layer IL2 may be disposed in the second light-emitting region EA2, but not in the first light-emitting region EA1 or the third light-emitting region EA3. The third stack layer IL3 may be disposed in the third light-emitting region EA3, but not in the first light-emitting region EA1 or the second light-emitting region EA2. In this case, the color filters CF1, CF2, and CF3 of the optical layer OPL can be omitted.

[0158] The second electrode CAT is disposed on the third stack layer IL3. The second electrode CAT is disposed on the third stack layer IL3 in each of the trenches TRC. The second electrode CAT may be formed of a transparent conductive material (TCO) such as ITO or IZO, or a semi-transmissive metallic material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the second electrode CAT is formed of a semi-transmissive metallic material, the microcavities increase the light output efficiency of each of the first to third sub-pixels SP1, SP2, and SP3.

[0159] The sealing layer TFE is disposed on the display element layer EML. The sealing layer TFE may include at least one inorganic film TFE1, TFE2 to prevent oxygen or moisture from permeating into the display element layer EML. For example, the sealing layer TFE may include a first sealing inorganic film TFE1 and a second sealing inorganic film TFE2.

[0160] The first encapsulation inorganic layer TFE1 is disposed on the second electrode CAT. The first encapsulation inorganic layer TFE1 may be formed of a multi-layer structure in which one or more inorganic layers selected from silicon nitride (SiNx), silicon oxynitride (SiON), and silicon oxide (SiOx) are alternately stacked. The first encapsulation inorganic layer TFE1 may be formed by a chemical evaporation deposition (CVD) process.

[0161] The second sealing inorganic film TFE2 is disposed on the first sealing inorganic film TFE1. The second sealing inorganic film TFE2 may be formed of titanium oxide (TiOx) or aluminum oxide (AlOx), but the embodiment of the present specification is not limited thereto. The second sealing inorganic film TFE2 may be formed by an atomic layer deposition (ALD) process. The thickness of the second sealing inorganic film TFE2 may be smaller than the thickness of the first sealing inorganic film TFE1.

[0162] The display panel 100 may further include an organic film APL. The organic film APL may be a layer for increasing the interfacial adhesion between the encapsulation layer TFE and the optical layer OPL. The organic film APL may be an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0163] The optical layer OPL may include a color filter layer CFL, a first fill layer FIL1, a base layer BAS, a nanopattern layer NPL, and a second fill layer FIL2. The color filter layer CFL may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The color filters CF1, CF2, and CF3 are disposed on the organic film APL.

[0164] The first color filter CF1 overlaps the first light-emitting area EA1 of the first sub-pixel SP1. The first color filter CF1 can transmit light of a first color, i.e., light in the red wavelength band. The red wavelength band can be a wavelength band of approximately 600 nm to 750 nm. Therefore, the first color filter CF1 can transmit light of the first color emitted from the first light-emitting area EA1.

[0165] The second color filter CF2 overlaps with the second light-emitting area EA2 of the second sub-pixel SP2. The second color filter CF2 can transmit light of a second color, i.e., light in the green wavelength band. The green wavelength band can be a wavelength band of approximately 480 nm to 560 nm. Therefore, the second color filter CF2 can transmit light of the second color emitted from the second light-emitting area EA2.

[0166] The third color filter CF3 overlaps with the third light-emitting area EA3 of the third sub-pixel SP3. The third color filter CF3 can transmit light of a third color, i.e., light in the blue wavelength band. The blue wavelength band can be a wavelength band of approximately 370 nm to 460 nm. Therefore, the third color filter CF3 can transmit light of the third color emitted from the third light-emitting area EA3.

[0167] The first filling layer FIL1 is disposed on the color filter layer CFL. The first filling layer FIL1 may have a predetermined refractive index so that light travels in the third direction DR3 at the interface between the color filter layer CFL and the first filling layer FIL1. The first filling layer FIL1 may also be a planarization layer. The first filling layer FIL1 may be an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0168] The base layer BAS is disposed on the first filler layer FIL1. The base layer BAS may include a transparent material with high transmittance so that light emitted from the display element layer EML can pass through. In one embodiment, the base layer BAS may include rigid glass. In another embodiment, the base layer BAS may include an insulating material such as a polymer resin, such as polyimide, that is flexible and allows bending, folding, rolling, and the like. In still another embodiment, the base layer BAS may include III-V compound semiconductor crystals such as gallium phosphide (GaP), aluminum gallium arsenide (AlGaAs), and gallium nitride (GaN), II-VI semiconductor crystals such as zinc sulfide (ZnS) and zinc selenide (ZnSe), and IV semiconductor crystals such as hexagonal or cubic silicon carbide (SiC).

[0169] The nanopattern layer NPL is disposed on the base layer BAS. The nanopattern layer NPL may include a plurality of nanopattern NPs. The plurality of nanopattern NPs in the nanopattern layer NPL can realize a metasurface. For example, the plurality of nanopattern NPs can diffract light emitted from the display element layer EML to change the path of the light. The nanopattern NPs may include a plurality of nanostructures STR (see FIG. 16). The nanopattern layer NPL will be described later with reference to FIG. 10, etc.

[0170] In this specification, the term "nanopattern" refers to a pattern formed with a fine structure at the nanometer level or less. The "nanometer level" includes not only nanometers but also picometers (10 -12 m), femtometer (10 -15 This includes units smaller than nanometers, such as nanometers (m).

[0171] The second fill layer FIL2 is disposed on the nanopattern layer NPL. The second fill layer FIL2 may be a planarization layer. The second fill layer FIL2 may be an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0172] The cover layer CVL is disposed on the second filling layer FIL2. The cover layer CVL can be a glass substrate or a polymer resin such as resin. If the cover layer CVL is a glass substrate, it is attached to the second filling layer FIL2. In this case, the second filling layer FIL2 serves to adhere the cover layer CVL. If the cover layer CVL is a glass substrate, it can serve as a sealing substrate. If the cover layer CVL is a polymer resin such as resin, it can be applied directly on the second filling layer FIL2.

[0173] The polarizer POL is disposed on one surface of the cover layer CVL. The polarizer POL may be a structure for preventing a decrease in visibility due to external light reflection. The polarizer POL may include a linear polarizer and a phase retardation film. For example, the phase retardation film may be a λ / 4 plate (quarter-wave plate), but the embodiment of the present specification is not limited thereto. However, if the visibility due to external light reflection is sufficiently improved by the multiple color filters CF1, CF2, and CF3, the polarizer POL may be omitted.

[0174] In the drawings, the polarizer POL is shown mounted on the display panel 100, but is not limited thereto. For example, the polarizer POL may be included in an optical module 800 (see FIG. 11) described below, in which case the polarizer POL may have the same configuration as the first optical module 810 (see FIG. 11) of the optical module 800 (see FIG. 11). That is, the polarizer POL may be mounted on the display panel 100 or the optical module 800 (see FIG. 11).

[0175] FIG. 8 is a cross-sectional view showing another example of the display panel taken along the line X1-X1' in FIG.

[0176] 8, the base layer BAS can be omitted, in which case the nanopattern layer NPL can be disposed directly on the first fill layer FIL1.

[0177] FIG. 9 is a cross-sectional view showing still another example of the display panel taken along the line X1-X1' in FIG.

[0178] 9, the optical layer OPL may further include a plurality of lenses LNS. Each of the plurality of lenses LNS is disposed on the first color filter CF1, the second color filter CF2, and the third color filter CF3, respectively. Each of the plurality of lenses LNS may be a structure for increasing the proportion of light directed toward the front of the display device 10. Each of the plurality of lenses LNS may have a cross-sectional shape that is convex upward. In some embodiments, the plurality of lenses LNS may be a microlens array (MLA).

[0179] 10 is a schematic cross-sectional view showing a display element layer, a color filter layer, a lens, a nanopattern layer, and an optical module of a display device according to an embodiment, and FIG. 11 is a schematic cross-sectional view showing a display panel and an optical module according to an embodiment.

[0180] 7 to 9, and referring to FIGS. 10 and 11, the display device 10 may include a display panel 100 and an optical module 800 disposed on the display panel 100. In the example shown in FIG.

[0181] The display panel 100 has been described with reference to FIG. 7 and the like, so a description of the display panel 100 will be omitted.

[0182] 11 , the optical module 800 may include a first optical module 810, a second optical module 820, a third optical module 830, and a fourth optical module 840. The first optical module 810 is disposed on the display panel 100, the second optical module 820 is disposed on the first optical module 810, the third optical module 830 is disposed on the second optical module 820, and the fourth optical module 840 is disposed on the third optical module 830.

[0183] In some embodiments, the first optical module 810 may be disposed directly on the display panel 100. For example, the first optical module 810 may be mounted on and in direct contact with the display panel 100. The second optical module 820 may be disposed at a distance from the first optical module 810, the third optical module 830 may be disposed at a distance from the second optical module 820, and the fourth optical module 840 may be disposed at a distance from the third optical module 830. Air gaps filled with air may be located between the second optical module 820 and the first optical module 810, between the third optical module 830 and the second optical module 820, and between the fourth optical module 840 and the third optical module 830, respectively.

[0184] The first optical module 810 may have the same configuration as the polarizer POL of the display panel 100 described with reference to FIG. 7 etc. The display device 10 may include either the polarizer POL of the display panel 100 or the first optical module 810 of the optical module 800.

[0185] The second through fourth optical modules 820, 830, and 840 may each include a lens. Each lens included in the second through fourth optical modules 820, 830, and 840 may magnify an image formed by light generated from the display panel 100. The lenses included in the second through fourth optical modules 820, 830, and 840 may have various shapes, such as a convex lens, a concave lens, a meniscus lens, or a Fresnel lens, and the shapes and types of the lenses included in the second through fourth optical modules 820, 830, and 840 are not limited thereto.

[0186] Each of the lenses included in the second through fourth optical modules 820, 830, and 840 may include at least one convex or concave surface. The convex surface may have a highest point (e.g., 820a or 840a in the drawings) that is the most convex portion, and the concave surface may have a lowest point (e.g., 830a in the drawings) that is the most concave portion. In some embodiments, the highest point 820a or 840a and the lowest point 830a of each of the lenses included in the second through fourth optical modules 820, 830, and 840 may be arranged on a straight line (in the example of FIG. 11 , on a straight line along a direction perpendicular to the plane of the display panel 100).

[0187] The display panel 100 may include a first pixel PX1, a second pixel PX2, and a third pixel PX3. The first pixel PX1 is a pixel PX located in the center of the plurality of pixels PX included in the display panel 100. The third pixel PX3 is a pixel PX located on the edge of the plurality of pixels PX included in the display panel 100. The second pixel PX2 is a pixel PX located between the first pixel PX1 and the third pixel PX3 of the plurality of pixels PX included in the display panel 100.

[0188] Here, the center refers to a point (for example, 100a in the drawing) located on the straight line where the highest points 820a and 840a and the lowest point 830a are located side by side.

[0189] The first to third pixels PX1, PX2, and PX3 may each include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 of the first to third pixels PX1, PX2, and PX3 may each include a first light-emitting region EA1, a second light-emitting region EA2, and a third light-emitting region EA3. For example, the first sub-pixel SP1 of each of the first to third pixels PX1, PX2, and PX3 may include the first light-emitting region EA1, the second sub-pixel SP2 of each of the first to third pixels PX1, PX2, and PX3 may include the second light-emitting region EA2, and the third sub-pixel SP3 of each of the first to third pixels PX1, PX2, and PX3 may include the third light-emitting region EA3.

[0190] In the display device 10 according to this embodiment, the lenses LNS and the color filters CF1, CF2, and CF3 are arranged in a line with the light-emitting regions EA1, EA2, and EA3, respectively. For example, as shown in the drawings, the centers of the lenses LNS and the color filters CF1, CF2, and CF3 may be arranged in a line with the light-emitting regions EA1, EA2, and EA3 on a first line L0 (FIG. 10) extending in the third direction DR3. That is, as shown in FIGS. 9 and 10, in the display device 10 according to this embodiment, in the first to third pixels PX1 to PX3 located at the center, edge, or between the center and edge of the display device 10, the first to third light-emitting regions EA1 to EA3, the color filters CF1 to CF3, and the lenses LNS are arranged in a line along the third direction DR3 (the first line L0 in the example of FIG. 10) in the first to third sub-pixels SP1 to SP3. The third direction DR3 is a direction perpendicular to the planar direction of the nanopattern layer NPL. As will be described later, in the nanopattern layer NPL, a plurality of nanopatterns NP are arranged in a plane including the first and second directions DR1 and DR2.

[0191] For example, in the display device 10 according to the comparative embodiment, the second light-emitting region EA2 of the second sub-pixel SP2 of the first pixel PX1 located at the center of the display panel 100, the second color filter CF2 overlapping the second light-emitting region EA2, and the lens LNS overlapping the second light-emitting region EA2 are arranged on a straight line. Note that, in the display device 10 according to the comparative embodiment, the third light-emitting region EA3 of the third sub-pixel SP3 of the third pixel PX3 located at the edge of the display panel 100, the third color filter CF3 overlapping the third light-emitting region EA3, and the lens LNS overlapping the third light-emitting region EA3 may be shifted relative to one another in one direction (e.g., the horizontal direction in the drawing) to improve the average luminance according to the chief ray angle (CRA) distribution. That is, in the display device according to the comparative embodiment, for the first pixel PX1 located at the center of the display device, the first to third light-emitting regions EA1 to EA3, color filters CF1 to CF3, and lenses LNS are arranged side by side along the third direction DR3 in the first to third sub-pixels SP1 to SP3. However, for the third pixel PX3 located on the edge of the display device, the first to third light-emitting regions EA1 to EA3, color filters CF1 to CF3, and lenses LNS are not arranged side by side along the third direction DR3 in the first to third sub-pixels SP1 to SP3, but are arranged offset along a plane (e.g., a horizontal plane) including the first and second directions DR1 and DR2.

[0192] As described above, the display device 10 according to this embodiment is provided with a nanopattern layer NPL, and therefore can achieve an improvement in average brightness according to the chief ray angle distribution without having to shift and arrange multiple color filters CF1, CF2, CF3 and multiple lenses LNS, for example, along a horizontal plane, as in the comparative embodiment.

[0193] Specifically, to increase the field of view (FOV), control stray light, and prevent image distortion, light emitted from a first pixel PX1 located at the center of the display panel 100 may be incident on the optical module 800 generally parallel to a normal (e.g., the third direction DR3 in the drawing). Meanwhile, light emitted from a third pixel PX3 located at the edge of the display panel 100 may be incident on the optical module 800 generally at a first angle (θ1) relative to the normal. The first angle (θ1) may be the chief ray angle of the light emitted from the third pixel PX3, which is an edge pixel. In some embodiments, the first angle (θ1) may be approximately 25 degrees to 35 degrees.

[0194] In the display device 10 according to the comparative embodiment, particularly for the third pixel PX3 located at the edge of the display device, the color filters CF1, CF2, and CF3 and the lenses LNS are shifted relative to the light-emitting regions EA1, EA2, and EA3, respectively, to increase the angle of view. This shifting adjusts the path of light according to the angular distribution of the chief ray. For example, in the comparative embodiment, the color filter CF1 and the lens LNS of the third pixel PX3 are not positioned along the third direction DR3 (the first straight line L0 in the example of FIG. 10) relative to the light-emitting region EA1, but are shifted horizontally. In contrast, in the display device 10 according to the present embodiment, the path of light can be adjusted according to the angular distribution of the chief ray by the diffraction of light by the multiple nanopatterns NP of the nanopattern layer NPL. Therefore, the angle of view can be increased by using the nanopattern layer NPL. Therefore, since there is no need to adopt a shifting arrangement as in the comparative embodiment to increase the angle of view, the manufacturing process of the display device 10 can be simplified, resulting in reduced costs and improved process efficiency.

[0195] Fig. 12 is a diagram showing an example of an image displayed by a display device according to a comparative embodiment, and Fig. 13 is a diagram showing an example of an image displayed by a display device according to an embodiment.

[0196] 12 and 13 in addition to Fig. 10, the display device 10 according to the comparative embodiment does not include an optical module 800. Therefore, as shown in Fig. 12, distortion of the edge of the image according to the chief ray angle may occur. On the other hand, the display device 10 according to the present embodiment may include an optical module 800. Therefore, as shown in Fig. 13, distortion of the edge of the image according to the chief ray angle does not occur.

[0197] Furthermore, the display device 10 according to this embodiment can improve the luminance according to the angular distribution of the chief ray through the nanopattern layer NPL. For example, the nanopattern layer NPL can minimize the luminance reduction of light while passing through the optical module 800 by diffracting light according to the angular distribution of the chief ray.

[0198] Fig. 14 is a cross-sectional view showing a nanopattern overlapping with the first pixel shown in Fig. 10. Fig. 15 is a cross-sectional view showing a nanopattern overlapping with the third pixel shown in Fig. 10.

[0199] 7 and 10, and referring to FIGS. 14 and 15, the display panel 100 may include a first pixel PX1 located in the center of the display panel 100 and a third pixel PX3 located on the edge of the display panel 100.

[0200] The first pixel PX1 may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. The first sub-pixel SP1 of the first pixel PX1 may include a first light-emitting region EA1, the second sub-pixel SP2 of the first pixel PX1 may include a second light-emitting region EA2, and the third sub-pixel SP3 of the first pixel PX1 may include a third light-emitting region EA3.

[0201] The third pixel PX3 may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. The first sub-pixel SP1 of the third pixel PX3 may include a first light-emitting region EA1, the second sub-pixel SP2 of the third pixel PX3 may include a second light-emitting region EA2, and the third sub-pixel SP3 of the third pixel PX3 may include a third light-emitting region EA3.

[0202] A plane (e.g., a horizontal plane) including the first and second directions DR1 and DR2 may include a plurality of nanopatterns NP. For example, the nanopattern layer NPL may include a first nanopattern NP1 overlapping the first light-emitting region EA1 of the first sub-pixel SP1 of the first pixel PX1, a second nanopattern NP2 overlapping the second light-emitting region EA2 of the second sub-pixel SP2 of the first pixel PX1, a third nanopattern NP3 overlapping the third light-emitting region EA3 of the third sub-pixel SP3 of the first pixel PX1, a fourth nanopattern NP4 overlapping the first light-emitting region EA1 of the first sub-pixel SP1 of the third pixel PX3, a fifth nanopattern NP5 overlapping the second light-emitting region EA2 of the second sub-pixel SP2 of the third pixel PX3, and a sixth nanopattern NP6 overlapping the third light-emitting region EA3 of the third sub-pixel SP3 of the third pixel PX3.

[0203] In a plane including the first and second directions DR1 and DR2 (e.g., a horizontal plane), the second nanopattern NP2 is located at the center of the display panel 100. The first nanopattern NP1 and the third nanopattern NP3 are located on one side and the other side of the second nanopattern NP2 in the plane. The sixth nanopattern NP6 is located at the edge of the display panel 100. For example, the sixth nanopattern NP6 is located at the left edge of the display panel 100 in the plane. The fifth nanopattern NP5 is located on one side of the sixth nanopattern NP6 in the plane, and the fifth nanopattern NP5 is located next to the sixth nanopattern NP6 at the edge of the display panel 100. The fourth nanopattern NP4 is located on one side of the fifth nanopattern NP5, and the fourth nanopattern NP4 is located next to the fifth nanopattern NP5 at the edge of the display panel 100. The fourth nanopattern NP4 is located closer to the center of the display panel 100 than the fifth nanopattern NP5, and the fifth nanopattern NP5 is located closer to the center of the display panel 100 than the sixth nanopattern NP6.

[0204] The first nanopattern NP1 may include at least one first sub-nanopattern SNP1. The second nanopattern NP2 may include at least one second sub-nanopattern SNP2. The third nanopattern NP3 may include at least one third sub-nanopattern SNP3. The fourth nanopattern NP4 may include at least one fourth sub-nanopattern SNP4. The fifth nanopattern NP5 may include at least one fifth sub-nanopattern SNP5. The sixth nanopattern NP6 may include at least one sixth sub-nanopattern SNP6.

[0205] The first to sixth sub-nanopatterns SNP1, SNP2, SNP3, SNP4, SNP5, and SNP6 may be unit patterns of the first to sixth nanopatterns NP1, NP2, NP3, NP4, NP5, and NP6, respectively. For example, if the first to sixth nanopatterns NP1, NP2, NP3, NP4, NP5, and NP6 each include a plurality of the first to sixth sub-nanopatterns SNP1, SNP2, SNP3, SNP4, SNP5, and SNP6, respectively, the first to sixth nanopatterns NP1, NP2, NP3, NP4, NP5, and NP6 may each include a plurality of the first to sixth sub-nanopatterns SNP1, SNP2, SNP3, SNP4, SNP5, and SNP6 that are repeatedly arranged.

[0206] 14 and 15, the first light-emitting region EA1 of the first sub-pixel SP1 of the first pixel PX1 overlaps with the plurality of first sub-nanopatterns SNP1, the second light-emitting region EA2 of the second sub-pixel SP2 of the first pixel PX1 overlaps with the plurality of second sub-nanopatterns SNP2, the third light-emitting region EA3 of the third sub-pixel SP3 of the first pixel PX1 overlaps with the plurality of third sub-nanopatterns SNP3, the first light-emitting region EA1 of the first sub-pixel SP1 of the third pixel PX3 overlaps with the plurality of fourth sub-nanopatterns SNP4, the second light-emitting region EA2 of the second sub-pixel SP2 of the third pixel PX3 overlaps with the plurality of fifth sub-nanopatterns SNP5, and the third light-emitting region EA3 of the third sub-pixel SP3 of the third pixel PX3 overlaps with the plurality of sixth sub-nanopatterns SNP6.

[0207] The first to sixth sub-nanopatterns SNP1, SNP2, SNP3, SNP4, SNP5, and SNP6 may each include a plurality of nanostructures STR (see FIG. 16). For example, as shown in the drawing, the first to sixth sub-nanopatterns SNP1, SNP2, SNP3, SNP4, SNP5, and SNP6 may each include four nanostructures STR (see FIG. 16). However, the number of nanostructures STR (see FIG. 16) included in each of the first to sixth sub-nanopatterns SNP1, SNP2, SNP3, SNP4, SNP5, and SNP6 is not limited to this.

[0208] In the display device 10 according to this embodiment, the second nanopattern NP2 can maintain the path of the light emitted from the second light-emitting region EA2 of the second sub-pixel SP2 of the first pixel PX1. For example, the second nanopattern NP2 can prevent the light emitted from the second light-emitting region EA2 of the second sub-pixel SP2 of the first pixel PX1 from being diffracted and allow it to travel straight.

[0209] The first nanopattern NP1 can change the path of light emitted from the first light-emitting region EA1 of the first sub-pixel SP1 of the first pixel PX1. The third nanopattern NP3 can change the path of light emitted from the third light-emitting region EA3 of the third sub-pixel SP3 of the first pixel PX1. The fourth nanopattern NP4 can change the path of light emitted from the first light-emitting region EA1 of the first sub-pixel SP1 of the third pixel PX3. The fifth nanopattern NP5 can change the path of light emitted from the second light-emitting region EA2 of the second sub-pixel SP2 of the third pixel PX3. The sixth nanopattern NP6 can change the path of light emitted from the third light-emitting region EA3 of the third sub-pixel SP3 of the third pixel PX3.

[0210] In some embodiments, the angle of light passing through the nanopattern NP relative to the front direction (e.g., the third direction DR3 in the drawings) increases from the nanopattern NP located in the center to the nanopattern NP located at the edge of the display panel 100. For example, the angle of light passing through the second nanopattern NP2 relative to the front direction may be 0°, and the angles of light passing through the first nanopattern NP1, the third nanopattern NP3, the fourth nanopattern NP4, the fifth nanopattern NP5, and the sixth nanopattern NP6 relative to the front direction may be greater than 0°.

[0211] The angle of travel of light passing through the first nanopattern NP1 relative to the frontal direction may be substantially the same as the angle of travel of light passing through the third nanopattern NP3 relative to the frontal direction. In other words, in the example of FIG. 14, the direction in which light passing through the first nanopattern NP1 travels at an angle relative to the frontal direction and the direction in which light passing through the third nanopattern NP3 travels at an angle relative to the frontal direction are generally symmetrical with respect to the frontal direction (or the angle of travel (0°) relative to the frontal direction) of light passing through the second nanopattern NP2. The angle of travel of light passing through the fourth nanopattern NP4 relative to the frontal direction may be larger than the angle of travel of light passing through the first nanopattern NP1 and the third nanopattern NP3 relative to the frontal direction. The angle of travel of light passing through the fifth nanopattern NP5 relative to the frontal direction may be larger than the angle of travel of light passing through the fourth nanopattern NP4 relative to the frontal direction. The angle of travel of light passing through the sixth nanopattern NP6 relative to the frontal direction may be larger than the angle of travel of light passing through the fifth nanopattern NP5 relative to the frontal direction.

[0212] Figure 16 is a perspective view showing a second nanopattern of a nanopattern layer according to an embodiment. Figure 17 is a perspective view showing a sixth nanopattern of a nanopattern layer according to an embodiment. Figure 18 is a plan view showing first to third nanopatterns of a nanopattern layer according to an embodiment. Figure 19 is a plan view showing fourth to sixth nanopatterns of a nanopattern layer according to an embodiment.

[0213] 16 to 19 in addition to FIGS. 7, 10, 14, and 15, the nanopattern NP may include a plurality of nanostructures STR. In one embodiment, the height of the nanostructures STR may be approximately 200 nm to 400 nm, and preferably 300 nm to 350 nm. In one embodiment, the diameter of the nanostructures STR may be approximately 100 nm to 200 nm. The plurality of nanostructures STR may be cylindrical in shape (e.g., nano-rod shape), but is not limited thereto.

[0214] In some embodiments, the nanostructures STR can comprise amorphous silicon, while in other embodiments, the nanostructures STR can comprise single-crystal silicon or polycrystalline silicon.

[0215] In some embodiments, the nanostructures STR can comprise a metal, for example, the nanostructures STR can comprise at least one of gold (Au), silver (Ag), aluminum (Al), copper (Cu), nickel (Ni), titanium (Ti), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), or alloys thereof.

[0216] The nanostructures STR included in the second sub-nanopattern SNP2 of the second nanopattern NP2 located at the center of the display panel 100 may have the same size, separation distance, and center-to-center distance.

[0217] For example, as shown in Figures 16 and 18, one second sub-nanopattern SNP2 may include four nanostructures STR0. The heights H0 of the nanostructures STR0 included in the second sub-nanopattern SNP2 may be the same. The diameters R0 (or widths) of the nanostructures STR0 included in the second sub-nanopattern SNP2 may be the same. The distances D0 between the nanostructures STR0 included in the second sub-nanopattern SNP2 may be the same. The center-to-center distances P0 of the nanostructures STR0 included in the second sub-nanopattern SNP2 may be the same.

[0218] The nanostructures STR included in the sixth sub-nanopatterns SNP6 of the sixth nanopattern NP6 located on the edge of the display panel 100 may differ from each other in at least one of size, separation distance, and center-to-center distance.

[0219] 17 and 19, one sixth sub-nanopattern SNP6 may include four nanostructures STR1, STR2, STR3, and STR4. The sixth sub-nanopattern SNP6 may include a first nanostructure STR1, a second nanostructure STR2, a third nanostructure STR3, and a fourth nanostructure STR4. The first nanostructure STR1 of the sixth sub-nanopattern SNP6 is disposed on one side, in the first direction DR1, of the second nanostructure STR2 of the sixth sub-nanopattern SNP6, the second nanostructure STR2 of the sixth sub-nanopattern SNP6 is disposed on one side, in the first direction DR1, of the third nanostructure STR3 of the sixth sub-nanopattern SNP6, and the third nanostructure STR3 of the sixth sub-nanopattern SNP6 is disposed on one side, in the first direction DR1, of the fourth nanostructure STR4 of the sixth sub-nanopattern SNP6. The first nanostructure STR1, the second nanostructure STR2, the third nanostructure STR3, and the fourth nanostructure STR4 of the sixth sub-nanopattern SNP6 are arranged in this order away from a position adjacent to the center of the display panel 100.

[0220] The heights H0 of the first nanostructure STR1, the second nanostructure STR2, the third nanostructure STR3, and the fourth nanostructure STR4 of the sixth sub-nanopattern SNP6 may be the same as each other.

[0221] The diameters of the first nanostructure STR1, the second nanostructure STR2, the third nanostructure STR3, and the fourth nanostructure STR4 of the sixth sub-nanopattern SNP6 may be different from one another. For example, the diameter R61 of the first nanostructure STR1 of the sixth sub-nanopattern SNP6 may be smaller than the diameter R62 of the second nanostructure STR2 of the sixth sub-nanopattern SNP6, which may be smaller than the diameter R63 of the third nanostructure STR3 of the sixth sub-nanopattern SNP6, which may be smaller than the diameter R64 of the fourth nanostructure STR4 of the sixth sub-nanopattern SNP6.

[0222] In one embodiment, the diameter R61 (or width) of the first nanostructure STR1 of the sixth sub-nanopattern SNP6 may be approximately 94 nm to 134 nm, the diameter R62 (or width) of the second nanostructure STR2 of the sixth sub-nanopattern SNP6 may be approximately 104 nm to 144 nm, the diameter R63 (or width) of the third nanostructure STR3 of the sixth sub-nanopattern SNP6 may be approximately 114 nm to 154 nm, and the diameter R64 (or width) of the fourth nanostructure STR4 of the sixth sub-nanopattern SNP6 may be approximately 150 nm to 190 nm.

[0223] In some embodiments, the mutual distances of the first nanostructure STR1, the second nanostructure STR2, the third nanostructure STR3, and the fourth nanostructure STR4 of the sixth sub-nanopattern SNP6 may be identical to one another. For example, the distance D61 between the first nanostructure STR1 of the sixth sub-nanopattern SNP6 and the second nanostructure STR2 of the sixth sub-nanopattern SNP6, the distance D62 between the second nanostructure STR2 of the sixth sub-nanopattern SNP6 and the third nanostructure STR3 of the sixth sub-nanopattern SNP6, and the distance D63 between the third nanostructure STR3 of the sixth sub-nanopattern SNP6 and the fourth nanostructure STR4 of the sixth sub-nanopattern SNP6 may be identical to one another.

[0224] In some embodiments, the center-to-center distances of the first nanostructure STR1, the second nanostructure STR2, the third nanostructure STR3, and the fourth nanostructure STR4 of the sixth sub-nanopattern SNP6 may be different from one another. For example, the center-to-center distance P61 between the first nanostructure STR1 of the sixth sub-nanopattern SNP6 and the second nanostructure STR2 of the sixth sub-nanopattern SNP6 may be smaller than the center-to-center distance P62 between the second nanostructure STR2 of the sixth sub-nanopattern SNP6 and the third nanostructure STR3 of the sixth sub-nanopattern SNP6, and the center-to-center distance P62 between the second nanostructure STR2 of the sixth sub-nanopattern SNP6 and the third nanostructure STR3 of the sixth sub-nanopattern SNP6 may be smaller than the center-to-center distance P63 between the third nanostructure STR3 of the sixth sub-nanopattern SNP6 and the fourth nanostructure STR4 of the sixth sub-nanopattern SNP6.

[0225] In this way, the second nanopattern NP2 located at the center of the display panel 100 has the same size and spacing of the nanostructures STR of the second sub-nanopattern SNP2, so the path of light passing through the nanopattern NP can maintain a straight direction (e.g., the third direction DR3). On the other hand, the sixth nanopattern NP6 located at the edge of the display panel 100 has at least one of the size, spacing, and center-to-center distance of the nanostructures STR of the sixth sub-nanopattern SNP6 that is different from the second nanopattern NP2 located at the center of the display panel 100. Therefore, the path of light passing through the nanopattern NP can be changed due to the light diffraction phenomenon. For example, as shown in Figures 15 and 19, in the sixth nanopattern NP6, the direction of light changes from the smaller first nanostructure STR1 to the larger fourth nanostructure STR4.

[0226] In addition, the nanopatterns NP located between the center and the edge of the display panel 100 can adjust the degree of light diffraction by adjusting the size, spacing, and center-to-center distance of the nanostructures STR.

[0227] 14, the first nanopattern NP1 arranged on one side of the second nanopattern NP2 in the first direction DR1 may include a first sub-nanopattern SNP1. The nanostructures STR included in the first sub-nanopattern SNP1 may differ from each other in at least one of size, separation distance, and center-to-center distance.

[0228] 18, one first sub-nanopattern SNP1 may include four nanostructures STR1, STR2, STR3, and STR4. The first sub-nanopattern SNP1 may include a first nanostructure STR1, a second nanostructure STR2, a third nanostructure STR3, and a fourth nanostructure STR4. The fourth nanostructure STR4 of the first sub-nanopattern SNP1 is arranged on one side in the first direction DR1 of the third nanostructure STR3 of the first sub-nanopattern SNP1, the third nanostructure STR3 of the first sub-nanopattern SNP1 is arranged on one side in the first direction DR1 of the second nanostructure STR2 of the first sub-nanopattern SNP1, and the second nanostructure STR2 of the first sub-nanopattern SNP1 is arranged on one side in the first direction DR1 of the first nanostructure STR1 of the first sub-nanopattern SNP1. The first nanostructure STR1, the second nanostructure STR2, the third nanostructure STR3, and the fourth nanostructure STR4 of the first sub-nanopattern SNP1 are arranged in this order away from a position adjacent to the center of the display panel 100.

[0229] The diameters of the first nanostructure STR1, the second nanostructure STR2, the third nanostructure STR3, and the fourth nanostructure STR4 of the first sub-nanopattern SNP1 may be different from one another. For example, the diameter R11 of the first nanostructure STR1 of the first sub-nanopattern SNP1 may be smaller than the diameter R12 of the second nanostructure STR2 of the first sub-nanopattern SNP1, which may be smaller than the diameter R13 of the third nanostructure STR3 of the first sub-nanopattern SNP1, which may be smaller than the diameter R14 of the fourth nanostructure STR4 of the first sub-nanopattern SNP1.

[0230] In some embodiments, the mutual distances of the first nanostructure STR1, the second nanostructure STR2, the third nanostructure STR3, and the fourth nanostructure STR4 of the first sub-nanopattern SNP1 may be the same. For example, the distance D11 between the first nanostructure STR1 of the first sub-nanopattern SNP1 and the second nanostructure STR2 of the first sub-nanopattern SNP1, the distance D12 between the second nanostructure STR2 of the first sub-nanopattern SNP1 and the third nanostructure STR3 of the first sub-nanopattern SNP1, and the distance D13 between the third nanostructure STR3 of the first sub-nanopattern SNP1 and the fourth nanostructure STR4 of the first sub-nanopattern SNP1 may be the same.

[0231] In some embodiments, the center-to-center distances of the first nanostructure STR1, the second nanostructure STR2, the third nanostructure STR3, and the fourth nanostructure STR4 of the first sub-nanopattern SNP1 may be different from one another. For example, the center-to-center distance P11 between the first nanostructure STR1 of the first sub-nanopattern SNP1 and the second nanostructure STR2 of the first sub-nanopattern SNP1 may be smaller than the center-to-center distance P12 between the second nanostructure STR2 of the first sub-nanopattern SNP1 and the third nanostructure STR3 of the first sub-nanopattern SNP1, and the center-to-center distance P12 between the second nanostructure STR2 of the first sub-nanopattern SNP1 and the third nanostructure STR3 of the first sub-nanopattern SNP1 may be smaller than the center-to-center distance P13 between the third nanostructure STR3 of the first sub-nanopattern SNP1 and the fourth nanostructure STR4 of the first sub-nanopattern SNP1.

[0232] Although not shown in the drawing, the heights of the first nanostructure STR1, the second nanostructure STR2, the third nanostructure STR3, and the fourth nanostructure STR4 of the first sub-nanopattern SNP1 may be the same as one another.

[0233] 18, the third nanopattern NP3 arranged on the other side of the second nanopattern NP2 in the first direction DR1 may include a third sub-nanopattern SNP3. The nanostructures STR included in the third sub-nanopattern SNP3 may differ from each other in at least one of size, separation distance, and center-to-center distance.

[0234] 18, one third sub-nanopattern SNP3 may include four nanostructures STR1, STR2, STR3, and STR4. The third sub-nanopattern SNP3 may include a first nanostructure STR1, a second nanostructure STR2, a third nanostructure STR3, and a fourth nanostructure STR4. The first nanostructure STR1 of the third sub-nanopattern SNP3 is disposed on one side, in the first direction DR1, of the second nanostructure STR2 of the third sub-nanopattern SNP3, the second nanostructure STR2 of the third sub-nanopattern SNP3 is disposed on one side, in the first direction DR1, of the third nanostructure STR3 of the third sub-nanopattern SNP3, and the third nanostructure STR3 of the third sub-nanopattern SNP3 is disposed on one side, in the first direction DR1, of the fourth nanostructure STR4 of the third sub-nanopattern SNP3. The first nanostructure STR1, the second nanostructure STR2, the third nanostructure STR3, and the fourth nanostructure STR4 of the third sub-nanopattern SNP3 are arranged in this order away from a position adjacent to the center of the display panel 100.

[0235] The diameters of the first nanostructure STR1, the second nanostructure STR2, the third nanostructure STR3, and the fourth nanostructure STR4 of the third sub-nanopattern SNP3 may be different from one another. For example, the diameter R31 of the first nanostructure STR1 of the third sub-nanopattern SNP3 may be smaller than the diameter R32 of the second nanostructure STR2 of the third sub-nanopattern SNP3, which may be smaller than the diameter R33 of the third nanostructure STR3 of the third sub-nanopattern SNP3, which may be smaller than the diameter R34 of the fourth nanostructure STR4 of the third sub-nanopattern SNP3.

[0236] In some embodiments, the mutual distances of the first nanostructure STR1, the second nanostructure STR2, the third nanostructure STR3, and the fourth nanostructure STR4 of the third sub-nanopattern SNP3 may be identical to one another. For example, the distance D31 between the first nanostructure STR1 of the third sub-nanopattern SNP3 and the second nanostructure STR2 of the third sub-nanopattern SNP3, the distance D32 between the second nanostructure STR2 of the third sub-nanopattern SNP3 and the third nanostructure STR3 of the third sub-nanopattern SNP3, and the distance D33 between the third nanostructure STR3 of the third sub-nanopattern SNP3 and the fourth nanostructure STR4 of the third sub-nanopattern SNP3 may be identical to one another.

[0237] In some embodiments, the center-to-center distances of the first nanostructure STR1, the second nanostructure STR2, the third nanostructure STR3, and the fourth nanostructure STR4 of the third sub-nanopattern SNP3 may be different from one another. For example, the center-to-center distance P31 between the first nanostructure STR1 of the third sub-nanopattern SNP3 and the second nanostructure STR2 of the third sub-nanopattern SNP3 may be smaller than the center-to-center distance P32 between the second nanostructure STR2 of the third sub-nanopattern SNP3 and the third nanostructure STR3 of the third sub-nanopattern SNP3, which may be smaller than the center-to-center distance P33 between the third nanostructure STR3 of the third sub-nanopattern SNP3 and the fourth nanostructure STR4 of the third sub-nanopattern SNP3.

[0238] Although not shown in the drawing, the heights of the first nanostructure STR1, the second nanostructure STR2, the third nanostructure STR3, and the fourth nanostructure STR4 of the third sub-nanopattern SNP3 may be the same as each other.

[0239] In some embodiments, as shown in FIG. 18, the first sub-nanopattern SNP1 and the third sub-nanopattern SNP3 may be bilaterally symmetrical with respect to the second sub-nanopattern SNP2.

[0240] In addition, the fifth nanopattern NP5 arranged on one side of the sixth nanopattern NP6 in the first direction DR1 may include a fifth sub-nanopattern SNP5. The nanostructures STR included in the fifth sub-nanopattern SNP5 may differ from each other in at least one of size, separation distance, and center-to-center distance.

[0241] 19, one fifth sub-nanopattern SNP5 may include four nanostructures STR1, STR2, STR3, and STR4. The fifth sub-nanopattern SNP5 may include a first nanostructure STR1, a second nanostructure STR2, a third nanostructure STR3, and a fourth nanostructure STR4. The first nanostructure STR1 of the fifth sub-nanopattern SNP5 is disposed on one side, in the first direction DR1, of the second nanostructure STR2 of the fifth sub-nanopattern SNP5, the second nanostructure STR2 of the fifth sub-nanopattern SNP5 is disposed on one side, in the first direction DR1, of the third nanostructure STR3 of the fifth sub-nanopattern SNP5, and the third nanostructure STR3 of the fifth sub-nanopattern SNP5 is disposed on one side, in the first direction DR1, of the fourth nanostructure STR4 of the fifth sub-nanopattern SNP5. The first nanostructure STR1, the second nanostructure STR2, the third nanostructure STR3, and the fourth nanostructure STR4 of the fifth sub-nanopattern SNP5 are arranged in this order away from the position adjacent to the center of the display panel 100.

[0242] The diameters of the first nanostructure STR1, the second nanostructure STR2, the third nanostructure STR3, and the fourth nanostructure STR4 of the fifth sub-nanopattern SNP5 may be different from one another. For example, the diameter R51 of the first nanostructure STR1 of the fifth sub-nanopattern SNP5 may be smaller than the diameter R52 of the second nanostructure STR2 of the fifth sub-nanopattern SNP5, which may be smaller than the diameter R53 of the third nanostructure STR3 of the fifth sub-nanopattern SNP5, which may be smaller than the diameter R54 of the fourth nanostructure STR4 of the fifth sub-nanopattern SNP5.

[0243] In some embodiments, the mutual distances of the first nanostructure STR1, the second nanostructure STR2, the third nanostructure STR3, and the fourth nanostructure STR4 of the fifth sub-nanopattern SNP5 may be identical to one another. For example, the distance D51 between the first nanostructure STR1 of the fifth sub-nanopattern SNP5 and the second nanostructure STR2 of the fifth sub-nanopattern SNP5, the distance D52 between the second nanostructure STR2 of the fifth sub-nanopattern SNP5 and the third nanostructure STR3 of the fifth sub-nanopattern SNP5, and the distance D53 between the third nanostructure STR3 of the fifth sub-nanopattern SNP5 and the fourth nanostructure STR4 of the fifth sub-nanopattern SNP5 may be identical to one another.

[0244] In some embodiments, the center-to-center distances of the first nanostructure STR1, the second nanostructure STR2, the third nanostructure STR3, and the fourth nanostructure STR4 of the fifth sub-nanopattern SNP5 may be different from one another. For example, the center-to-center distance P51 between the first nanostructure STR1 of the fifth sub-nanopattern SNP5 and the second nanostructure STR2 of the fifth sub-nanopattern SNP5 may be smaller than the center-to-center distance P52 between the second nanostructure STR2 of the fifth sub-nanopattern SNP5 and the third nanostructure STR3 of the fifth sub-nanopattern SNP5, and the center-to-center distance P52 between the second nanostructure STR2 of the fifth sub-nanopattern SNP5 and the third nanostructure STR3 of the fifth sub-nanopattern SNP5 may be smaller than the center-to-center distance P53 between the third nanostructure STR3 of the fifth sub-nanopattern SNP5 and the fourth nanostructure STR4 of the fifth sub-nanopattern SNP5.

[0245] Although not shown in the drawing, the heights of the first nanostructure STR1, the second nanostructure STR2, the third nanostructure STR3, and the fourth nanostructure STR4 of the fifth sub-nanopattern SNP5 may be the same as each other.

[0246] The fourth nanopattern NP4 arranged on one side of the fifth nanopattern NP5 in the first direction DR1 may include a fourth sub-nanopattern SNP4. The nanostructures STR included in the fourth sub-nanopattern SNP4 may differ from each other in at least one of size, separation distance, and center-to-center distance.

[0247] 19, one fourth sub-nanopattern SNP4 may include four nanostructures STR1, STR2, STR3, and STR4. The fourth sub-nanopattern SNP4 may include a first nanostructure STR1, a second nanostructure STR2, a third nanostructure STR3, and a fourth nanostructure STR4. The first nanostructure STR1 of the fourth sub-nanopattern SNP4 is disposed on one side of the second nanostructure STR2 of the fourth sub-nanopattern SNP4 in the first direction DR1, the second nanostructure STR2 of the fourth sub-nanopattern SNP4 is disposed on one side of the third nanostructure STR3 of the fourth sub-nanopattern SNP4 in the first direction DR1, and the third nanostructure STR3 of the fourth sub-nanopattern SNP4 is disposed on one side of the fourth nanostructure STR4 of the fourth sub-nanopattern SNP4 in the first direction DR1. The first nanostructure STR1, the second nanostructure STR2, the third nanostructure STR3, and the fourth nanostructure STR4 of the fourth sub-nanopattern SNP4 are disposed adjacent to the center of the display panel 100 in this order.

[0248] The diameters of the first nanostructure STR1, the second nanostructure STR2, the third nanostructure STR3, and the fourth nanostructure STR4 of the fourth sub-nanopattern SNP4 may be different from one another. For example, the diameter R41 of the first nanostructure STR1 of the fourth sub-nanopattern SNP4 may be smaller than the diameter R42 of the second nanostructure STR2 of the fourth sub-nanopattern SNP4, which may be smaller than the diameter R43 of the third nanostructure STR3 of the fourth sub-nanopattern SNP4, which may be smaller than the diameter R44 of the fourth nanostructure STR4 of the fourth sub-nanopattern SNP4.

[0249] In some embodiments, the mutual distances of the first nanostructure STR1, the second nanostructure STR2, the third nanostructure STR3, and the fourth nanostructure STR4 of the fourth sub-nanopattern SNP4 may be identical to one another. For example, the distance D41 between the first nanostructure STR1 of the fourth sub-nanopattern SNP4 and the second nanostructure STR2 of the fourth sub-nanopattern SNP4, the distance D42 between the second nanostructure STR2 of the fourth sub-nanopattern SNP4 and the third nanostructure STR3 of the fourth sub-nanopattern SNP4, and the distance D43 between the third nanostructure STR3 of the fourth sub-nanopattern SNP4 and the fourth nanostructure STR4 of the fourth sub-nanopattern SNP4 may be identical to one another.

[0250] In some embodiments, the center-to-center distances of the first nanostructure STR1, the second nanostructure STR2, the third nanostructure STR3, and the fourth nanostructure STR4 of the fourth sub-nanopattern SNP4 may be different from one another. For example, the center-to-center distance P41 between the first nanostructure STR1 of the fourth sub-nanopattern SNP4 and the second nanostructure STR2 of the fourth sub-nanopattern SNP4 may be smaller than the center-to-center distance P42 between the second nanostructure STR2 of the fourth sub-nanopattern SNP4 and the third nanostructure STR3 of the fourth sub-nanopattern SNP4, and the center-to-center distance P42 between the second nanostructure STR2 of the fourth sub-nanopattern SNP4 and the third nanostructure STR3 of the fourth sub-nanopattern SNP4 may be smaller than the center-to-center distance P43 between the third nanostructure STR3 of the fourth sub-nanopattern SNP4 and the fourth nanostructure STR4 of the fourth sub-nanopattern SNP4.

[0251] Although not shown in the drawing, the heights of the first nanostructure STR1, the second nanostructure STR2, the third nanostructure STR3, and the fourth nanostructure STR4 of the fourth sub-nanopattern SNP4 may be the same as each other.

[0252] In some embodiments, as one moves from the edge of the display panel 100 toward the center, the size of the nanostructures STR located at the same position in the sub-nanopattern increases, the distance between the nanostructures STR located at the same position decreases, and the center-to-center distance between the nanostructures STR located at the same position may be constant.

[0253] 19, the diameter R41 of the first nanostructure STR1 of the fourth sub-nanopattern SNP4 may be larger than the diameter R51 of the first nanostructure STR1 of the fifth sub-nanopattern SNP5, which in turn may be larger than the diameter R61 of the first nanostructure STR1 of the sixth sub-nanopattern SNP6. The diameter R42 of the second nanostructure STR2 of the fourth sub-nanopattern SNP4 may be larger than the diameter R52 of the second nanostructure STR2 of the fifth sub-nanopattern SNP5, which in turn may be larger than the diameter R62 of the second nanostructure STR2 of the sixth sub-nanopattern SNP6. The diameter R43 of the third nanostructure STR3 of the fourth sub-nanopattern SNP4 may be larger than the diameter R53 of the third nanostructure STR3 of the fifth sub-nanopattern SNP5, and the diameter R53 of the third nanostructure STR3 of the fifth sub-nanopattern SNP5 may be larger than the diameter R63 of the third nanostructure STR3 of the sixth sub-nanopattern SNP6. The diameter R44 of the fourth nanostructure STR4 of the fourth sub-nanopattern SNP4 may be larger than the diameter R54 of the fourth nanostructure STR4 of the fifth sub-nanopattern SNP5, and the diameter R54 of the fourth nanostructure STR4 of the fifth sub-nanopattern SNP5 may be larger than the diameter R64 of the fourth nanostructure STR4 of the sixth sub-nanopattern SNP6.

[0254] The distance D41 between the first nanostructure STR1 of the fourth sub-nanopattern SNP4 and the second nanostructure STR2 of the fourth sub-nanopattern SNP4, the distance D42 between the second nanostructure STR2 of the fourth sub-nanopattern SNP4 and the third nanostructure STR3 of the fourth sub-nanopattern SNP4, and the distance D43 between the third nanostructure STR3 of the fourth sub-nanopattern SNP4 and the fourth nanostructure STR4 of the fourth sub-nanopattern SNP4 may be smaller than the distance D51 between the first nanostructure STR1 of the fifth sub-nanopattern SNP5 and the second nanostructure STR2 of the fifth sub-nanopattern SNP5, the distance D52 between the second nanostructure STR2 of the fifth sub-nanopattern SNP5 and the third nanostructure STR3 of the fifth sub-nanopattern SNP5, and the distance D53 between the third nanostructure STR3 of the fifth sub-nanopattern SNP5 and the fourth nanostructure STR4 of the fifth sub-nanopattern SNP5. The distance D51 between the first nanostructure STR1 of the fifth sub-nanopattern SNP5 and the second nanostructure STR2 of the fifth sub-nanopattern SNP5, the distance D52 between the second nanostructure STR2 of the fifth sub-nanopattern SNP5 and the third nanostructure STR3 of the fifth sub-nanopattern SNP5, and the distance D53 between the third nanostructure STR3 of the fifth sub-nanopattern SNP5 and the fourth nanostructure STR4 of the fifth sub-nanopattern SNP5 may be smaller than the distance D61 between the first nanostructure STR1 of the sixth sub-nanopattern SNP6 and the second nanostructure STR2 of the sixth sub-nanopattern SNP6, the distance D62 between the second nanostructure STR2 of the sixth sub-nanopattern SNP6 and the third nanostructure STR3 of the sixth sub-nanopattern SNP6, and the distance D63 between the third nanostructure STR3 of the sixth sub-nanopattern SNP6 and the fourth nanostructure STR4 of the sixth sub-nanopattern SNP6.

[0255] The center-to-center distance P41 between the first nanostructure STR1 of the fourth sub-nanopattern SNP4 and the second nanostructure STR2 of the fourth sub-nanopattern SNP4, the center-to-center distance P51 between the first nanostructure STR1 of the fifth sub-nanopattern SNP5 and the second nanostructure STR2 of the fifth sub-nanopattern SNP5, and the center-to-center distance P61 between the first nanostructure STR1 of the sixth sub-nanopattern SNP6 and the second nanostructure STR2 of the sixth sub-nanopattern SNP6 may be identical to one another. The center-to-center distance P42 between the second nanostructure STR2 of the fourth sub-nanopattern SNP4 and the third nanostructure STR3 of the fourth sub-nanopattern SNP4, the center-to-center distance P52 between the second nanostructure STR2 of the fifth sub-nanopattern SNP5 and the third nanostructure STR3 of the fifth sub-nanopattern SNP5, and the center-to-center distance P62 between the second nanostructure STR2 of the sixth sub-nanopattern SNP6 and the third nanostructure STR3 of the sixth sub-nanopattern SNP6 may be identical to one another. The center-to-center distance P43 between the third nanostructure STR3 of the fourth sub-nanopattern SNP4 and the fourth nanostructure STR4 of the fourth sub-nanopattern SNP4, the center-to-center distance P53 between the third nanostructure STR3 of the fifth sub-nanopattern SNP5 and the fourth nanostructure STR4 of the fifth sub-nanopattern SNP5, and the center-to-center distance P63 between the third nanostructure STR3 of the sixth sub-nanopattern SNP6 and the fourth nanostructure STR4 of the sixth sub-nanopattern SNP6 may be identical to each other.

[0256] 15, the fourth nanopattern NP4 can diffract light less than the fifth nanopattern NP5 (the angle of light passing through the fourth nanopattern NP4 relative to the frontal direction is smaller than the angle of light passing through the fifth nanopattern NP5 relative to the frontal direction), and the fifth nanopattern NP5 can diffract light less than the sixth nanopattern NP6 (the angle of light passing through the fifth nanopattern NP5 relative to the frontal direction is smaller than the angle of light passing through the sixth nanopattern NP6 relative to the frontal direction). In this way, the nanopatterns NP located between the center and edge of the display panel 100 can adjust the degree of light diffraction by adjusting the size, separation distance, center-to-center distance, etc. of the nanostructures STR.

[0257] In the following, other embodiments of the display device according to the embodiment will be described. In the following embodiments, the same components as those in the above-described embodiment will be assigned the same reference numerals, and overlapping descriptions will be omitted or simplified, with differences being mainly described.

[0258] FIG. 20 is a cross-sectional view illustrating a nanopattern overlapping a first pixel of a display device according to another embodiment.

[0259] Referring to FIG. 20, the display device 10 according to this embodiment differs from the display device 10 according to the embodiment described with reference to FIG. 14 and the like in that it does not include the second nanopattern NP2.

[0260] More specifically, the nanopattern layer NPL may include a first nanopattern NP1 overlapping the first light-emitting region EA1 of the first sub-pixel SP1 of the first pixel PX1 and a third nanopattern NP3 overlapping the third light-emitting region EA3 of the third sub-pixel SP3 of the first pixel PX1. The nanopattern layer NPL may not include a nanopattern NP in an area overlapping the second light-emitting region EA2 of the second sub-pixel SP2 of the first pixel PX1.

[0261] This maintains the path of light emitted from the second light-emitting region EA2 of the second sub-pixel SP2 of the first pixel PX1. That is, the light emitted from the second light-emitting region EA2 of the second sub-pixel SP2 of the first pixel PX1 travels along the front direction, and the travel angle of the light with respect to the front direction may be 0°. Furthermore, since the nanopattern NP is not disposed in the region overlapping with the second light-emitting region EA2 of the second sub-pixel SP2 of the first pixel PX1, the light output efficiency of the display device 10 can be improved.

[0262] Figure 21 is a perspective view showing a nanopattern layer according to another embodiment, and Figure 22 is a perspective view showing a nanopattern layer according to another embodiment.

[0263] 21 and 22, the display device 10 according to this embodiment differs from the display device 10 according to the embodiment described with reference to FIG. 17 and the like in that the shape of the nanostructures is different.

[0264] In one embodiment, the nanostructure STR may be in the shape of a square pillar (e.g., a nano-pin shape) as shown in Figure 21. In another embodiment, the nanostructure STR may be in the shape of a cross pillar (e.g., a nano-polygon shape) as shown in Figure 22.

[0265] FIG. 23 is an exploded perspective view showing a head-mounted display device according to an embodiment.

[0266] Referring to FIG. 23, a head-mounted display device 1000 is formed in the form of glasses or a head-mounted device, and provides an image to a user using a display device 10_1.

[0267] The head-mounted display device 1000 may include a see-through type that provides augmented reality based on actual external objects, and a see-closed type that provides virtual reality to the user using a screen independent of external objects.

[0268] The head-mounted display device 1000 may include a main frame MF that is worn on the user's body, a display device 10_1 that is worn on the main frame MF and displays images, and a cover frame CF that covers the display device 10_1.

[0269] The display device 10_1 may be integrated with a head-mounted display device 1000 that a user can carry and easily wear on or remove from the face or head, or may be formed in a form that is incorporated into the head-mounted display device 1000. The display device 10_1 may be substantially the same as the display device 10 described with reference to FIG. 1 etc.

[0270] The display device 10_1 may include a display panel DP for displaying an image, first and second lens frames OS1, OS2 for refracting the image display light, and first and second multi-channel lenses LS1, LS2 for forming an optical path so that the image display light of the display panel DP is visible to the user.

[0271] The main frame MF is worn on the user's face and head, and can be formed in a shape that conforms to the structure of the user's head and face.

[0272] The display device 10_1, i.e., the display panel DP, first and second lens frames OS1, OS2, and first and second multi-channel lenses LS1, LS2, may be integrally formed with the main frame MF. Alternatively, the display panel DP, first and second lens frames OS1, OS2, and first and second multi-channel lenses LS1, LS2 may be assembled and attached to the main frame MF. To this end, the main frame MF may include a space or structure for accommodating the display panel DP, first and second lens frames OS1, OS2, and first and second multi-channel lenses LS1, LS2. The main frame MF may further include a strap or band-like structure for easy mounting, and may further include a control unit, an image processing unit, a lens housing unit, etc.

[0273] The display panel DP is divided into a front surface DP_FS on which an image is displayed and a rear surface DP_RS located opposite the front surface DP_FS. Image display light is emitted from the front surface DP_FS of the display panel DP. As will be described later, first and second lens frames OS1 and OS2 are disposed on the front surface DP_FS of the display panel DP, and first and second multi-channel lenses LS1 and LS2 are disposed in front of the first and second lens frames OS1 and OS2. Although not shown in the drawings, at least one infrared camera may be further disposed on at least one of the front surface DP_FS and the rear surface DP_RS of the display panel DP. The display panel DP may be substantially the same as the display panel 100 described with reference to FIG. 1, etc.

[0274] The display panel DP may be built into the main frame MF with the first and second lens frames OS1, OS2 and the first and second multi-channel lenses LS1, LS2 attached and fixed thereto, or may be detachably assembled to the main frame MF. The display panel DP may be configured to be opaque, transparent, or translucent depending on the design of the display device 10_1, for example, the manner in which the display device 10_1 is used.

[0275] Each of the first and second lens frames OS1, OS2 may have an area corresponding to the image display surface of the display panel DP and may be formed in a shape corresponding to the image display surface. Furthermore, each of the first and second lens frames OS1, OS2 may have an area and a shape corresponding to the rear surfaces of the first and second multi-channel lenses LS1, LS2. The rear surfaces of each of the first and second lens frames OS1, OS2 are attached to the image display surface of the display panel DP, and the first and second multi-channel lenses LS1, LS2 are attached to the front surfaces of the first and second lens frames OS1, OS2. The first and second lens frames OS1, OS2 refract image display light emitted from the image display surface of the display panel DP at a predetermined angle and provide the refracted light to the first and second multi-channel lenses LS1, LS2, respectively, on the front surface.

[0276] Specifically, the first and second lens frames OS1 and OS2 can refract the image display light emitted from the image display surface of the display panel DP in a front direction outward (or toward the outer periphery) relative to the front direction and provide the light to the first and second multi-channel lenses LS1 and LS2 arranged in front of them, respectively. In particular, each of the first and second lens frames OS1 and OS2 can refract the image display light incident on the rear surface outward (or toward the outer periphery) and provide the light to the rear surfaces of the first and second multi-channel lenses LS1 and LS2, respectively.

[0277] The first and second multi-channel lenses LS1, LS2 form a path for the light emitted through the first and second lens frames OS1, OS2, so that the image display light can be seen by the user's eyes in the front direction.

[0278] Each of the first and second multi-channel lenses LS1 and LS2 provides a plurality of channels (or paths) through which the image display light emitted from the display panel DP passes. The plurality of channels can transmit the image display light emitted from the display panel DP through different paths to provide it to the user. The image display light emitted through the first and second lens frames OS1 and OS2 is incident on each channel, and the images magnified through each channel are focused on the user's eyes.

[0279] The first and second multi-channel lenses LS1 and LS2 are arranged in front of the first and second lens frames OS1 and OS2 according to the positions of the user's left and right eyes, and are housed inside the main frame MF.

[0280] The first and second multi-channel lenses LS1 and LS2 refract and / or reflect the image display light emitted through the first and second lens frames OS1 and OS2 at least once each to form a path to the user's eyes. At least one infrared light source may be further disposed on one side of each of the first and second multi-channel lenses LS1 and LS2 facing the main frame MF or the user's eyes.

[0281] The cover frame CF is disposed on the rear surface DP_RS side of the display panel DP so as to cover the display panel DP and can protect the display panel DP. The cover frame CF is attached to the main frame MF, covering the display panel DP.

[0282] Although not shown in the drawings, the display device 10_1 may further include a control unit that controls the overall operation of the display device 10_1, including the display panel DP. The control unit controls the image display operation of the display panel DP, the audio equipment, etc. Specifically, the control unit performs image processing (e.g., image mapping) according to the image display path and magnification ratio of the first and second lens frames OS1 and OS2 and the first and second multi-channel lenses LS1 and LS2, and controls the mapped image to be displayed on the display panel DP. The control unit may be implemented by a dedicated processor including an embedded processor and / or a general-purpose processor including a central processing unit or application processor, but is not limited thereto.

[0283] Fig. 24 is a perspective view of an augmented reality content providing apparatus according to an embodiment, Fig. 25 is an exploded perspective view of the augmented reality content providing apparatus of Fig. 24 from the rear side, and Fig. 26 is an exploded perspective view of the augmented reality content providing apparatus of Fig. 24 from the front side.

[0284] Referring to Figures 24 to 26, the augmented reality content providing device 1000_1 may include a support frame 1002 supporting at least one transparent lens 1001, at least one image display module 1010, a surrounding environment detection unit 1040, and a control module 1020.

[0285] The support frame 1002 is formed in the form of glasses including a frame and temples that support the edge of at least one transparent lens 1001. The form of the support frame 1002 is not limited to glasses, and it can also be formed in the form of goggles or head-mounted type including the transparent lens 1001.

[0286] The transparent lens 1001 may be formed as an integrated left and right lens, or may be composed of first and second separated left and right lenses. The transparent lens 1001, configured as an integrated left and right lens or separated into the first and second transparent lenses, is formed of glass or plastic and is transparent or translucent. This allows a user to view a real image through the transparent lens 1001, configured as an integrated left and right lens or separated into the first and second transparent lenses. Here, the transparent lens 1001, i.e., the integrated lens or the first and second transparent lenses, may have refractive power taking into account the user's eyesight.

[0287] The transparent lens 1001 may further include at least one reflecting member that reflects an augmented reality content image provided from at least one image display module 1010 toward the transparent lens 1001 or a user's eyes, and an optical member that adjusts focus and size. The at least one reflecting member may be integrated into the transparent lens 1001 and may be formed of a plurality of refractive lenses or a plurality of prisms having a predetermined curvature.

[0288] The at least one image display module 1010 may include a micro LED display (micro-LED), a nano LED display (nano-LED), an organic light emitting display (OLED), an inorganic light emitting display (inorganic EL), a quantum dot light emitting display (QED), a cathode ray tube display (CRT), a liquid crystal display (LCD), etc. The image display module 1010 may substantially include the display device 10 described with reference to FIG. 1 etc.

[0289] The surrounding environment detection unit 1040 is incorporated into or integrally formed with the support frame 1002 and detects the distance (or depth) to an object in front of the support frame 1002, illuminance, the movement direction, movement distance, tilt, etc. of the support frame 1002. To this end, the surrounding environment detection unit 1040 includes a depth sensor 1041 such as an infrared sensor or a LiDAR sensor, and an image sensor 1050 such as a camera. The surrounding environment detection unit 1040 may further include at least one motion sensor selected from an illuminance sensor, a human body detection sensor, a gyro sensor, a tilt sensor, and an acceleration sensor. The surrounding environment detection unit 1040 may also include first and second biometric sensors 1031 and 1032 that detect movement information of the user's eyes or pupils.

[0290] The surrounding environment detection unit 1040 transmits sensing signals generated by the depth sensor 1041 and at least one motion sensor to the control module 1020 in real time. The image sensor 1050 transmits image data generated in real time in units of at least one frame to the control module 1020. The first and second biosensors 1031 and 1032 of the surrounding environment detection unit 1040 transmit pupil sensing signals detected by the first and second biosensors 1031 and 1032 to the control module 1020.

[0291] The control module 1020 may be incorporated into at least one side of the support frame 1002 together with the at least one image display module 1010, or may be integrally formed with the support frame 1002. The control module 1020 supplies augmented reality content data to the at least one image display module 1010 so that the at least one image display module 1010 displays augmented reality content, for example, an augmented reality content image. At the same time, the control module 1020 may receive a sensing signal, image data, and a pupil detection signal from the surrounding environment detection unit 1040 in real time.

[0292] Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art will understand that the present invention can be embodied in other specific forms without changing the technical idea or essential features of the present invention. Therefore, it should be understood that the above embodiments are illustrative in all respects and are not limiting. [Explanation of symbols]

[0293] 10 Display device 100 Display Panel 800 Optical Module NPL Nanopatterned Layer NP nanopatterns SNP1 to SNP6 1st to 6th sub-nanopatterns STR nanostructure

Claims

1. semiconductor substrate; a plurality of light emitting devices disposed on the semiconductor substrate; and a plurality of patterns disposed on the plurality of light emitting elements and overlapping the plurality of light emitting elements; The plurality of light emitting devices include a first light emitting device disposed at a center thereof and a second light emitting device disposed on one side of the first light emitting device, the plurality of patterns include a first pattern overlapping the first light-emitting element and a second pattern overlapping the second light-emitting element; the first pattern includes a first structure and a second structure; the second pattern includes a third structure and a fourth structure; the first structure and the second structure have the same width; The third structure and the fourth structure have different widths.

2. the third structure is disposed adjacent to the center relative to the fourth structure; The display device of claim 1 , wherein the width of the third structure is smaller than the width of the fourth structure.

3. the second pattern further includes a fifth structure and a sixth structure; the third structure, the fourth structure, the fifth structure, and the sixth structure are arranged adjacent to the center in this order; The display device according to claim 1 , wherein the widths of the third structure, the fourth structure, the fifth structure, and the sixth structure decrease in this order.

4. the width of the third structure is 94 nm to 134 nm; the width of the fourth structure is 104 nm to 144 nm; the width of the fifth structure is 114 nm to 154 nm; The display device according to claim 3 , wherein the width of the sixth structure is 150 nm to 190 nm.

5. 5. The display device according to claim 4, wherein the traveling direction of the light that has passed through the second pattern is inclined by 25 to 35 degrees from the thickness direction of the semiconductor substrate.

6. the plurality of light emitting elements include a third light emitting element disposed between the first light emitting element and the second light emitting element, the plurality of patterns includes a third pattern overlapping the third light-emitting element, the third pattern includes a seventh structure and an eighth structure; The display device according to claim 1 , wherein the seventh structure and the eighth structure have different widths.

7. the seventh structure is disposed adjacent to the center relative to the eighth structure, The display device according to claim 6 , wherein the width of the seventh structure is smaller than the width of the eighth structure.

8. the width of the third structure is smaller than the width of the seventh structure; The display device according to claim 6 , wherein the width of the fourth structure is smaller than the width of the eighth structure.

9. The display device according to claim 8 , wherein the distance between the third structure and the fourth structure is greater than the distance between the seventh structure and the eighth structure.

10. the plurality of light emitting elements include a fourth light emitting element disposed on the other side of the first light emitting element, the plurality of patterns includes a fourth pattern overlapping the fourth light-emitting element, the fourth pattern includes a ninth structure and a tenth structure; The display device of claim 1 , wherein the width of the ninth structure is the same as the width of the third structure, and the width of the tenth structure is the same as the width of the fourth structure.

11. The display device of claim 10 , wherein the second pattern and the fourth pattern are bilaterally symmetrical with respect to the first pattern.

12. The display device according to claim 1 , wherein the plurality of light-emitting elements and the plurality of patterns are respectively arranged on a straight line.

13. The display device of claim 1 , wherein the first to fourth structures include silicon or metal.

14. The display device of claim 1 , wherein the first to fourth structures are in the shape of a nanopin, a nanorod, or a nanopolygon.

15. semiconductor substrate; a plurality of light emitting devices disposed on the semiconductor substrate; and a pattern layer including a plurality of patterns overlapping the plurality of light emitting elements and disposed on the plurality of light emitting elements; The plurality of light emitting devices include a first light emitting device disposed at a center thereof and a second light emitting device disposed on one side of the first light emitting device, the pattern layer does not include the pattern in a region overlapping with the first light emitting element, and includes a first pattern overlapping with the second light emitting element; the first pattern includes a first structure and a second structure; The display device, wherein the first structures and the second structures have different widths.

16. the first structure is disposed adjacent to the center relative to the second structure; The display device of claim 15 , wherein the width of the first structures is smaller than the width of the second structures.

17. the first pattern further includes a third structure and a fourth structure; the first structure, the second structure, the third structure, and the fourth structure are arranged adjacent to the center in this order; The display device of claim 15 , wherein the widths of the first structure, the second structure, the third structure, and the fourth structure decrease in this order.

18. the plurality of light emitting elements include a third light emitting element disposed between the first light emitting element and the second light emitting element, the plurality of patterns includes a second pattern overlapping the third light-emitting element, the second pattern includes a fifth structure and a sixth structure; The display device of claim 15 , wherein the fifth structures and the sixth structures have different widths.

19. the plurality of light emitting elements include a fourth light emitting element disposed on the other side of the first light emitting element, the plurality of patterns includes a third pattern overlapping the fourth light-emitting element, the third pattern includes a seventh structure and an eighth structure; The display device of claim 15 , wherein the width of the seventh structure is the same as the width of the first structure, and the width of the eighth structure is the same as the width of the second structure.

20. The display device according to claim 15 , wherein the plurality of light-emitting elements and the plurality of patterns are respectively arranged on a straight line.

Images