Semiconductor device

Abstract

FIG. 1 is a cross-sectional view illustrating a semiconductor device according to a first embodiment; SOLUTION: A semiconductor device according to an embodiment includes a wiring substrate having a first bonding pad and a second bonding pad adjacent to the first bonding pad and arranged with the first bonding pad in a first direction along a surface direction of the first bonding pad, a semiconductor element provided on the wiring substrate, and a connection wiring connecting the first bonding pad and the semiconductor element and including a first bonding wire and a second bonding wire arranged in the first direction. In the first bonding pad, a region that is not connected by the connection wiring is regionally divided by a protrusion provided on a surface of the first bonding pad, regionally divided in a direction non-perpendicular to the first direction, or physically partially divided.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] In semiconductor packages, semiconductor elements mounted on a wiring board are connected by bonding wires. For example, to strengthen the power supply system, multiple bonding wires may be connected from one bonding pad to different bonding pads on the semiconductor element. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent Publication No. 2022 / 0328453 [Patent Document 2] U.S. Patent Publication No. 2023 / 0378018 Summary of the Invention [Problem to be solved by the invention]

[0004] Embodiments of the present invention provide semiconductor devices with improved durability or reliability. [Means for solving the problem]

[0005] A semiconductor device according to an embodiment includes a wiring substrate having a first bonding pad and a second bonding pad adjacent to the first bonding pad and aligned with the first bonding pad in a first direction along the surface direction of the first bonding pad, a semiconductor element provided on the wiring substrate, and connection wiring connecting the first bonding pad to the semiconductor element and including a first bonding wire and a second bonding wire aligned in the first direction. The first bonding pad is divided into regions by protrusions provided on the surface of the first bonding pad in a region not connected by the connection wiring, and is divided into regions in a direction non-perpendicular to the first direction, or is physically divided into parts. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a schematic diagram of a semiconductor device according to an embodiment; [Figure 2] 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment; [Figure 3] FIG. 2 is a schematic view of the vicinity of a first bonding pad of the semiconductor device according to the embodiment. [Figure 4] FIG. 10 is a schematic diagram of a first bonding pad of a semiconductor device according to a reference embodiment. [Figure 5] FIG. 2 is a schematic view of a first bonding pad of the semiconductor device according to the embodiment. [Figure 6] FIG. 2 is a schematic view of a first bonding pad of the semiconductor device according to the embodiment. [Figure 7] FIG. 2 is a schematic view of a first bonding pad of the semiconductor device according to the embodiment. [Figure 8] FIG. 2 is a schematic view of a first bonding pad of the semiconductor device according to the embodiment. [Figure 9] FIG. 2 is a schematic view of a first bonding pad of the semiconductor device according to the embodiment. [Figure 10] FIG. 2 is a schematic view of a first bonding pad of the semiconductor device according to the embodiment. [Figure 11] FIG. 2 is a schematic view of a first bonding pad of the semiconductor device according to the embodiment. [Figure 12] FIG. 2 is a schematic view of a first bonding pad of the semiconductor device according to the embodiment. [Figure 13] FIG. 2 is a schematic view of a first bonding pad of the semiconductor device according to the embodiment. [Figure 14] 1 is a schematic diagram of a semiconductor device according to an embodiment; [Figure 15] 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment; [Figure 16] 3 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings.

[0008] In this specification, some elements are given multiple examples of expressions. Note that these examples are merely illustrative and do not deny that the elements may be expressed using other expressions. Furthermore, elements that do not have multiple expressions may also be expressed using other expressions.

[0009] The drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Also, the drawings may include parts where the relationship and ratio of dimensions differ from each other. Also, some reference numerals are omitted in the drawings.

[0010] (First embodiment) The first embodiment relates to a semiconductor device. Fig. 1 shows a schematic diagram of a semiconductor device 100. Fig. 2 shows an AA cross-sectional view of the semiconductor device 100. The semiconductor device 100 of the embodiment is a semiconductor package equipped with a semiconductor element including one or more devices selected from the group consisting of an arithmetic unit, a control unit, and a memory unit. Note that the X direction, Y direction, and Z direction preferably intersect each other and are perpendicular to each other.

[0011] The semiconductor device 100 includes a wiring substrate 1, solder balls 7, a sealing material 8, a first semiconductor element 10, a second semiconductor element 21, a first insulating layer 40, and a second insulating layer 41.

[0012] The wiring board 1 is a support substrate for the first semiconductor element 10 and the second semiconductor element 21. More specifically, the wiring board 1 is a multi-layer wiring board. The first semiconductor element 10 and the second semiconductor element 21 are provided on a first surface side of the wiring board 1. A second surface side of the wiring board 1 opposite to the first surface is provided with hemispherical electrodes such as solder balls 7 for connecting the semiconductor device 100 to the outside.

[0013] The wiring board 1 is electrically connected to the first semiconductor element 10 and the second semiconductor element 21 via bonding wires. The wiring board 1 has terminals, such as first bonding pads 2A, that connect to the first semiconductor element 10. The terminals include power supply terminals including ground terminals and signal terminals including IO terminals, and each terminal is provided on the wiring board 1. For example, the signal terminals are terminals for inputting and outputting data to and from the first semiconductor element 10 and terminals for inputting control signals that control the operation of the first semiconductor element 10.

[0014] The wiring board 1 shown in the schematic diagram of Figure 1 has a first bonding pad 2A, a second bonding pad 3A, a fourth bonding pad 3B, a fifth bonding pad 3C, a sixth bonding pad 3D, a seventh bonding pad 3E, an eighth bonding pad 3F, a ninth bonding pad 3G, a tenth bonding pad 3H, an eleventh bonding pad 2B, a twelfth bonding pad 3I, a thirteenth bonding pad 3J, a fourteenth bonding pad 3K, a fifteenth bonding pad 3L, a sixteenth bonding pad 3M, a seventeenth bonding pad 3N, an eighteenth bonding pad 3O and a nineteenth bonding pad 3P.

[0015] The first semiconductor element 10 includes, for example, a first semiconductor chip 10A, a second semiconductor chip 10B, a third semiconductor chip 10C, a fourth semiconductor chip 10D, a fifth semiconductor chip 10E, a sixth semiconductor chip 10F, a seventh semiconductor chip 10G, and an eighth semiconductor chip 10H. The first semiconductor chip 10A, the second semiconductor chip 10B, the third semiconductor chip 10C, the fourth semiconductor chip 10D, the fifth semiconductor chip 10E, the sixth semiconductor chip 10F, the seventh semiconductor chip 10G, and the eighth semiconductor chip 10H are stacked in this order in the Z direction.

[0016] The four layers of semiconductor chips (first semiconductor chip 10A, second semiconductor chip 10B, third semiconductor chip 10C, and fourth semiconductor chip 10D) are stacked in the Z direction, shifted in the Y direction. The four layers of semiconductor chips (fifth semiconductor chip 10E, sixth semiconductor chip 10F, seventh semiconductor chip 10G, and eighth semiconductor chip 10H) are arranged in an orientation rotated 180 degrees from the four layers of semiconductor chips (first semiconductor chip 10A, second semiconductor chip 10B, third semiconductor chip 10C, and fourth semiconductor chip 10D), and are stacked in the Z direction, shifted in the direction opposite to the Y direction.

[0017] The first semiconductor chip 10A, the second semiconductor chip 10B, the third semiconductor chip 10C, the fourth semiconductor chip 10D, the fifth semiconductor chip 10E, the sixth semiconductor chip 10F, the seventh semiconductor chip 10G and the eighth semiconductor chip 10H are, for example, bare chips, and each have a plurality of terminals 12A, a plurality of terminals 12B, a plurality of terminals 12C, a plurality of terminals 12D, a plurality of terminals 12E, a plurality of terminals 12F, a plurality of terminals 12G and a plurality of terminals 12H.

[0018] The first semiconductor element 10 has, for example, multiple semiconductor memory chips. The semiconductor memory chips are semiconductor chips that read and write data. The semiconductor memory chips are non-volatile memory chips or volatile memory chips. Examples of non-volatile memory chips that can be used include NAND memory chips, phase change memory chips, resistance change memory chips, ferroelectric memory chips, and magnetic memory chips. Examples of volatile memory chips that can be used include DRAM (Dynamic Random Access Memory). It is preferable that the semiconductor memory chips be semiconductor chips with the same circuit and structure except for individual differences. If the first bonding pad 2A is a power supply terminal and multiple bonding wires are provided from the first bonding pad 2A, the power supply of the first semiconductor element 10 is strengthened, which is suitable for high-speed memory operation.

[0019] The first bonding pad 2A, the second bonding pad 3A, the fourth bonding pad 3B, the fifth bonding pad 3C, the sixth bonding pad 3D, the seventh bonding pad 3E, the eighth bonding pad 3F, the ninth bonding pad 3G, and the tenth bonding pad 3H are each connected to a plurality of terminals 12A of the first semiconductor chip 10A.

[0020] The first semiconductor chip 10A and the second semiconductor chip 10B are connected to each other by connecting the plurality of terminals 12A of the first semiconductor chip 10A and the plurality of terminals 12B of the second semiconductor chip 10B with bonding wires.

[0021] The second semiconductor chip 10B and the third semiconductor chip 10C are connected to each other by bonding wires connecting the plurality of terminals 12B of the second semiconductor chip 10B and the plurality of terminals 12C of the third semiconductor chip 10C.

[0022] The third semiconductor chip 10C and the fourth semiconductor chip 10D are connected to each other by bonding wires connecting the plurality of terminals 12C of the third semiconductor chip 10C and the plurality of terminals 12D of the fourth semiconductor chip 10D.

[0023] The 12th bonding pad 3I, the 13th bonding pad 3J, the 14th bonding pad 3K, the 15th bonding pad 3L, the 16th bonding pad 3M, the 17th bonding pad 3N, the 18th bonding pad 3O and the 19th bonding pad 3P are each connected to a plurality of terminals 12E of the fifth semiconductor chip 10E.

[0024] The fifth semiconductor chip 10E and the sixth semiconductor chip 10F are connected to each other by bonding wires connecting the plurality of terminals 12E of the fifth semiconductor chip 10E and the plurality of terminals 12F of the sixth semiconductor chip 10F.

[0025] The sixth semiconductor chip 10F and the seventh semiconductor chip 10G are connected to each other by bonding wires connecting the plurality of terminals 12F of the sixth semiconductor chip 10F to the plurality of terminals 12G of the seventh semiconductor chip 10G.

[0026] The seventh semiconductor chip 10G and the eighth semiconductor chip 10H are connected to each other by bonding wires connecting the plurality of terminals 12G of the seventh semiconductor chip 10G to the plurality of terminals 12H of the eighth semiconductor chip 10H.

[0027] The bonding pad group including the first bonding pad 2A and the terminal group including the terminal 12A are made of a metal film containing at least one metal selected from the group consisting of Cu, Ni, W, Au, Ag, Pd, Sn, Bi, Zn, Cr, Al, Ti, Ni-P, and Ni-B. The surface layers of the bonding pad group including the first bonding pad 2A and the terminal group including the terminal 12A preferably contain at least one metal selected from the group consisting of Au, Pd, Ni, and Cu. This surface layer is connected to the connecting wiring. More specifically, the bonding pad group including the first bonding pad 2A and the terminal group including the terminal 12A are formed by plating Ni and Au on a Cu layer. The layer configuration of the bonding pad group including the first bonding pad 2A and the terminal group including the terminal 12A is determined by selecting a suitable material depending on the material of the bonding wire.

[0028] The first bonding pad 2A provided on the wiring board 1 is a power supply terminal or a signal terminal, and is preferably a power supply terminal. A connection wiring including a first bonding wire 4A and a second bonding wire 4B, and optionally a third bonding wire 4C, connects the first bonding pad 2A to the first semiconductor element 10. A plurality of bonding wires are provided on the first bonding pad 2A. The number of bonding wires connected to the first bonding pad 2A may be two or four or more. The connection wiring including the first bonding wire 4A and the second bonding wire 4B, and optionally a third bonding wire 4C, is, for example, a power supply wiring or a signal wiring, and is preferably a power supply wiring.

[0029] The first bonding pad 2A is connected to the first semiconductor element 10 via a first bonding wire 4A, a second bonding wire 4B, and a third bonding wire 4C. On the first semiconductor element 10, there is no connection between any two bonding wires selected from the group consisting of the first bonding wire 4A, the second bonding wire 4B, and the third bonding wire 4C.

[0030] The first bonding wire 4A, the second bonding wire 4B, and the third bonding wire 4C are similar wires.

[0031] The first bonding wire 4A is composed of a bump (ball) 4AA provided on the first bonding pad 2A, a wire 4AB, a bump 4AC provided on terminal 12A of the first semiconductor chip 10A, a wire 4AD, a bump 4AE provided on terminal 12B of the second semiconductor chip 10B, a wire 4AF, a bump 4AG provided on terminal 12C of the third semiconductor chip 10C, a wire 4AH, and a bump 4AI provided on terminal 12D of the fourth semiconductor chip 10D.

[0032] The first bonding wire 4A contains one or more selected from the group consisting of Au, Ag, Cu, and Pd. The wire portion of the first bonding wire 4A is preferably an Au wire, an Ag wire, a Cu wire, or a Pd-coated Cu wire.

[0033] The wire 4AB connects the bump 4AA to the bump 4AC, and the wire 4AB connects the first bonding pad 2A to the first semiconductor chip 10A.

[0034] Wires 4AD connect bumps 4AC and 4AE, and wires 4AD connect first semiconductor chip 10A and second semiconductor chip 10B.

[0035] Wires 4AF connect the bumps 4AE and 4AG, and wires 4AF connect the second semiconductor chip 10B and the third semiconductor chip 10C.

[0036] Wires 4AH connect bumps 4AG and 4AI, and wires 4AF connect third semiconductor chip 10C and fourth semiconductor chip 10D.

[0037] The bumps 4AC, 4AE, 4AG, and 4AA on the first semiconductor element 10 side can be omitted. The bump 4AA on the first bonding pad 2A can be omitted. In other words, the shape of the connection portion of the bonding wire connecting the first semiconductor element 10 and the wiring board 1 can be not only a ball bond shape but also a wedge bond shape.

[0038] It is possible to omit the bump 4AA on the first bonding pad 2A and the bumps 4AC, 4AE, 4AG, and 4AA on the first semiconductor element 10 side. In other words, the shape of the connection portion of the bonding wire connecting the first semiconductor element 10 and the wiring board 1 can be not only a ball bond shape but also a wedge bond shape.

[0039] A convex portion is provided on the first bonding pad 2A. A first bump 5A, a second bump 5B, and a third bump 5C are provided on the first bonding pad 2A as convex portions. In the schematic diagram of Fig. 1, a first bonding wire 4A, a second bonding wire 4B, and a third bonding wire 4C are located between the first bump 5A, the second bump 5B, and the third bump 5C and the first semiconductor element 10.

[0040] The first bump 5A, the second bump 5B, and the third bump 5C, which are convex portions, contain one or more metals selected from the group consisting of Au, Ag, Cu, Pd, and Sn, or resin. The convex portions are, for example, wiring materials used when forming bonding wires. The convex portions are, for example, solder. Preferred resins for the convex portions include acrylic resins, phenolic resins, and epoxy resins. These resins preferably have high adhesion to both the molding resin and the bonding pad. The first bump 5A, the second bump 5B, and the third bump 5C, which are convex portions, may contain elements contained in the surface of the first bonding pad 2A. The convex portions do not necessarily have to contain elements contained in the surface of the first bonding pad 2A.

[0041] The second bonding wire 4B is connected to a terminal of the first semiconductor element 10 that is different from the terminal of the first semiconductor element 10 to which the first bonding wire 4A is connected. In the schematic diagram of Fig. 2, the second bonding wire 4B is connected to a terminal that is shifted in the -X direction from the terminal of the first semiconductor element 10 to which the first bonding wire 4A is connected.

[0042] The third bonding wire 4C is connected to a terminal of the first semiconductor element 10 that is different from the terminal of the first semiconductor element 10 to which the first bonding wire 4A is connected and the terminal of the first semiconductor element 10 to which the second bonding wire 4B is connected. In the schematic diagram of Fig. 2, the third bonding wire 4C is connected to a terminal that is shifted in the -X direction from the terminal of the first semiconductor element 10 to which the first bonding wire 4A is connected and that is shifted in the +X direction from the terminal of the first semiconductor element 10 to which the second bonding wire 4B is connected.

[0043] The second bonding pad 3A provided on the wiring substrate 1 is adjacent to the first bonding pad 2A. The second bonding pad 3A is a power terminal or a signal terminal. The first bonding pad 2A and the second bonding pad 3A are aligned in a first direction along the surface of the first bonding pad 2A. The first direction preferably includes the X direction and approximately the X direction. The first direction is the direction of a line segment connecting the center of the first bonding pad 2A and the center of the second bonding pad 3A. The second bonding pad 3A is connected to the first semiconductor element 10 via a fourth bonding wire 6A. The relationship between the first bonding pad 2A, the second bonding pad 3A, and the fourth bonding wire 6A corresponds to the relationship between the eleventh bonding pad 2B, the twelfth bonding pad 3I, and the fifteenth bonding wire 6I provided on the opposite side of the wiring substrate 1, respectively.

[0044] A fourth bonding pad 3B provided on the wiring board 1 is adjacent to the second bonding pad 3A. The fourth bonding pad 3B is a power terminal or a signal terminal. The second bonding pad 3A and the fourth bonding pad 3B are aligned in the first direction. The fourth bonding pad 3B is connected to the first semiconductor element 10 via a fifth bonding wire 6B. The relationship between the second bonding pad 3A, the fourth bonding pad 3B, and the fifth bonding wire 6B corresponds to the relationship between the twelfth bonding pad 3I, the thirteenth bonding pad 3J, and the sixteenth bonding wire 6J provided on the opposite side of the wiring board 1, respectively.

[0045] A fifth bonding pad 3C provided on the wiring board 1 is adjacent to the fourth bonding pad 3B. The fifth bonding pad 3C is a power terminal or a signal terminal. The fourth bonding pad 3B and the fifth bonding pad 3C are aligned in the first direction. The fifth bonding pad 3C is connected to the first semiconductor element 10 via a sixth bonding wire 6C. The relationship between the fourth bonding pad 3B, the fifth bonding pad 3C, and the sixth bonding wire 6C corresponds to the relationship between the thirteenth bonding pad 3J, the fourteenth bonding pad 3K, and the seventeenth bonding wire 6K provided on the opposite side of the wiring board 1, respectively.

[0046] The sixth bonding pad 3D provided on the wiring substrate 1 is adjacent to the first bonding pad 2A. The first bonding pad 2A is located between the sixth bonding pad 3D and the second bonding pad 3A. The sixth bonding pad 3D is located on the opposite side of the first bonding pad 2A from the second bonding pad 3A side. The sixth bonding pad 3D is a power terminal or a signal terminal. The first bonding pad 2A and the sixth bonding pad 3D are aligned in the first direction. The sixth bonding pad 3D is connected to the first semiconductor element 10 via a seventh bonding wire 6D. The relationship between the first bonding pad 2A, the sixth bonding pad 3D, and the seventh bonding wire 6D corresponds to the relationship between the eleventh bonding pad 2B, the fifteenth bonding pad 3L, and the eighteenth bonding wire 6L provided on the opposite side of the wiring substrate 1, respectively.

[0047] The seventh bonding pad 3E provided on the wiring board 1 is adjacent to the sixth bonding pad 3D. The seventh bonding pad 3E is a power terminal or a signal terminal. The sixth bonding pad 3D and the seventh bonding pad 3E are aligned in the first direction. The seventh bonding pad 3E is connected to the first semiconductor element 10 via an eighth bonding wire 6E. The relationship between the sixth bonding pad 3D, the seventh bonding pad 3E, and the eighth bonding wire 6E corresponds to the relationship between the fifteenth bonding pad 3L, the sixteenth bonding pad 3M, and the nineteenth bonding wire 6M provided on the opposite side of the wiring board 1, respectively.

[0048] An eighth bonding pad 3F provided on the wiring board 1 is adjacent to the seventh bonding pad 3E. The eighth bonding pad 3F is a power terminal or a signal terminal. The seventh bonding pad 3E and the eighth bonding pad 3F are aligned in the first direction. The eighth bonding pad 3F is connected to the first semiconductor element 10 via a ninth bonding wire 6F. The relationship between the seventh bonding pad 3E, the eighth bonding pad 3F, and the ninth bonding wire 6F corresponds to the relationship between the sixteenth bonding pad 3M, the seventeenth bonding pad 3N, and the twentieth bonding wire 6N provided on the opposite side of the wiring board 1, respectively.

[0049] The ninth bonding pad 3G provided on the wiring board 1 is adjacent to the eighth bonding pad 3F. The ninth bonding pad 3G is a power terminal or a signal terminal. The eighth bonding pad 3F and the ninth bonding pad 3G are aligned in the first direction. The ninth bonding pad 3G is connected to the first semiconductor element 10 via a tenth bonding wire 6G. The relationship between the eighth bonding pad 3F, the ninth bonding pad 3G, and the tenth bonding wire 6G corresponds to the relationship between the seventeenth bonding pad 3N, the eighteenth bonding pad 3O, and the twenty-first bonding wire 6O provided on the opposite side of the wiring board 1, respectively.

[0050] The tenth bonding pad 3H provided on the wiring substrate 1 is adjacent to the ninth bonding pad 3G. The tenth bonding pad 3H is a power terminal or a signal terminal. The ninth bonding pad 3G and the tenth bonding pad 3H are aligned in the first direction. The tenth bonding pad 3H is connected to the first semiconductor element 10 via an eleventh bonding wire 6H. The relationship between the ninth bonding pad 3G, the tenth bonding pad 3H, and the eleventh bonding wire 6H corresponds to the relationship between the eighteenth bonding pad 3O, the nineteenth bonding pad 3P, and the twenty-second bonding wire 6P provided on the opposite side of the wiring substrate 1, respectively.

[0051] The eleventh bonding pad 2B provided on the wiring substrate 1 is a power supply terminal or a signal terminal, and is preferably a power supply terminal. The eleventh bonding pad 2B is located on the opposite side of the first semiconductor element 10 from the first bonding pad 2A, i.e., on the opposite side of the first semiconductor element 10 in the Y direction. A connection wiring including a twelfth bonding wire 4D and a thirteenth bonding wire 4E, and optionally a fourteenth bonding wire 4F, connects the eleventh bonding pad 2B to the first semiconductor element 10. Multiple bonding wires are provided on the eleventh bonding pad 2B. The number of bonding wires connected to the eleventh bonding pad 2B may be two or four or more. The connection wiring including the twelfth bonding wire 4D and a thirteenth bonding wire 4E, and optionally a fourteenth bonding wire 4F, is, for example, a power supply wiring or a signal wiring, and is preferably a power supply wiring.

[0052] The eleventh bonding pad 2B is connected to the first semiconductor element 10 via the twelfth bonding wire 4D, the thirteenth bonding wire 4E, and the fourteenth bonding wire 4F. On the first semiconductor element 10, there is no connection between any two bonding wires selected from the group consisting of the twelfth bonding wire 4D, the thirteenth bonding wire 4E, and the fourteenth bonding wire 4F.

[0053] The 12th bonding wire 4D is composed of a bump (ball) 4DA provided on the 11th bonding pad 2B, a wire 4DB, a bump 4DC provided on terminal 12E of the fifth semiconductor chip 10E, a wire 4DD, a bump 4DE provided on terminal 12F of the sixth semiconductor chip 10F, a wire 4DF, a bump 4DG provided on terminal 12G of the seventh semiconductor chip 10G, a wire 4DH, and a bump 4DI provided on terminal 12H of the eighth semiconductor chip 10H.

[0054] The twelfth bonding wire 4D contains one or more selected from the group consisting of Au, Ag, Cu, and Pd. The wire portion of the twelfth bonding wire 4D is preferably an Au wire, an Ag wire, a Cu wire, or a Pd-coated Cu wire.

[0055] The wire 4DB connects the bump 4DA and the bump 4DC, and the wire 4DB connects the eleventh bonding pad 2B and the fifth semiconductor chip 10E.

[0056] Wires 4DD connect bumps 4DC and 4DE, and wires 4DD connect fifth semiconductor chip 10E and sixth semiconductor chip 10F.

[0057] The wires 4DF connect the bumps 4DE and 4DG, and the wires 4DF connect the sixth semiconductor chip 10F and the seventh semiconductor chip 10G.

[0058] Wires 4DH connect the bumps 4DG and 4DI, and wires 4DF connect the seventh semiconductor chip 10G and the eighth semiconductor chip 10H.

[0059] A protrusion is provided on the eleventh bonding pad 2B. A fourth bump 5D, a fifth bump 5E, and a sixth bump 5F are provided on the eleventh bonding pad 2B as protrusions. In the schematic diagram of FIG. 1, a twelfth bonding wire 4D, a thirteenth bonding wire 4E, and a fourteenth bonding wire 4F are located between the fourth bump 5D, the fifth bump 5E, and the sixth bump 5F and the first semiconductor element 10.

[0060] The fourth bump 5D, the fifth bump 5E, and the sixth bump 5F, which are convex portions, contain one or more metals selected from the group consisting of Au, Ag, Cu, Pd, and Sn, or resin. The convex portions are, for example, wiring materials used when forming bonding wires. The convex portions are, for example, solder. Preferred resins for the convex portions are, for example, acrylic resins, phenolic resins, and epoxy resins. The convex portions may contain elements contained in the surface of the eleventh bonding pad 2B. The convex portions do not have to contain elements contained in the surface of the eleventh bonding pad 2B.

[0061] The 13th bonding wire 4E is connected to a terminal of the first semiconductor element 10 that is different from the terminal of the first semiconductor element 10 to which the 12th bonding wire 4D is connected. In the schematic diagram of Fig. 2, the 13th bonding wire 4E is connected to a terminal that is shifted in the +X direction from the terminal of the first semiconductor element 10 to which the 12th bonding wire 4D is connected.

[0062] The fourteenth bonding wire 4F is connected to a terminal of the first semiconductor element 10 that is different from the terminal of the first semiconductor element 10 connected to the twelfth bonding wire 4D and the terminal of the first semiconductor element 10 connected to the thirteenth bonding wire 4E. In the schematic diagram of Fig. 2, the fourteenth bonding wire 4F is connected to a terminal that is shifted in the +X direction from the terminal of the first semiconductor element 10 connected to the twelfth bonding wire 4D and shifted in the -X direction from the terminal of the first semiconductor element 10 connected to the thirteenth bonding wire 4E.

[0063] The solder balls 7 are terminals that electrically connect the semiconductor device 100 to the outside.

[0064] The encapsulant 8 encapsulates the first semiconductor element 10, the first bonding pad 2A, the second bonding pad 3A, the bonding wires, and the like. The encapsulant 8 is, for example, a mold resin. As the mold resin, for example, a naphthalene-type epoxy resin or a dicyclopentadiene-type epoxy resin is preferable. Benzophenone-type epoxy resin is also preferable because it tends to be fast-curing. These epoxy resins may be used alone or in combination of two or more. The encapsulant 8 may also contain a filler such as silica or alumina.

[0065] The second semiconductor element 21 is, for example, a semiconductor chip that controls reading, writing, erasing, etc. of the first semiconductor element 10. The second semiconductor element 21 is surrounded by a first insulating layer 40 and covered with a second insulating layer 41 provided between the first semiconductor element 10 and the second semiconductor element 21. The schematic diagram of Fig. 2 shows an example of the position where the second semiconductor element 21 is arranged.

[0066] The second semiconductor element 21 is connected to the first semiconductor element 10 via the wiring board 1. The second semiconductor element 21 is connected, for example, by a bonding wire. A terminal 22 on the second semiconductor element 21 and a terminal 27 on the wiring board 1 are connected by a wire 26 via a bump 23 and a bump 28, respectively. A terminal 24 on the second semiconductor element 21 and a terminal 30 on the wiring board are connected by a wire 29 via a bump 25 and a bump 31, respectively. The first bonding pad 2A and its connection form may be adopted for the power supply system of the second semiconductor element 21, etc., to strengthen the power supply, etc.

[0067] The bumps 23 and 25 may be omitted. The bumps 28 and 31 may be omitted.

[0068] Next, the first bonding pad 2A and its bonding wire will be described with reference to the schematic diagram of the vicinity of the first bonding pad 2A of the semiconductor device 100 in Fig. 3. In the following description, reference will also be made to Fig. 4, which is a schematic diagram of the first bonding pad of a semiconductor device as a reference embodiment. The following description will focus on the first bonding pad 2A, but the description of the first bonding pad 2A and its connecting wire also corresponds to the description of the eleventh bonding pad 2B and its connecting wire.

[0069] 3 shows an enlarged view of the first bonding pad 2A and the second bonding pad 3A. The first bonding pad 2A and the second bonding pad 3A may extend straight in the second direction, or may extend at an angle different from the second direction. For simplicity, the following description will be given assuming that the first bonding pad 2A and the second bonding pad 3A extend straight in the second direction.

[0070] The fourth bonding wire 6A includes a bump 6AA and a wire 6AB.

[0071] Since the first bonding pad 2A includes the first bonding wire 4A, the second bonding wire 4B, and the third bonding wire 4C aligned in the first direction, the length in the first direction is longer than that of the second bonding pad 3A. Therefore, if no protrusion is provided, the area A4 of the undivided region where the first bonding pad 2A is not connected by a connecting wire becomes large as shown in FIG.

[0072] Specifically, the length of the first bonding pad 2A is defined as W1, and the direction intersecting the first direction in the plane of the first bonding pad 2A is defined as the second direction. Preferably, the direction perpendicular to the first direction in the plane of the first bonding pad 2A is defined as the second direction. The length of the first bonding pad 2A in the second direction is defined as D1. In this case, W1 is, for example, 0.5 to 5 times D1. If the first bonding pad 2A is long in the first direction, W1 is preferably 1.5 to 5 times D1.

[0073] To specify the length of the second bonding pad 3A, if the length of the second bonding pad 3A in the first direction is W2 and the length of the second bonding pad 3A in the second direction is D2, D2 is, for example, 1.5 times or more and 15 times or less than W2.

[0074] As the area of ​​the pad increases, the area of ​​the region of the first bonding pad 2A that is not in contact with the connection wiring increases on the side where the connection wiring is provided. Because the surface of the first bonding pad 2A is a metal surface, such as gold plating, the adhesion between the first bonding pad 2A and the encapsulant 8 is likely to be weaker than that between the second bonding pad 3A and the encapsulant 8. Therefore, even when a first bonding pad 2A with a configuration such as a reinforced power supply is adopted, the non-connected region of the first bonding pad 2A that is not connected to the connection wiring can be divided into regions so that the adhesion between the first bonding pad 2A and the encapsulant 8 is closer to that of the second bonding pad 3A, thereby improving the durability and / or reliability of the semiconductor device 100.

[0075] The first bonding pad 2A is divided into an area A1 (the area surrounded by the dashed line in FIG. 3, which is the area of ​​a rectangular region with its longer sides in the first direction, located inside the bump 4AA of the first bonding wire 4A, the bump 4BA of the second bonding wire 4B, the bump 4CA of the third bonding wire 4C, the first bump 5A, the second bump 5B, and the third bump 5C on the surface of the first bonding pad 2A), an area A2 (the area surrounded by the two-dot short-chain line in FIG. 3, which is the area of ​​a rectangular region with its longer sides in the second direction, located inside the bump 4AA of the first bonding wire 4A, the bump 4CA of the third bonding wire 4C, the first bump 5A, and the third bump 5C on the surface of the first bonding pad 2A), and an area A3 (FIG. 3 4, the area surrounded by the short-dotted dashed line in FIG. 4, which is the area of ​​a rectangular region located inside bump 4BA of second bonding wire 4B, bump 4CA of third bonding wire 4C, second bump 5B, and third bump 5C on the surface of first bonding pad 2A and with its longer side in the second direction) is smaller than area A4 (the area surrounded by the short-dotted dashed line in FIG. 4, which is the area of ​​the largest rectangular region located on the +Y direction side of bump 4AA of first bonding wire 4A, bump 4BA of second bonding wire 4B, and bump 4CA of third bonding wire 4C on the surface of first bonding pad 2A and with its longer side in the first direction), and therefore it is thought that contraction and expansion stress between encapsulant 8 and first bonding pad 2A is dispersed. Although the sum of areas A1, A2, and A3 is relatively large, reducing each area contributes to improving durability and / or reliability.

[0076] For example, by providing a convex portion on the surface layer of the first bonding pad 2A, the area of ​​the first bonding pad 2A that is not connected to the connecting wiring is divided into regions. It is preferable to provide multiple convex portions on the first bonding pad 2A. As an example of convex portions, the schematic diagram of FIG. 3 shows a configuration in which a first bump 5A, a second bump 5B, and a third bump 5C are provided on the first bonding pad 2A. The convex portions are not limited to bumps (dummy bumps) and may be any protrusions provided on the surface of the first bonding pad 2A. Although the first bonding pad 2A itself includes fine irregularities, providing the convex portions is thought to divide the area and distribute contraction / expansion stress.

[0077] The first bump 5A, the second bump 5B, and the third bump 5C are aligned in the first direction (X direction), with almost no misalignment in the second direction (Y direction), and have the same or nearly the same Y coordinates. The third bump 5C is sandwiched between the first bump 5A and the second bump 5B in the first direction. The first bump 5A and the bump 4AA of the first bonding wire 4A are aligned in the second direction and have the same or nearly the same X coordinates. The second bump 5B and the bump 4BA of the second bonding wire 4B are aligned in the second direction and have the same or nearly the same X coordinates. The third bump 5C is located at a position half or nearly half the W1 from the end of the first bonding pad 2A in the first direction. The third bump 5C and the bump 4CA of the third bonding wire 4C are aligned in the second direction and have the same or nearly the same X coordinates. The distance in the first direction between the first bump 5A and the third bump 5C is the same as or approximately the same as the distance in the first direction between the second bump 5B and the third bump 5C. The distance in the second direction between the first bump 5A and the bump 4AA of the first bonding wire 4A, the distance in the second direction between the second bump 5B and the bump 4BA of the second bonding wire 4B, and / or the distance in the second direction between the third bump 5C and the bump 4CA of the third bonding wire 4C are the same as or approximately the same as the distance in the second direction between the first bump 5A and the bump 4AA of the first bonding wire 4A.

[0078] FIG. 5 is a schematic diagram of a first bonding pad 2A of a semiconductor device 100. The first bonding pad 2A shown in the schematic diagram of FIG. 5 is provided with a connection wiring including two bonding wires and one first bump 5A, which effectively divides the area of ​​the first bonding pad 2A that is not connected to the connection wiring. Area A5 (the area surrounded by the dashed-dotted line in FIG. 5, which is a rectangular area located on the surface of the first bonding pad 2A closer to the −X direction than the bump 4AA of the first bonding wire 4A and the first bump 5A, and with its longer side extending in the first direction) and area A6 (the area surrounded by the dashed-dotted line in FIG. 5, which is a rectangular area located on the surface of the first bonding pad 2A closer to the +X direction than the bump 4BA of the second bonding wire 4B and the first bump 5A, and with its longer side extending in the first direction) are each sufficiently smaller than area A4. Therefore, the configuration shown in the schematic diagram of FIG. 5 is also preferable from the viewpoint of improving durability and / or reliability.

[0079] When dividing the area by providing a convex portion, if the largest rectangular area of ​​the area not in contact with the connection wiring on the surface of the first bonding pad 2A on which the connection wiring is provided is A4, the largest rectangular area of ​​the area not in contact with the connection wiring and the convex portion is preferably 70% or less of A4, and more preferably 10% to 60% of A4.

[0080] From the viewpoint of improving durability and / or reliability, it is also preferable that the protrusions are provided near the center of the first bonding pad 2 A. Specifically, it is preferable that one or more protrusions exist within an area within an imaginary circle having a diameter of 3 / 4 of D1 from the center of the first bonding pad 2 A, and it is more preferable that one or more protrusions exist within an area within an imaginary circle having a diameter of 1 / 2 of D1.

[0081] The number of protrusions is not particularly limited, but is preferably equal to or less than the number of bonding wires included in the connection wiring provided on the first bonding pad 2A, for example.

[0082] It is preferable that the connection wiring on the first bonding pad 2A is located on the first semiconductor element 10 side, and the convex portion is located on the opposite side from the first semiconductor element 10. By satisfying this positional relationship, the length of the connection wiring is short, which contributes to reducing the inductance of the connection wiring.

[0083] By employing ball bonding bumps as the convex portions, the anchor effect improves the adhesion between the convex portions and the sealing material 8. The improved adhesion between the convex portions and the sealing material 8 improves the durability and / or reliability of the semiconductor device 100.

[0084] As a form of dividing the region of the first bonding pad 2A that is not connected to the connection wiring, it is also preferable that the region that is not connected by the connection wiring is divided into regions in a direction non-perpendicular to the first direction. A form in which the region that is not connected by the connection wiring is divided into regions in a direction non-perpendicular to the first direction will be described with reference to the schematic diagrams of the first bonding pad 2A of the semiconductor device 100 in Figures 6, 7, and 8.

[0085] By shifting some of the bonding wires included in the connection wiring of the first bonding pad 2A in the second direction, it is possible to divide the region of the first bonding pad 2A that is not connected to the connection wiring in a direction non-perpendicular to the first direction. In other words, by spacing the bonding wires included in the connection wiring of the first bonding pad 2A apart in the second direction, it is possible to divide the region of the first bonding pad 2A that is not connected to the connection wiring in a direction non-perpendicular to the first direction.

[0086] In the first bonding pad 2A shown in the schematic diagram of FIG. 6, the first bonding wire 4A, the second bonding wire 4B, and the third bonding wire 4C are all offset in the second direction relative to the other bonding wires. This offset in the second direction divides the first bonding pad 2A into smaller regions where it is not connected to the connecting wiring. FIG. 6 illustrates a configuration in which the first bonding wire 4A has a bump 4AA. However, if the first bonding wire 4A or the like is formed by wedge bonding, the offset in the second direction can be evaluated by treating the elongated connection surface between the bonding wire and the first bonding pad 2A as the bump 4AA in FIG. 6. The imaginary line B1 in FIG. 6 divides the region of the first bonding pad 2A that is not connected to the connecting wiring in a direction non-perpendicular to the first direction (in the direction of the imaginary line L1).

[0087] The bump 4BA of the second bonding wire 4B is located in the -Y direction relative to the bump 4AA of the first bonding wire 4A. The bump 4BA of the second bonding wire 4B is located in the -Y direction relative to the bump 4CA of the third bonding wire 4C. The bump 4CA of the third bonding wire 4C is located in the -Y direction relative to the bump 4AA of the first bonding wire 4A. The bump 4CA of the third bonding wire 4C is located between the bump 4AA of the first bonding wire 4A and the bump 4BA of the second bonding wire 4B in the Y direction. In the schematic diagram of FIG. 6, the first bonding wire 4A and the second bonding wire 4B are selected so that the amount of deviation in the Y direction is largest.

[0088] When the connection surface between second bonding wires 4B (one or more arbitrarily selected bonding wires) and first bonding pad 2A and the connection surface between the bonding wire closest to the arbitrarily selected one or more bonding wires and first bonding pad 2A are offset in the second direction, the bonding wires of the connection wiring provided on first bonding pad 2A are also offset in the second direction. It is preferable that the connection surface between one or more arbitrarily selected bonding wires and first bonding pad 2A and the connection surface between the bonding wire closest to the arbitrarily selected one or more bonding wires and first bonding pad 2A be offset in the second direction by more than half the length in the second direction of each connection surface between the arbitrarily selected one or more bonding wires and first bonding pad 2A. It is more preferable that the connection surfaces between one or more arbitrarily selected bonding wires and the first bonding pad 2A and the connection surfaces between the bonding wires closest to the arbitrarily selected one or more bonding wires and the first bonding pad 2A are offset in the second direction by at least the length in the second direction of the connection surfaces between the one or more arbitrarily selected bonding wires and the first bonding pad 2A.

[0089] The imaginary line L1 shown in the schematic diagram of Figure 6 has the center of the connection area between the first bonding wire 4A and the first bonding pad 2A as the first base point, and the center of the connection area between the second bonding wire 4B and the first bonding pad 2A as the second base point, and represents the Voronoi boundary between the first base point and the second base point.

[0090] The imaginary line L2 shown in the schematic diagram of Figure 6 has the center of the connection area between the first bonding wire 4A and the first bonding pad 2A as the first base point, and the center of the connection area between the third bonding wire 4C and the first bonding pad 2A as the third base point, and represents the Voronoi boundary between the first base point and the third base point.

[0091] The imaginary line L3 shown in the schematic diagram of Figure 6 has the center of the connection area between the second bonding wire 4B and the first bonding pad 2A as the second generating point, and the center of the connection area between the third bonding wire 4C and the first bonding pad 2A as the third generating point, and represents the Voronoi boundary between the second generating point and the third generating point.

[0092] When the angles formed by these virtual lines L1, L2, and L3 with the first direction are 90°, the configuration shown in the schematic diagram of Fig. 4 is obtained. By tilting the angles formed by these virtual lines L1, L2, and L3 with the first direction from 90°, the non-connected region of the first bonding pad 2A with the connecting wiring can be divided into regions in a direction non-perpendicular to the first direction. The virtual lines L1, L2, and L3 are also shown in the schematic diagrams of Figs. 6, 7, and 8.

[0093] The angles formed by the virtual lines L1, L2, and L3 and the first direction are preferably 45° to 85° or 95° to 135°. When the angles are within this range, the first bonding wires 4A, the second bonding wires 4B, and the third bonding wires 4C are arranged in a well-balanced manner, and the area of ​​the unconnected portions is suitably reduced.

[0094] 7 and 8 show modified examples of the configuration shown in the schematic diagram of FIG. 6. In the configuration shown in the schematic diagram of FIG. 7, the first bonding wire 4A and the third bonding wire 4C are not arranged with a deviation in the second direction. Therefore, the angle between the virtual line L3 and the first direction is 90°. On the other hand, the second bonding wire 4B is arranged with a deviation in the second direction relative to the first bonding wire 4A, so the angle between the virtual line L1 and the first direction is inclined with respect to 90°. When three or more bonding wires are included in the first bonding pad 2A as connecting wiring, the first bonding wire 4A, the second bonding wire 4B, and the third bonding wire 4C are each identified from among the bonding wires included in the connecting wiring, taking into account the angle between the virtual line and the first direction, and the angle between the virtual line and the first direction is evaluated. The imaginary lines B2 in FIG. 7 divide the area of ​​the first bonding pad 2A that is not connected by the connection wiring into areas in a direction non-perpendicular to the first direction (in the direction of the imaginary lines L1).

[0095] In the configuration shown in the schematic diagram of FIG. 7, the bump 4BA of the second bonding wire 4B is located in the -Y direction relative to the bump 4AA of the first bonding wire 4A. In the configuration shown in the schematic diagram of FIG. 7, the bump 4BA of the second bonding wire 4B is located in the -Y direction relative to the bump 4CA of the third bonding wire 4C. The Y coordinate of the bump 4CA of the third bonding wire 4C is positioned so that it is the same or approximately the same as the Y coordinate of the bump 4AA of the first bonding wire 4A. In the configuration shown in the schematic diagram of FIG. 7, the first bonding wire 4A and the second bonding wire 4B can be selected so that the amount of deviation in the Y direction is largest.

[0096] In the schematic diagram of Fig. 8, the bonding wires included in the connection wiring of the first bonding pad 2A are spaced apart in the second direction, and a first bump 5A and a second bump 5B are provided as protrusions. It is also possible to combine other methods for dividing the non-connected portions into regions. The imaginary line B3 in Fig. 8 divides the region not connected by the connection wiring of the first bonding pad 2A into regions in a direction non-perpendicular to the first direction (in the direction of the imaginary line L1), and the imaginary line B4 in Fig. 8 divides the region not connected by the connection wiring of the first bonding pad 2A into regions in a direction non-perpendicular to the first direction (in the direction of the imaginary line L3).

[0097] The bump 4BA of the second bonding wire 4B in the configuration shown in the schematic diagram of Figure 8 is located in the -Y direction relative to the bump 4AA of the first bonding wire 4A. The bump 4BA of the second bonding wire 4B in the configuration shown in the schematic diagram of Figure 8 is located in the -Y direction relative to the bump 4CA of the third bonding wire 4C. The Y coordinate of the bump 4CA of the third bonding wire 4C is positioned so that it is the same or approximately the same as the Y coordinate of the bump 4AA of the first bonding wire 4A. In the schematic diagram of Figure 7, the first bonding wire 4A and the second bonding wire 4B are selected so that the amount of deviation in the Y direction is largest.

[0098] The first bump 5A in the configuration shown in the schematic diagram of Fig. 8 is located in the -Y direction relative to the bump 4AA of the first bonding wire 4A and in the -X direction relative to the bump 4BA of the second bonding wire 4B. The second bump 5B in the configuration shown in the schematic diagram of Fig. 8 is located in the -Y direction relative to the bump 4CA of the third bonding wire 4C and in the +X direction relative to the bump 4BA of the second bonding wire 4B. In the first direction, the bump 4BA of the second bonding wire 4B is located between the first bump 5A and the second bump 5B.

[0099] In any of the configurations shown in the schematic diagrams of Figures 6, 7, and 8, the regions can be divided so that the non-connected areas are small, and these configurations are preferable in terms of improving durability and / or reliability.

[0100] As a form of dividing the region of the first bonding pad 2A that is not connected to the connection wiring, a form in which the region that is not connected by the connection wiring is physically divided into parts is also preferable. A form in which the region that is not connected by the connection wiring is physically divided into parts will be described with reference to the schematic diagrams of the first bonding pad 2A of the semiconductor device 100 in Figures 9 and 10.

[0101] The first bonding pad 2A in the form shown in the schematic diagram of Fig. 9 has a slit. The first bonding pad 2A shown in the schematic diagram of Fig. 9 has a first slit S1 and a second slit S2. The first slit S1 and the second slit S2 physically divide the area of ​​the first bonding pad 2A that is not connected to the connection wiring into three areas. By physically dividing the area, the rectangular area A7 (the area surrounded by the dashed-dotted line in FIG. 9, which is the area of ​​the rectangular area located in the -Y direction from bump 4AA of first bonding wire 4A on the surface of first bonding pad 2A, on the -X direction side from first slit S1, and with its longer side in the second direction) of the area not in contact with the connecting wiring, area A8 (the area surrounded by the dashed line in FIG. 9, which is the area of ​​the rectangular area located in the -Y direction from bump 4BA of second bonding wire 4B on the surface of first bonding pad 2A, on the +X direction side from second slit S2, and with its longer side in the second direction), and area A9 (the area surrounded by the dashed-dotted line in FIG. 9, which is the area of ​​the rectangular area located in the -Y direction from bump 4CA of third bonding wire 4C on the surface of first bonding pad 2A, between first slit S1 and second slit S2, and with its longer side in the second direction) are effectively smaller than area A4 of the configuration shown in the schematic diagram of FIG. 4. By providing the first slit S1 and the second slit S2, it is possible to improve the durability and / or reliability of the semiconductor device 100 without significantly reducing the area of ​​the first bonding pad 2A. The number of slits is not limited, but is, for example, equal to or less than the number of bonding wires included in the connection wiring.

[0102] The first bonding pad 2A in the form shown in the schematic diagram of FIG. 10 has an opening. The first bonding pad 2A shown in the schematic diagram of FIG. 10 has a first opening H1 and a second opening H2. The first opening H1 and the second opening H2 allow the region of the first bonding pad 2A that is not connected to the connection wiring to be physically divided into three regions. By physically dividing the region that is not in contact with the connection wiring, a rectangular area A10 (the region surrounded by the two-dot dash line in FIG. 10, which is the area of ​​the rectangular region that is located in the -Y direction from the bump 4AA of the first bonding wire 4A on the surface of the first bonding pad 2A, located in the -X direction from the first opening H1, and with the longer side in the second direction) and an area A11 (the region surrounded by the dashed line in FIG. 10, which is the area of ​​the rectangular region that is located in the -Y direction from the bump 4CA of the third bonding wire 4C on the surface of the first bonding pad 2A) are obtained. 10 , the area A12 (the area of ​​a rectangular region located between the first opening H1 and the second opening H2, with its longer side in the second direction) is effectively smaller than the area A4 of the configuration shown in the schematic diagram of FIG. 4 . By providing the first slit S1 and the second slit S2, the durability and / or reliability of the semiconductor device 100 can be improved without significantly reducing the area of ​​the first bonding pad 2A. The number of openings is not limited, but is, for example, equal to or less than the number of bonding wires included in the connecting wiring.

[0103] 10, in a configuration in which the region not connected by the connecting wiring is physically divided into parts, it is also possible to provide, for example, first bumps 5A and second bumps 5B as convex portions, or to displace bonding wires included in the connecting wiring in the second direction. Any of the preferred configurations can be implemented in combination, and any combination contributes to improving the durability and / or reliability of the semiconductor device 100. Also, slits and openings can be combined.

[0104] From the viewpoint of effectively dividing the region of the first bonding pad 2A that is not connected to the connection wiring, it is preferable that the slit and the opening extend in the second direction.

[0105] If the areas of the slits and openings are large, the area of ​​the first bonding pad 2A will be small, so the total area of ​​the slits and openings is preferably 5% to 30% of the area of ​​the first bonding pad 2A.

[0106] 11 is a schematic diagram of the first bonding pad 2A of the semiconductor device 100. When the region of the first bonding pad 2A that is not connected to the connection wiring is divided using a protrusion, at least one or more protrusions and one or more bonding wires included in the connection wiring can be connected by a wire such as a bonding wire.

[0107] In the schematic diagram of Fig. 11, a first bump 5A, which is a convex portion, and a bump 4AA of a first bonding wire 4A are connected by a wire 9A extending in the second direction. In the schematic diagram of Fig. 11, a second bump 5B, which is a convex portion, and a bump 4BA of a second bonding wire 4B are connected by a wire 9B extending in the second direction. In the schematic diagram of Fig. 11, a third bump 5C, which is a convex portion, and a bump 4CA of a third bonding wire 4C are connected by a wire 9C extending in the second direction.

[0108] 12 is a schematic diagram of the first bonding pad 2A of the semiconductor device 100. When a protrusion is used to divide the region of the first bonding pad 2A that is not connected to the connection wiring, the protrusion can be disposed on the first semiconductor element 10 side. In this case, the protrusion and the bonding wire of the connection wiring can be connected by a wire, similar to the form shown in the schematic diagram of FIG.

[0109] 13 is a schematic diagram of a first bonding pad 2A of a semiconductor device 100. When a region of the first bonding pad 2A that is not connected to the connection wiring is divided using a protrusion, the protrusions can be connected to each other. In the configuration shown in the schematic diagram of FIG. 13, a first bump 5A and a second bump 5B are connected by a wire 9D that extends in a first direction.

[0110] The first bump 5A in the form shown in the schematic diagram of Fig. 13 is located in the -Y direction relative to the bump 4AA of the first bonding wire 4A and the bump 4CA of the third bonding wire 4C, and is located between the bump 4AA of the first bonding wire 4A and the bump 4CA of the third bonding wire 4C in the X direction. The second bump 5B shown in the schematic diagram of Fig. 13 is located in the -Y direction relative to the bump 4BA of the second bonding wire 4B and the bump 4CA of the third bonding wire 4C, and is located between the bump 4BA of the second bonding wire 4B and the bump 4CA of the third bonding wire 4C in the X direction.

[0111] Even if the position of the convex portion is changed or the convex portions are connected, the area of ​​the first bonding pad 2A that is not connected to the connection wiring can be effectively divided into areas, which contributes to improving the durability and / or reliability of the semiconductor device 100.

[0112] The embodiments can improve the durability and / or reliability of the semiconductor device 100 in various ways. The durability and / or reliability can be improved without making any design changes to the wiring layout or the like of the already designed wiring board 1, or with only minor design changes.

[0113] (Second embodiment) The second embodiment relates to a semiconductor device. The second embodiment is a modified example of the semiconductor device 100 of the first embodiment. Schematic diagrams of a semiconductor device 101 according to the second embodiment are shown in Fig. 14 and Fig. 15. The schematic diagram of Fig. 15 is a cross-sectional schematic diagram of the cross section BB of Fig. 14. Descriptions of content common to the first and second embodiments will be omitted.

[0114] Semiconductor device 101 differs from semiconductor device 100 in that it does not have bumps on the bonding wires, it uses third bonding pad 2C instead of fourth bonding pad 3B and fifth bonding pad 3C, it uses twentieth bonding pad 2D instead of thirteenth bonding pad 3J and fourteenth bonding pad 3K, it has seventh bump 5G on tenth bonding pad 3H, it has eighth bump 5H on nineteenth bonding pad 3P, and the second semiconductor element 21 is flip-chip connected to wiring board 1 via solder 32.

[0115] Like the first bonding pad 2A, the third bonding pad 2C has a connection wiring including multiple bonding wires extending from one bonding pad. The third bonding pad 2C has a slit S3, dividing the area of ​​the third bonding pad 2C that is not connected to the connection wiring. A single semiconductor device 101 may include one or more pads selected from the group consisting of a pad with a protruding portion (e.g., the first bonding pad 2A), a pad divided into areas in a direction non-perpendicular to the first direction (not shown in FIG. 15), and a physically divided pad (e.g., the third bonding pad 2C). The third bonding pad 2C has an area larger than the area of ​​two bonding pads, which is advantageous from the viewpoint of reducing resistance and further contributes to improving the durability and / or reliability of the semiconductor device 101.

[0116] The 20th bonding pad 2D, like the 11th bonding pad 2B, has a connection wiring including multiple bonding wires extending from a single bonding pad. The 20th bonding pad 2D has a slit S4, which divides the non-connected region of the 20th bonding pad 2D from the connection wiring. A single semiconductor device 101 may include one or more pads selected from the group consisting of a pad with a protruding portion (e.g., the 11th bonding pad 2B), a pad divided into regions in a direction non-perpendicular to the first direction (not shown in FIG. 15), and a physically divided pad (e.g., the 20th bonding pad 2D). The 20th bonding pad 2D has an area larger than the area of ​​two bonding pads, which is advantageous in terms of reducing resistance and further contributes to improving the durability and / or reliability of the semiconductor device 101.

[0117] The semiconductor elements such as the second semiconductor element 21 included in the semiconductor device 101 may be flip chips.

[0118] A convex portion can also be provided on a bonding pad where one bonding wire (one or more but one or less bonding wires) is connected to one bonding pad. Providing a convex portion on such a bonding pad also contributes to improving the durability and / or reliability of semiconductor device 101. For example, by providing seventh bump 5G and eighth bump 5H on tenth bonding pad 3H and nineteenth bonding pad 3P, respectively, the adhesive strength between tenth bonding pad 3H and nineteenth bonding pad 3P and sealing material 8 can be improved.

[0119] (Third embodiment) The third embodiment relates to a method for manufacturing a semiconductor device, more specifically, a method for manufacturing a bonding pad having a convex portion. Fig. 16 shows a flowchart of the method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device includes a step of forming a first bonding wire and a second bonding wire on a first bonding pad and a step of forming a convex portion on the first bonding pad. The step of forming the first bonding wire and the second bonding wire on the first bonding pad may be performed first, or the step of forming the convex portion on the first bonding pad may be performed first.

[0120] By manufacturing a bonding pad having a convex portion in the above process, the durability and / or reliability of the semiconductor device 101 is improved.

[0121] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the inventions and their equivalents as defined in the claims. [Explanation of symbols]

[0122] 1: Wiring board 2A: First bonding pad 2B: 11th bonding pad 2C: Third bonding pad 2D: 20th bonding pad 3A: Second bonding pad 3B: 4th bonding pad 3C: 5th bonding pad 3D: 6th bonding pad 3E: 7th bonding pad 3F: 8th bonding pad 3G: 9th bonding pad 3H: 10th bonding pad 3I: 12th bonding pad 3J: 13th bonding pad 3K: 14th bonding pad 3L: 15th bonding pad 3M: 16th bonding pad 3N: 17th bonding pad 3O: 18th bonding pad 3P: 19th bonding pad 4: Third bonding wire 4A: First bonding wire 4AA: Bump 4AB: Wire 4AC: Bump 4AD: Wire 4AE: Bump 4AF: Wire 4AG: Bump 4AH: Wire 4AI: Bump 4B: Second bonding wire 4BA: Bump 4C: Third bonding wire 4CA: Bump 4D: 12th bonding wire 4DA: Bump 4DC: Bump 4DD: Wire 4DE: Bump 4DF: Wire 4DG: Bump 4DH: Wire 4DI: Bump 4E: 13th bonding wire 4F: 14th bonding wire 4G: 7th semiconductor chip 5A: First bump 5B: Second bump 5C: 3rd bump 5D: 4th bump 5E: 5th bump 5F: 6th Bump 5G: The 7th Bump 5H: 8th bump 6A: 4th bonding wire 6AA: Bump 6AB: Wire 6B: 5th bonding wire 6C: 6th bonding wire 6D: 7th bonding wire 6E: 8th bonding wire 6F: 9th bonding wire 6G: 10th bonding wire 6H: 11th bonding wire 6I: 15th bonding wire 6J: 16th bonding wire 6K: 17th bonding wire 6L: No. 18 bonding wire 6M: No. 19 bonding wire 6N: No. 20 bonding wire 6O: 21st bonding wire 6P: No. 22 bonding wire 7: Solder ball 8: Encapsulating material 9A: Wire 9B: Wire 9C: Wire 9D: Wire 10: First semiconductor element 10A: First semiconductor chip 10B: Second semiconductor chip 10C: Third semiconductor chip 10D: 4th semiconductor chip 10E: 5th semiconductor chip 10F: 6th semiconductor chip 10G: 7th semiconductor chip 10H: 8th semiconductor chip 12A: Terminal 12B: Terminal 12C: Terminal 12D: Terminal 12E: Terminal 12F: Terminal 12G: Terminal 12H: Terminal 21: Second semiconductor element 22: Terminal 23: Bump 24: Terminal 25: Bump 26: Wire 27: Terminal 28: Bump 29: Wire 31: Terminal 40: First insulating layer 41: Second insulating layer 100: Semiconductor device 101: Semiconductor device H1: 1st opening H2: 2nd opening L1: Virtual line L2: Virtual line L3: Virtual line S1: First slit S2: Second slit S3: Slit S4: Slit

Claims

1. a wiring substrate having a first bonding pad and a second bonding pad adjacent to the first bonding pad and aligned with the first bonding pad in a first direction along a surface direction of the first bonding pad; a semiconductor element provided on the wiring substrate; a connection wiring that connects the first bonding pad and the semiconductor element and includes a first bonding wire and a second bonding wire that are aligned in the first direction; A semiconductor device in which the first bonding pad is divided into regions in a direction non-perpendicular to the first direction, or is physically divided into parts, by a convex portion provided on the surface of the first bonding pad in an area that is not connected by the connection wiring.

2. The semiconductor device according to claim 1 , wherein the protrusion is one or more bumps.

3. 2. The semiconductor device according to claim 1, wherein the second bonding pad includes a third bonding wire connected to the semiconductor element.

4. a direction intersecting the first direction is a second direction, The semiconductor device according to claim 1 , wherein the protrusions are misaligned in the second direction.

5. 2. The semiconductor device according to claim 1, wherein the first bonding pad is physically divided into portions and has a slit or / and an opening.

6. 2. The semiconductor device according to claim 1, wherein the connection wiring is a signal wiring or a power supply wiring.

7. The semiconductor device according to claim 1 , wherein the protrusion is connected to the semiconductor element via the first bonding pad and / or the connection wiring.

8. The length of the first bonding pad in the first direction is W1, a direction intersecting the first direction in a surface direction of the first bonding wire is defined as a second direction; The length of the first bonding pad in the second direction is defined as D1, 2. The semiconductor device according to claim 1, wherein W1 is 0.5 to 5 times D1.

9. The length of the second bonding pad in the first direction is W2, a direction intersecting the first direction in a surface direction of the first bonding wire is defined as a second direction; The length of the second bonding pad in the second direction is defined as D2, 2. The semiconductor device according to claim 1, wherein D2 is 1.5 to 15 times W2.

10. The semiconductor device according to claim 1 , wherein the protrusion contains an element different from an element contained in the first bonding pad.

11. The semiconductor device according to claim 1 , wherein the protrusion contains an element contained in the first bonding pad.

12. The semiconductor device according to claim 1 , wherein the protrusion includes a resin.

13. 2. The semiconductor device according to claim 1, wherein the semiconductor element, the first bonding pad, and the second bonding pad are sealed with a molding resin.

14. 2. The semiconductor device according to claim 1, wherein the number of said protrusions is equal to or less than the number of bonding wires included in said connection wiring.

15. the protrusion is in contact with a surface layer of the first bonding pad; the surface layer contains one or more elements selected from the group consisting of Au, Pd, Ni, and Cu, The semiconductor device according to claim 1 , wherein the connection wiring is connected to the surface layer.

16. a center of a connection region between the first bonding wire and the first bonding pad is defined as a first generating point; a center of a connection region between the second bonding wire and the first bonding pad is defined as a second generating point; 2 . The semiconductor device according to claim 1 , wherein an angle formed between the Voronoi boundary of the first generating point and the second generating point and the first direction is 45° to 85° or 95° to 135°.

17. the connection wiring is located on the semiconductor element side, The semiconductor device according to claim 1 , wherein the protrusion is located on an opposite side to the semiconductor element.

18. a direction intersecting the first direction in a surface direction of the first bonding wire is defined as a second direction; The length of the first bonding pad in the second direction is defined as D1, 2. The semiconductor device according to claim 1, wherein one or more of said protrusions are present in an area within an imaginary circle having a diameter of 3 / 4 of D1 from the center of said first bonding pad.

19. a direction intersecting the first direction in a surface direction of the first bonding wire is defined as a second direction; the first bonding pad, which is physically divided into portions, has a slit extending in the second direction and / or an opening extending in the second direction; the slit opens on a side of the first bonding pad opposite to the semiconductor element side, 2. The semiconductor device according to claim 1, wherein the sum of the area of ​​the slit and the area of ​​the opening is 5% to 30% of the area of ​​the first bonding pad.

20. 2. The semiconductor device according to claim 1, wherein the connection portions of the first bonding wire and the second bonding wire to the first bonding pad have a ball bond shape or a wedge bond shape.

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