Nitride semiconductor device and method for manufacturing nitride semiconductor device

Abstract

To suppress an increase in on-resistance caused by an extension part of a gate layer.SOLUTION: The nitride semiconductor device 10 includes a substrate 20, an electron transit layer 24 located on the substrate 20, an electron supply layer 26 located on the electron transit layer 24, a gate layer 30 located on the electron supply layer 26, a gate electrode 40 located on the gate layer 30, a passivation layer 50 covering the electron supply layer 26, the gate layer 30, and the gate electrode 40, and a source electrode 42 and a drain electrode 44 in contact with the electron supply layer 26. The gate layer 30 includes a ridge portion 31 having a ridge lower surface in contact with the electron supply layer 26 and a ridge upper surface on which the gate electrode 40 is formed, and an extension portion 32 extending from the ridge portion 31 in the first direction and thinner than the ridge portion 31. Passivation layer 50 includes interposing portion 53 interposed between electron supply layer 26 and extending portion 32.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a nitride semiconductor device and a method for manufacturing the nitride semiconductor device. [Background technology]

[0002] Currently, high electron mobility transistors (HEMTs) using group III nitride semiconductors (hereinafter simply referred to as "nitride semiconductors") such as gallium nitride (GaN) are being commercialized. HEMTs use the two-dimensional electron gas (2DEG) formed near the interface of semiconductor heterojunctions as the conductive path (channel). Power devices using HEMTs are recognized as devices that enable lower on-resistance and higher frequency operation compared to typical silicon (Si) power devices.

[0003] For example, the nitride semiconductor device described in Patent Document 1 includes a silicon substrate, an electron transit layer formed of a gallium nitride (GaN) layer, and an electron supply layer formed of an aluminum gallium nitride (AlGaN) layer. A 2DEG is formed in the electron transit layer near the heterojunction interface between the electron transit layer and the electron supply layer. Furthermore, in the nitride semiconductor device described in Patent Document 1, a gate layer, which is a GaN layer (p-type GaN layer) doped with acceptor-type impurities, is provided on the electron supply layer and directly below the gate electrode. In this configuration, the gate layer raises the energy level of the conduction band in the region directly below it near the heterojunction interface between the electron transit layer and the electron supply layer, thereby eliminating the channel directly below the gate layer. This allows the nitride semiconductor device to operate normally off.

[0004] Furthermore, in recent years, it has been proposed to employ a step structure in the gate layer of a HEMT, for example, from the viewpoint of improving gate breakdown voltage. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-73506

[0006] [overview] In a gate layer having a step structure, the on-resistance can increase even directly under the extensions (steps) of the gate layer due to a decrease in the 2DEG.

[0007] a gate electrode disposed on the gate layer; a passivation layer covering the electron supply layer, the gate layer, and the gate electrode, the passivation layer having a source opening and a drain opening spaced apart from each other in a first direction; a source electrode in contact with the electron supply layer through the source opening; and a drain electrode in contact with the electron supply layer through the drain opening. The gate layer has a rib contacting the electron supply layer. the ridge portion includes a ridge portion having a ridge lower surface and a ridge upper surface on which the gate electrode is formed, and an extension portion extending from the ridge portion in the first direction and thinner than the ridge portion, the ridge portion being a portion located between an end of the ridge lower surface on the source electrode side and an end of the ridge lower surface on the drain electrode side in the first direction, the extension portion being located between the ridge upper surface and the ridge lower surface and being a portion extending from the end of the ridge lower surface on the source electrode side toward the source opening or from the end of the ridge lower surface on the drain electrode side toward the drain opening, and the passivation layer includes an intervening portion interposed between the electron supply layer and the extension portion. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a schematic plan view of an exemplary nitride semiconductor device according to the first embodiment. [Figure 2]FIG. 2 is a schematic plan view showing a part of the interior of the nitride semiconductor device of FIG. [Figure 3] FIG. 3 is a schematic cross-sectional view of the nitride semiconductor device taken along line F3-F3 in FIG. [Figure 4] FIG. 4 is a schematic cross-sectional view showing a part of the nitride semiconductor device of FIG. [Figure 5] 5A to 5C are schematic cross-sectional views illustrating exemplary manufacturing steps for the nitride semiconductor device shown in FIG. [Figure 6] FIG. 6 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 7] FIG. 7 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 8] FIG. 8 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 9] FIG. 9 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 11] FIG. 11 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 12] FIG. 12 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 13] FIG. 13 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 14] FIG. 14 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 15] 15A to 15C are schematic cross-sectional views illustrating an exemplary manufacturing process for a gate layer using the FIELO method. [Figure 16] FIG. 16 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 17] FIG. 17 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 18] FIG. 18 is a schematic cross-sectional view showing a manufacturing step subsequent to the step shown in FIG. [Figure 19]FIG. 19 is a schematic cross-sectional view of an exemplary nitride semiconductor device according to the second embodiment. [Figure 20] FIG. 20 is a schematic cross-sectional view of an exemplary nitride semiconductor device according to the third embodiment.

[0009] [Detailed explanation] Hereinafter, embodiments of nitride semiconductor devices according to the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of explanation, components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered as limiting the present disclosure.

[0010] Terms such as "first," "second," and "third" used in this disclosure are used to clearly distinguish components of an object and are not used to rank the objects. Furthermore, the expression "at least one" used in this disclosure means one or more of a desired plurality of options. As an example, if the number of options is two, the expression "at least one" means only one option or both of the two options. As another example, if the number of options is three or more, the expression "at least one" means only one option or any combination of two or more options.

[0011] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0012] First Embodiment [Overall configuration of nitride semiconductor device] The overall configuration of a nitride semiconductor device 10 according to the first embodiment will be described with reference to Figures 1 to 3. Figure 1 shows a schematic planar structure of an exemplary nitride semiconductor device 10 according to the first embodiment. Figure 2 shows a schematic enlarged planar structure of a portion of the internal structure of the nitride semiconductor device 10 of Figure 1. Figure 3 shows a schematic cross-sectional structure of the nitride semiconductor device 10 taken along line F3-F3 of Figure 2.

[0013] As shown in FIG. 1, the nitride semiconductor device 10 includes a chip body 12. The chip body 12 is formed, for example, in the shape of a rectangular flat plate. The Z-axis direction of the mutually orthogonal X, Y, and Z axes shown in FIG. 1 and other drawings is a direction orthogonal to the main surface of the chip body 12 (top surface 13 in FIG. 1). The term "plan view" used in this disclosure refers to viewing the nitride semiconductor device 10 from above in the Z-axis direction, unless explicitly stated otherwise.

[0014] The nitride semiconductor device 10 includes at least one gate pad 14, at least one source pad 16, and at least one drain pad 18. In the example shown in FIG. 1 , the nitride semiconductor device 10 includes one gate pad 14, multiple source pads 16, and multiple drain pads 18. The gate pad 14, multiple source pads 16, and multiple drain pads 18 are formed on the top surface 13 of the chip body 12. These pads 14, 16, and 18 can be used as external connection terminals of the nitride semiconductor device 10.

[0015] Each of the gate pad 14, the source pad 16, and the drain pad 18 is formed, for example, in a rectangular shape in a plan view. The gate pad 14 can be disposed, for example, at one corner of the upper surface 13. Each of the source pads 16 and the drain pad 18 extends in the Y-axis direction in a plan view. The source pads 16 and the drain pads 18 are alternately arranged one by one in the X-axis direction, which is perpendicular to the Y-axis direction. In this way, each of the source pads 16 and the drain pads 18 can be said to extend in a direction (Y-axis direction) perpendicular to the arrangement direction of these pads 16, 18 in a plan view. Note that the shapes of each of the gate pad 14, the source pad 16, and the drain pad 18 in a plan view can be arbitrarily changed. Furthermore, the arrangement of the gate pad 14, the source pad 16, and the drain pad 18 can be arbitrarily changed.

[0016] 3, the nitride semiconductor device 10 is configured as a high electron mobility transistor (HEMT) using a nitride semiconductor. The nitride semiconductor device 10 includes a substrate 20, a buffer layer 22 formed on the substrate 20, an electron transit layer 24 formed on the buffer layer 22, and an electron supply layer 26 formed on the electron transit layer 24.

[0017] The substrate 20 may be made of silicon (Si), alumina (Al2O3), silicon carbide (SiC), gallium nitride (GaN), sapphire, or other substrate materials. For example, the substrate 20 is a heterogeneous substrate such as silicon (Si), aluminum oxide (Al2O3), or silicon carbide (SiC). For example, the substrate 20 is a Si substrate whose upper surface 20A is a (111) plane. In this case, the misorientation angle of the upper surface 20A is greater than 0 degrees. The misorientation angle of the upper surface 20A may be greater than 0 degrees and less than or equal to 1 degree. When the substrate 20 is a heterogeneous substrate, the misorientation angle of the upper surface 20A is advantageous for the formation of growth nuclei for nitride semiconductors on the substrate 20. The thickness of the substrate 20 may be, for example, 200 μm or more and 1500 μm or less. The Z-axis direction corresponds to the thickness direction of the substrate 20.

[0018] The buffer layer 22 can be composed of any material that can suppress the occurrence of wafer warpage and cracks due to the mismatch in the coefficient of thermal expansion between the substrate 20 and the electron traveling layer 24. The buffer layer 22 can include one or more nitride semiconductor layers. The buffer layer 22 can include, for example, at least one of an aluminum nitride (AlN) layer, an aluminum gallium nitride (AlGaN) layer, and a graded AlGaN layer having different aluminum (Al) compositions. For example, the buffer layer 22 can be composed of a single AlN layer, a single AlGaN layer, a layer having an AlGaN / GaN superlattice structure, a layer having an AlN / AlGaN superlattice structure, or a layer having an AlN / GaN superlattice structure.

[0019] The electron traveling layer 24 is composed of a nitride semiconductor. The electron traveling layer 24 can be, for example, a GaN layer. The thickness of the electron traveling layer 24 can be, for example, 0.1 μm or more and 2 μm or less. The electron traveling layer 24 can include one or more nitride semiconductor layers. Also, in order to suppress the leakage current in the electron traveling layer 24, impurities can be introduced into a part of the electron traveling layer 24 to make the region other than the surface layer region of the electron traveling layer semi-insulating. In this case, the impurity is, for example, carbon (C). The impurity concentration of the carbon is, for example, 1×10 19 cm -3 or more at the peak concentration.

[0020] The electron supply layer 26 is composed of a nitride semiconductor having a larger bandgap than the electron traveling layer 24. The electron supply layer 26 can be, for example, an AlGaN layer. Since the larger the Al composition, the larger the bandgap, the electron supply layer 26 which is an AlGaN layer has a larger bandgap than the electron traveling layer 24 which is a GaN layer. In one example, the electron supply layer 26 is composed of Al x Ga 1-x N. In this case, x satisfies 0.1 < x < 0.4, and more preferably, 0.1 < x < 0.3. The thickness of the electron supply layer 26 can be, for example, 5 nm or more and 20 nm or less.

[0021] The electron transit layer 24 and the electron supply layer 26 have different lattice constants in their bulk regions. Therefore, the nitride semiconductor (e.g., GaN) constituting the electron transit layer 24 and the nitride semiconductor (e.g., AlGaN) constituting the electron supply layer 26 form a lattice-mismatched heterojunction. Due to spontaneous polarization of the electron transit layer 24 and the electron supply layer 26 and piezoelectric polarization caused by compressive stress applied to the heterojunction of the electron transit layer 24, the energy level of the conduction band of the electron transit layer 24 near the heterojunction interface between the electron transit layer 24 and the electron supply layer 26 becomes lower than the Fermi level. As a result, a two-dimensional electron gas (2DEG) 28 is formed in the electron transit layer 24 near the heterojunction interface between the electron transit layer 24 and the electron supply layer 26 (e.g., at a distance of about several nanometers from the interface).

[0022] The nitride semiconductor device 10 includes a gate layer 30 formed on a portion of the electron supply layer 26 , and a gate electrode 40 formed on the gate layer 30 . The gate layer 30 is made of a nitride semiconductor. In one example, the gate layer 30 is made of a nitride semiconductor having a band gap smaller than that of the electron supply layer 26 and containing acceptor-type impurities. In one example, the gate layer 30 is GaN doped with acceptor-type impurities (p-type GaN layer). The acceptor-type impurities may be at least one of magnesium (Mg), zinc (Zn), and C. The maximum concentration of the acceptor-type impurities in the gate layer 30 is, for example, 7×10 18 cm -3 More than 1×10 20 cm -3 The following is the result.

[0023] The gate electrode 40 includes one or more metal layers. In one example, the gate electrode 40 may be a titanium nitride (TiN) layer. In another example, the gate electrode 40 may be composed of a first metal layer made of Ti and a second metal layer made of TiN provided on the first metal layer. The gate electrode 40 may be composed of, for example, a material that forms a Schottky junction with the gate layer 30. One example of such a material is TiN. The thickness of the gate electrode 40 may be, for example, 50 nm or more and 200 nm or less.

[0024] The nitride semiconductor device 10 includes a passivation layer 50. The passivation layer 50 covers the electron supply layer 26, the gate layer 30, and the gate electrode 40. The passivation layer 50 may be composed of, for example, one or any combination of silicon nitride (SiN), silicon dioxide (SiO), silicon oxynitride (SiON), alumina (AlO), AlN, and aluminum oxynitride (AlON). The passivation layer 50 may have a thickness of, for example, 50 nm to 200 nm, preferably 80 nm to 150 nm. The passivation layer 50 includes a source opening 50A and a drain opening 50B, each of which exposes a portion of the upper surface 26A of the electron supply layer 26. In the passivation layer 50, the source opening 50A and the drain opening 50B are spaced apart from each other in the X-axis direction, which is the first direction.

[0025] The nitride semiconductor device 10 includes a source electrode 42 formed in the source opening 50A and a drain electrode 44 formed in the drain opening 50B. The source electrode 42 includes a source contact portion 42A that contacts the electron supply layer 26 through the source opening 50A. The drain electrode 44 includes a drain contact portion 44A that contacts the electron supply layer 26 through the drain opening 50B.

[0026] The source electrode 42 and the drain electrode 44 include one or more metal layers. In one example, the source electrode 42 and the drain electrode 44 may be composed of one or any combination of Ti, TiN, Al, aluminum silicon copper (AlSiCu), and aluminum copper (AlCu). In one example, the source electrode 42 and the drain electrode 44 are composed of a first metal layer in contact with the electron supply layer 26, a second metal layer stacked on the second metal layer, a third metal layer stacked on the second metal layer, and a fourth metal layer stacked on the third metal layer. The first metal layer is, for example, a Ti layer, the second metal layer is, for example, an Al layer, the third metal layer is, for example, a Ti layer, and the fourth metal layer is, for example, a TiN layer.

[0027] A source contact portion 42A of the source electrode 42 is filled in the source opening 50A. The source contact portion 42A is in ohmic contact with the 2DEG 28 directly below the electron supply layer 26 through the source opening 50A. A drain contact portion 44A of the drain electrode 44 is filled in the drain opening 50B. The drain contact portion 44A is in ohmic contact with the 2DEG 28 directly below the electron supply layer 26 through the drain opening 50B. Although not shown, the substrate 20 is electrically connected to the source electrode 42. As a result, a voltage having the same potential as that of the source electrode 42 is applied to the substrate 20.

[0028] In a structure in which the gate layer 30 is formed of a nitride semiconductor containing acceptor-type impurities, the conduction path (channel) is blocked by depletion of the 2DEG 28 in the region directly below the gate layer 30 at zero bias, i.e., when no voltage is applied to the gate electrode 40. This realizes a normally-off HEMT in which the gate threshold voltage is a positive value.

[0029] The nitride semiconductor device 10 includes a field plate electrode 60 provided on the passivation layer 50. The field plate electrode 60 is electrically connected to the source electrode 42. In the example shown in FIG. 3, the field plate electrode 60 is formed integrally with the source electrode 42. That is, a part of the source electrode 42 is provided as the field plate electrode 60. Therefore, a voltage having the same potential as that of the source electrode 42 is applied to the field plate electrode 60. The field plate electrode 60 is also called a source field plate. The field plate electrode 60 covers the entire gate layer 30 in a plan view.

[0030] The field plate electrode 60 is spaced apart from the drain electrode 44. The field plate electrode 60 includes an end 61 located between the gate layer 30 and the drain electrode 44 in a plan view. The field plate electrode 60 plays a role in reducing electric field concentration near the end of the gate electrode 40 and in the gate layer 30 when a drain voltage is applied to the drain electrode 44 in a zero bias state where no voltage is applied to the gate electrode 40.

[0031] [Example Planar Layout of a Nitride Semiconductor Device] Next, an exemplary planar layout of the HEMT structure (nitride semiconductor device 10) will be described with reference to Fig. 2. For clarity, the passivation layer 50 is not shown in Fig. 2. Also, a source opening 50A, a drain opening 50B, and a field plate electrode 60 are depicted by dashed lines.

[0032] 2, the nitride semiconductor device 10 includes a plurality of transistor elements each having a HEMT structure in an element region. Note that while Fig. 2 only shows a plurality of transistor elements aligned in the X-axis direction, in reality, the transistor elements may be aligned in both the X-axis direction and the Y-axis direction.

[0033] A drain electrode 44 is provided for each transistor element. The drain electrode 44 extends in the Y-axis direction in a plan view. The source electrode 42 is provided, for example, to surround each drain electrode 44 in a plan view. As described with reference to FIG. 3, the source electrode 42 includes a field plate electrode 60. The field plate electrode 60 formed integrally with the source electrode 42 extends toward the adjacent drain electrode 44 in a plan view. Note that, in the example shown in FIG. 2, the source electrode 42 is formed continuously in the X-axis direction across multiple transistor elements adjacent in the X-axis direction, but it may be separated into multiple portions in the X-axis direction.

[0034] The gate layer 30 and the gate electrode 40 are provided for each transistor element. Each gate layer 30 and each gate electrode 40 is formed in a ring shape so as to surround one of the drain electrodes 44 in plan view.

[0035] The nitride semiconductor device 10 includes a gate wiring 72, a source wiring 74, and a drain wiring 76. The gate wiring 72, the source wiring 74, and the drain wiring 76 are formed on a first interlayer insulating layer (not shown) that covers the source electrode 42 and the drain electrode 44. In the example shown in FIG. 2, the gate wiring 72, the source wiring 74, and the drain wiring 76 each extend in the X-axis direction. The gate wiring 72, the source wiring 74, and the drain wiring 76 are arranged spaced apart from each other in the Y-axis direction. The gate wiring 72 is arranged at a position different from the drain electrode 44, the source opening 50A, and the drain opening 50B in the Y-axis direction. The source wiring 74 and the drain wiring 76 are arranged at positions that overlap the drain electrode 44, the source opening 50A, and the drain opening 50B in the Y-axis direction in a plan view.

[0036] For example, the gate wiring 72 is connected to the gate electrode 40 by a gate connection conductor 73 that penetrates the first interlayer insulating layer and extends to the gate electrode 40. The source wiring 74 is connected to the source electrode 42 by a source connection conductor 75 that penetrates the first interlayer insulating layer. The drain wiring 76 is connected to the drain electrode 44 by a drain connection conductor 77 that penetrates the first interlayer insulating layer. Each of the gate connection conductors 73, source connection conductors 75, and drain connection conductors 77 is, for example, a via that penetrates the first interlayer insulating layer. The number of each of the gate connection conductors 73, source connection conductors 75, and drain connection conductors 77 can be changed as desired.

[0037] For example, the gate wiring 72, the source wiring 74, and the drain wiring 76 are covered by a second interlayer insulating layer (not shown). In one example, the gate pad 14, the source pad 16, and the drain pad 18 shown in FIG. 1 are formed on the second interlayer insulating layer.

[0038] For example, the gate wiring 72 is connected to the gate pad 14 by a gate connection conductor (not shown) that penetrates the second interlayer insulating layer and extends to the gate pad 14. The source wiring 74 is connected to the source pad 16 by a source connection conductor (not shown) that penetrates the second interlayer insulating layer. The drain wiring 76 is connected to the drain pad 18 by a drain connection conductor (not shown) that penetrates the second interlayer insulating layer.

[0039] [Example Structure of Gate Layer and Passivation Layer] Next, exemplary structures of the gate layer 30 and the passivation layer 50 will be described with reference to Figures 3 and 4. Figure 4 shows an enlarged schematic cross-sectional structure of the gate layer 30 and its periphery in the nitride semiconductor device 10 of Figure 3. In Figure 4, the source electrode 42 and the field plate electrode 60 are omitted to avoid complicating the illustration.

[0040] 3, the gate layer 30 is located between the source contact portion 42A and the drain contact portion 44A in the X-axis direction. The gate layer 30 is spaced apart from each of the source contact portion 42A and the drain contact portion 44A. In one example, the gate layer 30 is located closer to the source contact portion 42A than the drain contact portion 44A.

[0041] 4, the gate layer 30 includes a ridge portion 31 having a ridge lower surface 31B in contact with the electron supply layer 26 and a ridge upper surface 31A on which the gate electrode 40 is formed, and extension portions 32 that are thinner than the ridge portion 31. In the example shown in Fig. 3, the extension portions 32 extend in the X-axis direction from each of the ridge side surfaces 31C, which are the side surfaces of the ridge portion 31 in the X-axis direction.

[0042] The ridge portion 31 is a portion located in the X-axis direction between an end 31BS of the ridge lower surface 31B on the source electrode 42 side and an end 31BD on the drain electrode 44 side. The ridge portion 31 can also be said to correspond to a relatively thick portion of the gate layer 30. The gate electrode 40 is in contact with the ridge upper surface 31A of the ridge portion 31. The electron supply layer 26 is in contact with the ridge lower surface 31B of the ridge portion 31. The ridge portion 31 may have a rectangular or trapezoidal shape in a cross section along the XZ plane.

[0043] The width WR of the ridge portion 31 may be, for example, not less than 600 nm and not more than 800 nm. The width WR of the ridge portion 31 can be defined as the distance in the X-axis direction between an end 31BS of the ridge underside 31B on the source electrode 42 side and an end 31BD on the drain electrode 44 side. The width WR of the ridge portion 31 is determined in consideration of various parameters such as the gate breakdown voltage.

[0044] In the X-axis direction, an end 31BS of the ridge undersurface 31B on the source electrode 42 side is located closer to the source electrode 42 than an end 40S of the gate electrode 40 on the source electrode 42 side. Similarly, an end 31BD of the ridge undersurface 31B on the drain electrode 44 side is located closer to the drain electrode 44 than an end 40D of the gate electrode 40 on the drain electrode 44 side. Therefore, the width WR of the ridge portion 31 is longer than the width of the gate electrode 40 in the X-axis direction.

[0045] In the X-axis direction, an end 31AS of the ridge upper surface 31A on the source electrode 42 side is located closer to the source electrode 42 than an end 40S of the gate electrode 40 on the source electrode 42 side. Similarly, an end 31AD of the ridge upper surface 31A on the drain electrode 44 side is located closer to the drain electrode 44 than an end 40D of the gate electrode 40 on the drain electrode 44 side. Therefore, the width of the ridge upper surface 31A is longer than the width of the gate electrode 40 in the X-axis direction. The range of the ridge upper surface 31A from the end 31AS to the end 40S of the gate electrode 40 and the range from the end 31AD to the end 40D of the gate electrode 40 are exposed from the gate electrode 40.

[0046] The thickness TR of the ridge portion 31 may be, for example, 100 nm or more and 200 nm or less. The thickness TR of the ridge portion 31 can be defined as the distance in the Z-axis direction between the ridge upper surface 31A and the ridge lower surface 31B of the ridge portion 31. The thickness TR of the ridge portion 31 is determined in consideration of various parameters such as the gate breakdown voltage.

[0047] The extension portion 32 is located between the ridge upper surface 31A and the ridge lower surface 31B in the Z-axis direction. The extension portion 32 includes a source-side extension portion 33 that extends from an end 32BS of the ridge lower surface 31B on the source electrode 42 side toward the source opening 50A in the X-axis direction. The source-side extension portion 33 can also be described as a portion that extends from the ridge side surface 31C located on the source electrode 42 side toward the source opening 50A. The extension portion 32 also includes a drain-side extension portion 34 that extends from an end 32BD of the ridge lower surface 31B on the drain electrode 44 side toward the drain opening 50B in the X-axis direction. The drain-side extension portion 34 can also be described as a portion that extends from the ridge side surface 31C located on the drain electrode 44 side toward the drain opening 50B.

[0048] Each of the extensions 32 includes an upper surface 32A and a lower surface 32B opposite to the upper surface 32A. The upper surface 32A of the extension 32 is located closer to the ridge lower surface 31B than the ridge upper surface 31A. The upper surface 32A of the extension 32 is connected to the ridge upper surface 31A via a portion of the ridge side surface 31C that is located closer to the ridge upper surface 31A than the extension 32.

[0049] The lower surface 32B of the extension 32 is located closer to the ridge upper surface 31A than the ridge lower surface 31B. Therefore, the lower surface 32B of the extension 32 is spaced apart from the upper surface 26A of the electron supply layer 26. The lower surface 32B of the extension 32 is connected to the ridge lower surface 31B via a portion of the ridge side surface 31C that is located closer to the ridge lower surface 31B than the extension 32.

[0050] An intervening portion 53 formed as part of the passivation layer 50 is located between the lower surface 32B of the extending portion 32 and the upper surface 26A of the electron supply layer 26. The lower surface 32B of the extending portion 32 is in contact with the intervening portion 53. The upper surface 26A of the electron supply layer 26 is in contact with the intervening portion 53.

[0051] The passivation layer 50 includes a first passivation layer 51 and a second passivation layer 52 . The first passivation layer 51 is located closer to the electron supply layer 26 than the lower surface 32B of the extension portion 32, and covers the electron supply layer 26, including the interposed portion 53. The first passivation layer 51 includes a gate opening 50C that exposes a portion of the upper surface 26A of the electron supply layer 26. The gate opening 50C is located between the source opening 50A and the drain opening 50B in the X-axis direction, and is spaced apart from each of the source opening 50A and the drain opening 50B. A portion of the ridge portion 31 of the gate layer 30 below the extension portion 32 is filled in the gate opening 50C. The ridge lower surface 31B of the ridge portion 31 contacts the upper surface 26A of the electron supply layer 26 via the gate opening 50C.

[0052] The first passivation layer 51 can also be said to be a portion located between the upper surface 26A of the electron supply layer 26 and the lower surface 32B of the extension portion 32 in the Z-axis direction. The intervening portion 53 is a portion of the first passivation layer 51 located between the electron supply layer 26 and the extension portion 32. The second passivation layer 52 is located on the first passivation layer 51 and covers the gate layer 30 and the gate electrode 40. The second passivation layer 52 can also be said to be a portion located above the lower surface 32B of the extension portion 32 in the Z-axis direction.

[0053] The extension portion 32 is sandwiched between the first passivation layer 51 and the second passivation layer 52 in the Z-axis direction. More specifically, the extension portion 32 is located on the intermediate portion 53 in the first passivation layer 51. The extension portion 32 is covered with the second passivation layer 52. An upper surface 32A of the extension portion 32 is in contact with the second passivation layer 52.

[0054] The first passivation layer 51 and the second passivation layer 52 may be made of the same material or different materials. In one example, the first passivation layer 51 and the second passivation layer 52 are made of the same material, for example, SiN. An interface may or may not be formed between the first passivation layer 51 and the second passivation layer 52.

[0055] Here, the ridge portion 31 and the extension portion 32 of the gate layer 30 can also be defined based on the first passivation layer 51 and the second passivation layer 52. For example, the ridge portion 31 can be defined as a portion of the gate layer 30 located within and above the gate opening 50C. The extension portion 32 can be defined as a portion of the gate layer 30 located between the first passivation layer 51 and the second passivation layer 52.

[0056] In the Z-axis direction, the distance from the upper surface 26A of the electron supply layer 26 to the lower surface 32B of the extension portion 32 is defined as a distance D1. The distance D1 is the separation distance between the electron supply layer 26 and the extension portion 32. In this embodiment, the distance D1 is equal to the thickness of the interposition portion 53.

[0057] The distance D1 may be, for example, 2 nm or more. The distance D1 may be 3 nm or more, or 5 nm or more. Increasing the distance D1 increases the effect of suppressing the reduction of the 2DEG 28 in the region R1 directly below the extension portion 32 based on the intervening portion 53. The effect of the intervening portion 53 will be described in detail later. The distance D1 may be, for example, 50 nm or less. The distance D1 may be 20 nm or less, or 10 nm or less. Reducing the distance D1 increases the effect of alleviating local electric field concentration near the end of the ridge portion 31.

[0058] Distance D1 is shorter than distance D2 from the lower surface 32B of the extension portion 32 to the ridge upper surface 31A. In other words, in the Z-axis direction, the ridge lower surface 31B is located closer to the ridge lower surface 31B than the center position of the ridge portion 31. Distance D1 may be the same as distance D2, or may be longer than distance D2. Distance D2 may be, for example, 50 nm or more. Distance D2 may be 70 nm or more, or 80 nm or more. Distance D2 may be, for example, 150 nm or less. Distance D2 may be 120 nm or less, or 110 nm or less.

[0059] In one example, the distances D1 and D2 are constant in the X-axis direction. Alternatively, the distances D1 and D2 may vary from one part to another in the X-axis direction. In this case, for example, the average values ​​of the distances can be set as the distances D1 and D2, respectively.

[0060] The thickness TE of the extension 32 may be, for example, 40 nm or less. The thickness TE of the extension 32 may be, for example, 30 nm or less, 25 nm or less, or 20 nm or less. By reducing the thickness TE of the extension 32, the degree of reduction in the 2DEG 28 in the region R1 directly below the extension 32 becomes smaller.

[0061] The thickness of the extension 32 can be, for example, 10 nm or more. The thickness TE of the extension 32 may be, for example, 15 nm or more, or 17 nm or more. When the thickness TE of the extension 32 is large, the degree of reduction of the 2DEG 28 in the region R1 directly below the extension 32 increases. Therefore, in this case, it is particularly effective to suppress the reduction of the 2DEG 28 by providing the intervening portion 53.

[0062] In one example, the thickness TE of the extension 32 may be greater than 30 nm and less than or equal to 40 nm, where the thickness TE of the extension 32 can be defined as the distance between the upper surface 32A and the lower surface 32B of the extension 32 in the Z-axis direction.

[0063] In one example, the thickness TE of the extension portion 32 is constant in the X-axis direction. Alternatively, the thickness TE of the extension portion 32 may vary from portion to portion in the X-axis direction. In this case, for example, the average thickness of the extension portion 32 can be set to the thickness TE.

[0064] In one example, the thickness TE of the source side extension portion 33 is the same as the thickness TE of the drain side extension portion 34. Alternatively, the thickness TE of the source side extension portion 33 and the thickness TE of the drain side extension portion 34 may be different from each other.

[0065] In one example, the thickness TE of the extension portion 32 is thinner than the distance D1 from the upper surface 26A of the electron supply layer 26 to the lower surface 32B of the extension portion 32. Furthermore, the thickness TE of the extension portion 32 may be the same as the distance D1 or may be thicker than the distance D1.

[0066] In one example, the thickness TE of the extension portion 32 is thinner than the distance D3 from the upper surface 32A of the extension portion 32 to the ridge upper surface 31A. Furthermore, the thickness TE of the extension portion 32 may be the same as the distance D3, or may be thicker than the distance D3.

[0067] In one example, the thickness TE of the extension portion 32 is smaller than the sum of the distance D1 from the upper surface 26A of the electron supply layer 26 to the lower surface 32B of the extension portion 32 and the distance D3 from the upper surface 32A of the extension portion 32 to the ridge upper surface 31A. Furthermore, the thickness TE of the extension portion 32 may be the same as or greater than the sum of the distances D1 and D3.

[0068] The width (length in the X-axis direction) of each of the extensions 32 may be, for example, not less than 100 nm and not more than 700 nm. The source-side extension 33 may have a width WS of, for example, 100 nm or more in the direction from the ridge portion 31 toward the source opening 50A (the width direction of the gate layer 30). The width WS of the source-side extension 33 may be, for example, 100 nm or more and 300 nm or less. The width WS of the source-side extension 33 can be defined by the length of the lower surface 32B of the source-side extension 33 in the X-axis direction. In one example, the width WS of the source-side extension 33 is shorter than the width WR of the ridge portion 31. Furthermore, the width WS of the source-side extension 33 may be the same as the width WR of the ridge portion 31, or may be longer than the width WR of the ridge portion 31.

[0069] The drain-side extension 34 may have a width WD of, for example, 400 nm or more in the direction from the ridge 31 toward the drain opening 50B (the width direction of the gate layer 30). The width WD of the drain-side extension 34 may be, for example, 500 nm or more and 700 nm or less. The width WD of the drain-side extension 34 can be defined by the length of the lower surface 32B of the drain-side extension 34 in the X-axis direction. In one example, the width of the drain-side extension 34 is longer than the width WR of the ridge 31. Furthermore, the width of the drain-side extension 34 may be the same as the width WR of the ridge 31, or may be shorter than the width WR of the ridge 31.

[0070] In one example, the width WD of the drain side extension portion 34 is larger than the width WS of the source side extension portion 33. The width WD of the drain side extension portion 34 and the width WS of the source side extension portion 33 can each be changed as desired. For example, the width WD of the drain side extension portion 34 and the width WS of the source side extension portion 33 may be equal to each other. The width WS of the source side extension portion 33 may also be larger than the width WD of the drain side extension portion 34.

[0071] The width of the gate layer 30, i.e., the sum of the width WR of the ridge portion 31, the width WS of the source-side extension portion 33, and the width WD of the drain-side extension portion 34, may be, for example, 1300 nm or more and 1800 nm or less. The sum of the width WS of the source-side extension portion 33 and the width WD of the drain-side extension portion 34 may be, for example, 700 nm or more and 1000 nm or less.

[0072] [Method of manufacturing a nitride semiconductor device] An example of a method for manufacturing the nitride semiconductor device 10 will be roughly described with reference to Figures 5 to 14. Figures 5 to 14 show schematic cross-sectional structures illustrating exemplary manufacturing steps for the nitride semiconductor device 10. The cross-sectional positions in Figures 5 to 14 are the same as those in Figure 3, for example. For ease of understanding, in Figures 5 to 14, components similar to those in Figure 3 may be assigned the same reference numerals.

[0073] As shown in FIG. 5, the method for manufacturing the nitride semiconductor device 10 includes forming, on a substrate 20, an electron transit layer 24 made of a nitride semiconductor, and forming an electron supply layer 26 made of a nitride semiconductor.

[0074] In one example, a buffer layer 22 may be formed on a substrate 20, such as a Si substrate, and then an electron transit layer 24 may be formed on the buffer layer 22. The buffer layer 22 and the electron transit layer 24 may be epitaxially grown using a metal organic chemical vapor deposition (MOCVD) method.

[0075] Although detailed illustration is omitted, in one example, the buffer layer 22 may be a multi-layer buffer layer. The multi-layer buffer layer may include an AlN layer (first buffer layer) formed on the substrate 20 and a graded AlGaN layer (second buffer layer) formed on the AlN layer. The graded AlGaN layer may be formed, for example, by stacking three AlGaN layers with Al compositions of 75%, 50%, and 25%, in that order, starting from the side closest to the AlN layer. The electron transit layer 24 formed on the buffer layer 22 may be a GaN layer.

[0076] Next, the electron supply layer 26 may be formed on the electron transit layer 24. The electron supply layer 26 may be epitaxially grown using, for example, an MOCVD method. The electron transit layer 24 may be a GaN layer, while the electron supply layer 26 may be an AlGaN layer. Therefore, the nitride semiconductor constituting the electron supply layer 26 has a larger band gap than the electron transit layer 24.

[0077] As shown in FIGS. 5 and 6 , the manufacturing method of the nitride semiconductor device 10 includes forming a first passivation layer 51 having a gate opening 50C on the electron supply layer 26. The first passivation layer 51 is formed to cover the upper surface 26A of the electron supply layer 26 and to expose the upper surface 26A of the electron supply layer 26 at the gate opening 50C. The first passivation layer 51 is formed, for example, by the LPCVD method. The first passivation layer 51 may be formed of at least one of SiN, SiO 2 , SiON, Al 2 O 3 , AlN, and AlON. In one example, the first passivation layer 51 is formed of SiN.

[0078] In one example, an insulating layer 86 that will become the first passivation layer 51 is formed over the entire upper surface 26A of the electron supply layer 26, and then a mask is formed on a portion of the upper surface of the insulating layer 86 where the gate opening 50C will not be formed. The insulating layer 86 exposed from the mask is removed to form the first passivation layer 51 having the gate opening 50C. The mask is removed after the gate opening 50C is formed.

[0079] As shown in FIG. 7, the method for manufacturing the nitride semiconductor device 10 includes forming a semiconductor layer 82 by epitaxial growth on the electron supply layer 26 and the first passivation layer 51 through the gate opening 50C.

[0080] The semiconductor layer 82 may be composed of a nitride semiconductor containing acceptor-type impurities. In one example, the semiconductor layer 82 containing acceptor-type impurities can be formed by doping the semiconductor layer 82 with Mg during growth. The semiconductor layer 82 may be composed of, for example, GaN. The semiconductor layer 82 is composed of a nitride semiconductor having a band gap smaller than that of the electron supply layer 26. The semiconductor layer 82 is a semiconductor layer that constitutes the gate layer 30 (see FIG. 3). The semiconductor layer 82 can be epitaxially grown using, for example, an MOCVD method.

[0081] As shown in FIGS. 7 and 8, the method for manufacturing the nitride semiconductor device 10 includes forming the gate electrode 40 on the semiconductor layer 82. As shown in Fig. 7, an electrode layer 84 is formed on the semiconductor layer 82. The electrode layer 84 can be formed on the semiconductor layer 82 by, for example, sputtering. The electrode layer 84 may be formed over the entire upper surface of the semiconductor layer 82. The electrode layer 84 is, for example, a TiN layer. The electrode layer 84 is a metal layer that constitutes the gate electrode 40 (see Fig. 3).

[0082] 8, a portion of the electrode layer 84 is removed to form the gate electrode 40. In one example, a mask is formed on the electrode layer 84. The mask is formed on a portion of the upper surface of the electrode layer 84, more specifically, on a region of the upper surface of the electrode layer 84 where the gate electrode 40 is to be formed. The electrode layer 84 exposed from the mask is then removed to form the gate electrode 40. The mask is removed after the gate electrode 40 is formed.

[0083] As shown in FIGS. 9 and 10 , the manufacturing method for the nitride semiconductor device 10 includes forming the gate layer 30 by etching the semiconductor layer 82. For example, the semiconductor layer 82 is etched by plasma etching. A chlorine-based (Cl2-based) gas can be used for the plasma etching. As a result, a ridge portion 31 and an extension portion 32 are formed in the semiconductor layer 82 directly below the gate electrode 40 and the insulating layer 86. The extension portion 32 includes a source-side extension portion 33 and a drain-side extension portion 34. In one example, the thickness of the extension portion 32 is approximately 30 nm.

[0084] Here, an example of a specific manufacturing process for the gate layer 30 will be described with reference to FIGS. 15 to 18. In this example, the semiconductor layer 82 is formed by the FIELO (Facet-Initiated Epitaxial Lateral Overgrowth) method using the first passivation layer 51. For ease of understanding, FIGS. 15 to 18 illustrate a state in which two gate openings 50C adjacent to each other in the X-axis direction are close to each other, and the shapes and dimensions of each part are different from those in FIGS. 6 to 10. Furthermore, the electrode layer 84 and the gate electrode 40 are not shown in FIGS. 15 to 17.

[0085] 15 and 16, a base 82A of a semiconductor layer 82 is formed by epitaxial growth on the electron supply layer 26 exposed through the gate opening 50C of the first passivation layer 51. The base 82A is formed so as to be located within the gate opening 50C in the X-axis direction, and is formed vertically, that is, in the thickness direction (Z-axis direction), so that a portion of the base 82A protrudes above the first passivation layer 51. As shown in FIG. 16, dislocation defects 82B extending in the thickness direction, that is, the growth direction, are generated within the base 82A. The dislocation defects 82B are formed, for example, by taking over from dislocation defects (not shown) in the upper surface 26A of the electron supply layer 26 on which the base 82A is formed.

[0086] 17, using the base 82A as a seed crystal, epitaxial growth is performed in both the vertical direction (Z-axis direction) which is the thickness direction and the horizontal direction (X-axis direction) along the first passivation layer 51 to form a semiconductor layer 82. At this time, the epitaxial growth in the horizontal direction causes left and right epitaxial growth surfaces to merge on the first passivation layer 51, thereby forming the semiconductor layer 82. Thereafter, as shown in FIG. 18, a portion of the semiconductor layer 82 located on the first passivation layer 51 is etched to form a gate layer 30 on and around the gate opening 50C.

[0087] As shown in FIG. 17 , the dislocation defects 82B generated in the base 82A extend laterally as the epitaxial growth proceeds in the lateral direction, and the laterally extending dislocation defects 82B connect with each other as the epitaxial growth surfaces from the left and right sides merge. The dislocation defects 82B connected from the left and right sides then extend vertically as the epitaxial growth proceeds in the vertical direction. This reduces the density of dislocation defects 82B in the semiconductor layer 82, particularly the density of dislocation defects 82B in the upper part of the semiconductor layer 82. As a result, as shown in FIG. 18 , the number of dislocation defects 82B in the formed gate layer 30 can be reduced from the ridge lower surface 31B in contact with the electron supply layer 26 to the ridge upper surface 31A in contact with the gate electrode 40.

[0088] As shown in FIGS. 11 and 12, the method for manufacturing the nitride semiconductor device 10 includes forming a second passivation layer 52 on the first passivation layer 51, the gate layer 30, and the gate electrode 40.

[0089] 11 , the second passivation layer 52 is formed to cover the portion of the first passivation layer 51 exposed from the gate layer 30, the portion of the gate layer 30 exposed from the gate electrode 40, and the gate electrode 40. The second passivation layer 52 is formed by, for example, an LPCVD method. The second passivation layer 52 may be formed of at least one of SiN, SiO 2 , SiON, Al 2 O 3 , AlN, and AlON. In one example, the second passivation layer 52 is formed of SiN.

[0090] 12, a source opening 50A and a drain opening 50B are formed through the first passivation layer 51 and the second passivation layer 52 in the Z-axis direction to expose the electron supply layer 26. The source opening 50A and the drain opening 50B are formed by, for example, etching. The source opening 50A and the drain opening 50B are formed in the gate layer 30 so as to be located closer to the source opening 50A than the drain opening 50B.

[0091] As shown in FIGS. 13 and 14, the method for manufacturing the nitride semiconductor device 10 includes forming a source electrode 42, a drain electrode 44, and a field plate electrode 60. 13, an electrode layer 92 is formed on the second passivation layer 52. The electrode layer 92 is a metal layer that forms the source electrode 42, the drain electrode 44, and the field plate electrode 60. The electrode layer 92 is formed to fill each of the source opening 50A and the drain opening 50B and to be in contact with the electron supply layer 26 through the source opening 50A and the drain opening 50B. This forms the source contact portion 42A and the drain contact portion 44A. In one example, the electrode layer 92 may include at least one of Ti, TiN, Al, AlSiCu, and AlCu.

[0092] 14, the electrode layer 92 is selectively removed by lithography and etching. As a result, the source electrode 42, the drain electrode 44, and the field plate electrode 60 are formed from the electrode layer 92. Through the above steps, the nitride semiconductor device 10 is manufactured.

[0093] [Operation of the first embodiment] The operation of the nitride semiconductor device 10 of the first embodiment will be described. 3 , the nitride semiconductor device 10 includes a substrate 20, an electron transit layer 24 located on the substrate 20, an electron supply layer 26 located on the electron transit layer 24 and having a band gap larger than that of the electron transit layer 24, a gate layer 30 located on the electron supply layer 26 and containing acceptor-type impurities, and a gate electrode 40 located on the gate layer 30. The gate layer 30 includes an extension portion 32 that is thinner than a ridge portion 31.

[0094] When a voltage is applied to the gate electrode 40, some of the equipotential lines in the ridge portion 31 pass through the extension portion 32. This can mitigate local electric field concentration near the end of the ridge portion 31, which can occur when the extension portion 32 is not present. This suppresses the generation of gate leakage current when a voltage is applied, thereby improving the gate breakdown voltage of the nitride semiconductor device 10. On the other hand, providing the extension portion 32 reduces the 2DEG 28 in the region R1 directly below the extension portion 32, which can increase the on-resistance of the nitride semiconductor device 10.

[0095] In the nitride semiconductor device 10 of the first embodiment, the intervening portion 53, which is a part of the passivation layer 50, is interposed between the electron supply layer 26 and the extension portion 32. That is, by interposing the intervening portion 53, which is the passivation layer 50, between the electron supply layer 26 and the extension portion 32, the extension portion 32 is positioned at a distance from the electron supply layer 26. This reduces the effect of reducing the 2DEG 28 in the region R1 directly below the extension portion 32, which is caused by the presence of the extension portion 32. As a result, when a gate layer 30 including the extension portion 32 is used, an increase in on-resistance caused by the extension portion 32 can be suppressed.

[0096] [Effects of the first embodiment] According to the nitride semiconductor device 10 of the first embodiment, the following effects can be obtained. (1-1) The nitride semiconductor device 10 includes a substrate 20, an electron transit layer 24 located on the substrate 20, an electron supply layer 26 located on the electron transit layer 24 and having a band gap larger than that of the electron transit layer 24, a gate layer 30 located on the electron supply layer 26 and containing acceptor-type impurities, and a gate electrode 40 located on the gate layer 30. The nitride semiconductor device 10 further includes a passivation layer 50 covering the electron supply layer 26, the gate layer 30, and the gate electrode 40 and having a source opening 50A and a drain opening 50B arranged spaced apart from each other in a first direction, a source electrode 42 in contact with the electron supply layer 26 via the source opening 50A, and a drain electrode 44 in contact with the electron supply layer 26 via the drain opening 50B.

[0097] The gate layer 30 includes a ridge portion 31 having a ridge lower surface 31B in contact with the electron supply layer 26 and a ridge upper surface 31A on which the gate electrode 40 is formed, and an extension portion 32 extending from the ridge portion 31 in the X-axis direction and thinner than the ridge portion 31. The ridge portion 31 is a portion located in the X-axis direction between an end 31BS of the ridge lower surface 31B facing the source electrode 42 and an end 31BD of the ridge lower surface 31B facing the drain electrode 44. The extension portion 32 is located between the ridge upper surface 31A and the ridge lower surface 31B, and includes a portion extending from the end 31BS of the ridge lower surface 31B facing the source electrode 42 toward the source opening 50A and a portion extending from the end 31BD of the ridge lower surface 31B facing the drain electrode 44 toward the drain opening 50B. The passivation layer 50 includes an intermediate portion 53 located between the electron supply layer 26 and the extension portion 32.

[0098] According to this configuration, by positioning the intervening portion 53, which is part of the first passivation layer 51, between the upper surface 26A of the electron supply layer 26 and the extension portion 32 in the Z-axis direction, it is possible to suppress a decrease in the 2DEG 28 in the region R1 directly below the extension portion 32. This makes it possible to suppress an increase in on-resistance caused by the extension portion 32. In other words, it is possible to obtain the effect of alleviating electric field concentration caused by providing the extension portion 32 without significantly increasing the on-resistance.

[0099] (1-2) In the thickness direction (Z-axis direction) of the substrate 20, the distance D1 from the upper surface 26A of the electron supply layer 26 to the lower surface 32B of the extension portion 32 is shorter than the distance D2 from the lower surface 32B to the ridge upper surface 31A. Alternatively, the distance D1 is 20 nm or less. With this configuration, by positioning the extension portion 32 closer to the upper surface 26A of the electron supply layer 26 in the Z-axis direction, the effect of alleviating electric field concentration by providing the extension portion 32 can be more significantly obtained.

[0100] (1-3) The distance D1 from the upper surface 26A of the electron supply layer 26 to the lower surface 32B of the extension portion 32 is 2 nm or more. With this configuration, by positioning the extension portion 32 at a position away from the upper surface 26A of the electron supply layer 26 in the Z-axis direction, the effect of suppressing the decrease in the 2DEG 28 in the region R1 directly below the extension portion 32 can be more significantly achieved.

[0101] (1-4) In the first direction (X-axis direction), the end 31BS of the ridge underside 31B on the source electrode 42 side is located closer to the source electrode 42 than the end 40S of the gate electrode 40 on the source electrode 42 side. The end 31BD of the ridge underside 31B on the drain electrode 44 side is located closer to the drain electrode 44 than the end 40D of the gate electrode 40 on the drain electrode 44 side. With this configuration, the effect of alleviating electric field concentration by providing the extension 32 in the gate layer 30 can be more significantly obtained.

[0102] (1-5) A method for manufacturing the nitride semiconductor device 10 includes forming an electron transit layer 24 on a substrate 20, forming an electron supply layer 26 on the electron transit layer 24, forming a first passivation layer 51 having a gate opening 50C on the electron supply layer 26, forming a semiconductor layer 82 containing acceptor-type impurities by epitaxial growth on the electron supply layer 26 through the gate opening 50C and on the first passivation layer 51, forming a gate electrode 40 on the semiconductor layer 82, etching the semiconductor layer 82 to form a gate layer 30, and forming a second passivation layer 52 on the first passivation layer 51, the gate layer 30, and the gate electrode 40. Forming the gate layer 30 includes forming a ridge portion 31 having a ridge lower surface 31B in contact with the electron supply layer 26 and a ridge upper surface 31A on which the gate electrode 40 is formed, and forming an extension portion 32 that is thinner than the ridge portion 31 and is located on the first passivation layer 51 and extends from the ridge portion 31 in the X-axis direction.

[0103] 8 to 10 , in the step of forming the gate layer 30 by etching the semiconductor layer 82, the etching is performed with the upper surface 26A of the electron supply layer 26 covered with the first passivation layer 51. Therefore, the upper surface 26A of the electron supply layer 26 is not exposed by the etching, and etching damage to the upper surface 26A of the electron supply layer 26 can be suppressed. In other words, the first passivation layer 51 functions as a protective layer that protects the upper surface 26A of the electron supply layer 26 from etching damage. As a result, current collapse caused by etching damage to the upper surface 26A of the electron supply layer 26 can be suppressed.

[0104] (1-6) Forming the semiconductor layer 82 by epitaxial growth includes forming a base 82A of the semiconductor layer 82 within the gate opening 50C and growing the base 82A vertically along the thickness direction of the substrate 20 and laterally along the first passivation layer 51.

[0105] This configuration reduces the number of dislocation defects 82B in the gate layer 30 that extend from the ridge lower surface 31B to the ridge upper surface 31A. In the gate layer 30, the dislocation defects 82B that extend from the ridge lower surface 31B to the ridge upper surface 31A can become an electrical leakage path between the gate electrode 40 and the electron supply layer 26. Therefore, by reducing the number of dislocation defects 82B that extend from the ridge lower surface 31B to the ridge upper surface 31A, the gate leakage current caused by the dislocation defects 82B in the gate layer 30 is suppressed. As a result, the rated gate voltage can be set higher.

[0106] Second Embodiment A nitride semiconductor device 10 of the second embodiment will be described with reference to Fig. 19. The nitride semiconductor device 10 of the second embodiment differs from the nitride semiconductor device 10 of the first embodiment mainly in the configuration of the gate layer 30. Below, differences from the nitride semiconductor device 10 of the first embodiment will be described in detail, and components common to the nitride semiconductor device 10 of the first embodiment will be denoted by the same reference numerals and will not be described again.

[0107] 19, the upper surface 32A of each of the extension portions 32 of the gate layer 30 is flush with the ridge upper surface 31A of the ridge portion 31. In other words, the upper surface 32A of the extension portion 32 and the ridge upper surface 31A are at the same position in the Z-axis direction, and the upper surface 32A and the ridge upper surface 31A are located on the same plane.

[0108] In this case, the thickness TE of the extension portion 32 is equal to the distance D2 from the lower surface 32B of the extension portion 32 to the ridge upper surface 31A. The sum of the distance D1 from the upper surface 26A of the electron supply layer 26 to the lower surface 32B of the extension portion 32 and the distance D2 from the lower surface 32B of the extension portion 32 to the ridge upper surface 31A (=the thickness TE of the extension portion 32) is equal to the thickness TR of the ridge portion 31.

[0109] In one example, in the X-axis direction, the end 40S of the gate electrode 40 on the source electrode 42 side is located closer to the drain electrode 44 (to the right of the paper surface in FIG. 19 ) than the end 32AS of the upper surface 32A of the source-side extension 33 on the source electrode 42 side. Furthermore, the end 40S of the gate electrode 40 is located closer to the drain electrode 44 than the end 31BS of the ridge lower surface 31B on the source electrode 42 side. Furthermore, the end 40S of the gate electrode 40 may be located between the end 32AS of the upper surface 32A of the source-side extension 33 and the end 31BS of the ridge lower surface 31B in the X-axis direction.

[0110] In one example, in the X-axis direction, the end 40D of the gate electrode 40 on the drain electrode 44 side is located closer to the source electrode 42 (to the left in FIG. 19 ) than the end 32AD of the upper surface 32A of the drain-side extension 34 on the drain electrode 44 side. Furthermore, the end 40D of the gate electrode 40 is located closer to the source electrode 42 than the end 31BD of the ridge undersurface 31B on the drain electrode 44 side. Alternatively, the end 40D of the gate electrode 40 may be located between the end 32AD of the upper surface 32A of the drain-side extension 34 and the end 31BD of the ridge undersurface 31B in the X-axis direction.

[0111] [Effects of the second embodiment] The nitride semiconductor device 10 of the second embodiment provides the same effects as those described above in (1-1) to (1-6). Furthermore, the nitride semiconductor device 10 of the second embodiment provides the following additional effects.

[0112] (2-1) The upper surface 32A of the extension 32 is flush with the ridge upper surface 31A. With this configuration, in the step of forming the gate layer 30 by etching the semiconductor layer 82, multi-stage etching is not required, and therefore the extension 32 can be easily formed.

[0113] <Third embodiment> A nitride semiconductor device 10 of the third embodiment will be described with reference to Fig. 20. The nitride semiconductor device 10 of the third embodiment differs from the nitride semiconductor device 10 of the second embodiment mainly in the configuration of the gate layer 30. Below, differences from the nitride semiconductor device 10 of the second embodiment will be described in detail, and components common to the nitride semiconductor device 10 of the second embodiment will be denoted by the same reference numerals and will not be described again.

[0114] 20, each of the extension portions 32 of the gate layer 30 has an inclined surface 32C that is inclined with respect to the lower surface 32B of the extension portion 32. In addition, the thickness of each of the extension portions 32 decreases with increasing distance from the ridge portion 31 in the X-axis direction within the range where the inclined surface 32C is located.

[0115] In the example shown in Fig. 20, the side surface located at the end in the X-axis direction of the extension portion 32 of the second embodiment shown in Fig. 19 is an inclined surface 32C. In this case, the extension portion 32 includes an upper surface 32A that is flush with the ridge upper surface 31A, and an inclined surface 32C. The inclined surface 32C is connected to the ridge upper surface 31A on one side in the X-axis direction, and is connected to the lower surface 32B of the extension portion 32 on the other side in the X-axis direction.

[0116] The angle θ formed between the inclined surface 32C and the lower surface 32B of the extending portion 32 may be, for example, 70 degrees or more and 90 degrees or less. The angle θ may be 75 degrees or more and 85 degrees or less. The length W1 of the inclined surface 32C in the X-axis direction may be, for example, 1 nm or more and 35 nm or less. The length W1 may be 10 nm or more and 25 nm or less.

[0117] As another example, the extension 32 may not include the upper surface 32A, and the inclined surface 32C may be positioned continuously from the ridge upper surface 31A. As another example, the extension portion 32 may have a configuration in which the upper surface 32A is located closer to the ridge lower surface 31B than the ridge upper surface 31A, as in the first embodiment. In this case, the upper surface 32A of the extension portion 32 is connected to the ridge upper surface 31A via the ridge side surface 31C (see FIG. 4) of the ridge portion 31 on one side in the X-axis direction, and is connected to the inclined surface 32C on the other side in the X-axis direction. In other words, the extension portion 32 may have a configuration in which the side surface located at the end of the extension portion 32 in the X-axis direction of the first embodiment shown in FIG. 4 is the inclined surface 32C.

[0118] [Effects of the third embodiment] The nitride semiconductor device 10 of the third embodiment provides the same effects as those of (1-1) to (1-6) and (2-1) above. Furthermore, the nitride semiconductor device 10 of the third embodiment provides the following additional effects.

[0119] (3-1) The extension portion 32 has an inclined surface 32C that is inclined relative to the lower surface 32B of the extension portion 32, and its thickness decreases with increasing distance from the ridge portion 31. In this case, the thickness TE of the extension portion 32 can be reduced in the area where the inclined surface 32C of the extension portion 32 is located. By reducing the thickness TE of the extension portion 32, the degree of reduction in the 2DEG 28 in the region R1 directly below the extension portion 32 is reduced. Furthermore, when the inclined surface 32C is located at the end of the extension portion 32 in the X-axis direction, the width of the extension portion 32 can be increased. Increasing the width of the extension portion 32 enhances the effect of alleviating electric field concentration.

[0120] <Example of change> The above-described embodiments can be modified as follows: Furthermore, the above-described embodiments and the following modifications can be combined with each other within the scope of technical compatibility.

[0121] In each embodiment, the nitride semiconductor device 10 is not limited to a HEMT using GaN, and may be a semiconductor device using other nitride semiconductors. The nitride semiconductor device 10 of each embodiment is not limited to being configured with the numerical values ​​or numerical ranges described in each embodiment.

[0122] In the first to third embodiments, the gate layer 30 is not limited to a configuration including both the source-side extension portion 33 and the drain-side extension portion 34. For example, the gate layer 30 may have the drain-side extension portion 34 but omit the source-side extension portion 33, or may have the source-side extension portion 33 but omit the drain-side extension portion 34.

[0123] In the first embodiment, the end 31BS of the ridge underside 31B on the source electrode 42 side may be located closer to the drain electrode 44 than the end 40S of the gate electrode 40 on the source electrode 42 side. Also, the end 31BD of the ridge underside 31B on the drain electrode 44 side may be located closer to the source electrode 42 than the end 40D of the gate electrode 40 on the drain electrode 44 side.

[0124] In the second and third embodiments, the end 40S of the gate electrode 40 may be located closer to the source electrode 42 than the end 32AS of the upper surface 32A of the source-side extension 33. Furthermore, the end 40D of the gate electrode 40 may be located closer to the drain electrode 44 than the end 32AD of the upper surface 32A of the drain-side extension 34.

[0125] In the region between the upper surface 26A of the electron supply layer 26 and the lower surface 32B of the extension portion 32 of the gate layer 30, another layer may be interposed between the upper surface 26A of the electron supply layer 26 and the intermediate portion 53, or between the intermediate portion 53 and the lower surface 32B of the extension portion 32, or both. In this case, the distance D1 from the upper surface 26A of the electron supply layer 26 to the lower surface 32B of the extension portion 32 is equal to the sum of the thickness of the intermediate portion 53 and the thickness of the other layer.

[0126] In the first embodiment, one or both of the ridge side surfaces 31C of the ridge portion 31 of the gate layer 30 may be inclined with respect to the lower surface 32B of the extension portion 32. In this case, the length in the X-axis direction of the ridge upper surface 31A is shorter than the width WR of the ridge portion 31, which is the length in the X-axis direction of the ridge lower surface 31B. Furthermore, the cross-sectional shape of the ridge portion 31 is such that the width in the X-axis direction gradually increases from the ridge upper surface 31A toward the ridge lower surface 31B, for example, a trapezoid.

[0127] One or more of the various examples described herein may be combined to the extent that they are not technically inconsistent. The term "on" as used in this disclosure includes the meanings of "on" and "above" unless the context clearly indicates otherwise. Thus, for example, the expression "a first element is disposed on a second element" means that in some embodiments, the first element may be disposed directly on the second element in contact with the second element, while in other embodiments, the first element may be disposed above the second element without contacting the second element. In other words, the term "on" does not exclude a structure in which another element is formed between the first element and the second element.

[0128] The Z-axis direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure are not limited to the "up" and "down" in the Z-axis direction described in this specification being "up" and "down" in the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0129] <Additional Notes> The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the above embodiment. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0130] [Appendix 1] A substrate (20); an electron transit layer (24) located on the substrate (20); an electron supply layer (26) located on the electron transit layer (24) and having a band gap larger than that of the electron transit layer (24); a gate layer (30) located on the electron supply layer (26) and containing acceptor-type impurities; a gate electrode (40) located on the gate layer (30); a passivation layer (50) covering the electron supply layer (26), the gate layer (30), and the gate electrode (40), and having a source opening (50A) and a drain opening (50B) spaced apart from each other in a first direction; a source electrode (42) in contact with the electron supply layer (26) through the source opening (50A); a drain electrode (44) in contact with the electron supply layer (26) through the drain opening (50B), The gate layer (30) a ridge portion (31) having a ridge lower surface (31B) in contact with the electron supply layer (26) and a ridge upper surface (31A) on which the gate electrode (40) is formed; an extension portion (32) extending from the ridge portion (31) in the first direction and thinner than the ridge portion (31); the ridge portion (31) is a portion located between an end (31BS) of the ridge lower surface (31B) on the source electrode (42) side and an end (31BD) of the ridge lower surface (31B) on the drain electrode (44) side in the first direction, the extension portion (32) is located between the ridge upper surface (31A) and the ridge lower surface (31B), and includes one or both of a portion extending from an end (31BS) of the ridge lower surface (31B) on the source electrode (42) side toward the source opening (50A) and a portion extending from an end (31BD) of the ridge lower surface (31B) on the drain electrode (44) side toward the drain opening (50B); The passivation layer (50) includes an intervening portion (52) interposed between the electron supply layer (26) and the extending portion (32).

[0131] [Appendix 2] 2. The nitride semiconductor device (10) according to claim 1, wherein a distance (D1) from an upper surface (26A) of the electron supply layer (26) to a lower surface (32B) of the extension portion (32) in a thickness direction of the substrate (20) is shorter than a distance (D2) from the lower surface (32B) to the ridge upper surface (31A).

[0132] [Appendix 3] The nitride semiconductor device (10) according to claim 1 or 2, wherein a distance (D1) from an upper surface (26A) of the electron supply layer (26) to a lower surface (32B) of the extension portion (32) is 2 nm or more.

[0133] [Appendix 4] 4. The nitride semiconductor device (10) according to any one of claims 1 to 3, wherein a distance (D1) from an upper surface (26A) of the electron supply layer (26) to a lower surface (32B) of the extension portion (32) is 20 nm or less.

[0134] [Appendix 5] The nitride semiconductor device (10) according to any one of appendices 1 to 4, wherein the distance from the lower surface of the extension to the upper surface of the ridge is 150 nm or less.

[0135] [Appendix 6] The nitride semiconductor device (10) according to any one of appendixes 1 to 5, wherein a thickness (TE) of the extension portion (32) is greater than a distance (D1) from an upper surface (26A) of the electron supply layer (26) to a lower surface (32B) of the extension portion (32).

[0136] [Appendix 7] The nitride semiconductor device (10) according to any one of appendices 1 to 6, wherein the thickness (TE) of the extension portion (32) is thinner than the distance (D3) from the upper surface (32A) of the extension portion (32) to the ridge upper surface (31A).

[0137] [Appendix 8] The nitride semiconductor device (10) according to any one of Appendices 1 to 7, wherein a thickness (TE) of the extension portion (32) is thinner than the sum of a distance (D1) from an upper surface (26A) of the electron supply layer (26) to a lower surface (32B) of the extension portion (32) and a distance (D3) from the upper surface (32A) of the extension portion (32) to the ridge upper surface (31A).

[0138] [Appendix 9] The nitride semiconductor device (10) according to any one of appendices 1 to 8, wherein the length (WS, WD) in the first direction of the extension (32) is 100 nm or more and 700 nm or less.

[0139] [Appendix 10] 10. The nitride semiconductor device (10) according to any one of appendices 1 to 9, wherein the extension portion (32) has a constant thickness in the first direction.

[0140] [Appendix 11] The nitride semiconductor device (10) according to any one of appendices 1 to 10, wherein an upper surface (32A) of the extension portion (32) is located closer to the ridge lower surface (31B) than the ridge upper surface (31A).

[0141] [Appendix 12] 11. The nitride semiconductor device (10) according to any one of claims 1 to 10, wherein an upper surface (32A) of the extension portion (32) is flush with an upper surface (31A) of the ridge.

[0142] [Appendix 13] The nitride semiconductor device (10C) according to any one of Appendices 1 to 10, wherein the extension portion (32) has an inclined surface (32) that is inclined with respect to a lower surface (32B) of the extension portion (32), and the thickness thereof decreases with increasing distance from the ridge portion (31).

[0143] [Appendix 14] In the first direction, an end (31BS) of the ridge underside (31B) on the source electrode (42) side is located closer to the source electrode (42) than an end (40S) of the gate electrode (40) on the source electrode (42) side; The nitride semiconductor device (10) according to any one of Appendices 1 to 13, wherein an end (31BD) of the ridge underside (31B) on the drain electrode (44) side is located closer to the drain electrode (44) than an end (40D) of the gate electrode (40) on the drain electrode (44) side.

[0144] [Appendix 15] The passivation layer (50) is a first passivation layer (51) located closer to the electron supply layer (26) than the lower surface (32B) of the extension portion (32) and covering the electron supply layer (26) including the intermediate portion (53); a second passivation layer (52) located on the first passivation layer (51) and covering the gate layer (30) and the gate electrode (40); The extension portion (32) is located on the intermediate portion (53) of the first passivation layer (51), 15. The nitride semiconductor device (10) according to any one of appendices 1 to 14, wherein the second passivation layer (52) covers the extension portion (32).

[0145] [Appendix 16] the first passivation layer (51) has a gate opening (50C); the gate layer (30) is in contact with the electron supply layer (26) through the gate opening (50C); 16. The nitride semiconductor device (10) according to claim 15, wherein the ridge portion (31) is a portion of the gate layer (30) located within and above the gate opening (50C).

[0146] [Appendix 17] A substrate (20); an electron transit layer (24) located on the substrate (20); an electron supply layer (26) located on the electron transit layer (24) and having a band gap larger than that of the electron transit layer (24); a gate layer (30) located on the electron supply layer (26) and containing acceptor-type impurities; a gate electrode (40) located on the gate layer (30); a passivation layer (50) covering the electron supply layer (26), the gate layer (30), and the gate electrode (40), and having a source opening (50A) and a drain opening (50B) spaced apart from each other in a first direction; a source electrode (42) in contact with the electron supply layer (26) through the source opening (50A); a drain electrode (44) in contact with the electron supply layer (26) through the drain opening (50B), The passivation layer (50) is a first passivation layer (51) covering the electron supply layer (26) and having a gate opening (50C); a second passivation layer (52) located on the first passivation layer (51) and covering the gate layer (30) and the gate electrode (40); The gate layer (30) a ridge portion (31) having a ridge lower surface (31B) in contact with the electron supply layer (26) at the gate opening (50C) and a ridge upper surface (31A) on which the gate electrode (40) is formed; an extension portion (32) extending from the ridge portion (31) in the first direction and thinner than the ridge portion (31), the ridge portion (31) is a portion of the gate layer (30) located within and above the gate opening (50C), the extension portion (32) is located between the first passivation layer (51) and the second passivation layer (52), and includes one or both of a portion extending toward the source opening (50A) and a portion extending toward the drain opening (50B); The nitride semiconductor device (10) includes a first passivation layer (51) including an intervening portion (53) interposed between the electron supply layer (26) and the extending portion (32).

[0147] [Appendix 18] forming an electron transit layer (24) on a substrate (20); forming an electron supply layer (26) on the electron transit layer (24) and having a band gap larger than that of the electron transit layer (24); forming a first passivation layer (51) having a gate opening (50C) on the electron supply layer (26); forming a semiconductor layer (82) containing an acceptor-type impurity by epitaxial growth on the electron supply layer (26) through the gate opening (50C) and on the first passivation layer (51); forming a gate electrode (40) on the semiconductor layer (82); forming a gate layer (30) by etching the semiconductor layer (82); forming a second passivation layer (52) on the first passivation layer (51), on the gate layer (30), and on the gate electrode (40); Forming the gate layer (30) forming a ridge portion (31) having a ridge lower surface (31B) in contact with the electron supply layer (26) and a ridge upper surface (31A) on which the gate electrode (40) is formed; forming an extension portion (32) that is positioned on the first passivation layer (51), extends from the ridge portion (31), and is thinner than the ridge portion (31).

[0148] [Appendix 19] Forming the semiconductor layer (82) by epitaxial growth includes: forming a base portion (82A) of the semiconductor layer (82) within the gate opening (50C); growing the base portion (82A) vertically along a thickness direction of the substrate (20) and laterally along the first passivation layer (51). [Explanation of symbols]

[0149] 10...Nitride semiconductor device 12...Chip body 13…Top surface 14...Gate pad 16...Sauce pad 18...Drain pad 20...Substrate 20A…Top surface 22...Buffer layer 24...Electron transit layer 26…electron supply layer 26A…Top surface 28...2DEG 30...Gate layer 31...Ridge 31A...Top of ridge 31B...underside of ridge 31BS,31BD…End part 31C…Ridge side 32...Extension part 32A…Top surface 32B…Bottom surface 32C…Slanted surface 40...Gate electrode 40S, 40D...End 42...Source electrode 42A...Source contact part 44...Drain electrode 44A...Drain contact part 50...passivation layer 50A...Source opening 50B...Drain opening 50C...Gate opening 51...First passivation layer 52...Second passivation layer 53…Intervening part 60...Field plate electrode 61...End 72...Gate wiring 73...Gate connecting conductor 74...Source wiring 75...Source connecting conductor 76...Drain wiring 77...Drain connecting conductor 82...Semiconductor layer 82A…Base 82B...Transposition defect 84...electrode layer 86...insulating layer 92...electrode layer D1: Distance from the top surface of the electron supply layer to the bottom surface of the extension D2: Distance from the bottom of the extension to the top of the ridge D3: Distance from the top surface of the extension to the top surface of the ridge R1: Area directly below the extension TR: Ridge thickness TE: Thickness of the extension WR: Ridge width WS: Width of source side extension WD: Width of the drain side extension W1: Length of the inclined surface in the first direction θ: angle of inclined surface

Claims

1. A substrate; an electron transit layer located on the substrate; an electron supply layer located on the electron transit layer and having a band gap larger than that of the electron transit layer; a gate layer located on the electron supply layer and containing an acceptor-type impurity; a gate electrode located on the gate layer; a passivation layer covering the electron supply layer, the gate layer, and the gate electrode, and having a source opening and a drain opening spaced apart from each other in a first direction; a source electrode in contact with the electron supply layer through the source opening; a drain electrode in contact with the electron supply layer through the drain opening, The gate layer a ridge portion having a ridge lower surface in contact with the electron supply layer and a ridge upper surface on which the gate electrode is formed; an extension portion that extends from the ridge portion in the first direction and is thinner than the ridge portion; the ridge portion is a portion located between an end of the ridge lower surface on the source electrode side and an end of the ridge lower surface on the drain electrode side in the first direction, the extension portion is located between the ridge upper surface and the ridge lower surface, and includes one or both of a portion extending from an end of the ridge lower surface on the source electrode side toward the source opening and a portion extending from an end of the ridge lower surface on the drain electrode side toward the drain opening, The passivation layer includes an intermediate portion interposed between the electron supply layer and the extension portion.

2. The nitride semiconductor device according to claim 1 , wherein a distance from an upper surface of said electron supply layer to a lower surface of said extension portion in a thickness direction of said substrate is shorter than a distance from said lower surface to an upper surface of said ridge.

3. The nitride semiconductor device according to claim 1 , wherein the distance from the upper surface of said electron supply layer to the lower surface of said extension portion is 2 nm or more.

4. The nitride semiconductor device according to claim 1 , wherein the distance from the upper surface of said electron supply layer to the lower surface of said extension portion is 20 nm or less.

5. The nitride semiconductor device according to claim 1 , wherein the distance from the lower surface of said extension portion to the upper surface of said ridge is 150 nm or less.

6. The nitride semiconductor device according to claim 1 , wherein the thickness of said extension portion is greater than the distance from the upper surface of said electron supply layer to the lower surface of said extension portion.

7. The nitride semiconductor device according to claim 1 , wherein the thickness of said extension is smaller than the distance from the upper surface of said extension to the upper surface of said ridge.

8. 2. The nitride semiconductor device according to claim 1, wherein the thickness of said extension is smaller than the sum of the distance from the upper surface of said electron supply layer to the lower surface of said extension and the distance from the upper surface of said extension to the upper surface of said ridge.

9. The nitride semiconductor device according to claim 1 , wherein the length of said extension in said first direction is not less than 100 nm and not more than 700 nm.

10. The nitride semiconductor device according to claim 1 , wherein said extension portion has a constant thickness in said first direction.

11. The nitride semiconductor device according to claim 10 , wherein the upper surface of said extension portion is located closer to the lower surface of said ridge than the upper surface of said ridge.

12. The nitride semiconductor device according to claim 10 , wherein an upper surface of said extension portion is flush with an upper surface of said ridge.

13. The nitride semiconductor device according to claim 1 , wherein said extension portion has an inclined surface inclined with respect to a lower surface of said extension portion, and the thickness of said extension portion decreases with increasing distance from said ridge portion.

14. In the first direction, an end portion of the lower surface of the ridge on the side of the source electrode is located closer to the source electrode than an end portion of the gate electrode on the side of the source electrode, The nitride semiconductor device according to claim 1 , wherein an end of said ridge underside on said drain electrode side is located closer to said drain electrode than an end of said gate electrode on said drain electrode side.

15. The passivation layer comprises: a first passivation layer located closer to the electron supply layer than a lower surface of the extension portion and covering the electron supply layer including the interposed portion; a second passivation layer located on the first passivation layer and covering the gate layer and the gate electrode; the extension portion is located on the intermediate portion of the first passivation layer; The nitride semiconductor device according to claim 1 , wherein said second passivation layer covers said extension portion.

16. the first passivation layer has a gate opening; the gate layer is in contact with the electron supply layer through the gate opening, The nitride semiconductor device according to claim 15 , wherein said ridge portion is a portion of said gate layer located within and above said gate opening.

17. A substrate; an electron transit layer located on the substrate; an electron supply layer located on the electron transit layer and having a band gap larger than that of the electron transit layer; a gate layer located on the electron supply layer and containing an acceptor-type impurity; a gate electrode located on the gate layer; a passivation layer covering the electron supply layer, the gate layer, and the gate electrode, and having a source opening and a drain opening spaced apart from each other in a first direction; a source electrode in contact with the electron supply layer through the source opening; a drain electrode in contact with the electron supply layer through the drain opening, The passivation layer comprises: a first passivation layer covering the electron supply layer and having a gate opening; a second passivation layer located on the first passivation layer and covering the gate layer and the gate electrode; The gate layer a ridge portion having a ridge lower surface in contact with the electron supply layer at the gate opening and a ridge upper surface on which the gate electrode is formed; an extension portion that extends from the ridge portion in the first direction and is thinner than the ridge portion; the ridge portion is a portion of the gate layer located within and above the gate opening, the extension portion is located between the first passivation layer and the second passivation layer, and includes one or both of a portion extending toward the source opening and a portion extending toward the drain opening; the first passivation layer includes an intermediate portion interposed between the electron supply layer and the extension portion.

18. forming an electron transit layer on a substrate; forming an electron supply layer on the electron transit layer, the electron supply layer having a band gap larger than that of the electron transit layer; forming a first passivation layer having a gate opening on the electron supply layer; forming a semiconductor layer containing an acceptor-type impurity by epitaxial growth on the electron supply layer through the gate opening and on the first passivation layer; forming a gate electrode on the semiconductor layer; forming a gate layer by etching the semiconductor layer; forming a second passivation layer on the first passivation layer, on the gate layer, and on the gate electrode; forming the gate layer forming a ridge portion having a ridge lower surface in contact with the electron supply layer and a ridge upper surface on which the gate electrode is formed; forming an extension portion located on the first passivation layer and extending from the ridge portion, the extension portion being thinner than the ridge portion.

19. forming the semiconductor layer by epitaxial growth, forming a base of the semiconductor layer within the gate opening; 20. The method for manufacturing a nitride semiconductor device according to claim 18, further comprising: growing the base portion vertically along a thickness direction of the substrate and laterally along the first passivation layer.

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